Motor control circuit, motor control ic, and motor drive control method

Abstract

To improve efficiency at high-speed rotation, and realize a high-speed and a small current.SOLUTION: A motor control circuit 10 supplying a driving voltage to a brushless DC motor 5 via a motor driving part 2, comprises: a current zero detection part 13 that detects a voltage corresponded to a driving circuit flowing in a coil of the motor 5, and detects timing when the driving current becomes zero; a position detection signal generation part 12 that outputs a position detection signal FG_offset that becomes a reference by a hall signal generated by a hall element 6; a phase adjustment part 14 that adjusts a phase of a position detection signal LAFG as a target after a sequence period of the position detection signal FG_offset that becomes the reference on the basis of timing when the driving current detected by the current zero detection part 13 becomes zero and a position detection signal that becomes the reference; and a driving control part 17 that controls the timing for switching a driving voltage so as to be matched to a phase switching point of the position detection signal LAFG as a target.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a motor control circuit, a motor control IC, and a motor drive control method. [Background technology]

[0002] In a brushless DC motor, in order to rotate the motor with high efficiency, it is known that when a rotor equipped with a magnet rotates, the rotational position of the rotor is grasped based on a Hall element output signal detected by a Hall element or by calculating a back electromotive force (BEMF) generated in a stator coil, and a drive current is passed in phase with the rotation of the rotor (for example, Patent Document 1).

[0003] With this technology, the drive voltage applied to both ends of the coil is switched between high and low in phase with the Hall element output signal or BEMF, causing a drive current to flow and rotate the motor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2004-153921 A Summary of the Invention [Problem to be solved by the invention]

[0005] Due to the coil characteristics of the brushless DC motor (V=L*dI / dt), the drive current changes with a time delay when the drive voltage is switched on and off. To increase the motor's rotation speed, a larger current is required, and the larger the current, the greater the time delay.

[0006] In this way, when the motor is rotating at high speed, the phase of the drive current is shifted from the phase indicating the actual position of the rotor, so the drive force is not sufficiently transmitted to torque. Even if the current is increased, the rotation speed does not increase proportionally as expected, and efficiency decreases.

[0007] In view of the above circumstances, the present invention provides a motor control circuit that improves the efficiency of a motor during high-speed rotation, allows the motor to rotate at a sufficiently high speed with a specified amount of current, and allows the motor to rotate at the same rotation speed with less current. [Means for solving the problem]

[0008] A motor control circuit according to one aspect of the present invention includes: A motor control circuit that supplies a drive voltage to a brushless DC motor via a motor drive unit, a current zero point detection unit that detects a voltage corresponding to a drive current flowing through a coil of the motor and detects a timing at which the drive current becomes zero; a position detection signal generating unit that outputs a reference position detection signal based on a hall signal generated by the hall element; a phase adjustment unit that adjusts a phase of a target position detection signal from the next period onward of the reference position detection signal, based on the timing at which the drive current becomes zero, detected by the current zero point detection unit, and the reference position detection signal; and a drive control unit that controls and outputs the timing for switching the drive voltage so as to coincide with the phase switching point of the target position detection signal. Effect of the Invention

[0009] According to one aspect, a motor control circuit can improve the efficiency of a motor when rotating at high speed, allowing the motor to rotate at a sufficiently high speed with a given amount of current, or to rotate at the same rotation speed with less current. [Brief description of the drawings]

[0010] [Figure 1]1 is a diagram showing a configuration of a motor drive control device according to an embodiment of the present invention; [Diagram 2] 4 is a circuit diagram of a current zero point detector, a position detection signal generator, and a phase adjuster. FIG. [Diagram 3] 1 is an explanatory diagram of a current flow in an H-bridge circuit and a motor when a phase inversion of a drive voltage occurs. FIG. [Figure 4] 11A to 11C are diagrams illustrating behaviors of a current zero point detection unit in different situations when an adjustment signal Offset Enable is off. [Diagram 5] 11 is an input / output characteristic diagram of an inverter included in a current zero point detection unit. FIG. [Figure 6] 11A to 11C are diagrams illustrating behaviors of a current zero point detection unit in different situations when an adjustment signal Offset Enable is on. [Figure 7] FIG. 13 is an explanatory diagram of the overall operation of a comparative example in which advance angle adjustment is not performed. [Figure 8] FIG. 4 is a diagram illustrating signal operations during steady rotation in the motor drive control device. [Figure 9] 5 is a schematic flowchart of control during steady rotation according to one embodiment. [Figure 10] 5 is a detailed flowchart of current zero point detection during steady rotation according to one embodiment. [Figure 11] FIG. 4 is an explanatory diagram of the overall operation when advance angle adjustment of the present invention is performed; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and duplicated descriptions may be omitted.

[0012] First, the configuration of a motor drive control device according to one embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a diagram showing the configuration of a motor drive control device according to one embodiment of the present invention. Figure 2 is a circuit diagram of a current zero point detection unit, a position detection signal generation unit, and a phase adjustment unit.

[0013] The motor drive control device 4 is incorporated in a fan motor for cooling heat-generating components such as a processor in an electronic device such as a notebook personal computer, for example. The motor driven by the motor drive control device 4 is a brushless DC (Direct Current) motor (BLDC).

[0014] The motor drive control device 4 is, for example, a circuit that drives a single-phase motor 5 for rotating a cooling fan, and includes a control circuit 10, an H-bridge circuit 2, and a detection resistor 3. The control IC1 (motor control IC) is a semiconductor integrated circuit that controls the motor drive unit, and includes terminals in the control circuit 10. A Hall signal is input to the motor drive control device 4 from a Hall element 6.

[0015] The control circuit 10 has a PWM signal generation unit 11, a position detection signal generation unit 12, a current zero point detection unit 13, a phase adjustment unit 14, an output control unit / soft switch period generation unit 15, and a gate driver 16. The output control unit / soft switch period generation unit 15 and the gate driver 16 function as a drive control unit 17.

[0016] The H-bridge circuit 2 is a motor drive unit and is composed of PchFETs M1 and M2 and NchFETs M3 and M4. The PchFET M1 functions as a first upper switch, the NchFET M4 as a first lower switch, the PchFET M2 as a second upper switch, and the NchFET M3 as a second lower switch.

[0017] The detection resistor 3 is connected to the H-bridge circuit 2 and is used to detect the current flowing through the coil L of the single-phase motor 5.

[0018] The rotor (not shown) of this single-phase motor 5 is equipped with a magnet, while the Hall element 6 is fixed so as to be able to detect the magnetic field of the magnet equipped on the rotor, and the Hall element 6 outputs Hall signals IN1, IN2 at a voltage level corresponding to the strength of the detected magnetic field to its terminals. The magnet also rotates as the rotor rotates, and the Hall element 6 detects the change in the magnetic field caused by the rotation of the magnet, thereby detecting the rotor position. The Hall signals IN1, IN2 in this embodiment are, for example, sine wave signals with an amplitude of a predetermined voltage level, and are output to the terminals of the control IC1. Note that the Hall signals IN1, IN2 are not limited to sine waves.

[0019] The position detection signal generating unit 12 compares the levels of the Hall signals IN1 and IN2, and generates an FG (frequency generation) signal, the frequency of which changes in accordance with the rotation speed of the single-phase motor 5.

[0020] In detail, the position detection signal generating unit 12 has hysteresis comparators 21 and 22, glitch filters 23 and 24, a signal processing unit 25, and an offset processing unit .

[0021] The hysteresis comparators 21 and 22 compare the levels of the Hall signals IN1 and IN2. When an inverted signal is input close to the input, a whisker-like glitch pulse may occur in the output due to the difference in noise signal delay time in the vicinity. The glitch filters 23 and 24 remove unnecessary glitch pulses, preventing them from adversely affecting the signal processing unit 25, which is the logic circuit in the next stage and thereafter, as noise.

[0022] Then, the signal processing unit 25 generates an FG signal that becomes a low level (hereinafter, "L" level) when the level of the Hall signal IN1 becomes higher than the level of the Hall signal IN2, and becomes a high level (hereinafter, "H" level) when the level of the Hall signal IN1 becomes lower than the level of the Hall signal IN2.

[0023] A predetermined amount of offset (a period shorter than the phase adjustment range) is stored in the offset processing unit 26, and during steady rotation, a position detection signal FG_offset in which the phase of the FG signal, which is a position detection signal, is advanced is output.

[0024] In this way, the position detection signal generating unit 12 outputs, at startup, a position detection signal FG that matches the Hall signal generated by the Hall element as a reference. During steady rotation, a position detection signal FG_offset that is phase-advanced (offset) from the Hall signal by a predetermined amount is output as a reference. In this way, when rotation is unstable, such as at startup, the motor is driven at an actual Hall signal switching position where the motor can operate reliably, and during steady rotation, the phase switching is driven at a position suitable for the motor characteristics. Note that, in this example, an example is shown in which the offset position detection signal FG_offset is phase-advanced with respect to the position detection signal FG, but the position detection signal FG_offset may be a signal whose phase is delayed by a predetermined amount with respect to the position detection signal FG depending on the situation.

[0025] A PWM (Pulse Width Modulation) signal generating unit 11 generates a PWM signal, which is a switching signal for driving the PchFETs M1 and M2 and the NchFETs M3 and M4 that constitute the H-bridge circuit 2, based on the position detection signal FG or FG_offset.

[0026] The duty ratio of the PWM signal generated by the PWM signal generating unit 11 is fixed, and the output voltage Vout does not change. In this control, when switching the drive voltage, a soft switch is performed in which the voltage changes stepwise between H and L, and the control of the soft switch is executed by the output control unit / soft switch period generating unit 15 at the subsequent stage.

[0027] The current zero point detection unit 13 detects the voltage Vsns between the H-bridge circuit 2 and the detection resistor 3 during a current monitoring period, which is an angular period before and after a phase switching point in a reference position detection signal.

[0028] The voltage Vsns between the H-bridge circuit 2 and the detection resistor 3 is calculated by (the fixed resistance value Rsns of the detection resistor 3) x (the current Idr flowing through the coil L), so the detection voltage Vsns can be said to be a voltage corresponding to the drive current Idr flowing through the coil L.

[0029] The sampling signal SW_SAMP_A, the standby signal SW_OFFSET_A, and the adjustment signal Offset Enable are input to the current zero point detection unit 13. The adjustment signal Offset Enable is turned on when it is desired to improve or change the motor characteristics, etc. For example, if an offset occurs in the actual Vsns level or the reference GND level due to wiring impedance, it is used to cancel that offset. In other words, the on / off setting of the adjustment signal Offset Enable does not move in conjunction with anything in a series of operations, but rather serves as an initial setting for whether or not to add an offset to the current zero point detection level.

[0030] In detail, the current zero point detection unit 13 has a switch group 31, a voltage comparison circuit 30, and a latch processing unit 33 as permanent circuits that are used regardless of whether the adjustment signal Offset Enable is on or off. The switches 311 and 312 that constitute the switch group 31 switch the input terminal of the voltage comparison circuit 30 between the detection voltage Vsns and the ground voltage GND based on the on / off (or high / low) states of two types of signals, a sampling signal SW_SAMP_A and a standby signal SW_OFFSET_A. The voltage comparison circuit 30 has capacitors 301 and 303, inverters 302, 304, and 305, and further has switches 306 and 307 that short-circuit the inverters 302 and 304, respectively. The latch processing unit 33 outputs a state notification signal Zero_det_latch based on the result of the zero point output Zero detection that is the output of the voltage comparison circuit 30.

[0031] Furthermore, the zero current detection unit 13 has a switch 32, a constant current source 34 connected to a resistor 342, a switch group 35, and a capacitor 308 as an additional offset circuit (adjustment circuit) that is used only when the adjustment signal Offset Enable is on. When the adjustment signal Offset Enable is on, the switch 32 is turned on to connect the adjustment circuit, the capacitor 308 is connected as part of the voltage comparison circuit 30a, and the constant voltage source 34 or the ground voltage GND is connected to the capacitor 308 by the operation of the switch group 35.

[0032] More specifically, when the adjustment signal Offset Enable is on, the capacitor (offset capacitor) 308 is connected in parallel with the capacitor 301 in front of the inverter 302 as part of the voltage comparison circuit 30a. The constant voltage source 34 generates a predetermined constant voltage that serves as the offset voltage. The switches 351 and 352 constituting the switch group 35 switch the input terminal of the offset capacitor 308 between a voltage Vofs based on the constant voltage source 34 and a ground voltage GND based on the on / off state of the sampling signal SW_SAMP_A and the standby signal SW_OFFSET_A. In this case, the voltage comparison circuit 30a compares a value having an offset from the GND level with the detection voltage Vsns and outputs the comparison result. In this way, the constant voltage source 34 that generates the offset level is selectively used depending on the state of the adjustment signal Offset Enable.

[0033] As shown in FIG. 2 and FIG. 4 described later, when the switch 32 is turned off by the adjustment signal Offset Enable, the current zero point detection unit 13 switches internal switches 311, 312, 306, and 307 on and off by a sampling signal SW_SAMP_A used during zero point detection of the current and a standby signal SW_OFFSET_A used during the current detection standby period during the current monitoring period.

[0034] In the current zero point detection unit 13, during the period in which the sampling signal SW_SAMP_A is input, the inverters 302, 304, and 305 functioning as comparators compare the voltages stored in the capacitors 301 and 303 with the ground voltage. If the detection voltage Vsns is smaller than 0, the zero point output Zero detection becomes H at the timing when the sampling signal SW_SAMP_A is input. Details of the behavior of the current zero point detection unit 13 will be described in detail with reference to Figs. 4 to 6.

[0035] Then, the latch processing unit 33 sets the state notification signal Zero_det_latch, which is a latch output signal and a continuous signal, to H at the timing when the sampling signal SW_SAMP_A falls to L, and maintains the H state until the next sampling signal SW_SAMP_A falls, and captures the state of the zero point output Zero detection again at the timing of the falling edge of this sampling signal SW_SAMP_A. If the zero point output Zero detection is H, the output state notification signal Zero_det_latch remains H, and if Vsns becomes larger than 0 and Zero detection is L, the output state notification signal Zero_det_latch switches to L and maintains the state until the next sampling signal SW_SAMP_A falls. This operation is repeated for a predetermined current monitoring period. Details of the behavior of the current zero point detection unit 13 will be described later with reference to Figs. 8 and 10.

[0036] With this structure, the zero current point detection unit 13 converts the motor current state into a continuous state notification signal Zero_det_latch during the current monitoring period, rather than a signal that is discretely generated by PWM. This makes it possible to recognize the end of the detection state, which corresponds to the falling edge of the state notification signal Zero_det_latch that notifies the state of the drive current, as the timing when the current starts to flow in the positive direction from zero, without being influenced by the on / off operation of PWM.

[0037] In addition, the phase adjustment unit 14 adjusts the phase of the target position detection signal from the next period onwards of the reference position detection signal based on the output result of the current zero point detection unit 13 and the reference position detection signal FG or FG_offset, and outputs it as a lead angle position detection signal (Lead_angle FG, referred to as the LAFG signal below).

[0038] In detail, as shown in FIG. 2, the phase adjustment unit 14 has a phase switching counter 41, an in-cycle time counter 42, and an LAFG signal generation unit 43.

[0039] The phase switching counter 41 counts the number of phase switchings of the position detection signal (FG or FG_offset) output from the position detection signal generating unit 12 (in this example, the number of times the signal falls from H to L).

[0040] As an example, the phase adjustment (advance angle adjustment) of the drive current is performed every 16 phase changes of the FG signal during steady state rotation when the rotation is stable. Therefore, the phase change number counter 41 counts the number of phase changes k, and when it reaches the 15th time since the previous phase adjustment, it starts the counter of the in-cycle time counter 42 to start the current zero point detection unit 13 and monitor the current zero point.

[0041] The in-period time counter 42 starts the time counter so as to monitor the current zero point near the phase switching point of the FG signal before the phase adjustment. The in-period time counter 42 counts the time within a half period T of the immediately preceding FG signal (or FG_offset signal), and when the time reaches T×(180°-θ) / 180°), starts the monitoring operation of the current zero point (current zero crossing point) and enters the current monitoring period.

[0042] During the current monitoring period, the in-cycle time counter 42 outputs a sampling signal SW_SAMP_A used during zero point detection of the current and a standby signal SW_OFFSET_A used during periods other than current detection to the current zero point detection unit 13. Then, when the time reaches half a cycle T×(180°+θ) / 180°, the current zero point monitoring operation is terminated. Here, θ is set to any value between 30° and 60°, for example.

[0043] The LAFG signal generating unit 43 outputs an LAFG signal, which is an FG signal obtained by adjusting (advancing or retarding) the phase of the FG signal or the FG_offset signal based on the detection result of the current zero point.

[0044] The output control unit / soft switch period generating unit 15 adjusts the timing at which the drive voltage is changed by controlling the PWM signal, that is, the voltage on / off timing, based on the LAFG signal.

[0045] Furthermore, the output control unit / soft switch period generating unit 15 internally generates a signal for indicating the period for soft switching the single-phase motor 5 based on the voltage generated internally and the position detection signal FG or FG_offset output from the position detection signal generating unit.

[0046] As a result, the output control unit / soft switch period generating unit 15 gradually changes the duty ratio just before the reciprocity point of the FG signal / or FG_offset. When the output voltage Vout is increased as in the period Ti in Fig. 7, the duty ratio is gradually increased, and when the output voltage Vout is decreased as in the period Td, the duty ratio is gradually decreased. Then, when the soft switch period ends, the duty ratio of the PWM signal becomes a predetermined value or becomes 0.

[0047] Then, the output control unit / soft switch period generation unit 15 generates control signals IN1H, IN2H, IN1L, and IN2L that are set to become soft switches that change stepwise between H and L when the drive voltage for switching each of the FETs M1, M2, M3, and M4 in the H-bridge circuit 2 is switched, and outputs the control signals to the gate driver 16.

[0048] The gate driver 16 controls each MOSFET in the H-bridge circuit 2 to vary the drive current Idr that drives the motor coil L of the single-phase motor 5. In detail, the gate driver 16 outputs gate control voltages GH1, GH2, GL1, and GL2 for turning on and off the gates of the FETs M1, M2, M3, and M4 in the H-bridge circuit 2, respectively.

[0049] Here, the flow of the drive current will be described with reference to Fig. 3. Fig. 3 is an explanatory diagram of the current flow in the H-bridge circuit 2 when the phase of the drive voltage is inverted. In Fig. 3, (a) shows the current flow when the first switches M1 and M4 are ON before the FG signal is switched, (b) shows the current flow when the second switches M2 and M3 are ON immediately after the switching, and (c) shows the current flow when the second switches M2 and M3 are ON a short time after the switching. Note that in Fig. 3, the single-phase motor 5 is shown as a coil L, but other elements of the single-phase motor such as a reverse voltage and a resistor are included but are not shown.

[0050] When the gate driver 16 generates a positive drive current Iout, for example, it turns off the second switches FETM2 and M3 and turns on the first switches FETM1 and M4 with a PWM signal. Then, while generating a positive drive voltage Vout, a drive current flows in the Idr1 direction through the motor coil L, and a positive detection voltage Vsns is generated across the detection resistor 3, as shown in FIG. 3(a).

[0051] For example, when a current flows through the motor coil L in the direction of Idr1, if the gate driver 16 switches the drive phase to turn off FETM1 and M4 and turn on FETM2 and M3, the direction of this current cannot be changed rapidly due to the characteristics of the coils, and the current continues to flow in the direction of Idr1, passing through FETM2 and M3, which are on. At this time, the drive voltage Vout becomes negative, but the drive current Iout is still positive.

[0052] Because of the direction of the current here, a negative current flows from the source side to the drain side of FETs M2 and M3 from GND via detection resistor 3. In other words, because current flows from the GND level in the direction of the arrow in Figure 3(b), a negative detection voltage Vsns is generated across detection resistor 3.

[0053] As time progresses, the direction of the current flowing through the coil L changes, and the current flows as shown in Figure 3(c). As a result, a drive current flows in the Idr2 direction through the motor coil L of the motor 5. At this time, the drive voltage Vout is negative, and the drive current Iout also becomes negative, causing a positive voltage Vsns to be generated across the detection resistor 3.

[0054] (Details of the behavior of the current zero point detection section) Here, the behavior of the zero current point detection unit 13 will be described in detail with reference to Fig. 4 to Fig. 6. Fig. 4 is a diagram showing the behavior of the zero current point detection unit 13 in different situations when the adjustment signal Offset Enable is off. Fig. 5 is an input / output characteristic diagram of an inverter included in the zero current detection unit 13. Fig. 6 is a diagram showing the behavior of the zero current point detection unit 13 in different situations when the adjustment signal Offset Enable is on.

[0055] First, the behavior of the zero current point detection unit 13 when the adjustment signal Offset Enable is off will be described with reference to Fig. 4 and Fig. 5. When the adjustment signal Offset Enable is off, the switch 32 is off, and the adjustment circuit, that is, the switch 32, the constant voltage source 34, the switch group 35, and the capacitor 308, are not used at all times, and therefore are omitted from Fig. 4.

[0056] 4(a), in the current zero point detection unit 13, first, with SW_OFFSET_A at H level and SW_SAMP_A at L level, the switch (FET) 312 is turned on, and one end of the capacitor 301 is biased to the GND level. In addition, when the switch 306 is turned on, the input and output of the inverter 302 become an intermediate potential Vth2 that is neither H nor L due to the inverter characteristics, and the other end of the capacitor 301 is charged up to the intermediate potential Vth2. Therefore, a charge equal to the difference between these potentials is stored in the capacitor 301 (Vc1=Vth2-0). Furthermore, when switch 307 is turned on, the input and output of inverter 304 become an intermediate potential Vth4 which is neither H nor L due to its characteristics, one end of capacitor 303 is biased with intermediate potential Vth2 generated by inverter 302, and the other end is biased with intermediate potential Vth4 generated by inverter 304, and a charge equal to the difference between them is stored in capacitor 303 (Vc3=Vth4-Vth2). Through the above operation, the offset voltages (Vc1, Vc3) stored and generated in capacitors 301, 303 when the GND level is used as a reference become the reference for the operating points of inverters 302, 304.

[0057] Here, the inverter threshold value in the zero current detection unit will be explained with reference to Fig. 5. Fig. 5 is a diagram showing the input / output characteristics of inverters 302 and 304 included in the zero current detection unit. Here, it is assumed that the characteristics of the two inverters are slightly different, and in Fig. 5, the input / output characteristics of the first-stage inverter 302 are shown by a dashed line, and the input / output characteristics of the second-stage inverter 304 are shown by a solid line.

[0058] In the voltage comparison circuit 30, it is necessary to detect the level difference of the first-stage input voltage (Vsns-GND) to a very small level. Therefore, in the first-stage inverter 302, (Vsns-GND(0)) is amplified to (302_OUT-Vth2). Even if the characteristics are further deviated, due to the effect of the input capacitor 303, the intermediate potential Vth4 is added to 302_OUT-Vth2 and input to the second-stage inverter 304. It is then amplified by the inverter 304 to become 304_OUT, which is at a level very close to the H level. When amplified to this extent, it can be seen that the output of the third-stage inverter 305 becomes the so-called "L level" due to the input 305_IN (=304_OUT) of the third-stage inverter 305.

[0059] In this way, the purpose of the three-stage inverter is to amplify the signal level, and the input capacitors 301 and 303 can add the input voltage level of the inverter based on the threshold level of the inverter without being affected by the characteristics of the inverter. In this way, even a small voltage level of the detection voltage Vsns can ultimately be output as a binary value, H / L.

[0060] More specifically, as shown in Fig. 4(a), after a charge equivalent to the offset voltage is stored in the capacitors 303 and 304, when the standby signal SW_OFFSET_A switches to the L level and the sampling signal SW_SAMP_A switches to the H level, the switch (FET) 312 turns off and the switch 311 turns on, as shown in Fig. 4(b), so that one end of the capacitor 301 is biased to the detection voltage Vsns. When the potential of the detection voltage Vsns is higher than the GND level as in the states of Fig. 3(a) and Fig. 3(c), the voltage of the other end of the capacitor 301 rises from the intermediate potential by the potential of Vsns in accordance with the offset voltage stored in the capacitor 301 (Vth2+Vsns).

[0061] 4(b), the switches 306 and 307 are off, so that the inverters 302 and 304 operate purely as inverters. When the potential of the detection voltage Vsns is higher than the GND level, the input voltage of the inverter 302 rises from the intermediate potential Vth2 by the potential of Vsns as described above, so that it becomes higher than the phase switching point of the inverter 302, the input becomes H, the output of the inverter 302 transitions to L, and the inverter 302 outputs the output voltage 302_OUT shown in FIG. In the next capacitor 303, in addition to the original intermediate potential Vth4, a potential equivalent to (302_OUT-Vth2) is stored in accordance with the output voltage of the inverter 302 (Vc3=Vth4-(302_OUT-Vth2)). Therefore, as shown in Fig. 5, the input to the inverter 304 becomes smaller than the phase switching point and becomes L, causing the output of the inverter 304 to become H. Also, the next-stage inverter 305 behaves in an opposite manner to the inverter 304, and when the input to the inverter 305 becomes H, the output of the inverter 305, i.e., the Zero_detection signal, becomes L.

[0062] On the other hand, when the potential of the detection voltage Vsns is lower than the GND level as in the state of Fig. 3(b), the voltage at the other end of the capacitor 301 decreases by the potential of Vsns from the intermediate potential Vth2 according to the offset voltage stored in the capacitor 301 (Vc1=Vth2-Vsns) as shown in Fig. 4(c). Then, the input of the inverter 302 becomes L, and the output transitions to H. Thereafter, the capacitor 303, the switch 307, and the inverter 304 perform the same operation as above, and the input of the inverter 304 becomes H, causing the output to become L, and further, the input of the inverter 305 becomes L, causing the output of the inverter 305, i.e., the Zero_detection signal, to become H.

[0063] The Zero_detection signal output from the voltage comparison circuit 30 is input to the latch processing unit 33, and the latch processing unit 33 outputs a continuous state notification signal Zero_det_latch that switches between H and L only when the H and L levels of the Zero_detection signal change between the previous and next on periods of the switch 311 that inputs the detection voltage Vsns (see Figure 8).

[0064] In this way, the current zero point detection unit 13 detects when the drive current reaches the zero point by detecting the timing when the voltage Vsns corresponding to the output current Iout switches from zero or a negative value to a positive value, and notifies the user of this by the timing when the state notification signal Zero_det_latch changes from H to L.

[0065] Furthermore, the behavior of the zero current point detection unit 13 when the adjustment signal Offset Enable is on will be described with reference to Fig. 6. The adjustment circuit in Fig. 6 shows a schematic example in which a standby signal SW_OFFSET_A is input to a switch 351 and a sampling signal SW_SAMP_A is input to a switch 352 in order to set a positive offset. Thus, in the case where the switch 32 is on by the adjustment signal Offset Enable, the zero current point detection unit 13 switches on and off the internal switches 311, 312, 306, 307 and the switches 351, 352 by the sampling signal SW_SAMP_A used during detection of the zero current point and the signal SW_OFFSET_A used during the current detection standby period during the current monitoring period.

[0066] 6(a), in the current zero point detection unit 13, first, with SW_OFFSET_A at H level and SW_SAMP_A at L level, the switch (FET) 312 is turned on and the switch 352 in the adjustment circuit is turned on. As a result, a voltage (voltage based on the constant voltage source) Vofs, which is grounded via a resistor 342 from the constant voltage VDD generated by the constant voltage source 34, is biased to one end of the capacitor 308. On the other hand, the other end of the capacitor 308 becomes the voltage of the intermediate potential Vth2 of the connection destination, and the difference is stored in the capacitor 308 (Vc8=Vth2-Vofs). In addition, in this state, since capacitors 301 and 308 are connected in parallel to inverter 302, the offset voltage (Vc1) stored and generated in capacitor 301 when the GND level is used as the reference is compared with the offset voltage (Vc8) stored and generated in capacitor 301 when the GND level is used as the reference, and the voltage adjusted by charging and discharging becomes the reference for the operating point of inverter 302.

[0067] In this way, after the charge equivalent to the offset voltage is stored in the capacitors 303, 304, and 308, the standby signal SW_OFFSET_A switches to the L level and the sampling signal SW_SAMP_A switches to the H level, and as shown in Fig. 6(b), the switch (FET) 312 switches off and the switch 311 switches on, biasing one end of the capacitor 301 to the detection voltage Vsns. Furthermore, as shown in Fig. 6(b), the switch 351 switches on, discharging from the capacitor 301 to the capacitor 308, and if the capacitance of the capacitor 308 is 1 / 20 of that of the capacitor 301, the input voltage of the inverter 302 becomes [Vth2-Vofs / 20+Vsns].

[0068] Here, when the potential of the detection voltage Vsns is higher than the GND level as in the states of FIGS. 3(a) and 3(c), the detection voltage Vsns is further compared with the offset voltage Vofs / 20. When the detection voltage Vsns is greater than the positive offset voltage Vofs / 20, Vth2 - Vofs / 20+(Vsns(+))>Vth2, the input of the inverter 302 becomes H, and the output of the inverter 302 shifts to L. Thereafter, the capacitor 303, the switch 307, and the inverter 304 also perform the same operations as described above. At the inverter 304, the input becomes L, so the output becomes H. Further, when the input of the inverter 305 becomes H, the output of the inverter 305, that is, the Zero_detection signal, becomes L.

[0069] On the other hand, when comparing the detection voltage Vsns with the offset voltage Vofs / 20 and the positive detection voltage (Vsns) is smaller than the positive offset voltage Vofs / 20, Vth2 - Vofs / 20+(Vsns(+))<Vth2, the input of the inverter 302 becomes L, and the output of the inverter 302 shifts to H. Thereafter, the capacitor 303, the switch 307, and the inverter 304 also perform the same operations as described above. At the inverter 304, the input becomes H, so the output becomes L. Further, when the input of the inverter 305 becomes L, the output of the inverter 305, that is, the Zero_detection signal, becomes H.

[0070] Also, when the detection voltage Vsns is a negative value as in the state of FIG. 3(b), without even comparing with Vofs / 20 as shown in FIG. 6(c), Vth2 - Vofs / 20+(Vsns(-))<Vth2, so the input of the inverter 302 becomes L, and the output of the inverter 302 shifts to H. Thereafter, the capacitor 303, the switch 307, and the inverter 304 also perform the same operations as described above. At the inverter 304, the input becomes H, so the output becomes L. Further, when the input of the inverter 305 becomes L, the output of the inverter 305, that is, the Zero_detection signal, becomes H.

[0071] In this way, by connecting the adjustment circuit including the constant voltage source 34 by the adjustment signal Offset Enable, it is possible to offset the threshold level of the inverter 302 in the voltage comparison circuit from the GND level. That is, in the example shown in Fig. 6, the zero point of the detection voltage Vsns simply shifts from the GND level by a positive level of Vofs / 20.

[0072] In addition, in FIG. 6, the standby signal SW_OFFSET_A is input to the switch 351 and the sampling signal SW_SAMP_A is input to the switch 352, thereby shifting the zero point of the detection voltage Vsns from the GND level by a positive Vofs / 20 level. However, as shown in parentheses in FIG. 2, by inputting the standby signal SW_OFFSET_A to the switch 352 and inputting the sampling signal SW_SAMP_A to the switch 351, the zero point of the detection voltage Vsns can be shifted from the GND level by a negative Vofs / 20 level.

[0073] The offset generation by such an additional adjustment circuit is turned on and off for the purpose of correcting a deviation between the GND level of the motor current zero point detection unit 13 and the GND level of the device (the entire motor drive device 4) when this deviation occurs due to, for example, differences in wiring impedance, or to prevent malfunction by providing an offset when false detection / malfunction occurs due to minute noise near the GND. Note that this adjustment function is turned on and off at timings other than the current monitoring period, without linking with the FG cycle.

[0074] (Comparative Example) FIG. 7 is a diagram illustrating the overall operation of a comparative example in which advance angle adjustment is not performed. In a BLDC motor, the drive current changes with a time delay with respect to the on / off switching of the drive voltage due to the coil characteristics (V=L*dI / dt). In the example of Figure 7, the zero point of the drive current Iout is delayed by time D from the zero point (zero crossing point) of the drive voltage Vout.

[0075] Here, to increase the motor's rotation speed, a larger current is required, and the larger the current, the greater the time delay. Thus, when the motor rotates at high speed, the phase of the drive current is shifted from the phase indicating the actual position of the motor detected by the Hall element, so the drive force is not sufficiently transmitted to torque, and even if the current is increased, the rotation speed does not increase proportionally as expected, resulting in a decrease in efficiency.

[0076] (Motion Control) Therefore, in the present invention, the timing of changing the drive voltage is adjusted based on the timing of the zero point of the detected actual current, thereby controlling so that the phase switching point of the position detection signal FG or FG_offset coincides with the zero crossing point of the drive current.

[0077] Here, with reference to the operation diagram of FIG. 8 and the flowcharts of FIG. 9 and FIG. 10, a case where advance angle control is performed every 16 phase changes will be described as an example of control in the present invention. FIG. 8 is an explanatory diagram of signal operation during steady rotation in a motor drive control device. FIG. 9 is a schematic flowchart of control during steady rotation according to one embodiment of the present invention. FIG. 10 is a detailed flowchart of current zero point detection during steady rotation according to one embodiment of the present invention. As described above, in the present invention, the current zero point in the actual drive current is detected and controlled to match the rotor position detection signal.

[0078] 8, 9, and 10 show behavior during steady rotation (high speed rotation). The rotor position detection signal that is the target position during high speed rotation is the FG_offset signal.

[0079] FIG. 8 shows an example in which one step (predetermined amount) of the advance angle control corresponds to one period of the PWM signal and is 1 / 1024 (≈0.35 deg) of one period of the FG signal.

[0080] When the lead angle adjustment in FIG. 9 is started, first in step S101, the LAFG signal generating unit 43 sets the LAFG signal (Lead_angle FG) to the same phase as the FG_offset signal.

[0081] Then, when a phase switch occurs in the FG_offset signal in S102, the phase switch counter 41 adds 1 to the number k of phase switches of the FG_offset signal (S103).

[0082] No current zero point detection or advance angle adjustment is performed until the number of phase changes k reaches 15 (No in S104). After repeating S102 and S103, when the number of phase changes k reaches 15 (Yes in S104), the process proceeds to the next step, and the in-period time counter 42 starts counting the time within the half period T of the FG_offset signal (S105).

[0083] When the in-period time counter 42 counts up to a time of half a period T×(180°-θ) / 180° (S106), the current starts to be monitored and the current zero point detection operation is started (S107). Details of the zero current detection will be described later with reference to FIG. 10. In the operation diagram of FIG. 8, an example is shown in which the start angle of the current zero point detection operation is −45° of the phase switching of the FG_offset signal.

[0084] Thereafter, when the in-period time counter 42 counts up to a half-period T×(180°+θ) / 180°, it is determined that the current monitoring period has ended, and the current zero point monitoring operation is terminated (S108). In the operation diagram of FIG. 8, an example is shown in which the end angle of the current zero point detection operation (current monitoring period) is +44.65° of the phase switching of the FG_offset signal.

[0085] Here, in parallel with the current zero point detection process, the drive voltage drops with a gradient in accordance with the phase switching of the FG_offset signal, and the phase of the drive current also switches accordingly (S109). When the number of phase switching times k of the FG_offset signal becomes 16, the number of phase switching times k of the FG_offset signal is reset to 0 (S110).

[0086] Thereafter, the process proceeds to the FG phase adjustment (advance angle adjustment) steps S111 to S117.

[0087] First, between S106 and S108, the LAFG signal generating unit 43 checks whether a zero current point has been detected as shown in FIG. 8, that is, whether the output state notification signal Zero_det_latch has ever become H (detection state) within the current monitoring period (S111).

[0088] If the current zero point is not detected (No in S111), it is determined that the phase of the drive current is significantly delayed with respect to the current monitoring period, and the phase of LAFG is advanced one step forward (S114). Note that one step when advancing or advancing the phase of LAFG in the next period corresponds to one period of the PWM signal and is significantly shorter than the current monitoring period in the FG_offset signal, for example, 0.35 deg.

[0089] If the current zero point is detected (Yes in S111), it is confirmed whether the falling edge of the state notification signal Zero_det_latch (end of the detection state) is detected.

[0090] If the falling edge of the status notification signal Zero_det_latch is not detected (No in S112), this means that the end point of the current monitoring period is within the period in which the status notification signal Zero_det_latch holds H, so it is determined that the phase of the drive current is significantly delayed relative to the current monitoring period, and the phase of LAFG is advanced one step forward (S114).

[0091] When a falling edge of the state notification signal Zero_det_latch is detected (Yes in S112), the timing of the falling edge is compared with the timing of phase switching of k=16 of the FG_offset signal (S113).

[0092] If the falling timing of the state notification signal Zero_det_latch is after the phase switching timing of the FG_offset signal (Yes in S113), the phase of LAFG is advanced by one step (S114).

[0093] If the falling timing of the state notification signal Zero_det_latch precedes the phase switching timing of the FG_offset signal (No in S113), the phase of LAFG is delayed by one step (S115).

[0094] The timing of switching the LAFG for the next cycle of the FG_offset signal is determined by steps S111 to S115, and the timing at which the voltage changes is adjusted by controlling the drive voltage generated by the output control unit / soft switch period generation unit 15 and the gate driver 16 in accordance with the timing of switching the LAFG (S116).

[0095] Here, the detection of the current zero point during the current monitoring period will be described in detail with reference to FIG.

[0096] When the in-period time counter 42 counts up to a half period T×(180°-θ) / 180° (S107 in FIG. 9), it starts to monitor the current and starts the current zero point detection operation (START).

[0097] First, the state notification signal Zero_det_latch is reset to L (S201).

[0098] Just before the drive PWM signal is turned on, the standby signal SW_OFFSET_A is turned off (S202), and when the drive PWM signal (1N1H that drives M1) is turned on at the timing of the PWM cycle (S203), the sampling signal SW_SAMP_A is simultaneously turned on (S204).

[0099] In the soft switch, the on-period is controlled to gradually shorten in the PWM cycle as it approaches 0, but if there is a portion in the current monitoring period where the on-period of the drive PWM signal is t (1.0 μs) or less (Yes in S205), the on-period is set to be longer than t (1.0 μs) (S206). Figure 8 shows an example where the minimum value of the PWM on-period is set to 1.1 μs and t = 1.0 μs.

[0100] If all of the on periods of the drive PWM signals are longer than t (1.0 μs) (No in S205), no adjustment is required and the process proceeds to the next step.

[0101] After that, when the sampling signal SW_SAMP_A is turned on, the detection voltage Vsns is monitored for a predetermined period t (1.0 μs) (S207).

[0102] Then, the monitor result of the detection voltage Vsns is output to the latch processing unit 33 as a zero point output Zero detection (S208).

[0103] Then, the latch processing unit 33 samples the zero point output Zero detection after a predetermined period t (1.0 μs) has elapsed since the sampling signal SW_SAMP_A was turned on (S209).

[0104] As a result of sampling, if the zero point output Zero detection input to the latch processing unit 33 is H during the on period of the sampling signal SW_SAMP_A (Yes in S210), that is, if the detection voltage Vsns is negative at the timing of sampling by SW_SAMP_A, the output voltage Vout<0 and the output current Iout≧0 are assumed to be in a state, and the state notification signal Zero_det_latch is set to H (detection state) (S211).

[0105] On the other hand, if the zero point output Zero detection input to the latch processing unit 33 is L during the on period of the sampling signal SW_SAMP_A (Yes in S210), that is, if a period during which the detection voltage Vsns is negative is not detected at the timing of sampling by SW_SAMP_A, the state notification signal Zero_det_latch is set to L. At this time, if the state notification signal Zero_det_latch has not risen, the L state is maintained. On the other hand, if the state notification signal Zero_det_latch has risen in the previous PWM period, it is determined that the output voltage Vout<0 and the output current Iout<0 have occurred and the current has fallen below the zero point, so the state notification signal Zero_det_latch is lowered and the detection state is terminated (S212).

[0106] Then, the state of the state notification signal Zero_det_latch is maintained (S213).

[0107] Meanwhile, in parallel with the high / low switching operation of the state notification signal in S210 to S213, when the PWM off period arrives in S214, the sampling signal SW_SAMP_A is turned off and the standby signal SW_OFFSET_A is turned on (S215).

[0108] Then, the process waits for the next drive PWM ON period (S216), and if it is within the current monitoring period (No in S217), the process returns to before S202 and repeats the operation of detecting the current zero point for each PWM period.

[0109] On the other hand, when the in-period time counter 42 counts up to the time of half the period T×(180°+θ) / 180°) (Yes in S217), the current monitoring is stopped and the current monitoring period ends (END).

[0110] Although the behavior during steady rotation when the rotation is stable has been explained in the above FIGS. 8, 9, and 10, phase control (advance angle control) of the drive current can also be executed in cases other than the stable rotation state.

[0111] In the example of Fig. 8, the FG_offset signal has a phase that is earlier than that of the FG signal. The phase shift of the drive current with respect to the phase of the rotor BEMF detected by the position detection signal of the Hall element 6 is larger during high-speed rotation than during startup. For this reason, it is preferable to switch so that the original FG signal is used as the reference signal during soft start, which is when power is started, and the FG_offset signal is used as the reference signal during high-speed rotation.

[0112] In detail, when starting up or restarting after the motor locks up, the PWM input, which is the speed control input, changes and the speed fluctuates, so output phase switching (advance angle control) is performed according to the FG signal. In this case, during the period of rotation fluctuation until the rotation stabilizes, it is preferable to perform phase adjustment more frequently than when the rotation is stable, for example, every two periods of the FG signal.

[0113] During startup and restart, when detecting the zero current point during the current monitoring period, the sampling signal SW_SAMP_A is turned on at the same time as the drive PWM signal (IN2H that drives M2) is turned on according to the control of FIG. 10, which is different from the steady rotation period.

[0114] (Current after advance angle adjustment) FIG. 11 is a diagram for explaining the overall operation when advance angle adjustment of the present invention is performed.

[0115] 11, as described above, the timing of the change in the drive voltage is slightly advanced by adjusting the advance angle of the LAFG signal in the next period based on the result of detecting the zero-cross point of the current at the immediately preceding phase change of the FG_offset signal. As a result, the zero-cross point of the current Iout, which is slightly delayed from the change in the output voltage Vout, exactly matches the phase change (falling edge) of the FG_offset signal.

[0116] In this way, when the motor rotates at high speed, the phase of the drive current matches the phase of the Hall signal indicating the actual position of the motor, so that the drive force is sufficiently transmitted to torque, and when the current is increased, the rotation speed increases proportionally as expected, improving efficiency. Therefore, the motor control circuit of the present invention improves the efficiency of a single-phase motor at high speed, allowing it to rotate at a sufficiently high speed with a specified amount of current, and to rotate with less current at the same rotation speed.

[0117] (Variation 1) In the above example, the phase reversal point at which the position detection signal (FG or FG_offset) falls from H to L is detected as the detection timing for phase switching, but the phase switching may be detected by detecting the phase reversal point at which the position detection signal rises from L to H. In this case, the timing of the transition from negative to positive, which corresponds to the time when the position detection signal rises from L to H, is monitored and detected as the zero point detection of the current.

[0118] (Variation 2) In FIG. 1, a configuration has been described in which FETs are used as the switches of the H-bridge circuit, but the switches of the H-bridge may be configured with bipolar transistors.

[0119] (Variation 3) Furthermore, the motor control circuit of the present invention is applicable to a BLDC motor with not only a 1-channel H-bridge but also a 1.5-channel H-bridge (three half-bridges).

[0120] Although preferred embodiments have been described above in detail, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0121] This application claims priority based on Japanese Patent Application No. 2023-112642, filed on July 7, 2023, the entire contents of which are incorporated by reference into this international application. [Explanation of symbols]

[0122] 1 Motor control IC 2 H-bridge circuit (motor drive section) 3 Detect resistor 4. Motor drive control device 5 Single-phase motor (brushless DC motor) 6 Hall element 10 Control circuit (motor control circuit) 11 PWM signal generation section 12 Position detection signal generator 13 Current zero point detection section 14 Phase adjustment section 15 Output control section / soft switch period generation section 16 Gate Drivers 17 Drive control unit 30, 30a Voltage comparison circuit 301, 303 Capacitor 302, 304, 305 Inverter 306, 307 Switch 308 Capacitor (Offset Capacitor) 31 Switches 311, 312 Switches 32 Switch 34 Constant current source 35 Switches 351, 352 Switch L coil M1 PchFET (first upper switch, first switch) M2 PchFET (second upper switch, second switch) M3 NchFET (second lower switch, second switch) M4 NchFET (first lower switch, first switch) Idr Drive current FG Position detection signal that matches the hall signal (reference position detection signal) FG_offset Position detection signal with phase advance (reference position detection signal) LAFG (Lead_angleFG) Target position detection signal (lead-angle adjusted position detection signal) Vsns Detection voltage (voltage associated with the drive current) Zero_det_latch status notification signal SW_SAMP_A Sampling signal (one of two types of signals) SW_OFFSET_A standby signal (one of two types of signals) Offset Enable adjustment signal

Claims

1. A motor control circuit that supplies a drive voltage to a brushless DC motor via a motor drive unit, a current zero point detection unit that detects a voltage corresponding to a drive current flowing through a coil of the motor and detects a timing at which the drive current becomes zero; a position detection signal generating unit that outputs a reference position detection signal based on a hall signal generated by the hall element; a phase adjustment unit that adjusts a phase of a target position detection signal from a next period onward of the reference position detection signal, based on the timing at which the drive current becomes zero, detected by the current zero point detection unit, and the reference position detection signal; a drive control unit that controls and outputs the timing of switching the drive voltage so as to coincide with the phase switching point of the target position detection signal. Motor control circuit.

2. the current zero point detection unit is connected to the motor drive unit together with a grounded resistor, The current zero point detection unit detects when the drive current reaches the zero point by detecting a timing at which a detection voltage corresponding to the drive current switches from zero or a negative value to a positive value.

2. The motor control circuit of claim 1.

3. The current zero point detection unit monitors the drive current during a current monitoring period that is an angular period before and after a phase switching point in the reference position detection signal.

3. The motor control circuit of claim 2.

4. Two types of signals are input to the current zero point detection unit, The current zero point detection unit is A voltage comparator circuit; a switch connected to an input terminal of the voltage comparison circuit, for switching an input voltage of the voltage comparison circuit between the detection voltage or a ground voltage in response to an on / off state of the signal; a latch processing unit that outputs a state notification signal that notifies a state of the drive current based on a comparison result of the voltage comparison circuit, The voltage comparison circuit includes: a capacitor to which the input voltage is input; An inverter connected to a downstream stage of the capacitor; and a switch for shorting the inverter during a period in which the ground voltage is input in response to states of the two types of signals; The voltage comparison circuit compares the ground voltage with the detection voltage and outputs a comparison result.

4. The motor control circuit according to claim 3.

5. The current zero point detection unit is an adjustment circuit connected via a switch that is turned on when an adjustment signal different from the two types of signals is on; The adjustment circuit includes: A constant voltage source for generating a constant voltage; an offset capacitor connected in parallel with the capacitor in a stage preceding the inverter of the voltage comparator; and a switch for switching a voltage input to one end of the offset capacitor between the ground voltage or the constant voltage depending on a state of the signal; The voltage comparator circuit compares the detected voltage with a value having an offset from the ground voltage, and outputs a comparison result.

5. The motor control circuit according to claim 4.

6. the motor driving unit is an H-bridge circuit including a first upper switch, a second upper switch, a first lower switch, and a second lower switch; a PWM generating unit that generates a PWM signal for switching between a state in which the first upper switch and the second upper switch are turned on and a state in which the first lower switch and the second lower switch are turned on in the H-bridge circuit, and outputs the PWM signal to the drive control unit; the current zero point detection unit generates a state notification signal for notifying a state of the drive current during the current monitoring period; The state notification signal goes into the detection state at the timing when the drive current becomes zero, and the state notification signal goes into the end of the detection state one PWM period after the drive current becomes zero.

4. The motor control circuit according to claim 3.

7. The phase adjustment unit, during the current monitoring period, When the end of the detection state of the state notification signal is later than the phase switching of the reference position detection signal, and when the detection state or the end of the detection state is not output, The phase of the target position detection signal is advanced by a specified amount.

7. The motor control circuit according to claim 6.

8. The phase adjustment unit delays the phase of the target position detection signal by a predetermined amount when the end of the detection state of the state notification signal occurs earlier than a phase change of the reference position detection signal during the current monitoring period.

7. The motor control circuit according to claim 6.

9. The phase adjustment unit makes the current zero point detection unit monitor the drive current at every predetermined number of phase switching points in the reference position detection signal, and adjusts the phase of the target position detection signal.

7. The motor control circuit according to claim 6.

10. The position detection signal generating unit outputs a position detection signal that matches the Hall signal generated by the Hall element as a reference during startup, and outputs a position detection signal that is advanced or delayed in phase from the Hall signal by a predetermined amount during steady rotation.

4. The motor control circuit according to claim 3.

11. The drive control unit includes a soft switch period generation unit that adjusts a pulse width of a PWM in a stepwise manner when switching the drive voltage, thereby making the switching of the drive voltage a soft switch with a gradient.

7. The motor control circuit according to claim 6.

12. The motor control circuit according to any one of claims 1 to 11 is a semiconductor integrated circuit that controls the motor drive unit. Motor control IC.

13. A motor drive control method for supplying a drive voltage to a brushless DC motor via a motor drive unit, comprising: a step of monitoring a voltage corresponding to a drive current flowing through a coil of the motor and detecting a timing at which the drive current becomes zero; outputting a reference position detection signal based on a Hall signal generated by the Hall element; adjusting a phase of a target position detection signal from a next period onward of the reference position detection signal based on the timing at which the detected drive current becomes zero and the reference position detection signal; and controlling a timing for changing the drive voltage so as to coincide with a phase switching point of the target position detection signal, and supplying the controlled drive voltage to the motor drive unit. A motor drive control method.

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