Printed circuit board

Abstract

To provide a printed circuit board capable of forming a capacitor with a desired size and capacity without constraints on design.SOLUTION: A printed circuit board 100A includes: a glass layer 110; a first wiring layer 120 arranged on an upper surface of the glass layer; and a capacitor 150 including a plurality of blind holes VH each of which penetrates a part of the glass layer from an upper surface to a lower surface of the glass layer, a first electrode layer 151 arranged on the upper surface of the glass layer and extending into each of the plurality of blind holes, a second electrode layer 152 arranged on the first electrode layer and filling each of the plurality of blind holes, and a first dielectric layer 153 arranged between the first electrode layer and the second electrode layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] Recently, packaging technology has been constantly evolving, and in particular, there have been attempts to use glass materials instead of organic materials, which are the traditional method for manufacturing substrates. In addition, in order to improve power characteristics, recent package substrates have adopted a structure in which passive elements such as chip capacitors and silicon capacitors are mounted on the outside of the substrate, or a through cavity or blind cavity is formed in the core of the substrate and then the passive elements such as chip capacitors and silicon capacitors are embedded. However, in this case, a mounting or embedding process of the passive elements must be added, and the cavity must be formed according to the size of the passive elements, which may cause design restrictions. In addition, the process may become more difficult when a large number of passive elements are mounted. Furthermore, if the substrate is thick, the cavity processing and embedding process may become more difficult. Summary of the Invention [Problem to be solved by the invention]

[0003] One of several objects of the present invention is to provide a printed circuit board on which a capacitor of a desired size and capacitance can be formed without design constraints.

[0004] Another of several objects of the present invention is to provide a printed circuit board which can omit the steps of cavity processing and filling.

[0005] It is yet another object of the present invention to provide a printed circuit board that can have a better effect in terms of distribution of insulation thickness. [Means for solving the problem]

[0006] One of the solutions proposed in the present invention is to form the wiring layers, through vias and capacitors directly on the glass core.

[0007] For example, one example of a printed circuit board may include a glass layer, a first wiring layer disposed on an upper surface of the glass layer, a capacitor including a plurality of blind holes each penetrating a portion of the glass layer from the upper surface to the lower surface of the glass layer, a first electrode layer disposed on the upper surface of the glass layer and extending into each of the plurality of blind holes, a second electrode layer disposed on the first electrode layer and filling each of the plurality of blind holes, and a first dielectric layer disposed between the first and second electrode layers.

[0008] Alternatively, one example of a printed circuit board may include a glass layer, a through hole penetrating the glass layer from a top surface to a bottom surface of the glass layer, a plurality of blind holes each penetrating a portion of the glass layer from the top surface to the bottom surface of the glass layer, a first conductor layer disposed on the top and bottom surfaces of the glass layer and extending onto a wall surface of the through hole and each of the wall surfaces and bottom surfaces of the plurality of blind holes, a third conductor layer disposed on the first conductor layer and filling the through hole and each of the plurality of blind holes, and a dielectric layer disposed between the first and third conductor layers on the top surface of the glass layer, the wall surface of the through hole, and each of the wall surfaces and bottom surfaces of the plurality of blind holes. Effect of the Invention

[0009] Among the various advantages of the present invention, one advantage is that it provides a printed circuit board on which a capacitor of a desired size and capacitance can be formed without design restrictions.

[0010] Among the various effects of the present invention, another effect is that it is possible to provide a printed circuit board that can omit the steps of cavity processing and filling.

[0011] Among the various advantages of the present invention, still another advantage is that it provides a printed circuit board that has a superior effect in terms of distribution of insulation thickness. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] FIG. 1 is a perspective view illustrating an example of a printed circuit board. [Figure 4] FIG. 4 is a plan view illustrating a schematic top view of the printed circuit board of FIG. [Figure 5a] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5b] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5c] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5d] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5e] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5f] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5g] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5h] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5i] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5j] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5k] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5l] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5m] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5n] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 6] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0014] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0015] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also connected to other electronic components described below to form various signal lines 1090.

[0016] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, the chip-related components 1020 may include other types of chip-related electronic components. Needless to say, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0017] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020 and with each other.

[0018] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may also include passive elements in the form of chip components used for various other different applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0019] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. The other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Needless to say, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0020] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0021] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0022] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components such as a camera module 1130 and / or a speaker 1140 that may or may not be physically and / or electrically connected to the motherboard 1110 are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built-in. Meanwhile, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0023] Printed Circuit Board FIG. 3 is a perspective view that illustrates an example of a printed circuit board, and FIG. 4 is a plan view that illustrates a top view of the printed circuit board of FIG.

[0024] Referring to the drawings, an example printed circuit board 100A may include a glass layer 110, a first wiring layer 120 arranged on an upper surface of the glass layer 110, a second wiring layer 130 arranged on a lower surface of the glass layer 110, a through via 140 penetrating the glass layer 1110 and connecting at least a portion of each of the first and second wiring layers 120, 130, and a capacitor 150 arranged on the upper surface of the glass layer 110 and penetrating at least a portion of the glass layer 110.

[0025] The first wiring layer 120 can include a first seed layer 121 disposed on the upper surface of the glass layer 110, and a first metal layer 122 disposed on the upper surface of the first seed layer 121. The second wiring layer 130 can include a second seed layer 131 disposed on the lower surface of the glass layer 110, and a second metal layer 132 disposed on the lower surface of the second seed layer 131. The through via 140 can include a through hole TH penetrating the glass layer 110 from the upper surface to the lower surface of the glass layer 110, a third seed layer 141 disposed on the wall surface of the through hole TH, a second dielectric layer 143 disposed on the third seed layer 141, a fourth seed layer 145 disposed on the second dielectric layer 143, and a third metal layer 142 disposed on the fourth seed layer 145 and filling the through hole TH. The capacitor 150 may include a plurality of blind holes VH each penetrating a portion of the glass layer 110 from the upper surface to the lower surface of the glass layer 110, a first electrode layer 151 disposed on the upper surface of the glass layer 110 and extending into each of the blind holes VH, a second electrode layer 152 disposed on the first electrode layer 151 and filling each of the blind holes VH, and a first dielectric layer 153 disposed between the first and second electrode layers 151 and 152. The second electrode layer 152 may include a fifth seed layer 152-1 disposed on the first dielectric layer 153, and a fourth metal layer 152-2 disposed on the fifth seed layer 152-1 and filling each of the blind holes VH.

[0026] The first to third seed layers 121, 131, 141 may contain the same metal as the first electrode layer 151. For example, the first to third seed layers 121, 131, 141 and the first electrode layer 151 may be formed by electroless plating such as chemical copper plating. For example, the first to third seed layers 121, 131, 141 and the first electrode layer 151 may be the first conductor layer M1. Since the first to third seed layers 121, 131, 141 may be formed by a single plating process, there may be no boundary between the first and second seed layers 121, 131 and the third seed layer 141. That is, they may be formed integrally with each other. The fourth and fifth seed layers 145, 152-1 may contain the same metal as each other. For example, the fourth and fifth seed layers 145, 152-1 may be formed by electroless plating such as chemical copper plating. The fourth and fifth seed layers 145 and 152-1 may be formed in a single plating process. For example, the fourth and fifth seed layers 145 and 152-1 may be the second conductor layer M2.

[0027] The first to fourth metal layers 122, 132, 142, 152-2 may each include the same metal. For example, the first to fourth metal layers 122, 132, 142, 152-2 may be formed by electrolytic plating such as copper electroplating. For example, the first to fourth metal layers 122, 132, 142, 152-2 may be the third conductor layer M3. Since the first and second metal layers 122, 132 and the third metal layer 142 may be formed by two plating processes, there may be a boundary between each of the first and second metal layers 122, 132 and the third metal layer 142. For example, the third and fourth metal layers 142, 152-2 may be the 3-1 conductor layer M3-1, which is disposed on at least a portion of the first conductor layer M1 and may fill each of the through holes TH and the blind holes VH. In addition, the first and second metal layers 122 and 132 may be a 3-2 conductor layer M3-2, which is disposed on at least another part of the first conductor layer M1 and covers the part of the 3-1 conductor layer M3-1 that fills the through hole TH. The 3-1 and 3-2 conductor layers M3-1 and M3-2 may have a boundary at the connection portion.

[0028] The first and second dielectric layers 153, 143 may include the same insulating material. For example, the first and second dielectric layers 153, 143 may be formed in the same coating process. For example, the first and second dielectric layers 153, 143 may be simultaneously formed in one coating process. For example, the dielectric layer D may include the first and second dielectric layers 153, 143. Thus, the first and second dielectric layers 153, 143 may have substantially the same thickness.

[0029] At least a portion of each of the fourth seed layer 145 and the third metal layer 142 may further protrude upward from each of the third seed layer 141 and the second dielectric layer 143. At least another portion of each of the fourth seed layer 145 and the third metal layer 142 may further protrude downward from each of the third seed layer 141 and the second dielectric layer 143. The protruding thickness of each of the fourth seed layer 145 and the third metal layer 142 may be substantially the same as the thickness of each of the first and second dielectric layers 153, 143.

[0030] On the upper surface of the glass layer 110, the first wiring layer 120, the first electrode layer 151, and the second electrode layer 152 may have different thicknesses. More specifically, on the upper surface of the glass layer 110, the first wiring layer 120 may be thicker than the first and second electrode layers 151 and 152, and the second electrode layer 152 may be thicker than the first electrode layer 151. For example, on the upper surface of the glass layer 110, the first seed layer 121 may have substantially the same thickness as the first electrode layer 151, and the first metal layer 122 may be thicker than the second electrode layer 152. For example, on the upper surface of the glass layer 110, the 3-2 conductor layer M3-2 may be thicker than the 3-1 conductor layer M3-1. For example, the upper surface of the first wiring layer 120 may be disposed at a different level from the upper surface of the second electrode layer 152. For example, the upper surface of the first wiring layer 120 may be disposed higher than the upper surface of the second electrode layer 152 .

[0031] At least a portion of the first electrode layer 151 on the upper surface of the glass layer 110 may extend in the horizontal direction so as not to be covered by the second electrode layer 152. For example, at least another portion of the first conductor layer M1 on the upper surface of the glass layer 110 may extend in the horizontal direction so as not to be covered by the 3-1 conductor layer M3-1. On the upper surface of the glass layer 110, the first electrode layer 151, the second electrode layer 152, and the first dielectric layer 153 may have a step structure.

[0032] The printed circuit board 100A having such a structure has various advantages when using a glass material instead of an organic material including the glass layer 110 as a core layer. In addition, in the case of a board including a silicon core layer, even if the board structure has a capacitor embedded therein, a circuit can be formed only on the cross section, and an insulating material must be added between the silicon and the metal in the case of a capacitor built in the core layer. In contrast, the printed circuit board 100A according to the example including a glass core layer allows a double-sided circuit to be formed, and furthermore, since the glass itself can perform an insulating function, the formation of an additional insulating material can be omitted in the capacitor built in the core layer. In other words, the number of layers can be reduced.

[0033] In addition, the printed circuit board 100A having such a structure can directly form the first and second wiring layers 120 and 130, the through via 140, and the capacitor 150 on the glass layer 110, so that a capacitor of a desired size and capacity can be formed without design restrictions, and fine circuits can be formed more easily. In addition, the cavity processing and embedding process for embedding the capacitor can be omitted, and in this case, since there is no cavity that occupies an asymmetric volume when embedding, it can have a better effect in terms of dispersion of insulation thickness. In addition, since the printed circuit board 100A according to an example can include a fine circuit and a capacitor, it can be used as a glass interposer mounted and disposed on a FCB (Flip Chip Bonding) board or a BGA (Ball Grid Array) board, and in this case, a plurality of semiconductor chips may be mounted and disposed on the printed circuit board 100A according to an example.

[0034] The components of the example printed circuit board 100A are described in more detail below with reference to the drawings.

[0035] The glass layer 110 may include glass, which is a non-crystalline solid. Glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc. Alternative glass materials, such as, but not limited to, fluoride glass, phosphate glass, chalcogenide glass, etc., may also be used. Other additives may also be included to form glasses with specific physical properties. Such additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and / or oxides of such elements and other elements.

[0036] The glass layer 110 may be a layer distinct from an organic insulating material including glass fiber (glass fiber, glass cloth, glass fabric), for example, copper clad laminate (CCL), prepreg (PPG), etc. For example, the glass layer 110 may include plate glass. The glass layer 110 may be a core layer. For example, it may be a glass core.

[0037] The through hole TH may penetrate the glass layer 110 in a thickness direction. For example, the through hole TH may penetrate between the upper surface and the lower surface of the glass layer 110. The through hole TH may have one or more holes. The through hole TH may have a shape of an elliptical cylinder or a circular cylinder, but is not limited thereto, and may have an hourglass-like cylinder shape, etc.

[0038] The blind hole VH may partially penetrate the glass layer 110 in the thickness direction. For example, the blind hole VH may partially penetrate from the upper surface of the glass layer 110 to the lower surface thereof. There may be a plurality of blind holes VH. The blind hole VH may have a shape of an elliptical cylinder or a circular cylinder, but is not limited thereto, and may have an hourglass-like column shape, or the like. The blind hole VH may also have a shape with a rounded edge at the bottom.

[0039] The first and second wiring layers 120 and 130 may each perform various functions according to the design. For example, they may include a signal pattern, a power pattern, a ground pattern, etc., and these patterns may each have various forms such as a line (or trace), a plane (or plate), a pad (or land), etc. The first and second wiring layers 120 and 130 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). If necessary, they may include a sputtering layer instead of the electroless plating layer (or chemical copper), or may include both the electroless plating layer (or chemical copper) and the sputtering layer.

[0040] The through via 140 can perform various functions depending on the design. For example, it can include a ground via, a power via, a signal via, etc. The through via 140 can include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). If necessary, it can include a sputtering layer instead of the electroless plating layer (or chemical copper), or it can include both the electroless plating layer (or chemical copper) and the sputtering layer.

[0041] The capacitor 150 can store electric potential energy as capacitance through the plurality of blind holes VH, the first electrode layer 151, the second electrode layer 152, and the first dielectric layer 153. For example, it can function as an electronic element that charges a voltage and outputs a current by utilizing the characteristic of repeated charging and discharging. This can stabilize an unstable power supply and remove noise. It can also block direct current and pass alternating current. Furthermore, it can be used for the stable operation of a semiconductor chip.

[0042] The first to fifth seed layers 121, 131, 141, 145, 152-1 and the first electrode layer 151 may each include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof, and may preferably include copper (Cu), but is not limited thereto. The first to third seed layers 121, 131, 141 may be integrated layers that do not have a boundary at the connection portion. The first to fifth seed layers 121, 131, 141, 145, 152-1 and the first electrode layer 151 may each be formed by electroless plating (e.g., chemical copper plating) and / or sputtering.

[0043] The first to fourth metal layers 122, 132, 142, and 152-2 may each include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof, and may preferably include copper (Cu), but is not limited thereto. The first to fourth metal layers 122, 132, 142, and 152-2 may each be formed by electrolytic plating (e.g., copper electroplating). The first to fifth seed layers 121, 131, 141, 145, and 152-1 and the first electrode layer 151 may each be thinner than the first to fourth metal layers 122, 132, 142, and 152-2.

[0044] From the viewpoint of insulating property and relative dielectric constant, the first and second dielectric layers 153 and 143 may contain at least one of alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, strontium titanate, etc. However, the first and second dielectric layers 153 and 143 are not limited thereto, and may contain an organic polymer insulating material.

[0045] 5a to 5n are cross-sectional views illustrating steps of a manufacturing method for the printed circuit board of FIG.

[0046] 5a, a glass layer 110 is prepared, and a through hole TH and a plurality of blind holes VH are formed in the glass layer 110. The through hole TH and the plurality of blind holes VH can be formed by various methods such as laser processing, mechanical processing, chemical processing, etc.

[0047] 5b, a first conductor layer M1 is formed on the upper and lower surfaces of the glass layer 110, the wall surfaces of the through holes TH, and the wall and bottom surfaces of each of the blind holes VH. The first conductor layer M1 can be formed by electroless plating, for example, chemical copper plating. If necessary, it may be formed by sputtering.

[0048] 5c, a dielectric layer D is formed on the first conductor layer M1. The dielectric layer D may be formed in the form of a thin film by a known coating process.

[0049] Referring to Fig. 5d, a second conductor layer M2 is formed on the dielectric layer D. The second conductor layer M2 can be formed by electroless plating, for example, chemical copper plating. If necessary, it may be formed by sputtering.

[0050] 5e, a 3-1 conductor layer M3-1 is formed on the second conductor layer M2. The 3-1 conductor layer M3-1 can fill the through holes TH and the blind holes VH. The 3-1 conductor layer M3-1 can be formed by electrolytic plating, for example, copper electroplating.

[0051] 5f, a first dry film 210 is formed on a portion of the 3-1 conductor layer M3-1. The first dry film 210 may be formed by depositing an uncured insulating film and then curing it, but is not limited thereto, and may also be formed by a coating process.

[0052] 5g, an etching process is performed to remove the second and third-1 conductor layers M2 and M3-1 from the remaining areas except the area covered with the first dry film 210.

[0053] 5h, the first dry film 210 is peeled off, and a portion of the dielectric layer D disposed on the upper and lower surfaces of the glass layer 110 and exposed is removed by etching. When the dielectric layer D is removed, the first conductor layer M1 can be exposed.

[0054] 5i, second and third dry films 220 and 230 having patterned openings for forming circuits are formed on the upper and lower surfaces of the glass layer 110. The second and third dry films 220 and 230 may be formed by depositing an uncured insulating film and then curing the film, but are not limited thereto, and may also be formed by a coating process.

[0055] Referring to FIG. 5j, the patterned openings of the second and third dry films 220 and 230 are filled with electrolytic plating, for example, copper electroplating, to form a 3-2 conductor layer M3-2.

[0056] Referring to FIG. 5k, the second and third dry films 220, 230 are peeled off.

[0057] 5l, a fourth dry film 240 is formed on a portion of the first conductor layer M1. The fourth dry film 240 may be formed by depositing an uncured insulating film and then curing it, but is not limited thereto, and may also be formed by a coating process.

[0058] 5m, an etching process is performed to remove the first conductor layer M1 from the remaining area except the area covered with the fourth dry film 240.

[0059] 5n, the fourth dry film 240 is peeled off. As a result, the first to fourth seed layers 121, 131, 141, 152S, the first to third metal layers 122, 132, 142, the first and second electrode layers 151, 152, the first and second wiring layers 120, 130 including the first and second dielectric layers 153, 143, the through via 140, and the capacitor 150 can be formed. That is, the printed circuit board 100A according to the above-mentioned example can be manufactured.

[0060] The other details are substantially the same as those described in the printed circuit board 100A according to the above-mentioned example, and therefore will not be described again.

[0061] FIG. 6 is a cross-sectional view that illustrates a schematic diagram of another example of a printed circuit board.

[0062] Referring to the drawings, the printed circuit board 100B according to another example may further include build-up layers disposed on the upper side and the lower side with respect to the printed circuit board according to the above example. For example, the printed circuit board 100B according to another example may include one or more first build-up insulating layers 161 disposed on the upper surface of the glass layer 110, one or more first build-up wiring layers 162 disposed on or within the one or more first build-up insulating layers 161, one or more first build-up via layers 163 each penetrating at least one of the one or more first build-up insulating layers 161, one or more second build-up insulating layers 171 disposed on the lower surface of the glass layer 110, one or more second build-up insulating layers 171 disposed on or within the one or more second build-up insulating layers 171, and one or more first build-up wiring layers 162 disposed on or within the one or more first build-up insulating layers 161. may further include one or more second build-up wiring layers 172 disposed therein, one or more second build-up via layers 173 each penetrating at least one of the one or more second build-up insulating layers 171, a first resist layer 181 disposed on the first build-up insulating layer 161 disposed on the uppermost side of the one or more first build-up insulating layers 161, and a second resist layer 182 disposed on the second build-up insulating layer 171 disposed on the lowermost side of the one or more second build-up insulating layers 171. For example, the printed circuit board 100B according to another example may be a film chip bonding (FCB) board or a ball grid array (BGA) board including the glass layer 110 as a core layer.

[0063] The components of the printed circuit board 100B according to another example will be described in more detail below with reference to the drawings.

[0064] Each of the one or more first and second build-up insulating layers 161, 171 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including inorganic filler, organic filler, and / or glass fiber (glass fiber, glass cloth, glass fabric) together with these resins. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymer materials may be used. The insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric). The one or more first and second build-up insulating layers 161, 171 may include substantially the same insulating material as each other, or may include different insulating materials from each other.

[0065] Each of the one or more first and second build-up wiring layers 162, 172 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal may include copper (Cu), but is not limited thereto. Each of the one or more first and second build-up wiring layers 162, 172 may perform various functions according to the design. For example, the metal may include a signal pattern, a power pattern, a ground pattern, and the like. Each of these patterns may have various forms, such as a line, a plane, and a pad. Each of the one or more first and second build-up wiring layers 162, 172 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Alternatively, the metal foil (or copper foil) and the electrolytic plating layer (or electrolytic copper) may be included. Alternatively, it may include a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electrolytic copper). It may include a sputtering layer instead of the electroless plating layer (or chemical copper), or it may include both as necessary.

[0066] Each of the one or more first and second build-up via layers 163, 173 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal may include copper (Cu), but is not limited thereto. Each of the one or more first and second build-up via layers 163, 173 may include a filled via that fills a via hole, but may also include a conformal via that is arranged along the wall surface of the via hole. The one or more first and second build-up via layers 163, 173 may perform various functions depending on the design. For example, they may include a ground via, a power via, a signal via, and the like. The one or more first and second build-up via layers 163, 173 may have a tapered shape in opposite directions on a cross section. The one or more first and second build-up via layers 163, 173 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be included instead of the electroless plating layer (or chemical copper), or both may be included as necessary.

[0067] The first and second resist layers 181, 182 may include, but are not limited to, a liquid or film type solder resist, and other types of insulating materials may be used. The first and second resist layers 181, 182 may have first and second openings exposing the patterns, respectively. A surface treatment layer may be formed on the patterns exposed in the first opening and / or the second opening, if necessary. Alternatively, a metal bump may be formed on the patterns exposed in the first opening and / or the second opening.

[0068] The other details are substantially the same as those described in the printed circuit board 100A according to the above-mentioned example, and therefore will not be described again.

[0069] In the present invention, the depth, thickness, width, length, etc. can be measured using a scanning microscope, optical microscope, etc. based on a cross section obtained by polishing or cutting the printed circuit board. The cut section may be a vertical section or a horizontal section, and each value can be measured based on the required cut section. When the value is not constant, the value can be determined as the average value of values ​​measured at any five points.

[0070] In the present invention, the term "cover" can include not only the case of covering entirely, but also the case of covering at least a part, and further, can include not only the case of covering directly, but also the case of covering indirectly. Furthermore, the term "fill" can include not only the case of filling completely, but also the case of filling approximately, for example, the case where some gaps or voids are present.

[0071] In the present invention, "substantially" can be determined by taking into account process errors, positional deviations, measurement errors, etc. that occur in the manufacturing process. For example, "substantially the same" line width, interval, thickness, height, etc. can include not only being completely identical in numerical terms, but also having almost similar numerical values. Furthermore, "substantially coplanar" can include not only being on the completely same plane, but also being on almost the same plane.

[0072] In the present invention, the term "same insulating material" refers not only to the completely same insulating material, but also to the same type of insulating material. Thus, although the compositions of the insulating materials are substantially the same, the specific composition ratios thereof may differ slightly.

[0073] In the present invention, the meaning of "on a cross section" can mean the cross-sectional shape of an object cut vertically, or the cross-sectional shape of an object cut vertically, or the cross-sectional shape of an object when viewed from a side, and the meaning of "on a plane" can mean the planar shape of an object cut horizontally, or the planar shape of an object when viewed from a top or bottom.

[0074] In the present invention, for convenience, the terms lower, bottom, and bottom surface are used to mean the downward direction based on the cross section of the drawing, and the terms upper, top, and top surface are used to mean the opposite direction. Also, the terms side and lateral surface are used to mean the direction perpendicular to the top and bottom surfaces. However, these are merely definitions of directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of the directions, and the concepts of up / down can be changed at any time.

[0075] In the present invention, "connected" is a concept including not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept including both physical connection and no connection. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component, within the scope of the right.

[0076] The term "one example" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe unique features that are different from each other. However, the above-mentioned one example does not exclude that it is realized in combination with the features of another example. For example, even if the matter described in a specific example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0077] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0078] 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera 1060:Antenna 1070:Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts package 1130: Camera module 1140: Speaker 100A, 100B: Printed circuit board 110: Glass layer 120, 130: Wiring layer 140:Through via 150: Capacitor 151, 152: Electrode layer 121, 131, 141, 145, 152-1: seed layer 122, 132, 142, 152-2: Metal layer 143, 153: dielectric layer 161, 171: Build-up insulation layer 162, 172: Build-up wiring layers 163, 173: Build-up via layer 181, 182: resist layer

Claims

1. A glass layer; a first wiring layer disposed on an upper surface of the glass layer; a capacitor including a plurality of blind holes each penetrating a portion of the glass layer from a top surface to a bottom surface of the glass layer, a first electrode layer disposed on the top surface of the glass layer and extending into each of the plurality of blind holes, a second electrode layer disposed on the first electrode layer and filling each of the plurality of blind holes, and a first dielectric layer disposed between the first electrode layer and the second electrode layer.

2. On an upper surface of the glass layer, The printed circuit board according to claim 1 , wherein the first wiring layer, the first electrode layer, and the second electrode layer have different thicknesses.

3. On an upper surface of the glass layer, the first wiring layer is thicker than the second electrode layer; The printed circuit board of claim 2 , wherein the second electrode layer has a thickness greater than that of the first electrode layer.

4. On an upper surface of the glass layer, The printed circuit board of claim 1 , wherein at least a portion of the first electrode layer extends horizontally so as not to be covered by the second electrode layer.

5. The printed circuit board of claim 1 , wherein the first wiring layer includes a first seed layer disposed on an upper surface of the glass layer and a first metal layer disposed on an upper surface of the first seed layer.

6. On an upper surface of the glass layer, the first seed layer has substantially the same thickness as the first electrode layer; The printed circuit board of claim 5 , wherein the first metal layer has a thickness greater than that of the second electrode layer.

7. a second wiring layer disposed on the lower surface of the glass layer; The printed circuit board of claim 5 , wherein the second wiring layer includes a second seed layer disposed on the lower surface of the glass layer and a second metal layer disposed on the lower surface of the second seed layer.

8. a through via penetrating the glass layer and connecting at least a portion of the first wiring layer and the second wiring layer to each other; 8. The printed circuit board of claim 7, wherein the through via includes a through hole penetrating the glass layer from the upper surface to the lower surface of the glass layer, a third seed layer disposed on a wall surface of the through hole, a second dielectric layer disposed on the third seed layer, a fourth seed layer disposed on the second dielectric layer, and a third metal layer disposed on the fourth seed layer and filling the through hole.

9. 9. The printed circuit board of claim 8, wherein the first and second dielectric layers comprise the same insulating material.

10. There is no boundary between each of the first and second seed layers and the third seed layer; The printed circuit board according to claim 8 , wherein there are boundaries at connection portions between the first metal layer, the second metal layer, and the third metal layer.

11. At least a portion of each of the fourth seed layer and the third metal layer further protrudes above the third seed layer and the second dielectric layer, The printed circuit board of claim 8 , wherein at least another portion of each of the fourth seed layer and the third metal layer further protrudes below each of the third seed layer and the second dielectric layer.

12. 12. The printed circuit board of claim 11, wherein a further protruding thickness of at least a portion of each of the fourth seed layer and the third metal layer, and at least another portion, is substantially the same as a respective thickness of the first and second dielectric layers.

13. one or more first build-up insulation layers disposed on an upper surface of the glass layer; one or more first build-up wiring layers disposed on or within the one or more first build-up insulating layers; one or more first build-up via layers each penetrating at least one of the one or more first build-up insulating layers; one or more second build-up insulation layers disposed on a lower surface of the glass layer; one or more second build-up wiring layers disposed on or within the one or more second build-up insulating layers; one or more second build-up via layers each penetrating at least one of the one or more second build-up insulating layers; a first resist layer disposed on a first build-up insulating layer that is disposed on the uppermost side of the one or more first build-up insulating layers; The printed circuit board according to claim 8 , further comprising: a second resist layer disposed on a second build-up insulation layer that is disposed on the lowermost side of the one or more second build-up insulation layers.

14. the second electrode layer includes a fifth seed layer disposed on the first dielectric layer and a fourth metal layer disposed on the fifth seed layer and filling each of the plurality of blind holes; On an upper surface of the glass layer, The printed circuit board of claim 1 , wherein the fourth metal layer has a thickness greater than that of the fifth seed layer.

15. The printed circuit board of claim 1 , wherein the glass layer comprises plate glass.

16. The printed circuit board according to claim 1 , wherein an upper surface of the first wiring layer is disposed at a different level from an upper surface of the second electrode layer.

17. A glass layer; a through hole penetrating the glass layer from the upper surface to the lower surface of the glass layer; a plurality of blind holes each penetrating a portion of the glass layer from an upper surface to a lower surface of the glass layer; a first conductor layer disposed on the upper and lower surfaces of the glass layer and extending onto a wall surface of the through hole and a wall surface and a bottom surface of each of the plurality of blind holes; a third conductor layer disposed on the first conductor layer and filling the through hole and each of the blind holes; a dielectric layer disposed between the first conductor layer and the third conductor layer on the top surface of the glass layer, on the wall surfaces of the through hole, and on the wall and bottom surfaces of each of the plurality of blind holes.

18. the third conductor layer includes a 3-1 conductor layer disposed on at least a portion of the first conductor layer and filling each of the through holes and the plurality of blind holes, and a 3-2 conductor layer disposed on at least another portion of the first conductor layer and covering the portion of the 3-1 conductor layer that fills the through holes; On an upper surface of the glass layer, The printed circuit board according to claim 17, wherein the 3-2 conductor layer is thicker than the 3-1 conductor layer.

19. On an upper surface of the glass layer, 20. The printed circuit board according to claim 18, wherein at least another portion of the first conductor layer extends horizontally so as not to be covered by the 3-1 conductor layer.

20. The printed circuit board of claim 18, further comprising a second conductor layer disposed between the dielectric layer and the 3-1 conductor layer.

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