Semiconductor device

Abstract

To provide a semiconductor device capable of improving an electric characteristic by preventing a leakage current to a semiconductor substrate from a transistor, and by preventing a short circuit phenomenon.SOLUTION: A semiconductor device comprises: an insulation substrate 105; a silicon layer 100 thereon; a dopant layer DEP thereon; an embedded spacer on the side surface; a source / drain pattern SD1 thereon; channel patterns CH1 and CH2 on the dopant layer; a gate electrode GE thereon; lower power wirings VPR1 and VPR2 of a lower part of the insulation substrate; and a back surface contact that electrically couples each lower power wiring and the source / drain pattern each other so as to penetrate the insulation substrate and the silicon layer. Each channel pattern includes a plurality of semiconductor patterns SP1 to SP4 laminated so as to be separated each other. The source / drain pattern is coupled to each channel pattern. The gate electrode includes a plurality of inner side electrodes PO1 to PO3 interposed to between the plurality of semiconductor patterns, and an outer side electrode PO4.SELECTED DRAWING: Figure 5E

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices including field effect transistors. [Background technology]

[0002] Semiconductor devices include integrated circuits made up of MOS (Metal Oxide Semiconductor) FETs. As the size and design rules of semiconductor devices are gradually reduced, the scale down of the size of MOS FETs is also accelerating. As the size of MOS FETs is reduced, the operating characteristics of semiconductor devices are degraded. Therefore, various methods are being researched to form semiconductor devices with better performance while overcoming the limitations imposed by the high integration of semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 1,135,5601 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor element having improved electrical characteristics. [Means for solving the problem]

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising: an insulating substrate; a silicon layer on the insulating substrate; a dopant layer on the silicon layer; a buried spacer on a side of the dopant layer; a channel pattern on the dopant layer; a source / drain pattern on the buried spacer; a gate electrode on the channel pattern; a lower power wiring on a lower portion of the insulating substrate; and a back contact penetrating the insulating substrate and the silicon layer to electrically connect the lower power wiring and the source / drain pattern to each other, the channel pattern comprising a plurality of semiconductor patterns stacked apart from each other, the source / drain pattern being connected to the channel pattern, the gate electrode comprising a plurality of inner electrodes respectively interposed between the plurality of semiconductor patterns, and a side of the back contact contacting the silicon layer and the buried spacer.

[0006] According to another aspect of the present invention, there is provided a semiconductor device comprising: an insulating substrate including a horizontal portion and a protruding portion; a silicon layer on the insulating substrate; a dopant layer on the silicon layer; a first buried spacer and a second buried spacer on both sides of the dopant layer; a channel pattern on the dopant layer; a first source / drain pattern and a second source / drain pattern connected to both sides of the channel pattern; a gate electrode on the channel pattern; a lower power wiring on a lower portion of the insulating substrate; and a back contact penetrating the insulating substrate and the silicon layer to electrically connect the lower power wiring and the first source / drain pattern to each other, wherein the protruding portion contacts a lower portion of the second source / drain pattern, the silicon layer is interposed between the protruding portion and the back contact, a first side of the first buried spacer contacts the back contact, and a second side of the second buried spacer contacts the protruding portion, and the first buried spacer and the second buried spacer comprise an insulating material having a dielectric constant lower than that of silicon oxide.

[0007] According to an embodiment, a semiconductor device includes an insulating substrate, a silicon layer on the insulating substrate, a dopant layer on the silicon layer, embedded spacers on sides of the dopant layer, a channel pattern on the dopant layer, source / drain patterns on the embedded spacers, a gate electrode on the channel pattern, a lower power wiring on a lower portion of the insulating substrate, and a back contact penetrating the insulating substrate and the silicon layer to electrically connect the lower power wiring and the source / drain pattern to each other, the channel pattern including a plurality of semiconductor patterns spaced apart from each other and stacked, the source / drain pattern being connected to the channel pattern, each of the dopant layer and the silicon layer including at least one impurity selected from the group consisting of fluorine (F), argon (Ar), oxygen (O), and nitrogen (N), and a first impurity concentration of the impurity in the dopant layer being greater than a second impurity concentration of the impurity in the silicon layer. Effect of the Invention

[0008] According to the present invention, a buried spacer is formed between a nanosheet and a semiconductor substrate, thereby preventing leakage current from a channel pattern. Also, the buried spacer can prevent a short phenomenon occurring between source / drain patterns. Therefore, leakage current from a transistor to a semiconductor substrate is prevented, and the electrical characteristics of a semiconductor device can be improved by preventing a short phenomenon.

[0009] According to the present invention, it is possible to prevent a short phenomenon occurring between a back contact connected to a source / drain pattern and a gate electrode through a buried spacer, and as a result, the electrical characteristics of a semiconductor device to which the lower power wiring of the present invention is applied can be improved. [Brief description of the drawings]

[0010] [Figure 1] 1 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention; [Diagram 3] 1 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention; [Figure 4] 1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention; [Figure 5A] FIG. 5 is a cross-sectional view taken along line AA' in FIG. [Figure 5B] FIG. 5 is a cross-sectional view taken along line BB' in FIG. [Figure 5C] 5 is a cross-sectional view taken along line CC' in FIG. 4. [Figure 5D] FIG. 5 is a cross-sectional view taken along line DD' in FIG. [Figure 5E] 5 is a cross-sectional view taken along line EE' in FIG. 4. [Figure 5F] 5C is a graph showing the impurity concentration of a silicon layer along the third center line of FIG. 5B. [Figure 6A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6C] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7C] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8C]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11C] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11D] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12C] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13C] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13D] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14C] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14D] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14E] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15C] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15D] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16C] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16D] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] FIG. 11B is an enlarged view for explaining a method for forming the N region in FIG. 11A. [Figure 18] FIG. 11B is an enlarged view for explaining a method for forming the N region in FIG. 11A. [Figure 19] FIG. 11B is an enlarged view for explaining a method for forming the N region in FIG. 11A. [Figure 20]FIG. 11B is an enlarged view for explaining a method for forming the N region in FIG. 11A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of the embodiments of the present invention will be described in detail with reference to the drawings.

[0012] 1 to 3 are conceptual diagrams illustrating a logic cell of a semiconductor device according to one embodiment of the present invention.

[0013] 1, a single height cell (SHC) is provided. Specifically, a first lower power wiring VPR1 and a second lower power wiring VPR2 are provided under a substrate 105. The first lower power wiring VPR1 is a path through which a source voltage VSS, for example, a ground voltage, is provided. The second lower power wiring VPR2 is a path through which a drain voltage VDD, for example, a power voltage, is provided.

[0014] A single height cell SHC is defined between the first lower power wiring VPR1 and the second lower power wiring VPR2. The single height cell SHC includes one PMOSFET region PR and one NMOSFET region NR. Again, the single height cell SHC has a CMOS structure provided between the first lower power wiring VPR1 and the second lower power wiring VPR2.

[0015] Each of the PMOSFET region PR and the NMOSFET region NR has a single width W_SHC in the first direction D1. The length of the single height cell SHC in the first direction D1 is defined as a first height HE1. The first height HE1 is substantially equal to the distance (e.g., pitch) between the first lower power wiring VPR1 and the second lower power wiring VPR2.

[0016] The single-height cell SHC constitutes one logic cell. In this specification, a logic cell refers to a logic element (e.g., AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. That is, a logic cell includes transistors for constituting the logic element and wiring that connects the transistors to each other.

[0017] 2, a double height cell (DHC) is provided. Specifically, a first lower power wiring VPR1, a second lower power wiring VPR2, and a third lower power wiring VPR3 are provided on a substrate 105. The second lower power wiring VPR2 is disposed between the first lower power wiring VPR1 and the third lower power wiring VPR3. The third lower power wiring VPR3 is a path through which a source voltage VSS is provided.

[0018] A double-height cell DHC is defined between the first lower power wiring VPR1 and the third lower power wiring VPR3. The double-height cell DHC includes a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0019] The first NMOSFET region NR1 is adjacent to the first lower power wiring VPR1. The second NMOSFET region NR2 is adjacent to the third lower power wiring VPR3. The first and second PMOSFET regions (PR1, PR2) are adjacent to the second lower power wiring VPR2. In plan view, the second lower power wiring VPR2 is disposed between the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0020] The length of the double-height cell DHC in the first direction D1 is defined as a second height HE2. The second height HE2 is approximately twice the first height HE1 of FIG. 1. The first PMOSFET region PR1 and the second PMOSFET region PR2 of the double-height cell DHC are connected to operate as one PMOSFET region. Therefore, the size of the channel of the PMOS transistor of the double-height cell DHC is larger than the size of the channel of the PMOS transistor of the single-height cell SHC of FIG. 1.

[0021] For example, the size of the channel of the PMOS transistor of the double-height cell DHC is about twice the size of the channel of the PMOS transistor of the single-height cell SHC. As a result, the double-height cell DHC operates faster than the single-height cell SHC. In the present invention, the double-height cell DHC shown in FIG. 2 is defined as a multi-height cell. Although not shown, the multi-height cell may include a triple-height cell whose cell height is about three times that of the single-height cell SHC.

[0022] 3, a first single height cell SHC1, a second single height cell SHC2, and a double height cell DHC are two-dimensionally arranged on a substrate 105. The first single height cell SHC1 is arranged between a first lower power wiring VPR1 and a second lower power wiring VPR2. The second single height cell SHC2 is arranged between a second lower power wiring VPR2 and a third lower power wiring VPR3. The second single height cell SHC2 is adjacent to the first single height cell SHC1 in a first direction D1.

[0023] The double height cell DHC is disposed between the first lower power wiring VPR1 and the third lower power wiring VPR3. The double height cell DHC is adjacent to the first and second single height cells SHC1 and SHC2 in the second direction D2.

[0024] An isolation structure DB is provided between the first single height cell SHC1 and the double height cell DHC, and between the second single height cell SHC2 and the double height cell DHC, such that the active area of ​​the double height cell DHC is electrically isolated from the respective active areas of the first and second single height cells (SHC1, SHC2).

[0025] Fig. 4 is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figs. 5A to 5E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' in Fig. 4, respectively. Fig. 5F is a graph showing the impurity concentration of the silicon layer along the third center line in Fig. 5B. The semiconductor device shown in Figs. 4 and 5A to 5E is a more specific example of the first and second single height cells (SHC1, SHC2) in Fig. 3.

[0026] 4 and 5A to 5E, first and second single height cells (SHC1, SHC2) are provided on a substrate 105. Logic transistors constituting a logic circuit are disposed on each of the first and second single height cells (SHC1, SHC2). The substrate 105 includes an insulating layer of a silicon substrate. Again, the substrate 105 is an insulating substrate. For example, the substrate 105 includes a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0027] The substrate 105 includes a horizontal portion HZ and a protruding portion PJ. Lower power wirings (VPR1 to VPR3), which will be described later, are disposed within the horizontal portion HZ of the substrate 105. The protruding portion PJ extends from the horizontal portion HZ in a third direction D3, which is a direction perpendicular to the substrate 105. The protruding portion PJ contacts the lower portions of a first source / drain pattern SD1 and a second source / drain pattern SD2, which will be described later.

[0028] The substrate 105 has a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. The first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 each extend in a second direction D2. The first single height cell SHC1 includes the first NMOSFET region NR1 and the first PMOSFET region PR1, and the second single height cell SHC2 includes the second PMOSFET region PR2 and the second NMOSFET region NR2.

[0029] A first insulation pattern AP1 and a second insulation pattern AP2 are defined by trenches TR formed in the upper portion of the substrate 105. The first insulation pattern AP1 is provided on each of the first and second PMOSFET regions PR1, PR2. The second insulation pattern AP2 is provided on each of the first and second NMOSFET regions NR1, NR2. The first and second insulation patterns AP1, AP2 extend in a second direction D2. The first and second insulation patterns AP1, AP2 are vertically protruding portions of the substrate 105.

[0030] The trench TR is filled with an isolation layer ST. The isolation layer ST covers the sidewalls of the first and second insulating patterns AP1 and AP2. The isolation layer ST includes a silicon oxide layer. The isolation layer ST does not cover the first and second channel patterns CH1 and CH2, which will be described later.

[0031] A silicon layer 100 is provided on a substrate 105. The silicon layer 100 is provided between protrusions PJ of the substrate 105. Specifically, the silicon layer 100 is interposed between the protrusions PJ and a back contact BDC, which will be described later. The silicon layer 100 is a semiconductor layer including silicon, germanium, silicon-germanium, etc., or a compound semiconductor layer.

[0032] A dopant layer DEP, a first buried spacer BSP1, and a second buried spacer BSP2 are provided on the silicon layer 100. The dopant layer DEP is a silicon layer containing impurities. The width of the dopant layer DEP in the second direction D2 gradually decreases and then increases again according to a predetermined vertical distance.

[0033] The first embedded spacer BSP1 and the second embedded spacer BSP2 are provided on the sides of the dopant layer DEP, in other words, the dopant layer DEP is interposed between the first embedded spacer BSP1 and the second embedded spacer BSP2.

[0034] The first buried spacer BSP1 has a first side surface SW1 and a second side surface SW2 facing the first side surface SW1 in the second direction D2. The first side surface SW1 contacts a back contact BDC described below, and the second side surface SW2 contacts the dopant layer DEP. The first and second side surfaces (SW1, SW2) are curved surfaces. The first and second side surfaces (SW1, SW2) bulge toward the dopant layer DEP. The curvature of the first side surface SW1 is smaller than the curvature of the second side surface SW2.

[0035] The second embedded spacer BSP2 has a third side surface SW3 and a fourth side surface SW4 facing the third side surface SW3 in the second direction D2. The third side surface SW3 contacts the dopant layer DEP, and the fourth side surface SW4 contacts the protruding portion PJ of the substrate 105. The third side surface SW3 is a curved surface, and the fourth side surface SW4 is a flat surface. The curvature of the first side surface SW1 is smaller than the curvature of the third side surface SW3.

[0036] The second side SW2 and the third side SW3 correspond to both side walls of the dopant layer DEP. That is, the first embedded spacer BSP1 and the second embedded spacer BSP2 are spaced apart from each other by the dopant layer DEP, so that the second side SW2 and the third side SW3 face each other. The curvature of the second side SW2 is the same as the curvature of the third side SW3.

[0037] The curvatures being the same is defined as the radii of curvature of the second side surface SW2 and the third side surface SW3 being the same or similar. Similar means, for example, that the ratio of the radius of curvature of the third side surface SW3 to the radius of curvature of the second side surface SW2 is 0.9 to 1.1. In other words, the curvatures of the second side surface SW2 and the third side surface SW3 are considered to be substantially the same when the ratio of the radii of curvature is 0.9 to 1.1, or is preferably 1.0.

[0038] The first and second buried spacers (BSP1, BSP2) include an insulating material having a dielectric constant lower than that of silicon oxide, for example, the insulating material is SiOx, SiNy, SiON, SiOCN, SiCN, SiOF, or a combination thereof.

[0039] 5E, the first insulation pattern AP1 includes a first part P1 on the first PMOSFET region PR1, a silicon layer 100 on the first part P1, and a dopant layer DEP on the silicon layer 100. The second insulation pattern AP2 includes a second part P2 on the first NMOSFET region NR1, a silicon layer 100 on the second part P2, and a dopant layer DEP on the silicon layer 100. For example, the first and second parts (P1, P2) include a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0040] The silicon layer 100 and the dopant layer DEP contain at least one impurity. For example, the impurities contained in the silicon layer 100 and the dopant layer DEP are fluorine (F), argon (Ar), oxygen (O), and nitrogen (N). The impurity concentration of the dopant layer DEP is higher than the impurity concentration of the silicon layer 100. For example, the impurity concentration in the dopant layer DEP is 0.5 at% to 2 at%. The impurity concentration in the silicon layer 100 is 0.1 at% to 0.5 at%.

[0041] 4 and 5A to 5E again, a first channel pattern CH1 is provided on a first insulating pattern AP1. A second channel pattern CH2 is provided on a second insulating pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 includes a first semiconductor pattern SP1, a second semiconductor pattern SP2, a third semiconductor pattern SP3, and a fourth semiconductor pattern SP4 that are sequentially stacked. The first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) are spaced apart from each other in the vertical direction (i.e., the third direction D3).

[0042] Each of the first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) includes silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) includes crystalline silicon. Each of the first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) is a nanosheet.

[0043] A plurality of first source / drain patterns SD1 are provided on the first insulating pattern AP1. A plurality of first recesses RS1 are formed on the first insulating pattern AP1. The first source / drain patterns SD1 are provided in the first recesses RS1, respectively. The first source / drain patterns SD1 are impurity regions of a first conductivity type (e.g., p-type). A first channel pattern CH1 is interposed between the pair of first source / drain patterns SD1. Again, stacked first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) connect the pair of first source / drain patterns SD1 to each other.

[0044] A plurality of second source / drain patterns SD2 are provided on the second insulating pattern AP2. A plurality of second recesses RS2 are formed on the second insulating pattern AP2. The second source / drain patterns SD2 are provided in the second recesses RS2, respectively. The second source / drain patterns SD2 are impurity regions of a second conductivity type (e.g., n-type). A second channel pattern CH2 is interposed between the pair of second source / drain patterns SD2. Again, stacked first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) connect the pair of second source / drain patterns SD2 to each other.

[0045] The first and second source / drain patterns (SD1, SD2) are epitaxial patterns formed by a selective epitaxial growth (SEG) process. As an example, the top surfaces of the first and second source / drain patterns (SD1, SD2) are located at substantially the same level as the top surface of the fourth semiconductor pattern SP4. As another example, the top surfaces of the first and second source / drain patterns (SD1, SD2) are higher than the top surface of the fourth semiconductor pattern SP4.

[0046] The first source / drain pattern SD1 includes a semiconductor element (e.g., SiGe) having a lattice constant larger than that of the semiconductor element of the first channel pattern CH1. Thus, the pair of first source / drain patterns SD1 provide compressive stress to the first channel pattern CH1 therebetween. The second source / drain pattern SD2 includes the same semiconductor element (e.g., Si) as the second channel pattern CH2.

[0047] Each of the first source / drain patterns SD1 includes a buffer layer BFL and a main layer MAL on the buffer layer BFL. Referring again to FIG. 5A, the buffer layer BFL covers the inner wall of the first recess RS1. The main layer MAL fills the remaining area of ​​the first recess RS1 except for the buffer layer BFL. The volume of the main layer MAL is larger than the volume of the buffer layer BFL. Each of the buffer layer BFL and the main layer MAL includes silicon-germanium (SiGe). Specifically, the buffer layer BFL includes a relatively low concentration of germanium (Ge). In another embodiment of the present invention, the buffer layer BFL includes only silicon (Si) without germanium (Ge). The concentration of germanium GE in the buffer layer BFL is 0 at% to 30 at%.

[0048] The main layer MAL contains a relatively high concentration of germanium GE. As an example, the concentration of germanium GE in the main layer MAL is 30 at% to 70 at%. The concentration of germanium (Ge) in the main layer MAL increases in the third direction D3. For example, the main layer MAL adjacent to the buffer layer BFL has a germanium (Ge) concentration of about 40 at%, while the upper part of the main layer MAL has a germanium (Ge) concentration of about 60 at%.

[0049] Each of the buffer layer BFL and the main layer MAL includes an impurity (e.g., boron, gallium, or indium) that causes the first source / drain pattern SD1 to have a p-type. The impurity concentration of each of the buffer layer BFL and the main layer MAL is 1E18 atom / cm 3 ~5E22atom / cm 3 The impurity concentration of the main layer MAL is greater than the impurity concentration of the buffer layer BFL.

[0050] The buffer layer BFL protects the main layer MAL during a process of replacing the second semiconductor layer SAL with the first to third inner electrodes (PO1, PO2, PO3) of the gate electrode GE, which will be described later. In other words, the buffer layer BFL prevents the etching material for removing the second semiconductor layer SAL from penetrating into and etching the main layer MAL.

[0051] Each of the second source / drain patterns SD2 includes silicon (Si). The second source / drain pattern SD2 further includes an impurity (e.g., phosphorus, arsenic, or antimony) that causes it to have an n-type. The impurity concentration of the second source / drain pattern SD2 is 1E18 atom / cm 3 ~5E22atom / cm 3 It is.

[0052] Gate electrodes GE are provided extending in a first direction D1 across the first and second channel patterns CH1 and CH2. The gate electrodes GE are arranged in a second direction D2 according to the first pitch. Each gate electrode GE overlaps the first and second channel patterns CH1 and CH2 vertically.

[0053] The gate electrode GE includes a first inner electrode PO1 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a second inner electrode PO2 interposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, a third inner electrode PO3 interposed between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, and an outer electrode PO4 on the fourth semiconductor pattern SP4.

[0054] According to the present embodiment, the dopant layer DEP is interposed between the first semiconductor pattern SP1 and the silicon layer 100. The gate insulating film GI is interposed between the first to fourth semiconductor patterns (SP1 to SP4) and the first to third inner electrodes (PO1 to PO3). The gate insulating film GI does not directly cover the dopant layer DEP.

[0055] 5E, a gate electrode GE is provided on a top surface TS, a bottom surface BS, and both side walls SW of each of the first to fourth semiconductor patterns (SP1, SP2, SP3, SP4). Again, the transistor according to this embodiment is a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the channel.

[0056] Representatively, the first single height cell SHC1 has a first boundary BD1 and a second boundary BD2 facing each other in the second direction D2. The first and second boundaries BD1, BD2 extend in the first direction D1. The first single height cell SHC1 has a third boundary BD3 and a fourth boundary BD4 facing each other in the first direction D1. The third and fourth boundaries BD3, BD4 extend in the second direction D2.

[0057] The gate cutting patterns CT are disposed on the boundaries of the first and second single height cells (SHC1, SHC2) in the second direction D2. For example, the gate cutting patterns CT are disposed on the third and fourth boundaries (BD3, BD4) of the first single height cell SHC1. The gate cutting patterns CT are arranged at a first pitch along the third boundary BD3. The gate cutting patterns CT are arranged at a first pitch along the fourth boundary BD4. In a plan view, the gate cutting patterns CT on the third and fourth boundaries (BD3, BD4) are disposed so as to overlap with the gate electrodes GE, respectively. The gate cutting patterns CT include an insulating material such as a silicon oxide film, a silicon nitride film, or a combination thereof.

[0058] The gate electrode GE on the first single height cell SHC1 is separated from the gate electrode GE on the second single height cell SHC2 by a gate cutting pattern CT. The gate electrode GE on the first single height cell SHC1 and the gate electrode GE on the second single height cell SHC2 aligned therewith in a first direction D1 are interposed by the gate cutting pattern CT. Again, the gate electrode GE extending in the first direction D1 is separated into a plurality of gate electrodes GE by the gate cutting pattern PP.

[0059] 4 and 5A to 5E again, a pair of gate spacers GS are respectively disposed on both side walls of the outer electrode PO4 of the gate electrode GE. The gate spacers GS extend in a first direction D1 along the gate electrode GE. An upper surface of the gate spacer GS is higher than an upper surface of the gate electrode GE. An upper surface of the gate spacer GS is coplanar with an upper surface of a first interlayer insulating film 110 described below. The gate spacer GS includes at least one of SiCN, SiCON, and SiN. As another example, the gate spacer GS includes a multi-layer made of at least two of SiCN, SiCON, and SiN.

[0060] A gate capping pattern GP is provided on the gate electrode GE. The gate capping pattern GP extends in a first direction D1 along the gate electrode GE. The gate capping pattern GP includes a material having an etch selectivity with respect to the first and second interlayer insulating films 110 and 120 described below. Specifically, the gate capping pattern GP includes at least one of SiON, SiCN, SiCON, and SiN.

[0061] A gate insulating film GI is interposed between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating film GI covers the top surface TS, bottom surface BS, and both side walls SW of each of the first to fourth semiconductor patterns (SP1, SP2, SP3, SP4). The gate insulating film GI covers the top surface of the element isolation film ST below the gate electrode GE.

[0062] In one embodiment of the present invention, the gate insulating film GI includes a silicon oxide film, a silicon oxynitride film, and / or a high dielectric film. The high dielectric film includes a high dielectric constant material having a higher dielectric constant than a silicon oxide film. As an example, the high dielectric constant material includes at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0063] The gate electrode GE includes a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern is provided on the gate insulating film GI and is adjacent to the first to fourth semiconductor patterns (SP1, SP2, SP3, SP4). The first metal pattern includes a work function metal that adjusts the threshold voltage of the transistor. The thickness and composition of the first metal pattern are adjusted to achieve a desired threshold voltage of the transistor. For example, the first to third inner electrodes (PO1, PO2, PO3) of the gate electrode GE are composed of the first metal pattern, which is a work function metal.

[0064] The first metal pattern includes a metal nitride film. For example, the first metal pattern includes at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo) and nitrogen (N). Furthermore, the first metal pattern may further include carbon (C). The first metal pattern includes stacked metal films with multiple work functions.

[0065] The second metal pattern includes a metal having a lower resistance than the first metal pattern. For example, the second metal pattern includes at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the outer electrode PO4 of the gate electrode GE includes a first metal pattern and a second metal pattern on the first metal pattern.

[0066] Referring again to FIG. 5B, an inner spacer IP is provided on the first and second NMOSFET regions (NR1, NR2). In other words, an inner spacer IP is provided on the second insulating pattern AP2. The inner spacer IP is interposed between the first to third inner electrodes (PO1, PO2, PO3) of the gate electrode GE and the second source / drain pattern SD2, respectively. The inner spacer IP is in direct contact with the second source / drain pattern SD2. Each of the first to third inner electrodes (PO1, PO2, PO3) of the gate electrode GE is spaced from the second source / drain pattern SD2 by the inner spacer IP.

[0067] A first interlayer insulating film 110 is provided on the substrate 105. The first interlayer insulating film 110 covers the gate spacer GS and the first and second source / drain patterns (SD1, SD2). An upper surface of the first interlayer insulating film 110 is substantially coplanar with an upper surface of the gate capping pattern GP and an upper surface of the gate spacer GS. A second interlayer insulating film 120 is provided on the first interlayer insulating film 110 to cover the gate capping pattern GP. A third interlayer insulating film 130 is provided on the second interlayer insulating film 120. A fourth interlayer insulating film 140 is provided on the third interlayer insulating film 130. As an example, the first to fourth interlayer insulating films (110 to 140) include silicon oxide films.

[0068] A pair of isolation structures DB facing each other in the second direction D2 are provided on both sides of each of the first and second single height cells SHC1 and SHC2. For example, the pair of isolation structures DB are provided on the first and second boundaries BD1 and BD2 of the first single height cell SHC1, respectively. The isolation structures DB extend parallel to the gate electrode GE in the first direction D1. The pitch between the isolation structures DB and the adjacent gate electrode GE is equal to the first pitch.

[0069] The isolation structure DB penetrates the gate capping pattern GP and the gate electrode GE and extends into the first and second insulating patterns AP1, AP2. The isolation structure DB penetrates the upper portions of the first and second insulating patterns AP1, AP2. The isolation structure DB penetrates the dopant layer DEP. The isolation structure DB electrically isolates the active regions of the first and second single height cells SHC1, SHC2 from the active regions of the adjacent cells.

[0070] Active contacts AC are provided through the first and second interlayer insulating films 110 and 120 and electrically connected to the first and second source / drain patterns SD1 and SD2, respectively. Each active contact AC is provided adjacent to one side of the gate electrode GE. In a plan view, the active contacts AC have a bar shape extending in a first direction D1.

[0071] The active contact AC is a self-aligned contact. In other words, the active contact AC is formed in a self-aligned manner using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC covers at least a portion of the sidewall of the gate spacer GS. Although not shown, the active contact AC may cover a portion of the top surface of the gate capping pattern GP.

[0072] A metal-semiconductor compound layer SC, for example a silicide layer, is interposed between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC is electrically connected to the source / drain patterns SD1, SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC includes at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0073] Gate contacts GC are provided through the second interlayer insulating film 120 and the gate capping pattern GP, ​​and are electrically connected to the gate electrodes GE. In plan view, two gate contacts GC on the first single height cell SHC1 are arranged to overlap the first PMOSFET region PR1. Again, two gate contacts GC on the first single height cell SHC1 are provided on the first insulating pattern AP1 (see FIG. 5A). In plan view, one gate contact GC on the first single height cell SHC1 is arranged to overlap the first NMOSFET region NR1. Again, one gate contact GC on the first single height cell SHC1 is provided on the second insulating pattern AP2 (see FIG. 5B).

[0074] The gate contact GC is freely arranged on the gate electrode GE without any positional restrictions. For example, the gate contact GC on the second single-height cell SHC2 is arranged on the second PMOSFET region PR2, the second NMOSFET region NR2, and the element isolation film ST filling the trench TR (see FIG. 4).

[0075] 5B, in one embodiment of the present invention, the upper portion of the active contact AC adjacent to the gate contact GC is filled with an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP is lower than the bottom surface of the gate contact GC. In other words, the upper surface of the active contact AC adjacent to the gate contact GC is lowered below the bottom surface of the gate contact GC by the upper insulating pattern UIP. Therefore, it is possible to prevent a problem in which the gate contact GC contacts the adjacent active contact AC and a short occurs. For example, the upper insulating pattern UIP includes a silicon-based insulating material (e.g., a silicon oxide film, a silicon nitride film, or a silicon oxynitride film).

[0076] Each of the active contact AC and the gate contact GC includes a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM includes at least one metal among aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM covers the sidewall and bottom surface of the conductive pattern FM. The barrier pattern BM includes a metal film / metal nitride film. The metal film includes at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film includes at least one of titanium nitride film (TiN), tantalum nitride film (TaN), tungsten nitride film (WN), nickel nitride film (NiN), cobalt nitride film (CoN), and platinum nitride film (PtN).

[0077] 5B and 5F, the dopant layer DEP has a first center line CL1. The gate electrode GE has a second center line CL2. The dopant layer DEP and the silicon layer 100 have a third center line CL3. The first to third center lines (CL1, CL2, CL3) are defined as lines indicating the center positions of the dopant layer DEP, the gate electrode GE, and the silicon layer 100 in the second direction D2, respectively.

[0078] The first center line CL1 and the second center line CL2 are aligned to be vertically coincident. In other words, the first center line CL1 and the second center line CL2 are at the same position in the second direction D2. Therefore, the dopant layer DEP and the gate electrode GE overlap vertically without being offset. Specifically, the dopant layer DEP overlaps vertically with the first to third inner electrodes (PO1 to PO3) and the outer electrode PO4 without being offset. The dopant layer DEP overlaps vertically with the first to fourth semiconductor patterns (SP1 to SP4) interposed between the first to third inner electrodes (PO1 to PO3) and the outer electrode PO4 without being offset. That is, the dopant layer DEP overlaps vertically with the channel patterns (CH1, CH2).

[0079] 5F, the relationship between the impurity concentrations of the silicon layer 100 and the dopant layer DEP along the third center line CL3 can be seen. A first impurity concentration C1 of the dopant layer DEP is greater than a second impurity concentration C2 of the silicon layer 100. According to a method for manufacturing a semiconductor device described below, an EPI process is performed on the silicon layer 100. This is a process for EPI-growing a silicon-based layer containing impurities. For example, a silicon layer (Si-layer) containing fluorine (F) impurities is grown to form the dopant layer DEP.

[0080] The concentration of the dopant decreases exponentially from the dopant layer DEP toward the silicon layer 100. In this case, the exponential decrease means that the impurity concentration decreases rapidly at the boundary between the dopant layer DEP and the silicon layer 100. The impurity concentration of the silicon layer 100 converges to 0 toward the substrate 105.

[0081] Referring again to FIG. 4 and FIG. 5A to FIG. 5E, first to third lower power wirings (VPR1, VPR2, VPR3) are provided on the lower part of the substrate 105. The first to third lower power wirings (VPR1, VPR2, VPR3) extend parallel to each other in the second direction D2. The first lower power wiring VPR1 is disposed on the fourth boundary BD4 of the first single height cell SHC1. The second lower power wiring VPR2 is disposed on the third boundary BD3 of the first single height cell SHC1. Again, the first single height cell SHC1 is defined between the first lower power wiring VPR1 and the second lower power wiring VPR2. The second single height cell SHC2 is defined between the second lower power wiring VPR2 and the third lower power wiring VPR3. Specifically, the second lower power wiring VPR2 is disposed to overlap the boundary between the first and second single height cells (SHC1, SHC2).

[0082] In one embodiment of the present invention, the first lower power wiring VPR1 vertically overlaps the first NMOSFET region NR1, the second lower power wiring VPR2 vertically overlaps the first PMOSFET region PR1 and the second PMOSFET region PR2, and the third lower power wiring VPR3 vertically overlaps the second NMOSFET region NR2.

[0083] The first to third lower power wirings (VPR1 to VPR3) include at least one selected from the group consisting of copper, molybdenum, tungsten, and ruthenium. The bottom surfaces of the first to third lower power wirings (VPR1 to VPR3) are coplanar with the bottom surface of the substrate 105.

[0084] A power transmission network layer PDN is provided on the bottom surface of the substrate 105. The power transmission network layer PDN includes a plurality of lower wirings electrically connected to the first to third lower power wirings (VPR1-VPR3). As an example, the power transmission network layer PDN includes a wiring network for applying a source voltage VSS to the first and third lower power wirings (VPR1, VPR3). The power transmission network layer PDN includes a wiring network for applying a drain voltage VDD to the second lower power wiring VPR2.

[0085] 4, 5A, 5B, and 5D, a first back contact BDC1 is provided that extends vertically from the second lower power wiring VPR2 to the first source / drain pattern SD1 through the substrate 105. A second back contact BDC2 is provided that extends vertically from the first lower power wiring VPR1 to the second source / drain pattern SD2 through the substrate 105.

[0086] The first back contact BDC1 has a conductive pillar shape for vertically and electrically connecting the second lower power wiring VPR2 and the first source / drain pattern SD1 A drain voltage VDD is applied to the first source / drain pattern SD1 through the first back contact BDC1.

[0087] The second back contact BDC2 has a conductive pillar shape for vertically and electrically connecting the first lower power wiring VPR1 and the second source / drain pattern SD2 A source voltage VSS is applied to the second source / drain pattern SD2 through the second back contact BDC2.

[0088] The first and second rear contacts (BDC1, BDC2) penetrate the substrate 105 and the silicon layer 100. The first and second rear contacts (BDC1, BDC2) electrically connect the lower power wirings (VPR1 to VPR3) to the first and second source / drain patterns (SD1, SD2). Each side of the first and second rear contacts (BDC1, BDC2) contacts the silicon layer 100 and the first buried spacer BSP1.

[0089] Each of the first and second back contacts (BDC1, BDC2) includes a contact plug PCP connected to the lower power wiring (VPR1 to VPR3), a contact portion SEC on the contact plug PCP, and a metal-semiconductor compound layer SC between the contact portion SEC and the source / drain pattern (SD1, SD2). The contact portion SEC and the source / drain pattern (SD1, SD2) are connected through the metal-semiconductor compound layer SC. A liner pattern LIN is interposed between the first and second back contacts (BSC1, BSC2) and the first buried spacer BSP1, and between the first and second back contacts (BSC1, BSC2) and the silicon layer 100. In other words, the liner pattern LIN is provided on the side of the contact portion SEC and the contact plug PCP.

[0090] The contact plug PCP is connected to the lower power wirings (VPR1 to VPR3). Specifically, the contact plug PCP is connected to the lower power wirings (VPR1 to VPR3) through the via parts VVI of each of the lower power wirings (VPR1 to VPR3). The width of the via parts VVI in the second direction D2 increases toward the lower power wirings (VPR1 to VPR3). The via parts VVI vertically overlap the contact plug PCP and the contact part SEC. The via parts VVI vertically overlap the contact part SEC and the first buried spacer BSP1. Specifically, the via parts VVI vertically overlap the contact part SEC and a part of the first buried spacer BSP1.

[0091] The width of the contact plug PCP in the second direction D2 is smaller than the width of the contact portion SEC in the second direction D2. The width of the contact portion SEC in the second direction D2 gradually increases and then decreases again according to a predetermined vertical distance.

[0092] Both side surfaces of the contact portion SEC are curved. Both side surfaces of the contact portion SEC have a curved shape corresponding to the first side surface SW1 of the first embedded spacer BSP1. That is, the curvatures of the side surfaces of the contact portion SEC are identical to the curvature of the first side surface SW1. The curvatures being identical to each other means that the ratio of the radius of curvature of the side surface of the contact portion SEC to the radius of curvature of the first side surface SW1 is 0.9 to 1.1. That is, when the ratio of the radii of curvature is 0.9 to 1.1, or is preferably 1.0, it is considered that the curvatures of the first side surface SW1 and the side surface of the contact portion SEC are substantially identical to each other. Both side surfaces of the contact portion SEC bulge toward the first embedded spacer BSP1.

[0093] The contact plug PCP and the contact portion SEC include at least one metal selected from the group consisting of tungsten, molybdenum, ruthenium, cobalt, aluminum, and copper. As another example, the contact portion SEC includes a semiconductor material such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The liner pattern LIN includes a silicon-based insulating material (e.g., SiO, SiN, SiOC, or SiOCN).

[0094] 4 and 5A to 5E, a first metal layer M1 is provided in the third interlayer insulating film 130. The first metal layer M1 includes first wirings M1_I. The first wirings M1_I of the first metal layer M1 extend in parallel to each other in the second direction D2.

[0095] According to an embodiment of the present invention, power wiring for supplying power to the single height cell SHC is embedded in the substrate 105 in the form of lower power wiring (VPR1 to VPR3). Therefore, the power wiring is omitted in the first metal layer M1. A first wiring M1_I for signal transmission is disposed in the first metal layer M1.

[0096] The first metal layer M1 further includes a first via VI1. The first via VI1 is provided under each of the first wirings M1_I of the first metal layer M1. The active contact AC and the first wiring M1_I of the first metal layer M1 are electrically connected to each other through the first via VI1. The gate contact GC and the first wiring M1_I of the first metal layer M1 are electrically connected to each other through the first via VI1.

[0097] The first wiring M1_I of the first metal layer M1 and the first via VI1 thereunder are formed in separate processes. In other words, the first wiring M1_I of the first metal layer M1 and the first via VI1 are each formed in a single damascene process. The semiconductor device according to this embodiment is formed using a process of less than 20 nm.

[0098] A second metal layer M2 is provided in the fourth interlayer insulating layer 140. The second metal layer M2 includes a plurality of second wirings M2_I. Each of the second wirings M2_I of the second metal layer M2 has a line shape or a bar shape extending in the first direction D1. Again, the second wirings M2_I extend in parallel to each other in the first direction D1.

[0099] The second metal layer M2 further includes a second via VI2 provided under each of the second wirings M2_I. The first wiring M1_I of the first metal layer M1 and the second wiring M2_I of the second metal layer M2 are electrically connected to each other through the second via VI2. For example, the second wiring M2_I of the second metal layer M2 and the second via VI2 thereunder are formed together by a dual damascene process.

[0100] The first wiring M1_I of the first metal layer M1 and the second wiring M2_I of the second metal layer M2 may be the same or may include different conductive materials. For example, the first wiring M1_I of the first metal layer M1 and the second wiring M2_I of the second metal layer M2 may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt. Although not shown, additional metal layers (e.g., M3, M4, M5...) may be disposed on the fourth interlayer insulating film 140. Each of the stacked metal layers includes a wiring for routing between cells.

[0101] The semiconductor device according to the embodiment of the present invention forms buried spacers (BSP1, BSP2) to prevent leakage current from the channel patterns (CH1, CH2). The leakage current occurs when current carriers generated by a tunnel effect move through a layer of a silicon substrate below the channel patterns (CH1, CH2). The buried spacers (BSP1, BSP2) are a barrier film including an insulating material between the channel patterns (CH1, CH2) and the silicon layer 100, and can prevent the generation of such leakage current. In addition, the buried spacers (BSP1, BSP2) can prevent a short phenomenon between the source / drain patterns (SD1, SD2). Therefore, the leakage current from the transistor to the semiconductor substrate is prevented, and the electrical characteristics of the semiconductor device can be improved by preventing the short phenomenon.

[0102] The semiconductor device according to the embodiment of the present invention can prevent a short phenomenon occurring between the back contacts (BDC1, BDC2) connected to the source / drain patterns (SD1, SD2) and the gate electrode GE through the buried spacers (BSP1, BSP2). As a result, the electrical characteristics of the semiconductor device to which the lower power wiring of the present invention is applied can be improved.

[0103] 6A to 16D are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11A, FIG. 12A, FIG. 13A, FIG. 14A, FIG. 15A, and FIG. 16A are cross-sectional views corresponding to the line A-A' in FIG. 4. FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, FIG. 10B, FIG. 11B, FIG. 12B, FIG. 13B, FIG. 14B, FIG. 15B, and FIG. 16B are cross-sectional views corresponding to the line B-B' in FIG. 4. FIG. 8C, FIG. 11C, FIG. 12C, FIG. 13C, FIG. 14C, FIG. 15C, and FIG. 16C are cross-sectional views corresponding to the line C-C' in FIG. 4. FIG. 11D, FIG. 14D, FIG. 15D, and FIG. 16D are cross-sectional views corresponding to the line D-D' in FIG. 4. 6C, 7C, 13D, and 14E are cross-sectional views corresponding to the line EE' in FIG.

[0104] 6A to 6C, a semiconductor substrate 100 including first and second PMOSFET regions (PR1, PR2) and first and second NMOSFET regions (NR1, NR2) is provided. For example, the semiconductor substrate 100 is a silicon wafer. A preliminary dopant layer DEL containing impurities is formed on the semiconductor substrate 100. The preliminary dopant layer DEL is a doped-Si layer based on the silicon wafer.

[0105] Specifically, forming the preliminary dopant layer DEL includes performing a selective epitaxial growth (SEG) process on the semiconductor substrate 100. During the SEG process, impurities (e.g., fluorine (F), argon (Ar), oxygen (O), nitrogen (N), or a combination thereof) are implanted in-situ. The preliminary dopant layer DEL formed on the semiconductor substrate 100 includes silicon doped with fluorine (F), argon (Ar), oxygen (O), nitrogen (N), or a combination thereof. The concentration of impurities (oxygen, carbon, or a combination thereof) in the preliminary dopant layer DEL is 0.5 at% to 2 at%.

[0106] A first semiconductor layer ACL and a second semiconductor layer SAL are formed on the preliminary dopant layer DEL, the first semiconductor layer ACL including one of silicon (Si), germanium (Ge) and silicon-germanium (SiGe), and the second semiconductor layer SAL including the other one of silicon (Si), germanium (Ge) and silicon-germanium (SiGe).

[0107] The second semiconductor layer SAL includes a material having an etching selectivity with respect to the first semiconductor layer ACL. For example, the first semiconductor layer ACL includes silicon (Si), and the second semiconductor layer SAL includes silicon-germanium (SiGe). The concentration of germanium (Ge) in each of the second semiconductor layers SAL is 10 at% to 50 at%.

[0108] Mask patterns are formed on the first and second PMOSFET regions PR1, PR2 and the first and second NMOSFET regions NR1, NR2 of the semiconductor substrate 100. The mask patterns have a line shape or a bar shape extending in a second direction D2.

[0109] A patterning process is performed using the mask pattern as an etching mask to form trenches TR defining a first active pattern PAP1 and a second active pattern PAP2. The first active pattern PAP1 is formed on each of the first and second PMOSFET regions PR1 and PR2. The second active pattern PAP2 is formed on each of the first and second NMOSFET regions NR1 and NR2. In a plan view, the first and second active patterns PAP1 and PAP2 have line shapes extending parallel to each other in a second direction D2.

[0110] A stack pattern STP is formed on each of the first and second active patterns (PAP1, PAP2). The stack pattern STP further includes a first semiconductor layer ACL and a second semiconductor layer SAL alternately stacked on the preliminary dopant layer DEL. The stack pattern STP is formed together with the first and second active patterns (PAP1, PAP2) during a patterning process.

[0111] An isolation film ST is formed to fill the trench TR. Specifically, an insulating film covering the first and second active patterns PAP1 and PAP2 and the stack pattern STP is formed on the entire surface of the semiconductor substrate 100. The insulating film is recessed until the stack pattern STP is exposed, and the isolation film ST is formed.

[0112] The isolation film ST includes an insulating material such as a silicon oxide film. The stack pattern STP is exposed on the isolation film ST. Again, the stack pattern STP protrudes vertically onto the isolation film ST.

[0113] 7A to 7C, sacrificial patterns PP are formed across stack patterns STP on a semiconductor substrate 100. Each sacrificial pattern PP is formed in a line shape or a bar shape extending in a first direction D1. The sacrificial patterns PP are arranged in a second direction D2 at a first pitch.

[0114] Specifically, forming the sacrificial pattern PP includes forming a sacrificial film on the entire surface of the semiconductor substrate 100, forming a hard mask pattern MP on the sacrificial film, and patterning the sacrificial film using the hard mask pattern MP as an etching mask. The sacrificial film includes polysilicon.

[0115] A pair of gate spacers GS are formed on both sidewalls of each of the sacrificial patterns PP. Forming the gate spacers GS includes conformally forming a gate spacer film on the entire surface of the semiconductor substrate 100 and anisotropically etching the gate spacer film. The gate spacer film includes at least one of SiCN, SiCON, and SiN. As another example, the gate spacer film is a multi-layer including at least two of SiCN, SiCON, and SiN.

[0116] 8A to 8C, a first recess RS1 is formed in the stack pattern STP on the first active pattern PAP1. A second recess RS2 is formed in the stack pattern STP on the second active pattern PAP2. The first and second recesses (RS1, RS2) are recessed to the top of the preliminary dopant layer DEL. During the formation of the first and second recesses (RS1, RS2), the isolation film ST on both sides of each of the first and second active patterns (PAP1, PAP2) is further recessed (see FIG. 8C).

[0117] Specifically, the stack pattern STP on the first active pattern PAP1 is etched using the hard mask pattern MP and the gate spacer GS as an etching mask to form the first recess RS1. The first recess RS1 is formed between a pair of sacrificial patterns PP. The second recess RS2 in the stack pattern STP on the second active pattern PAP2 is formed in the same manner as the first recess RS1.

[0118] 8C, a fence pattern FNP is formed on each of the first and second active patterns PAP1 and PAP2, and is a part of the remaining gate spacer GS.

[0119] Referring again to FIGS. 8A to 8C, first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) are formed in the first semiconductor layer ACL between adjacent first recesses RS1. First to fourth semiconductor patterns (SP1, SP2, SP3, SP4) are formed in the first semiconductor layer ACL between adjacent second recesses RS2. The first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) between adjacent first recesses RS1 constitute a first channel pattern CH1. The first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) between adjacent second recesses RS2 constitute a second channel pattern CH2.

[0120] 9A and 9B, a first sacrificial spacer PSP1 is formed in each first recess RS1. The first sacrificial spacer PSP1 is formed along the inner wall of the first recess RS1. The first sacrificial spacer PSP1 extends from the inner wall of the first recess RS1 to the side of the gate spacer GS. The first sacrificial spacer PSP1 is a film that prevents loss of the first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) and the second semiconductor layer SAL when an etching process described below is performed. The top surface of the first sacrificial spacer PSP1 is at the same position as the top surface of the sacrificial pattern PP in the third direction D3.

[0121] A second sacrificial spacer PSP2 is formed in each of the second recesses RS2. The second sacrificial spacer PSP2 is formed along the inner wall of the second recess RS2. The second sacrificial spacer PSP2 extends from the inner wall of the second recess RS2 to the side of the gate spacer GS. The second sacrificial spacer PSP2 is a film that prevents loss of the first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) and the second semiconductor layer SAL when an etching process described below is performed. The top surface of the second sacrificial spacer PSP2 is at the same position as the top surface of the sacrificial pattern PP in the third direction D3.

[0122] A pair of first and second sacrificial spacers (PSP1, PSP2) are formed on the inner walls of the first and second recesses (RS1, RS2), respectively. Forming the first and second sacrificial spacers (PSP1, PSP2) includes conformally forming a sacrificial spacer film on the entire surface of the semiconductor substrate 100 and anisotropically etching the sacrificial spacer film (e.g., an etch back process). The etched sacrificial spacer film is the first and second sacrificial spacers (PSP1, PSP2). That is, the first and second sacrificial spacers (PSP1, PSP2) are not formed on the upper part of the preliminary dopant layer DEL.

[0123] The first and second sacrificial spacers (PSP1, PSP2) include silicon oxide or silicon nitride. For example, the first and second sacrificial spacers (PSP1, PSP2) include at least one of SiO, SiCN, SiCON, and SiN. The first and second sacrificial spacers (PSP1, PSP2) have an etching selectivity with respect to the preliminary dopant layer DEL. For example, when the preliminary dopant layer DEL includes silicon doped with fluorine (F), argon (Ar), oxygen (O), or a combination thereof, the first and second sacrificial spacers (PSP1, PSP2) include silicon nitride. As another example, when the preliminary dopant layer DEL includes silicon doped with nitrogen (N), the first and second sacrificial spacers (PSP1, PSP2) include silicon oxide.

[0124] 10A and 10B, an etching process is performed using the hard mask pattern MP and the first and second sacrificial spacers PSP1 and PSP2 as an etching mask to form a third recess ARS1 and a fourth recess ARS2. A third recess ARS1 is formed in the preliminary dopant layer DEL and the first active pattern PAP1. A fourth recess ARS2 is formed in the preliminary dopant layer DEL and the second active pattern PAP2.

[0125] Specifically, the preliminary dopant layer DEL and the first active pattern PAP1 are etched using the hard mask pattern MP and the first and second sacrificial spacers PSP1 and PSP2 as an etching mask to form the third recess ARS1. The etching is performed by performing an anisotropic etching process. The third recess ARS1 is formed between the pair of first sacrificial spacers PSP1. The preliminary dopant layer DEL and the fourth recess ARS2 in the second active pattern PAP2 are formed in the same manner as the third recess ARS1.

[0126] 11A to 11D, a sacrificial plug film PSG is formed in each of the third recesses ARS1. A sacrificial plug film PSG is formed in each of the fourth recesses ARS2. The sacrificial plug film PSG is formed in the first active pattern PAP1 and the second active pattern PAP2. In other words, the sacrificial plug film PSG fills the third recess ARS1 and the fourth recess ARS2.

[0127] Buried spacers BSP are formed on both sides of the sacrificial plug film PSG. The buried spacers BSP are spaced apart from each other via the sacrificial plug film PSG. The buried spacers BSP have a symmetrical shape in the second direction D2. The buried spacers BSP are formed under the first semiconductor pattern SP1.

[0128] A part of the preliminary dopant layer DEL remains after the sacrificial plug film PSG and the buried spacer BSP are formed. The remaining preliminary dopant layer (DEL in FIG. 10A) is the dopant layer DEP. The dopant layer DEP is interposed between the buried spacers BSP.

[0129] 17 to 20 are enlarged views for explaining a method of forming the N region in FIG. 11A.

[0130] 17, a deposition process is performed in the third recess ARS1 as described above to form the pre-fill spacer PBSP and the pre-film SOL. For example, the deposition process may be a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process.

[0131] The deposition process is an oxidation process. As an example, when the pre-dopant layer DEL includes silicon doped with fluorine (F), argon (Ar), oxygen (O), or a combination thereof, the pre-buried spacer PBSP includes SiOx or SiOF. The pre-film SOL is SiOx.

[0132] As another example, the deposition process is a nitridation process. When the pre-dopant layer DEL includes silicon doped with nitrogen (N), the pre-buried spacer PBSP includes SiNy, SiON, SiOCN, or SiCN. The pre-film SOL is SiNy.

[0133] Specifically, a preliminary film SOL is formed in the adjacent third recess ARS1 of the semiconductor substrate 100. A preliminary buried spacer PBSP is formed in the adjacent third recess ARS1 of the preliminary dopant layer DEL. Since the preliminary dopant layer DEL has a higher impurity concentration than the semiconductor substrate 100, when a deposition process is performed, the thickness of the deposited film varies from region to region. In other words, the width of the preliminary buried spacer PBSP in the second direction D2 is larger than the width of the preliminary film SOL in the second direction D2.

[0134] The deposition process is performed so that the pre-buried spacer PBSP is formed faster in the vacant portion of the third recess ARS1 than in the portion adjacent to the semiconductor substrate 100 and the first semiconductor pattern SP1. That is, since the pre-buried spacer PBSP is formed slower at the interface of the third recess ARS1, the pre-buried spacer PBSP bulges toward the dopant layer DEP. The side surface of the pre-buried spacer PBSP is curved.

[0135] Referring to FIG. 18, an etching process is performed on the pre-buried spacer PBSP and the preliminary film SOL to form a buried spacer BSP. The etching process is performed using the first sacrificial spacer PSP1 as a mask. The etching process is a wet etching process or a dry etching process. As an example, when the pre-buried spacer PBSP includes SiOx or SiOF, the etchant for the etching process is HF gas. As another example, when the pre-buried spacer PBSP includes SiNy, SiON, SiOCN, or SiCN, the etchant for the etching process is phosphoric acid (H 3 PO 4) solution. By performing an etching process, the preliminary film SOL is entirely removed, and the preliminary embedded spacer PBSP is only partially removed.

[0136] 19, after the buried spacer BSP is formed, a sacrificial plug film PSG is formed in the third recess ARS1. The formation of the sacrificial plug film PSG includes performing a selective epitaxial growth (SEG) process using the semiconductor substrate 100 as a seed. The sacrificial plug film PSG includes one of silicon, germanium, and silicon-germanium. Preferably, the sacrificial plug film PSG includes silicon-germanium.

[0137] 20, after the sacrificial plug film PSG is formed, the first sacrificial spacer PSP1 is removed. The first sacrificial spacer PSP1 is removed by performing an etching process. The etching process is a wet etching process or a dry etching process. An etchant in the etching process is a material having an etching selectivity for the first sacrificial spacer PSP1 compared to the sacrificial plug film PSG. That is, the first sacrificial spacer PSP1 is removed by performing an etching process while leaving the sacrificial plug film PSG. The second sacrificial spacer PSP2 is removed in the same manner as the first sacrificial spacer PSP1.

[0138] 12A to 12C, a first source / drain pattern SD1 is formed in each of the first recesses RS1. The first source / drain pattern SD1 is formed on the sacrificial plug film PSG. Specifically, a first SEG process is performed using the inner wall of the first recess RS1 as a seed layer to form a buffer layer BFL. The buffer layer BFL is grown using the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4 exposed by the first recess RS1 and the sacrificial plug film PSG as seeds. As an example, the first SEG process includes a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0139] The buffer layer BFL includes a semiconductor element (e.g., SiGe) having a lattice constant larger than that of the semiconductor element of the semiconductor substrate 100. The buffer layer BFL includes a relatively low concentration of germanium GE. In another embodiment of the present invention, the buffer layer BFL includes only silicon (Si) without germanium (Ge). The concentration of germanium GE in the buffer layer BFL is 0 at% to 30 at%.

[0140] A second SEG process is performed on the buffer layer BFL to form a main layer MAL. The main layer MAL is formed to completely or substantially fill the first recess RS1. The main layer MAL contains a relatively high concentration of germanium GE. For example, the concentration of germanium GE in the main layer MAL is 30 at% to 70 at%.

[0141] In one embodiment of the present invention, a capping layer is formed on the main layer MAL by performing a third SEG process. The capping layer includes silicon (Si). The concentration of silicon (Si) in the capping layer is 98 at% to 100 at%.

[0142] During the formation of the buffer layer BFL and the main layer MAL, impurities (e.g., boron, gallium, or indium) that cause the first source / drain pattern SD1 to have a p-type are implanted in-situ. As another example, after the first source / drain pattern SD1 is formed, impurities are implanted into the first source / drain pattern SD1.

[0143] A second source / drain pattern SD2 is formed in each of the second recesses RS2. The second source / drain pattern SD2 is formed on the sacrificial plug layer PSG. Specifically, the second source / drain pattern SD2 is formed by performing a selective epitaxial growth (SEG) process using the inner wall of the second recess RS2 as a seed layer. As an example, the second source / drain pattern SD2 includes the same semiconductor element (e.g., Si) as the semiconductor substrate 100.

[0144] During the formation of the second source / drain pattern SD2, impurities (e.g., phosphorus, arsenic, or antimony) that cause the second source / drain pattern SD2 to have n-type conductivity are implanted in-situ. As another example, after the second source / drain pattern SD2 is formed, impurities are implanted into the second source / drain pattern SD2.

[0145] In one embodiment of the present invention, before forming the second source / drain pattern SD2, a portion of the second semiconductor layer SAL exposed through the second recess RS2 is replaced with an insulating material to form an inner spacer IP. As a result, the inner spacer IP is formed between the second source / drain pattern SD2 and the second semiconductor layer SAL.

[0146] 13A to 13D, a first interlayer insulating film 110 is formed to cover the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS. As an example, the first interlayer insulating film 110 includes a silicon oxide film.

[0147] The first interlayer insulating film 110 is planarized until the top surface of the sacrificial pattern PP is exposed. The planarization of the first interlayer insulating film 110 is performed using an etch back or CMP (Chemical Mechanical Polishing) process. During the planarization process, the hard mask pattern MP is entirely removed. As a result, the top surface of the first interlayer insulating film 110 is coplanar with the top surfaces of the sacrificial pattern PP and the gate spacer GS.

[0148] A region of the sacrificial pattern PP is selectively opened using photolithography. For example, the region of the sacrificial pattern PP on the third and fourth boundaries (BD3, BD4) of the first single height cell SHC1 is selectively opened. The opened region of the sacrificial pattern PP is selectively etched and removed. An insulating material is filled in the space from which the sacrificial pattern PP is removed to form a gate cutting pattern CT (see FIG. 13D).

[0149] The exposed sacrificial pattern PP is selectively removed. By removing the sacrificial pattern PP, an outer region ORG exposing the first and second channel patterns CH1 and CH2 is formed (see FIG. 13D). The removal of the sacrificial pattern PP includes wet etching using an etchant that selectively etches polysilicon.

[0150] The second semiconductor layer SAL exposed through the outer region ORG is selectively removed to form the inner region IRG (see FIG. 13D). Specifically, an etching process is performed to selectively etch the second semiconductor layer SAL, thereby removing only the second semiconductor layer SAL while leaving the first to third semiconductor patterns (SP1, SP2, SP3) as they are. The etching process has a high etching rate for silicon-germanium having a relatively high germanium concentration. For example, the etching process has a high etching rate for silicon-germanium having a germanium concentration greater than 10 at %.

[0151] During the etching process, the second semiconductor layer SAL on the first and second PMOSFET regions PR1, PR2 and the first and second NMOSFET regions NR1, NR2 is completely removed. The etching process is a wet etching process. An etching material used in the etching process quickly removes the second semiconductor layer SAL having a relatively high germanium concentration. Meanwhile, the first source / drain pattern SD1 on the first and second PMOSFET regions PR1, PR2 is protected during the etching process by the buffer layer BFL having a relatively low germanium concentration.

[0152] Referring again to FIG. 13D, the second semiconductor layer SAL is selectively removed, so that only the stacked first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) remain on the first and second active patterns (PAP1, PAP2). First to third inner regions (IRG1, IRG2, IRG3) are formed through the regions from which the second semiconductor layer SAL has been removed. Specifically, a first inner region IRG1 is formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a second inner region IRG2 is formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a third inner region IRG3 is formed between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4.

[0153] 14A to 14E, a gate insulating film GI is conformally formed on the exposed first to fourth semiconductor patterns (SP1, SP2, SP3, SP4). A gate electrode GE is formed on the gate insulating film GI. The gate electrode GE includes first to third inner electrodes (PO1, PO2, PO3) formed in the first to third inner regions (IRG1, IRG2, IRG3), respectively, and an outer electrode PO4 formed in the outer region ORG.

[0154] The gate electrode GE is recessed to reduce its height. While the gate electrode GE is recessed, the upper portion of the gate cutting pattern CT is also slightly recessed. A gate capping pattern GP is formed on the recessed gate electrode GE.

[0155] A second interlayer insulating film 120 is formed on the first interlayer insulating film 110. The second interlayer insulating film 120 includes a silicon oxide film. An active contact AC is formed through the second interlayer insulating film 120 and the first interlayer insulating film 110 and electrically connected to at least one of the first and second source / drain patterns SD1 and SD2. A gate contact GC is formed through the second interlayer insulating film 120 and the gate capping pattern GP and electrically connected to the gate electrode GE.

[0156] Forming the active contacts AC and the gate contacts GC includes forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM is conformally formed and includes a metal film / metal nitride film. The conductive pattern FM includes a low resistance metal.

[0157] 4 and 5A to 5E again, a third interlayer insulating film 130 is formed on the active contacts AC and the gate contacts GC. A first metal layer M1 is formed in the third interlayer insulating film 130. The first metal layer M1 includes a first wiring M1_I electrically connected to at least one of the active contacts AC and the gate contacts GC. A fourth interlayer insulating film 140 is formed on the third interlayer insulating film 130. A second metal layer M2 is formed in the fourth interlayer insulating film 140.

[0158] 15A to 15D, after the BEOL process is completed, the semiconductor substrate 100 is turned upside down to expose the bottom surface of the semiconductor substrate 100. The exposed semiconductor substrate 100 is removed to expose the sacrificial plug film PSG. In other words, a part of the semiconductor substrate 100 is removed.

[0159] In one embodiment of the present invention, removing the semiconductor substrate 100 includes performing a planarization process (SAF) on the bottom surface of the semiconductor substrate 100 to reduce the thickness of the semiconductor substrate 100, and performing a cleaning process to selectively remove silicon (Si) on the semiconductor substrate 100. The cleaning process is performed until the sacrificial plug layer PSG and the device isolation layer ST are exposed. After the cleaning process is performed, the bottom surface of the exposed sacrificial plug layer PSG and the bottom surface of the exposed device isolation layer ST are substantially coplanar.

[0160] 16A to 16D, the exposed sacrificial plug film PSG is removed by performing an etching process. Only the sacrificial plug film PSG is selectively removed using an etchant that does not remove the element isolation film ST and the remaining semiconductor substrate 100. An insulating material is filled in the area from which the sacrificial plug film PSG and the semiconductor substrate 100 have been removed, to form the substrate 105. The substrate 105 includes an insulating layer of a silicon substrate. The substrate 105 includes a first insulating pattern AP1 and a second insulating pattern AP2. After the sacrificial plug film PSG is removed, the filled portion is the protruding portion PJ of the substrate 105 described above. The portion outside the protruding portion PJ is the horizontal portion HZ of the substrate 105 described above.

[0161] A mask pattern is formed on the substrate 105. The mask pattern is formed through a photolithography process. An anisotropic etching process is performed on the substrate 105 using the mask pattern as an etching mask to form first and second rear contact holes BCH1 and BCH2. The first rear contact hole BCH1 exposes the first source / drain pattern SD1. The second rear contact hole BCH2 exposes the second source / drain pattern SD2.

[0162] A liner pattern LIN is formed on each of the inner walls of the first and second back contact holes BCH1 and BCH2. The liner pattern LIN is formed in a spacer shape. The liner pattern LIN is made of a silicon-based insulating material (e.g., SiO, SiN, SiOC, or SiOCN). Preferably, the liner pattern LIN includes silicon nitride (SiN).

[0163] 4 and 5A to 5E again, the first and second back contact holes (BCH1, BCH2) are filled with metal to form contact plugs PCP and contact portions SEC. A metal-semiconductor compound layer SC is formed between the contact portions SEC and the source / drain patterns (SD1, SD2). The metal-semiconductor compound layer SC, contact portions SEC, and contact plugs PCP in the first back contact hole BCH1 constitute a first back contact BDC1. The metal-semiconductor compound layer SC, contact portions SEC, and contact plugs PCP in the second back contact hole BCH2 constitute a second back contact BDC2.

[0164] Lower power wirings (VPR1 to VPR3) are formed on the substrate 105. The lower power wirings (VPR1 to VPR3) are connected to at least one of the first and second rear contacts (BDC1, BDC2). Specifically, the lower power wirings (VPR1 to VPR3) are connected to the first and second rear contacts (BDC1, BDC2) through via parts VVI. A power transmission network layer PDN is formed on the lower power wirings (VPR1 to VPR3). The power transmission network layer PDN is formed to apply a source voltage or a drain voltage to the lower power wirings (VPR1 to VPR3).

[0165] Although the embodiment of the present invention has been described in detail above with reference to the drawings, the present invention is not limited to the above-mentioned embodiment and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0166] 100 Silicon Layer 105 (insulating) board 110, 120, 130, 140: first to fourth interlayer insulating films AC Active Contact ACL 1st semiconductor layer AP1, AP2 1st and 2nd insulation patterns ARS1, ARS2 3rd and 4th recesses BCH1, BCH2 1st and 2nd rear contact holes BD1, BD2, BD3, BD4 1st to 4th boundaries BDC1, BDC2 1st and 2nd rear contacts BFL Buffer Layer BM Barrier Pattern BS bottom BSC1, BSC2 1st and 2nd rear contacts BSP embedded spacer BSP1, BSP2 First and second embedded spacers CH1, CH2 1st and 2nd channel patterns CL1, CL2, CL3 1st to 3rd center line CT Gate Cutting Pattern DB separation structure DEL preliminary dopant layer DEP dopant layer DHC Double Height Cell FM Conductive Pattern FNP fence pattern GC Gate Contact GE gate electrode GI Gate Insulator GS Gate Spacer GP Gate Capping Pattern HZ horizontal part IP Inner Spacer IRG inner region IRG1, IRG2, IRG3 1st to 3rd inner area LIN Liner pattern M1, M2 1st, 2nd metal layer M1_I, M2_I 1st and 2nd wiring MAL Main Layer MP hard mask pattern NR NMOSFET area NR1, NR2 1st, 2nd NMOSFET area ORG outer area P1, P2 1st and 2nd Part PAP1, PAP2 1st and 2nd activation patterns PBSP Pre-embedded spacer PCP Contact Plug PDN Power Transmission Network Layer PJ protrusion PO1, PO2, PO3 1st to 3rd inner electrode PO4 outer electrode PP Sacrificial Pattern PR PMOSFET area PR1, PR2 1st, 2nd PMOSFET area PSG sacrificial plug membrane PSP1, PSP2 1st and 2nd sacrificial spacers RS1, RS2 1st and 2nd recesses SAF planarization process SAL Second semiconductor layer SC Metal-semiconductor compound layer SD1, SD2 1st and 2nd source / drain patterns SEC contact part SHC Single Height Cell SHC1, SHC2 1st and 2nd single height cells SOL spare film SP1, SP2, SP3, SP4 1st to 4th semiconductor patterns ST element separation membrane STP stacking pattern SW side wall SW1, SW2, SW3, SW4 1st to 4th sides TR Trench TS top surface UIP Upper Insulation Pattern VDD Drain voltage (power voltage) VI1, VI2 1st and 2nd vias VPR1, VPR2, VPR3 1st to 3rd lower power wiring VSS Source voltage (ground voltage) VVI via section

Claims

1. An insulating substrate; a silicon layer on the insulating substrate; a dopant layer on the silicon layer; embedded spacers on the sides of the dopant layer; a channel pattern on the dopant layer; a source / drain pattern on the buried spacer; a gate electrode on the channel pattern; a lower power wiring on a lower portion of the insulating substrate; a back contact penetrating the insulating substrate and the silicon layer to electrically connect the lower power wiring and the source / drain pattern to each other; The channel pattern includes a plurality of semiconductor patterns stacked and spaced apart from each other, the source / drain pattern is connected to the channel pattern; the gate electrode includes a plurality of inner electrodes each interposed between the plurality of semiconductor patterns, A semiconductor device, comprising: a back contact having a side surface contacting the silicon layer and the buried spacer.

2. The back contact is a metal-semiconductor compound layer connected to a lower portion of the source / drain pattern; a contact provided beneath said metal-semiconductor compound layer; a contact plug connected to the lower power wiring; 2. The semiconductor device of claim 1, further comprising: a liner pattern on each side of the contact portion and the contact plug.

3. The semiconductor device of claim 2 , wherein the contact plug is connected to a via portion of the lower power wiring.

4. The semiconductor device according to claim 3 , wherein the width of the contact plug is smaller than the width of the contact portion.

5. The semiconductor element according to claim 4 , wherein the side surface of the contact portion is curved.

6. The semiconductor element according to claim 2 , wherein a side surface of the contact portion bulges toward the embedded spacer.

7. 5. The semiconductor device of claim 4, wherein the width of the contact portion gradually increases and then decreases over a predetermined vertical distance.

8. The semiconductor device according to claim 3 , wherein the via portion vertically overlaps the contact portion and the buried spacer.

9. The semiconductor device of claim 3 , wherein the width of the via portion increases toward the lower power wiring.

10. an insulating substrate including a horizontal portion and a protruding portion; a silicon layer on the insulating substrate; a dopant layer on the silicon layer; a first embedded spacer and a second embedded spacer on opposite sides of the dopant layer, respectively; a channel pattern on the dopant layer; a first source / drain pattern and a second source / drain pattern connected to both sides of the channel pattern; a gate electrode on the channel pattern; a lower power wiring on a lower portion of the insulating substrate; a back contact penetrating the insulating substrate and the silicon layer to electrically connect the lower power wiring and the first source / drain pattern to each other; the protrusion contacts a lower portion of the second source / drain pattern; the silicon layer is interposed between the protrusion and the back contact; a first side of the first buried spacer contacting the back contact; a second side surface of the second embedded spacer contacts the protrusion; 13. A semiconductor device comprising: a first buried spacer and a second buried spacer, the first buried spacer and the second buried spacer including an insulating material having a dielectric constant lower than that of silicon oxide.

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