Semiconductor package and manufacturing method of the same

Abstract

To provide a semiconductor package which minimizes the total thickness of the package and maximizes heat dissipation characteristics, and to provide a manufacturing method of the semiconductor package.SOLUTION: A semiconductor package according to the invention includes: a rewiring board; a first semiconductor chip provided on a right side in a first direction of the rewiring board; through posts provided at a left side in the first direction on the rewiring board and located adjacent to the first semiconductor chip; a heat dissipation chip provided on the first semiconductor chip; and a second semiconductor chip disposed adjacent to the heat dissipation chip on the through posts. The heat dissipation chip is laminated on the first semiconductor chip through metal pads and an adhesion layer.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package including a rewiring substrate below a semiconductor chip and a method for manufacturing the same. [Background technology]

[0002] 2. Description of the Related Art With the rapid development of the electronics industry and the demands of users, electronic devices are becoming smaller and lighter. 2. Description of the Related Art As electronic devices become smaller and lighter, the semiconductor packages used therein are also becoming smaller and lighter. Furthermore, the semiconductor packages are required to have high reliability as well as high performance and large capacity.

[0003] As such semiconductor packages become more sophisticated and have higher capacities, the power consumption of the semiconductor packages increases. As a result, the heat dissipation characteristics of semiconductor packages are becoming increasingly important in response to the size and performance of the semiconductor packages, and improving these characteristics has become a challenge. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned problems in conventional semiconductor packages, and an object of the present invention is to provide a semiconductor package and a manufacturing method thereof that minimizes the overall thickness of the package and maximizes heat dissipation characteristics. [Means for solving the problem]

[0005] In order to achieve the above-mentioned object, a semiconductor package according to the present invention comprises a rewiring substrate, a first semiconductor chip arranged on the right side in a first direction on the rewiring substrate, a through post arranged on the left side in the first direction on the rewiring substrate adjacent to the first semiconductor chip, a heat dissipation chip arranged on the first semiconductor chip, and a second semiconductor chip arranged on the through post adjacent to the heat dissipation chip, wherein the heat dissipation chip is stacked on the first semiconductor chip via a metal pad and an adhesive layer.

[0006] In addition, a semiconductor package according to the present invention, which has been made to achieve the above-mentioned object, is characterized by having a rewiring board having multi-layer wiring lines, a first semiconductor chip stacked on the rewiring board on the right side in a first direction via a first bump, a through post arranged on the rewiring board on the left side in the first direction adjacent to the first semiconductor chip, a sealing material arranged on the rewiring board, surrounding the first semiconductor chip and the through post and exposing upper surfaces of the first semiconductor chip and the through post, a heat dissipation chip stacked on the first semiconductor chip via a metal pad and an adhesive layer, and a second semiconductor chip stacked on the through post adjacent to the heat dissipation chip via a second bump.

[0007] In addition, a semiconductor package according to the present invention, which has been made to achieve the above-mentioned object, is characterized by having a rewiring board having external connection terminals arranged on its underside and having multi-layer wiring lines arranged inside, a first semiconductor chip stacked on the rewiring board on the right side in a first direction via a first bump, a through post adjacent to the first semiconductor chip and arranged on the rewiring board on the left side in the first direction and on a portion of both sides of the first semiconductor chip on the left side in the first direction and in a second direction perpendicular to the first direction, a sealing material arranged on the rewiring board, covering side surfaces of the first semiconductor chip and the through post and exposing upper surfaces of the first semiconductor chip and the through post, a heat dissipation chip stacked on the first semiconductor chip via a metal pad and an adhesive layer, and a second semiconductor chip stacked on the through post adjacent to the heat dissipation chip via a second bump.

[0008] In order to achieve the above object, a method for manufacturing a semiconductor package according to the present invention includes forming alignment metal pads and through posts on a first carrier substrate, stacking a first semiconductor chip on the alignment metal pads with an active surface facing the first carrier substrate, forming an encapsulant surrounding the through posts and the first semiconductor chip, bonding a second carrier substrate to the through posts and an inactive surface of the first semiconductor chip and removing the first carrier substrate, grinding the encapsulant to expose a first surface of the through posts and a first bump of the first semiconductor chip, forming a redistribution substrate on the first surface of the through posts and the first bump of the first semiconductor chip, bonding the redistribution substrate to a film ring mount and removing the second carrier substrate, stacking a second semiconductor chip on a second surface of the through posts opposite to the first surface, and stacking a heat dissipation chip adjacent to the second semiconductor chip on the inactive surface of the first semiconductor chip via a metal pad and an adhesive layer. Effect of the Invention

[0009] According to the semiconductor package and the manufacturing method thereof of the present invention, the heat dissipation effect of the first semiconductor chip is maximized by disposing the heat dissipation chip on the upper surface of the first semiconductor chip, which is an SoC, through the heat dissipation connection part. In addition, since the sealing material is formed to a low thickness of 100 μm or less, warpage control is easy and the overall thickness of the package is reduced. Moreover, the first semiconductor chip is placed on the rewiring substrate in a self-aligned manner. This allows the rewiring lines in the rewiring substrate to be designed to have fine lines and spaces (L / S). [Brief description of the drawings]

[0010] [Figure 1A]1 is a plan view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention; [Figure 1B] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention; [Figure 1C] FIG. 2 is an enlarged cross-sectional view of part A in FIG. 1B. [Diagram 2] FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor package according to another embodiment of the present invention. [Diagram 3] FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor package according to another embodiment of the present invention. [Figure 4A] FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor package according to another embodiment of the present invention. [Figure 4B] 4B is a cross-sectional view showing a schematic configuration of a third semiconductor chip in FIG. 4A. [Diagram 5] FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor package according to another embodiment of the present invention. [Figure 6] FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor package according to another embodiment of the present invention. [Figure 7] FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor package according to another embodiment of the present invention. [Figure 8A] 2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor package of FIG. 1B according to an embodiment of the present invention. [Figure 8B] 2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor package of FIG. 1B according to an embodiment of the present invention. [Figure 8C] 2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor package of FIG. 1B according to an embodiment of the present invention. [Figure 8D] 2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor package of FIG. 1B according to an embodiment of the present invention. [Figure 8E] 2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor package of FIG. 1B according to an embodiment of the present invention. [Figure 8F] 2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor package of FIG. 1B according to an embodiment of the present invention. [Figure 8G] 2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor package of FIG. 1B according to an embodiment of the present invention. [Figure 8H] 2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor package of FIG. 1B according to an embodiment of the present invention. [Figure 8I] 2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor package of FIG. 1B according to an embodiment of the present invention. [Figure 8J] 2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor package of FIG. 1B according to an embodiment of the present invention. [Figure 8K] 2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor package of FIG. 1B according to an embodiment of the present invention. [Figure 9] FIG. 8E is a plan view of the semiconductor package at the stage of FIG. 8D. [Figure 10A] FIG. 8B is a cross-sectional view for more specifically illustrating the stage of FIG. 8A. [Figure 10B] FIG. 8B is a cross-sectional view for more specifically explaining the stage of FIG. 8A. [Figure 10C] FIG. 8B is a cross-sectional view for more specifically explaining the stage of FIG. 8A. [Figure 10D] FIG. 8B is a cross-sectional view for more specifically illustrating the stage of FIG. 8A. [Figure 10E] FIG. 8B is a cross-sectional view for more specifically illustrating the stage of FIG. 8A. [Figure 10F] FIG. 8B is a cross-sectional view for more specifically illustrating the stage of FIG. 8A. [Figure 10G] FIG. 8B is a cross-sectional view for more specifically explaining the stage of FIG. 8A. [Figure 10H] FIG. 8B is a cross-sectional view for more specifically illustrating the stage of FIG. 8A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, a specific example of an embodiment for carrying out a semiconductor package and a manufacturing method thereof according to the present invention will be described with reference to the drawings. The same reference numerals are used in the drawings to refer to the same components, and duplicate descriptions thereof will be omitted.

[0012] 1A to 1C are a plan view and a cross-sectional view showing a schematic configuration of a semiconductor package according to one embodiment of the present invention. 1B is a cross-sectional view taken along line II' in FIG. 1A, and FIG. 1C is an enlarged cross-sectional view of part A in FIG. 1B. 1A to 1C, the semiconductor package 100 of the present embodiment includes a redistribution substrate 100, a first semiconductor chip 120, a through post 130, a second semiconductor chip 140, a heat dissipation chip 150, a heat dissipation connection part 160, and an encapsulant 170.

[0013] The redistribution substrate 100 is disposed below the first semiconductor chip 120 , the through posts 130 , and the sealant 170 . The redistribution substrate 100 serves to redistribute the chip pads of the first semiconductor chip 120 to an external region of the first semiconductor chip 120 . The redistribution substrate 110 includes a body insulating layer 112 , redistribution lines 114 , and vias 116 .

[0014] The body insulating layer 112 is made of an insulating material, for example, a photo imageable dielectric (PID) or a photo imageable polyimide (PIP) resin, and further contains an inorganic filler. However, the material of the body insulating layer 112 is not limited to the above-mentioned materials. For example, the body insulating layer 112 may include Polyimide Isoindro Quirazorindione (PIQ), Polyimide (PI), Polybenzoxazole (PBO), and the like. The body insulating layer 112 has a multi-layer structure due to the multi-layer structure of the redistribution line 114 . However, in FIG. 1, for convenience, the body insulating layer 112 is shown as having a single layer structure. On the other hand, when the body insulating layer 112 has a multi-layer structure, all layers of the body insulating layer 112 may be made of the same material, or at least one layer may be made of a different material.

[0015] The redistribution lines 114 are disposed in multiple layers within the body insulating layer 112 . Redistribution lines 114 disposed on other layers are connected to each other by vias 116 . The redistribution lines 114 and the vias 116 are made of, for example, copper (Cu). However, the material of the redistribution line 114 and the via 116 is not limited to Cu. An external connection terminal 115 is disposed on the lower surface of the body insulating layer 112 . The external connection terminal 115 is disposed on an external connection pad formed on the lower surface of the body insulating layer 112 . The external connection pads are included as part of the redistribution lines 114 . However, in some embodiments, the external connection pads may be treated as separate components from the redistribution lines 114.

[0016] The external connection terminal 115 is electrically connected to the redistribution line 114 through an external connection pad. Therefore, the external connection terminals 115 are electrically connected to the first semiconductor chip 120 via the rewiring lines 114 of the rewiring substrate 110 and the first bumps 125 . Furthermore, the external connection terminals 115 can connect the semiconductor package 100 to a package substrate of an external system or a main board of an electronic device such as a mobile phone. The external connection terminals 115 include a conductive material, for example, at least one of solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). However, the material of the external connection terminal 115 is not limited to the above-mentioned substances.

[0017] The external connection terminals 115 are arranged on a first lower surface portion of the rewiring substrate 110 corresponding to the lower surface of the first semiconductor chip 120, and a second lower surface portion of the rewiring substrate 110 that extends outward in the x-direction from the first lower surface portion. Such a package structure in which external connection terminals 115 are arranged in an area larger than the bottom surface of first semiconductor chip 120 is called a fan-out (FO) package structure. Meanwhile, a package structure in which external connection terminals 115 are arranged only on a portion corresponding to the bottom surface of first semiconductor chip 120 is called a fan-in (FI) package structure.

[0018] The first semiconductor chip 120 is mounted on the rewiring substrate 110 via first bumps 125 . The first bump 125 includes a metal pillar. In some embodiments, the first bump 125 includes a metal pillar and solder. Here, the metal pillar contains, for example, Cu. However, the material of the metal pillar is not limited to Cu. The first semiconductor chip 120 is disposed on the rewiring substrate 110, offset toward one side in the x direction. For example, as shown in FIG. 1, the first semiconductor chip 120 is disposed on the redistribution substrate 110, offset to the right in the x direction. In addition, since the first semiconductor chip 120 is disposed to the right in the x direction, the heat dissipation chip 150 on the upper part of the first semiconductor chip 120 is also disposed to the right. This arrangement is intended to effectively dissipate heat generated by the first semiconductor chip 120.

[0019] The first semiconductor chip 120 may be an analog chip. The first semiconductor chip 120 may include a plurality of logic elements therein. Here, the logic element is an element that performs various signal processes and may include, for example, AND, OR, NOT, flip-flop, and the like. Logic elements may also include elements for supporting communications. In the semiconductor package 100 of the present embodiment, the first semiconductor chip 120 may be, for example, an AP (Application Processor) chip. Depending on its function, the first semiconductor chip 120 is also referred to as a control chip, a process chip, a CPU chip, etc. In terms of integrated functions, the first semiconductor chip 120 is also referred to as a System on Chip (SoC). Meanwhile, according to an embodiment, a device supporting communication is provided separately as another chip, for example, a modem chip, and is disposed on the redistribution substrate 110 in a structure in which it is coupled to the first semiconductor chip. An embodiment relating to a semiconductor package having such a structure will be described in further detail in the description of Figures 4A and 4B.

[0020] The first semiconductor chip 120 includes a substrate and multiple wiring layers. Meanwhile, an integrated circuit layer is formed on the active surface of the substrate. The integrated circuit layer includes a plurality of logic elements. The multiple wiring layer is disposed on the bottom surface of the substrate and includes multiple layers of wiring. In the first semiconductor chip 120, the lower surface is a front surface that is an active surface, and the upper surface is a back surface that is a non-active surface. That is, the lower surface of the substrate on which the multiple wiring layers are arranged corresponds to the front surface of the first semiconductor chip 120, and the upper surface of the substrate corresponds to the rear surface of the first semiconductor chip 120.

[0021] The through post 130 is disposed between the rewiring substrate 110 and the second semiconductor chip 140 . Meanwhile, a sealant 170 is disposed between the rewiring substrate 110 and the second semiconductor chip 140 . Thus, the through post 130 has a structure that extends through the sealing material 170 . The through posts 130 electrically connect the rewiring substrate 110 and the second semiconductor chip 140 . For example, the lower surface of the through post 130 is connected to the rewiring line 114 of the rewiring substrate 110 , and the upper surface of the through post 130 is connected to the second semiconductor chip 140 via the second bump 145 .

[0022] The through post 130 includes, for example, Cu. Thereby, the through-posts 130 are referred to as Cu-posts. However, the material of the through post 130 is not limited to Cu. The through posts 130 are formed through electroplating with a seed metal. The seed metal may include a variety of metal materials, such as, for example, Cu, titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN). In the semiconductor package 100 of the present embodiment, the seed metal is included as a part of the through post 130 . For example, the seed metal is made of Cu, and the through post 130 is also made of Cu. Therefore, the seed metal is not separately shown in FIG.

[0023] A second semiconductor chip 140 is mounted on the through-posts 130 adjacent to the heat dissipating chip 150 . The second semiconductor chip 140 is a memory chip. Thereby, the second semiconductor chip 140 includes a plurality of memory devices therein. The second semiconductor chip 140 may include, for example, a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory device such as a flash memory. In the semiconductor package 100 of the present embodiment, the second semiconductor chip 140 includes, for example, a DRAM element. Meanwhile, in some embodiments, instead of the second semiconductor chip 140, a memory device having a package structure in which a plurality of memory chips are stacked may be stacked on the through-post 130. When the memory devices having a package structure are stacked on the through posts 130, the entire semiconductor package corresponds to a package on package (POP) structure. The POP structure semiconductor package will be described in further detail in the description of FIG.

[0024] The second semiconductor chip 140 is mounted on the through posts 130 via second bumps 145 in a flip-chip bonding structure. For example, the second bumps 145 are disposed between the chip pads of the second semiconductor chip 140 and the upper surfaces of the corresponding through-posts 130 . In some embodiments, post pads are formed on the through posts 130, and second bumps 145 are disposed between the chip pads and the corresponding post pads. Meanwhile, an underfill 147 is filled between the second semiconductor chip 140 and the sealing material 170 and between the second bumps 145 . In some embodiments, the underfill 147 may be omitted.

[0025] The heat dissipating chip 150 is stacked on the first semiconductor chip 120 adjacent to the second semiconductor chip 140 . The heat dissipation chip 150 is stacked on the first semiconductor chip 120 via the heat dissipation connection part 160 . The heat dissipating chip 150 is, for example, a silicon (Si) chip. There may be cases where no elements or wiring are formed inside the heat dissipation chip 150. Generally, the thermal conductivity of Si is higher than that of the resin constituting the sealing material, such as EMC. Therefore, the heat dissipation chip 150 contributes to efficient dissipation of heat generated from the first semiconductor chip 120 .

[0026] The heat dissipation connection 160 includes a metal pad 162 and an adhesive layer 164 . The metal pad 162 is disposed on the bottom surface of the heat dissipating chip 150 and is made of a metal with high thermal conductivity. For example, the metal pads 162 may include Cu, nickel (Ni), aluminum (Al), tin (Sn), gold (Au), silver (Ag), and the like. However, the material of the metal pad 162 is not limited to the above-mentioned metal. Meanwhile, according to an embodiment, the heat dissipating chip 150 includes a passivation layer on a bottom surface thereof, and the metal pad 162 is disposed on the bottom surface of the heat dissipating chip 150 so as to penetrate the passivation layer. The passivation layer is formed of, for example, silicon oxide or silicon nitride.

[0027] The adhesive layer 164 adhesively secures the heat dissipating chip 150 onto the first semiconductor chip 120 . As shown in FIG. 1B, adhesive layer 164 covers metal pads 162 on the underside of heat dissipating chip 150 and protrudes slightly from the sides of heat dissipating chip 150 . Meanwhile, the adhesive layer 164 includes a material with high thermal conductivity in order to efficiently transfer heat from the first semiconductor chip 120 to the metal pad 162 and the heat dissipating chip 150 . For example, the adhesive layer 164 may be made of a thermal interface material (TIM), a thermally conductive resin, a thermally conductive polymer, or SiO 2 The material may be a silicon oxide such as SiCN or a silicon nitride. Here, the TIM may include a material with high thermal conductivity, i.e., low thermal resistance, such as grease, tape, elastomer-filled pads, phase change materials, and the like.

[0028] As shown in FIG. 1C, the metal pad 162 maintains a gap G with the first semiconductor chip 120 . That is, a gap G exists between the lower surface of the metal pad 162 and the upper surface of the first semiconductor chip 120, and the adhesive layer 164 is interposed in the gap G. In the semiconductor package 100 of the present embodiment, the gap G is, for example, 1 μm or less. In this manner, the metal pad 162 and the first semiconductor chip 120 maintain the gap G, and the adhesive layer 164 is interposed in the gap G, thereby relieving stress caused by the difference in thermal expansion coefficient between the metal pad 162 and the first semiconductor chip 120, thereby preventing warpage. On the other hand, if the warp problem is not significant, the bottom surface of the metal pad 162 contacts the top surface of the first semiconductor chip 120 according to the embodiment.

[0029] For reference, in the case of a typical semiconductor package, the first semiconductor chip 120 is surrounded on the top and sides by an encapsulant, and a redistribution substrate is disposed on top, or an upper package is disposed via connection terminals between the substrates. In such a structure, the first semiconductor chip 120 is covered with a sealing material having low thermal conductivity, so that the heat dissipation efficiency is significantly reduced. However, in the case of the semiconductor package 100 of the present embodiment, the top surface of the first semiconductor chip 120 is exposed, and the Si heat dissipation chip 150 is stacked on the first semiconductor chip 120 via the heat dissipation connection part 160, thereby significantly improving heat dissipation efficiency.

[0030] The encapsulant 170 is disposed between the redistribution substrate 110 and the second semiconductor chip 140 and between the redistribution substrate 110 and the heat dissipation chip 150 . The encapsulant 170 covers and seals the side surfaces of the first semiconductor chip 120 . The sealant 170 also covers the sides of the through posts 130 . On the other hand, as shown in FIG. 1B, the sealant 170 fills the gap between the redistribution substrate 110 and the first semiconductor chip 120 and the gap between the first bumps 125 on the lower surface of the first semiconductor chip 120 . However, in some embodiments, an underfill is filled between the first bumps 125 on the underside of the first semiconductor chip 120, and the encapsulant 170 covers the sides of the first semiconductor chip 120 and the underfill.

[0031] The sealant 170 may include an insulating material, for example, a thermosetting resin such as an epoxy resin, or a thermoplastic resin such as a polyimide, or a resin containing a reinforcing material such as an inorganic filler. For example, the sealant 170 may include ABF, FR-4, BT resin, and the like. The encapsulant 170 may also include a molding material such as EMC or a photosensitive material such as a Photo Imageable Encapsulant (PIE). However, the material of the sealant 170 is not limited to the above-mentioned materials.

[0032] As shown in FIG. 1B, the encapsulant 170 encapsulates the first semiconductor chip 120 in a structure that exposes the top surface of the first semiconductor chip 120 . Since the encapsulant 170 has a structure that exposes the top surface of the first semiconductor chip 120, the thickness of the encapsulant 170 is minimized. For example, the sealant 170 has a first thickness H1, and the first thickness H1 is less than or equal to 100 μm. However, the thickness of the sealant 170 is not limited to the above-mentioned numerical range. In this manner, the sealant 170 is formed to a low thickness of 100 μm or less, so that warpage control is easy. For example, by making the encapsulant 170 thinner, stress due to the difference in thermal expansion coefficient between the encapsulant 170 and the first semiconductor chip 120 is reduced, thereby reducing warpage. In addition, since the encapsulant 170 is formed thin, the overall thickness of the semiconductor package 100 is reduced accordingly.

[0033] Referring to FIG. 1A, when the planar sizes and positional relationships of the rewiring substrate 110 and the chips (120, 140, 150) are simply viewed, the rewiring substrate 110 has a size substantially equal to that of the sealing material 170 in a planar view. Therefore, the first semiconductor chip 120 and the through-posts 130 are located within the rewiring substrate 110 in a plan view. Further, the second semiconductor chip 140 and the heat dissipation chip 150 arranged on the first semiconductor chip 120 and the through-post 130 are also located within the rewiring substrate 110 in plan view. Meanwhile, most of the first semiconductor chip 120 is overlapped by the heat dissipation chip 150 , and only a portion of the first semiconductor chip 120 is overlapped by the second semiconductor chip 140 .

[0034] In the semiconductor package 100 of the present embodiment, the heat dissipation chip 150 is disposed on the upper surface of the first semiconductor chip 120, which is an SoC, via the heat dissipation connection part 160, thereby maximizing the heat dissipation effect of the first semiconductor chip 120. In addition, in the semiconductor package 100 of the present embodiment, the sealant 170 is formed to a low thickness of 100 μm or less, which facilitates warpage control and reduces the overall thickness of the package. Meanwhile, signal exchange between the first semiconductor chip 120 and the second semiconductor chip 140 is performed through the second bumps 145 , the through posts 130 , the rewirings 114 of the rewiring substrate 110 , and the first bumps 125 . In the semiconductor package 100 of this embodiment, the thickness of the encapsulant 170 is reduced, so the length of the through-post 130 is also reduced. Therefore, the signal exchange path between the first semiconductor chip 120 and the second semiconductor chip 140 is shortened.

[0035] In the semiconductor package 100 of this embodiment, the first semiconductor chip 120 is placed on the rewiring substrate 110 in a self-aligned manner. This allows the rewiring lines 114 in the rewiring substrate 110 to be designed to have minute line widths and intervals (Line & Space, hereinafter, for example, abbreviated as L / S (μm)). For example, in the rewiring lines 114 of the rewiring substrate 110 of the semiconductor package 100 of this embodiment, the uppermost rewiring lines 114 connected to the first bumps 125 of the first semiconductor chip 120 have a line width and interval of about 2 / 2 μm. Further, the redistribution lines 114 smaller than this have a line width and interval of, for example, about 7 / 8 μm. The self-aligned placement of the first semiconductor chip 120 will be described in further detail in the description of the semiconductor package manufacturing method of FIGS. 8A to 10G.

[0036] FIG. 2 is a cross-sectional view showing a schematic configuration of a semiconductor package according to another embodiment of the present invention. The contents already explained in the explanation of FIGS. 1A to 1C will be explained briefly or omitted. 2, the semiconductor package 100A of the present embodiment differs from the semiconductor package 100 of FIG. 1B in the structure of a heat dissipation chip 150a. Specifically, in the semiconductor package 100A of this embodiment, a plurality of metal lines 155 are disposed inside the heat dissipation chip 150a.

[0037] The metal line 155 is, for example, a through via that passes vertically through the heat dissipating chip 150a. The metal line 155 includes a metal with high thermal conductivity. For example, the metal line 155 may include Cu, Ni, Al, Sn, Au, Ag, etc. However, the material of the metal line 155 is not limited to the above-mentioned metals. The metal line 155 has a higher thermal conductivity than the Si of the heat dissipation chip 150a, and therefore contributes to more efficient dissipation of heat from the first semiconductor chip 120. The metal line 155 is connected to a metal pad 162 disposed on the bottom of the heat dissipating chip 150a. However, at least a portion of the metal line 155 is not connected to the metal pad 162 .

[0038] FIG. 3 is a cross-sectional view showing a schematic configuration of a semiconductor package according to another embodiment of the present invention. The contents already explained in the explanation of FIGS. 1A to 2 will be explained briefly or omitted. 3, the semiconductor package 100b of the present embodiment differs from the semiconductor package 100 of FIG. 1B in that a memory element 140a of the package structure is stacked on the through-posts 130 instead of a second semiconductor chip. In the semiconductor package 100b of this embodiment, the memory element 140a is a High Bandwidth Memory (HBM) package.

[0039] More specifically, the memory device 140 a in the HBM package includes a base chip 142 and a number of core chips 144 on the base chip 142 . The base chip 142 and the core chip 144 include through electrodes 148 therein. Here, the through electrode 148 is a TSV. As shown in FIG. 3, the uppermost core chip 144 among the core chips 144 does not include a through electrode 148 . On the other hand, although not shown in the figure, fine bumps and adhesive layers are disposed between the base chip 142 and the core chip 144 and between adjacent core chips 144 . Moreover, the fine bumps are connected to the through electrodes 148 .

[0040] The base chip 142 includes logic elements, and thus the base chip 142 is a logic chip. Such a base chip 142 is disposed under the core chip 144, and integrates and transmits signals of the core chip 144 to the outside, and transmits signals and power from the outside to the core chip 144. Thereby, the base chip 142 is also referred to as a buffer chip or a control chip. On the other hand, each of the core chips 144 is a memory chip. For example, each of the core chips 144 is a DRAM chip. Meanwhile, the core chip 144 is stacked on the base chip 142 or the lower core chip 144 through pad-to-pad bonding, hybrid bonding (HB), bonding using a bonding material, or bonding using an anisotropic conductive film (ACF), etc. In FIG. 3, four core chips 144 are stacked on base chip 142, but the number of core chips 144 is not limited to four. For example, three or less core chips 144 may be stacked on the base chip 142, or five or more core chips 144 may be stacked on the base chip 142.

[0041] The memory element 140 a is mounted on the through post 130 via the second bump 145 . More specifically, the second bump 145 is disposed between the lower surface of the base chip 142 and the through post 130 . Although not shown in the figure, chip pads are disposed on the lower surface of base chip 142, and second bumps 145 are disposed on the chip pads. Also, in some embodiments, post pads are formed on the through posts 130, and second bumps 145 are disposed between the chip pads and the corresponding post pads. The core chip 144 on the base chip 142 is sealed by an inner sealant 146 . However, the topmost core tip 144 among the core tips 144 is not covered by the inner sealant 146 . However, in other embodiments, the top surface of the top core chip 144 may be covered by the inner encapsulant 146 .

[0042] In the semiconductor package 100b of the present embodiment, the memory element 140a is not limited to an HBM package. For example, memory device 140a may have a conventional packaging structure. For example, memory device 140a may include an upper packaging substrate and multiple memory chips stacked on the upper packaging substrate. The upper package substrate may be stacked on the through posts 130 through the second bumps 145 . Also, the memory chip may be stacked on the upper package substrate via bonding wires, or may be stacked on the upper package substrate via bumps and TSVs. The semiconductor package 100b of this embodiment has a POP structure. Specifically, the rewiring substrate 110, the first semiconductor chip 120, the through-posts 130, and the sealing material 170 form a first package PKG1, and the memory element 140a forms a second package PKG2. Therefore, the semiconductor package 100b of this embodiment has a POP structure in which the second package PKG2 is stacked on the first package PKG1 via the second bumps 145.

[0043] 4A and 4B are cross-sectional views showing a schematic configuration of a semiconductor package according to another embodiment of the present invention, and FIG. 4B is a cross-sectional view showing a third semiconductor chip 120a in more detail in the semiconductor package of FIG. 4A. The contents already explained in the explanation of FIGS. 1A to 3 will be explained briefly or omitted. 4A and 4B, a semiconductor package 100c of the present embodiment differs from the semiconductor package 100 of FIG. 1B in that a third semiconductor chip 120a disposed below the first semiconductor chip 120 is further included.

[0044] In the semiconductor package 100c of the present embodiment, the third semiconductor chip 120a is a modem chip that supports the communication of the first semiconductor chip 120. However, the type of third semiconductor chip 120a is not limited to a modem chip. For example, the third semiconductor chip 120a may include various types of integrated elements that support the operation of the first semiconductor chip 120. The third semiconductor chip 120a may include a multi-channel I / O interface for exchanging memory signals with the second semiconductor chip 140.

[0045] As shown in FIG. 4B, the third semiconductor chip 120a includes a substrate 121, a lower multiple wiring layer 123, an upper wiring layer 127, and a through electrode 129. Substrate 121 constitutes the body of third semiconductor chip 120a and is based on Si. An active surface of substrate 121 has integrated circuit layers formed thereon. The integrated circuit layer includes a plurality of logic elements. The lower multiple wiring layer 123 is disposed on the lower surface of the substrate 121 and includes multiple layers of wiring. Meanwhile, a chip pad is disposed on the lower surface of the lower multiple wiring layer 123, and a first bump 125 is disposed on the chip pad.

[0046] The upper wiring layer 127 is disposed on the upper part of the substrate 121 . In the upper wiring layer 127, wiring is arranged, and the wiring is arranged in a single layer or in multiple layers. In the case of multiple layers of wiring, the wiring of the other layers is connected to each other through vias. On the top surface of the upper wiring layer 127, upper pads connected to wiring are disposed. Depending on the embodiment, the upper wiring layer 127 may be omitted. When the upper wiring layer 127 is omitted, the upper surface of the through electrode 129 is exposed from the substrate 121 , or the electrode pad on the upper surface of the through electrode 129 is exposed from the substrate 121 .

[0047] The through electrodes 129 penetrate the substrate 121 and connect the wiring of the upper wiring layer 127 and the wiring of the lower multiple wiring layer 123 to each other. The through electrode 129 has a structure that penetrates the silicon that constitutes the substrate 121, and is therefore also referred to as a TSV (Through Silicon Via). The through electrodes 129 are classified into a via-first structure formed before the formation of an integrated circuit layer on the substrate 121, a via-middle structure formed after the formation of the integrated circuit layer but before the formation of the multiple wiring layer, and a via-last structure formed after the formation of the multiple wiring layer. In FIG. 4B, the through electrode 129 corresponds to, for example, a via middle structure.

[0048] In the third semiconductor chip 120a, the lower surface is the front surface which is the active surface, and the upper surface is the back surface which is the non-active surface. That is, the lower surface of lower multiple wiring layer 123 corresponds to the front surface of third semiconductor chip 120a, and the upper surface of upper wiring layer 127 corresponds to the rear surface of third semiconductor chip 120a. Chip pads are formed on the front surface, which is the active surface, and the third semiconductor chip 120a is mounted on the redistribution substrate 110 through the first bumps 125 in a flip chip structure. Meanwhile, the first semiconductor chip 120 may be stacked on the third semiconductor chip 120a via bonding using bumps, bonding using ACF, HB, or the like. For reference, HB stands for a combination of pad-to-pad bonding and insulator-to-insulator bonding. ACF is an anisotropic conductive film that allows electricity to flow in only one direction, and refers to a conductive film made by mixing fine conductive particles into an adhesive resin to form a film.

[0049] FIG. 5 is a cross-sectional view showing a schematic configuration of a semiconductor package according to another embodiment of the present invention. The contents already explained in the explanation of FIGS. 1A to 4B will be explained briefly or omitted. 5, a semiconductor package 100d of the present embodiment differs from the semiconductor package 100 of FIG. 1B in that it further includes a passive element 180. In the semiconductor package 100d of the present embodiment, as shown in FIG.

[0050] Specifically, in the semiconductor package 100d of the present embodiment, the passive element 180 is disposed on the lower surface of the rewiring substrate 110. However, depending on the embodiment, the passive components 180 may be located on or within the redistribution substrate 110 . Passive elements 180 include two-terminal elements such as resistors, inductors, and capacitors. In the semiconductor package 100d of the present embodiment, the passive element 180 includes an MLCC 182 (Multi-Layer Ceramic Capacitor) and a Si capacitor 184.

[0051] FIG. 6 is a cross-sectional view showing a schematic configuration of a semiconductor package according to another embodiment of the present invention. The contents already explained in the explanation of FIGS. 1A to 5 will be explained briefly or omitted. 6, the semiconductor package 100e of the present embodiment further includes an upper encapsulant 175 that encapsulates the second semiconductor chip 140 and the heat dissipation chip 150 on the first semiconductor chip 120, the through posts 130, and the encapsulant 170. As shown in FIG. The materials and properties of the top encapsulant 175 are the same as those described for the encapsulant 170 of the semiconductor package 100 of FIG. 1B.

[0052] As shown in FIG. 6, the upper encapsulant 175 covers the sides of the second semiconductor chip 140 and the underfill 147, and the sides of the heat dissipation chip 150 and the heat dissipation connector 160. As shown in FIG. In some embodiments, underfill 147 is omitted and top encapsulant 175 fills between second semiconductor chip 140 and encapsulant 170 and between second bumps 145 . On the other hand, the upper encapsulant 175 does not cover the top surfaces of the second semiconductor chip 140 and the heat dissipating chip 150 . However, in some embodiments, the top encapsulant 175 covers the top surface of the second semiconductor chip 140 . In such a structure, the top surface of the second semiconductor chip 140 is lower than the top surface of the heat dissipating chip 150 .

[0053] FIG. 7 is a cross-sectional view showing a schematic configuration of a semiconductor package according to another embodiment of the present invention. The contents already explained in the explanation of FIGS. 1A to 6 will be explained briefly or omitted. 7, a semiconductor package 100f of the present embodiment differs from the semiconductor package 100e of FIG. 6 in that a heat dissipation structure 190 is further included on the second semiconductor chip 140 and the heat dissipation chip 150. As shown in FIG. Furthermore, the heat dissipation structure 190 of the semiconductor package 100f of this embodiment may be disposed not only on the semiconductor package 100e of FIG. 6, but also on the semiconductor packages (100, 100a to 100d) of FIG. 1B and FIGS.

[0054] The heat dissipation structure 190 may include, for example, a heat sink or a heat slug. The heat dissipation structure 190 is adhered and stacked on the second semiconductor chip 140 and the heat dissipation chip 150 via an upper adhesive layer 195 . The upper adhesive layer 195 is made of a material with high thermal conductivity, such as a TIM or a thermally conductive resin.

[0055] 8A to 8K are schematic cross-sectional views illustrating a method for manufacturing the semiconductor package of FIG. 1B according to one embodiment of the present invention, and FIG. 9 is a plan view of the semiconductor package at the stage of FIG. 8D. The description will be made with reference to FIG. 1B as well, and the contents already described in the description of FIGS. 1A to 7 will be briefly described or omitted.

[0056] 8A, in the method for manufacturing a semiconductor package according to the present embodiment, first, an alignment metal pad 310 and an initial through-post 130 a are formed on a first carrier substrate 200 . The alignment metal pads 310 and the initial through-posts 130 a are formed on the first adhesive layer 210 of the first carrier substrate 200 . The first adhesive layer 210 is, for example, a glue coating layer. However, the material of the first adhesive layer 210 is not limited to glue. The alignment metal pads 310 and the initial through posts 130a are formed through a plating process. The manufacturing process of the alignment metal pads 310 and the initial through posts 130a will be described in more detail in the description of FIGS. 10A to 10H.

[0057] The alignment metal pad 310 includes, for example, Cu or Ti / Cu. However, the material of the alignment metal pad 310 is not limited thereto. The alignment metal pads 310 have minute widths and intervals. Furthermore, the alignment metal pads 310 are stacked on the first semiconductor chip 120 in a self-aligned manner on the rewiring substrate 110 . In addition, since the alignment metal pads 310 are formed with fine widths and intervals, the widths and intervals of the redistribution lines formed on the redistribution substrate 110, for example, the redistribution lines disposed at the top, can be made very fine.

[0058] The initial through-post 130a also comprises Cu or Ti / Cu. However, the material of the initial through-post 130a is not limited to this. The initial through posts 130 a have a relatively larger width and spacing than the alignment metal pads 310 . The initial through posts 130a are arranged in a two-dimensional array structure on at least one side of the region in which the alignment metal pads 310 are arranged.

[0059] Referring to FIG. 8B, the first semiconductor chip 120 is then stacked on the alignment metal pads 310. As shown in FIG. Specifically, the first semiconductor chip 120 includes initial bumps 125a on its bottom surface. The initial bump 125a includes a metal pillar (125-1) and a solder (125-2). The metal pillar (125-1) contains, for example, Cu. However, the material of the metal pillar (125-1) is not limited to Cu. The first semiconductor chip 120 is stacked on the alignment metal pads 310 in such a manner that the initial bumps 125 a are coupled to the corresponding alignment metal pads 310 .

[0060] Referring to FIG. 8C, after the first semiconductor chip 120 is laminated, an initial encapsulant 170a is formed on the first adhesive layer 210 to cover the initial through posts 130a and the first semiconductor chip 120. As shown in FIG. 8C, the initial encapsulant 170a covers the initial through-posts 130a and the side and top surfaces of the first semiconductor chip 120. As shown in FIG. Furthermore, the initial encapsulant 170a fills the spaces between the first semiconductor chip 120 and the first adhesive layer 210, and between the initial bumps 125a. The material and characteristics of the initial encapsulant 170a are the same as those described for the encapsulant 170 of the semiconductor package 100 of FIG. 1B.

[0061] 8D and 9, a top portion of the initial sealant 170a is subsequently removed by a first grinding process as indicated by an arrow to form a primarily thin initial sealant 170b. Through the first grinding, the initial through posts 130a and the top surface of the first semiconductor chip 120 are exposed from the initial encapsulant 170b. Meanwhile, as can be seen from FIG. 9, the initial through posts 130a are arranged in a two-dimensional array structure on at least one side of the first semiconductor chip 120, for example, on the left side in the x direction. Further, some of the initial through-posts 130a are also disposed on parts of both sides of the first semiconductor chip 120 in the y direction.

[0062] Referring to FIG. 8E, after the initial encapsulant 170b is formed, a second carrier substrate 400 is bonded onto the first semiconductor chip 120, the initial through-posts 130a, and the upper surface of the initial encapsulant 170b. The second carrier substrate 400 is adhered and fixed onto the upper surfaces of the first semiconductor chip 120, the initial through posts 130a, and the initial encapsulant 170b via a second adhesive layer 410. After the second carrier substrate 400 is bonded, the first carrier substrate 200 is removed from the alignment metal pads 310, the initial through posts 130a, and the initial encapsulant 170b. When the first carrier substrate 200 is removed, the first adhesive layer 210 is also removed. However, in some embodiments, the first adhesive layer 210 may be retained and only the first carrier substrate 200 removed.

[0063] Referring to FIG. 8F, after removing the first carrier substrate 200, the entire structure is turned upside down so that the second carrier substrate 400 is located below and the alignment metal pads 310 are located above. Thereafter, as indicated by the arrows, the alignment metal pads 310 and parts of the initial bumps 125a are removed by a second grinding process. For example, the solder (125-2) of the initial bump 125a is removed through the second grinding to form the first bump 125 on the first semiconductor chip 120. Also, the initial through-posts 130a and the initial sealant 170b are thinned by a second grinding process to form the through-posts 130 and the second thinned sealant 170. The encapsulant 170 is substantially identical to the encapsulant 170 of the semiconductor package 100 of FIG. 1B and thus has a first thickness H1.

[0064] Referring to FIG. 8G, the redistribution substrate 110 is then formed on the first semiconductor chip 120, the through posts 130, and the encapsulant 170. As shown in FIG. The redistribution substrate 110 includes a body insulating layer 112 , redistribution lines 114 , and vias 116 . As described above, the first bumps 125 of the first semiconductor chip 120 are self-aligned using the alignment metal pads 310 and are formed very finely. Correspondingly, the rewiring lines 114 of the rewiring substrate 110 are also formed to have very fine widths and intervals. For example, among the rewiring lines 114 of the rewiring substrate 110, the rewiring lines 114 coupled to the first bumps 125 of the first semiconductor chip 120 have a line width and interval of about 2 / 2 μm.

[0065] Referring to FIG. 8H, after the rewiring substrate 110 is formed, the external connection terminals 115 are formed on the rewiring substrate 110. As shown in FIG. The external connection terminals 115 are the same as those of the external connection terminals 115 of the semiconductor package 100 in FIG. 1B.

[0066] Referring to FIG. 8I, the external connection terminal 114 is then attached onto the adhesive film 520 of the film frame mount 500 . The film frame mount 500 includes a circular support ring 510 and an adhesive film 520 that covers the opening of the support ring 510 . Thereby, the film frame mount 500 is also referred to as a ring frame mount. After the external connection terminals 115 of the rewiring substrate 110 are attached to the film frame mount 500 , the second carrier substrate 400 is removed from the first semiconductor chip 120 , the through posts 130 , and the encapsulant 170 . When the second carrier substrate 400 is removed, the second adhesive layer 410 is also removed.

[0067] Referring to FIG. 8J, after removal of the second carrier substrate 400, the second semiconductor chip 140 is stacked on the through-posts 130. As shown in FIG. The second semiconductor chip 140 is stacked via second bumps 145 . Thereafter, the spaces between the second semiconductor chip 140 and the encapsulant 170 and between the second bumps 145 are filled with an underfill 147 . However, in some embodiments, the underfill 147 may be omitted.

[0068] Referring to FIG. 8K, a heat dissipating chip 150 is then stacked on the first semiconductor chip 120 adjacent to the second semiconductor chip 140. As shown in FIG. The heat dissipating chip 150 is stacked with a heat dissipating joint 160 . The heat dissipation connection 160 includes a metal pad 162 and an adhesive layer 164 . By stacking second semiconductor chip 140 on first semiconductor chip 120, semiconductor package 100 of FIG. 1B is completed.

[0069] 10A to 10G are cross-sectional views for more specifically explaining the stage of FIG. 8A. The description will be made with reference to FIG. 1B as well, and the contents already described in the description of FIGS. 1A to 8K will be briefly described or omitted. 10A, in the process of manufacturing the alignment metal pads 310 and the initial through-posts 130 a, a first adhesive layer 210 is formed on a first carrier substrate 200 . The first adhesive layer 210 is, for example, a glue coating layer. However, the material of the first adhesive layer 210 is not limited to glue.

[0070] Referring to FIG. 10B, after the first adhesive layer 210 is formed, a metal seed layer 301 is formed on the first adhesive layer 210 . The metal seed layer 301 includes, for example, a Cu single layer or a Ti / Cu multilayer. However, the material and layer structure of the metal seed layer 301 are not limited to the above-mentioned materials and layer structure. On the other hand, in the case of a Ti / Cu multilayer, the lower layer is a Ti layer and the upper layer is a Cu layer.

[0071] Referring to FIG. 10C, after the metal seed layer 301 is formed, a first photoresist (PhotoResist: PR) pattern PH1 is formed on the metal seed layer 301. More specifically, first, the first PR layer 610 is formed to a small thickness on the entire surface of the metal seed layer 301 . Thereafter, a photolithography process is performed on the first PR layer 610 to form a first PR pattern PH1 in a portion where the first semiconductor chip 120 is to be disposed. Meanwhile, the first PR pattern PH1 has a very fine width and interval in consideration of the size and interval of the alignment metal pads 310 to be formed later. On the other hand, the first PR pattern PH1 exposes the metal seed layer 301 on the bottom surface.

[0072] Referring to FIG. 10D, after the first PR pattern PH1 is formed, a plating process is performed on the metal seed layer 301 exposed through the first PR pattern PH1 to form a metal pad 310a for initial alignment. The plating process is, for example, a Cu plating process. However, the plating process is not limited to a Cu plating process.

[0073] Referring to FIG. 10E, after the initial alignment metal pads 310a are formed, the first PR layer 610 and the first PR pattern PH1 are removed. The first PR layer 610 and the first PR pattern PH1 are removed through a PR strip and / or ashing process. By removing the first PR layer 610 and the first PR pattern PH1, the metal seed layer 301 and the initial alignment metal pad 310a are exposed.

[0074] Referring to FIG. 10F, a second PR pattern PH2 is then formed adjacent to the initial alignment metal pad 310a. More specifically, first, the second PR layer 620 is formed to be relatively thick and covers the entire surfaces of the metal seed layer 301 and the initial alignment metal pads 310a. Thereafter, a photolithography process is performed on the second PR layer 620 to form a second PR pattern PH2 in a portion where the through-post 130 is to be disposed. On the other hand, the second PR pattern PH3 exposes the metal seed layer 301 on the bottom surface.

[0075] Referring to FIG. 10G, after the second PR pattern PH2 is formed, a plating process is performed on the metal seed layer 301 exposed through the second PR pattern PH2 to form an initial through post 130b. The plating process is, for example, a Cu plating process. However, the plating process is not limited to a Cu plating process.

[0076] Referring to FIG. 10H, after the formation of the initial through post 130b, the second PR layer 620 and the second PR pattern PH2 are removed. The second PR layer 620 and the second PR pattern PH2 are removed through a PR strip and / or ashing process. By removing the second PR layer 620 and the second PR pattern PH2, the metal seed layer 301 is exposed between the initial through posts 130b, between the initial alignment metal pads 310a, and outside the areas where the initial through posts 130b and the initial alignment metal pads 310a are located. Subsequently, the exposed metal seed layer 301 is removed by an etching process to form the initial through posts 130a and the alignment metal pads 310.

[0077] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0078] 100, 100a~100f Semiconductor packages 110 Rewiring board 112 Body insulation layer 114 Rewiring Line 116 Beer 115 External connection terminal 120 First semiconductor chip 120a Third semiconductor chip 121 Substrate 123 Lower multiple wiring layer 125 First Bump 127 Upper wiring layer 129 Through electrode 130 Through Post 130a Initial penetration post 140 Second semiconductor chip 140a Memory element 142 Base Chip 144, 144-1~4 Core chip 145 2nd Bump 146 Internal sealant 147 Underfill 148 Through electrode 150 Heat Dissipation Chip 160 Heat Dissipation Connection 162 Metal Pad 164 Adhesive layer 170 Sealing material 170b Initial sealant 175 Upper sealant 180 Passive elements 182 MLCC 184 Silicon capacitor 190 Heat dissipation structures 195 Top adhesive layer 200 First carrier board 210 1st adhesive layer 310 Alignment metal pad 400 Second Carrier Board 410 Second adhesive layer 500 film frame mount 610, 620 PR tier PH1, PH2 PR pattern

Claims

1. A rewiring board; a first semiconductor chip disposed on the rewiring substrate on the right side in a first direction; a through post disposed on the rewiring substrate adjacent to the first semiconductor chip and on the left side in the first direction; a heat dissipation chip disposed on the first semiconductor chip; a second semiconductor chip disposed on the through post adjacent to the heat dissipating chip; The heat dissipation chip is laminated on the first semiconductor chip via a metal pad and an adhesive layer.

2. a sealing material disposed on the rewiring substrate and surrounding the first semiconductor chip and the through post; The semiconductor package of claim 1 , wherein top surfaces of the first semiconductor chip and the through posts are exposed from the encapsulant.

3. The semiconductor package of claim 1 , wherein the adhesive layer comprises a thermal interface material (TIM), a polymer, or an oxide.

4. a gap between a lower surface of the metal pad and an upper surface of the first semiconductor chip is 1 μm or less; The semiconductor package according to claim 1 , wherein the gap is filled with the adhesive layer.

5. the first semiconductor chip includes a logic element; The semiconductor package of claim 1 , wherein the second semiconductor chip includes a memory device.

6. The semiconductor package according to claim 1 , wherein the heat dissipation chip includes a metal line therein.

7. The rewiring substrate includes multiple layers of wiring lines; 2. The semiconductor package of claim 1, wherein a pitch of the first wiring lines of the top layer coupled to the first semiconductor chip is smaller than a pitch of the wiring lines of the layer below the first wiring lines.

8. 8. The semiconductor package according to claim 7, wherein the first wiring lines in the uppermost layer have a line width of 2 [mu]m and are spaced apart from each other by 2 [mu]m.

9. a rewiring board having multiple layers of wiring lines; a first semiconductor chip stacked on the rewiring substrate via a first bump on the right side in a first direction; a through post disposed on the rewiring substrate adjacent to the first semiconductor chip and on the left side in the first direction; a sealing material disposed on the rewiring substrate, surrounding the first semiconductor chip and the through-post, and exposing upper surfaces of the first semiconductor chip and the through-post; a heat dissipation chip laminated on the first semiconductor chip via a metal pad and an adhesive layer; a second semiconductor chip adjacent to the heat dissipation chip and stacked on the through posts via second bumps.

10. The semiconductor package according to claim 9 , wherein the through post penetrates the sealing material to connect the redistribution substrate and the second semiconductor chip.

11. The semiconductor package of claim 9 , wherein the through posts are further disposed on at least one of both of the first semiconductor chips in a second direction perpendicular to the first direction.

12. 10. The semiconductor package of claim 9, wherein a left portion of the first semiconductor chip overlaps with the second semiconductor chip in a direction perpendicular to an upper surface of the redistribution substrate.

13. 10. The semiconductor package of claim 9, wherein a pitch of the first wiring lines of the top layer coupled to the first semiconductor chip is smaller than a pitch of the wiring lines of a layer below the first wiring lines.

14. 10. The semiconductor package of claim 9, wherein the second semiconductor chip is connected to the first semiconductor chip via the second bumps, the through posts, the wiring lines of the rewiring substrate, and the first bumps.

15. a rewiring board having external connection terminals arranged on a lower surface thereof and including multi-layer wiring lines arranged inside; a first semiconductor chip stacked on the rewiring substrate via a first bump on the right side in a first direction; a through post disposed adjacent to the first semiconductor chip on the rewiring substrate at a left side in the first direction and at a portion of both sides of the first semiconductor chip in a second direction perpendicular to the first direction; a sealing material disposed on the rewiring substrate, covering side surfaces of the first semiconductor chip and the through post and exposing upper surfaces of the first semiconductor chip and the through post; a heat dissipation chip laminated on the first semiconductor chip via a metal pad and an adhesive layer; a second semiconductor chip adjacent to the heat dissipation chip and stacked on the through posts via second bumps.

16. 16. The semiconductor package of claim 15, wherein the second semiconductor chip is connected to the first semiconductor chip via the second bumps, the through posts, the wiring lines of the rewiring substrate, and the first bumps.

17. forming alignment metal pads and through posts on a first carrier substrate; stacking a first semiconductor chip on the alignment metal pads such that an active surface of the first semiconductor chip faces the first carrier substrate; forming an encapsulant surrounding the through post and the first semiconductor chip; bonding a second carrier substrate to the through posts and a non-active surface of the first semiconductor chip and removing the first carrier substrate; grinding the encapsulant to expose a first surface of the through post and a first bump of a first semiconductor chip; forming a redistribution substrate on the first surface of the through post and the first bump of the first semiconductor chip; bonding the redistribution substrate to a film ring mount and removing the second carrier substrate; stacking a second semiconductor chip on a second surface of the through post opposite the first surface; and stacking a heat dissipation chip adjacent to the second semiconductor chip on the inactive surface of the first semiconductor chip via a metal pad and an adhesive layer.

18. The step of forming the alignment metal pads and the through posts includes: forming a glue coating layer on the first carrier substrate; forming a metal seed layer on the glue coating layer; forming the alignment metal pad on the metal seed layer on a right side in a first direction; forming the through post on the metal seed layer on a left side in the first direction; 20. The method of claim 17, further comprising removing the metal seed layer exposed between the alignment metal pads, between the through posts, and outside the through posts and the alignment metal pads.

19. The step of forming the alignment metal pads includes: forming a first photoresist (PR) layer on the metal seed layer; patterning the first PR layer to form a first photoresist (PR) pattern on the right side; growing the alignment metal pads through plating on the metal seed layer exposed by the first PR pattern; The step of forming the through post comprises: forming a second PR layer on the metal seed layer and the alignment metal pad; patterning the second PR layer to form a second PR pattern on the left side; 20. The method of claim 18, further comprising: growing the through posts by plating on the metal seed layer exposed by the second PR pattern.

20. In the step of exposing the first surface of the through post and the first bump of the first semiconductor chip, 20. The method of claim 17, wherein the sealing material has a thickness of 100 [mu]m or less.

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