Integrated circuit memory device having improved memory cell layout
The semiconductor device addresses leakage current issues in miniaturized DRAM devices by employing a bit line with a mold structure and oxide semiconductor layers, achieving improved electrical performance through reduced leakage current.
Patent Information
- Application Number
- JP2024107159
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-07-04
- Filing Date
- 2024-07-03
- Publication Date
- 2025-01-20
AI Technical Summary
As semiconductor devices, particularly DRAM devices, shrink in size, leakage current through the channel region increases, necessitating improved electrical performance.
The semiconductor device incorporates a bit line with a mold structure and active semiconductor layers, including a vertical channel layer made of oxide semiconductor materials, and a specific layout that reduces leakage current through the use of a gate insulating layer and word lines, along with a landing pad and storage node configuration.
This configuration enhances the electrical performance of the semiconductor device by reducing leakage current and improving overall functionality.
Smart Images
Figure 2025010090000001_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates to semiconductor devices, and more particularly to integrated circuit memory devices. [Background technology]
[0002] The size of DRAM devices is shrinking due to the downscaling of semiconductor devices. In DRAM devices with a 1T-1C structure in which one transistor is connected to one capacitor, the leakage current through the channel region increases as the device becomes smaller. To reduce the leakage current, a vertical channel transistor using an oxide semiconductor material as the channel layer has been proposed. Summary of the Invention [Problem to be solved by the invention]
[0003] The technical problem to be solved by the present invention is to provide a semiconductor device such as a DRAM device having excellent electrical performance. [Means for solving the problem]
[0004] A semiconductor device according to an exemplary embodiment for achieving the technical problem includes: a bit line extending in a first horizontal direction on a substrate; a mold structure including a mold opening extending on the bit line and extending in a second horizontal direction perpendicular to the first horizontal direction, the mold structure including a mold insulating layer, a cover insulating layer disposed on the mold insulating layer, and an interface insulating layer disposed on an upper surface of the cover insulating layer and on at least a portion of a sidewall; an active semiconductor layer, the active semiconductor layer being disposed on an inner wall of the mold opening of the mold structure and including a first portion extending in a vertical direction perpendicular to an upper surface of the substrate and a second portion connected to a bottom of the first portion and extending in the first horizontal direction, the second portion being disposed on an upper surface of the bit line, the first portion including a first sidewall in contact with a sidewall of the mold opening and a second sidewall opposite to the first sidewall; a word line disposed on the second sidewall of the active semiconductor layer and extending in the second horizontal direction; and a gate insulating layer interposed between the active semiconductor layer and the word line.
[0005] A semiconductor device according to an exemplary embodiment for achieving the technical problem includes: a bit line extending in a first horizontal direction on a substrate; a mold structure including a mold opening extending on the bit line and extending in a second horizontal direction perpendicular to the first horizontal direction, the mold structure including a mold insulating layer, a cover insulating layer disposed on the mold insulating layer, and an interface insulating layer disposed on an upper surface of the cover insulating layer and on at least a portion of a sidewall; an active semiconductor layer extending on an inner wall of the mold opening of the mold structure, the active semiconductor layer including a first portion extending in a vertical direction perpendicular to an upper surface of the substrate, and a second portion connected to a bottom of the first portion and extending in the first horizontal direction; a word line extending on a sidewall of the semiconductor layer and extending in the second horizontal direction; a gate insulating layer extending between the active semiconductor layer and the word line; and a landing pad electrically connected to an upper surface of the first portion of the active semiconductor layer, the landing pad including an upper portion extending on the upper surface of the mold structure and a lower portion connected to the upper portion and extending within a landing pad recess space, a bottom surface of the lower portion of the landing pad extending at the same level as a bottom surface of the interfacial insulating layer, the first portion including a first sidewall contacting a sidewall of the mold opening and a second sidewall opposite the first sidewall, the second portion extending over an upper surface of the bit line.
[0006] A semiconductor device according to an exemplary embodiment for achieving the technical problem includes: a bit line extending in a first horizontal direction on a substrate; a mold structure including a mold opening extending on the bit line and extending in a second horizontal direction perpendicular to the first horizontal direction, the mold structure including a mold insulating layer, a cover insulating layer disposed on the mold insulating layer, and an interface insulating layer disposed on an upper surface of the cover insulating layer and on at least a portion of a sidewall; a first portion disposed on an inner wall of the mold opening of the mold structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a second portion connected to a bottom of the first portion and extending in the first horizontal direction, the second portion extending on an upper surface of the bit line, the first portion including a first sidewall contacting a sidewall of the mold opening and a second sidewall opposite to the first sidewall; an active semiconductor layer having a top surface extending at a level lower than a top surface of a mold structure; word lines extending on the second sidewalls of the active semiconductor layer and extending in the second horizontal direction; a gate insulating layer interposed between the active semiconductor layer and the word lines; a buried insulating layer extending on sidewalls of the word lines and filling the mold openings; a landing pad electrically coupled to a top surface of the first portion of the active semiconductor layer, the landing pad including an upper portion disposed on the top surface of the mold structure and a lower portion connected to the upper portion and disposed within a landing pad recess space; and a storage node coupled onto the landing pad, wherein the interfacial insulating layer extends on sidewalls of the cover insulating layer extending within the landing pad recess space from above the top surface of the cover insulating layer.
[0007] An integrated circuit memory device according to an exemplary embodiment for achieving the above technical objectives includes a substrate having a bit line thereon; an insulating region having a first opening exposing a first portion of the bit line. A first semiconductor active layer lines opposing first and second sidewalls of the first opening and lines the exposed first portion of the bit line, and a direct electrical connection is provided between a portion of the first semiconductor active layer extending between the first and second sidewalls of the first opening and the exposed first portion of the bit line. A first word line is provided on a first portion of the first semiconductor active layer extending opposite the first sidewall of the first opening, and a second word line is provided on a second portion of the first semiconductor active layer extending opposite the second sidewall of the first opening. Preferably, a portion of the first word line extending opposite the first sidewall of the first opening operates as a gate electrode of an access transistor of a first memory cell, and a portion of the second word line extending opposite the second sidewall of the first opening operates as a gate electrode of an access transistor of a second memory cell. [Brief description of the drawings]
[0008] [Figure 1] FIG. 1 is a layout diagram showing a semiconductor device according to an exemplary embodiment. [Diagram 2] 2 is an enlarged layout diagram of a cell array region portion of FIG. 1. [Diagram 3] 3 is a cross-sectional view taken along the line A1-A1' in FIG. 2. [Figure 4] 3 is a cross-sectional view taken along the line A2-A2' in FIG. 2. [Diagram 5] FIG. 4 is an enlarged view of a portion CX1 in FIG. [Figure 6] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 7] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 8] FIG. 7 is an enlarged view of a portion CX1 in FIG. [Figure 9]1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 10] FIG. 10 is an enlarged view of a portion CX1 in FIG. [Figure 11] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 12A] 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. [Figure 12B] FIG. 12B is a top view of FIG. 12A. [Figure 13A] 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. [Figure 13B] FIG. 13B is a top view of FIG. 13A. [Figure 14] 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. [Figure 15A] 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. [Figure 15B] 3 is a cross-sectional view taken along the line A2-A2' in FIG. 2. [Figure 15C] FIG. 15B is a top view of FIG. 15A. [Figure 16A] 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. [Figure 16B] 3 is a cross-sectional view taken along the line A2-A2' in FIG. 2. [Figure 16C] FIG. 16B is a top view of FIG. 16A. [Figure 17] 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. [Figure 18] 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. [Figure 19]3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. [Figure 20] 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. [Figure 21A] 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. [Figure 21B] 3 is a cross-sectional view taken along the line A2-A2' in FIG. 2. [Figure 22] 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. [Figure 23] 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an exemplary embodiment, which is a cross-sectional view taken along line A1-A1' in FIG. 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0009] FIG 1 is a layout diagram showing a semiconductor device 100 according to an exemplary embodiment. FIG 2 is an enlarged layout diagram of a cell array region MCA portion of FIG 1. FIG 3 is a cross-sectional view taken along line A1-A1' in FIG 2. FIG 4 is a cross-sectional view taken along line A2-A2' in FIG 2. FIG 5 is an enlarged view of a CX1 portion of FIG 3.
[0010] 1 to 5, the semiconductor device 100 may include a substrate 110 including a cell array region MCA and a peripheral circuit region PCA. In some embodiments, the cell array region MCA may also be a memory cell region of a DRAM device, and the peripheral circuit region PCA may also be a core region or a peripheral circuit region of the DRAM device. For example, the peripheral circuit region PCA may include peripheral circuit transistors (not shown) for transmitting signals and / or power to a memory cell array included in the cell array region MCA. In an exemplary embodiment, the peripheral circuit transistors (not shown) may include various circuits such as a command decoder, a control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.
[0011] 2, a plurality of word lines WL extending along a first horizontal direction X and a plurality of bit lines BL extending along a second horizontal direction Y may be disposed on a cell array region MCA of a substrate 110. A plurality of cell transistors CTR may be disposed at intersections of the plurality of word lines WL and the plurality of bit lines BL. A plurality of storage nodes 180 may be disposed on each of the plurality of cell transistors CTR.
[0012] The plurality of word lines WL may include a first word line WL1 and a second word line WL2 arranged in a second horizontal direction Y, and the plurality of cell transistors CTR may include a first cell transistor CTR1 and a second cell transistor CTR2 arranged in a second horizontal direction Y. The first cell transistor CTR1 may be arranged adjacent to the first word line WL1, and the second cell transistor CTR2 may be arranged adjacent to the second word line WL2.
[0013] The first cell transistor CTR1 and the second cell transistor CTR2 have a mirror-symmetric structure with respect to each other. For example, the first cell transistor CTR1 and the second cell transistor CTR2 have a mirror-symmetric structure with respect to a center line of the first cell transistor CTR1 and the second cell transistor CTR2 extending along the first horizontal direction X.
[0014] As shown in FIG. 3, a lower insulating layer 112 may be disposed on a substrate 110. The substrate 110 may include silicon, such as single crystal silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 110 may include a conductive region, such as an impurity-doped well or an impurity-doped structure. The lower insulating layer 112 may include an oxide layer, a nitride layer, or a combination thereof.
[0015] In some embodiments, peripheral circuit structures may be disposed on the substrate 110, and a lower insulating layer 112 may be disposed to cover the peripheral circuit structures. The peripheral circuit structures may include, but are not limited to, sense amplifiers electrically connected to the bit lines BL and / or sub-word line drivers electrically connected to the word lines WL.
[0016] A bit line BL extending in a second horizontal direction Y may be disposed on the lower insulating layer 112. In an exemplary embodiment, the bit line BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. A bit line isolation insulating layer 122 extending in the second horizontal direction Y may be disposed on a sidewall of the bit line BL. For example, the bit line isolation insulating layer 122 may be formed to the same height as the bit line BL, filling a space between two adjacent bit lines BL.
[0017] A mold structure 130 may be disposed on the bit lines BL and the bit line isolation insulating layer 122. The mold structure 130 may include an etch stop layer 132, a mold insulating layer 134, a cover insulating layer 136, and an interface insulating layer 138. In an exemplary embodiment, the etch stop layer 132 may be disposed to a small thickness on the top surfaces of the bit lines BL and the bit line isolation insulating layer 122. The etch stop layer 132 may include silicon nitride.
[0018] In an exemplary embodiment, a mold insulating layer 134 may be disposed on the etch stop layer 132. The mold insulating layer 134 may be formed to a relatively large height. In an exemplary embodiment, the mold insulating layer 134 may include silicon oxide.
[0019] In an exemplary embodiment, the cover insulating layer 136 may be disposed on an upper surface of the mold insulating layer 134. The cover insulating layer 136 may include a material having an etch selectivity with the mold insulating layer 134. In an exemplary embodiment, the cover insulating layer 136 may include silicon nitride.
[0020] In an exemplary embodiment, the interfacial insulating layer 138 may be disposed on an upper surface of the cover insulating layer 136 and on a portion of the sidewalls of the cover insulating layer 136. In some embodiments, the interfacial insulating layer 138 may include silicon oxynitride or silicon oxide. In some embodiments, the interfacial insulating layer 138 may include a material layer formed by oxidizing a portion of the cover insulating layer 136 as a result of performing an oxygen annealing process on the upper surface of the cover insulating layer 136.
[0021] In an exemplary embodiment, the interface insulating layer 138 disposed on the sidewall of the cover insulating layer 136 has a first thickness t11, and the interface insulating layer 138 disposed on the upper surface of the cover insulating layer 136 has a second thickness t12. In an exemplary embodiment, the first thickness t11 and the second thickness t12 are in the range of several to several tens of angstroms. In some embodiments, the first thickness t11 is substantially the same as the second thickness t12. In some embodiments, the first thickness t11 is thinner than the second thickness t12.
[0022] In an example embodiment, the mold structure 130 may include a plurality of mold openings 130H. The plurality of mold openings 130H may extend along a first horizontal direction X, and an upper surface of the bit line BL may be exposed at a bottom of each of the plurality of mold openings 130H. For example, the plurality of mold openings 130H may include a first sidewall 130H1 and a second sidewall 130H2, and the first sidewall 130H1 and the second sidewall 130H2 may be spaced apart from each other and extend along the first horizontal direction X.
[0023] A plurality of active semiconductor layers 140 may be disposed on the inner walls of the plurality of mold openings 130H. Each of the plurality of active semiconductor layers 140 may include a first portion 140P1 and a second portion 140P2. The first portion 140P1 indicates a portion extending in the vertical direction Z on the first sidewall 130H1 and the second sidewall 130H2 of the mold opening 130H. The second portion 140P2 indicates a portion disposed at the bottom of the mold opening 130H, disposed on the bit line BL, and in contact with the upper surface of the bit line BL. For example, each of the plurality of active semiconductor layers 140 has a U-shaped vertical cross section.
[0024] The first portion 140P1 of the active semiconductor layer 140 disposed adjacent to the first sidewall 130H1 of the mold opening 130H functions as a vertical channel layer of the first cell transistor CTR1, and the first portion 140P1 of the active semiconductor layer 140 disposed adjacent to the second sidewall 130H2 of the mold opening 130H functions as a vertical channel layer of the second cell transistor CTR2. As a result, the first cell transistor CTR1 and the second cell transistor CTR2 can be arranged in a mirror symmetrical shape to each other within one mold opening 130H.
[0025] The first portion 140P1 of the plurality of active semiconductor layers 140 includes a first sidewall S11 and a second sidewall S12 opposite each other, and the first sidewall S11 may contact the mold insulating layer 134. In an exemplary embodiment, each of the plurality of active semiconductor layers 140 has a top surface disposed at a level lower than a top surface of the mold structure 130 and at the same level as a bottom surface of the cover insulating layer 136. In some embodiments, each of the plurality of active semiconductor layers 140 may have a top surface disposed at an even lower level than the bottom surface of the cover insulating layer 136.
[0026] In an example embodiment, the active semiconductor layers 140 may include an oxide semiconductor material. For example, the active semiconductor layers 140 may include indium gallium zinc oxide (In x Ga y Zinc z O), indium tungsten oxide (In x W y O), indium tin gallium oxide (In x Sn y Ga z O), indium aluminum zinc oxide (In x Al y Zinc z O), indium gallium oxide (In x Ga y O), indium tin zinc oxide (In x Sn y Zinc z O), indium gallium silicon oxide (In x Ga y S z O), indium zinc oxide (In x Zinc y O), indium oxide (In x O), and magnesium aluminum zinc oxide (Mg x Al y Zinc z O), zinc tin oxide (Zn x Sn y O), zirconium zinc tin oxide (Zr x Zinc y Sn zO), gallium zinc tin oxide (Ga x Zinc y Sn z O), aluminum zinc tin oxide (Al x Zinc y Sn z O), and tin oxide (Sn x In addition to the materials mentioned above, in some embodiments, the plurality of active semiconductor layers 140 may include an oxide semiconductor material having a bandgap energy greater than the bandgap energy of silicon.
[0027] A gate insulating layer 150 may be disposed on the second sidewalls S12 of the plurality of active semiconductor layers 140. For example, the gate insulating layer 150 may be conformally disposed on the second sidewalls S12 of the first portions 140P1 of the plurality of active semiconductor layers 140 and on the top surfaces of the second portions 140P2.
[0028] In an exemplary embodiment, the gate insulating layer 150 may have a top surface that is disposed at a higher level than a top surface of the active semiconductor layer 140. The gate insulating layer 150 may have a top surface that is disposed at the same level as a top surface of the cover insulating layer 136.
[0029] In an exemplary embodiment, the gate insulating layer 150 may be made of at least one of a high-k dielectric material having a dielectric constant higher than that of silicon oxide and a ferroelectric material. In some embodiments, the gate insulating layer 150 may be made of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), or the like. , titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).
[0030] The word line WL may be disposed on the second sidewall S12 of the first portion 140P1 of the plurality of active semiconductor layers 140 and on the top surface of the second portion 140P2 such that the gate insulating layer 150 is interposed between the word line WL and the second sidewall S12. In an exemplary embodiment, the word line WL has an L-shaped vertical cross section. In an exemplary embodiment, the word line WL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.
[0031] A first insulating liner 162 and a second insulating liner 164 may be disposed on sidewalls of the two spaced apart word lines WL in the mold opening 130H, and a buried insulating layer 166 may be disposed on the first insulating liner 162 and the second insulating liner 164 to fill a space between the two spaced apart word lines WL. For example, the first insulating liner 162 and the second insulating liner 164 may include silicon nitride, and the buried insulating layer 166 may include silicon oxide.
[0032] A landing pad 170 may be disposed on an upper surface of the mold structure 130 and the buried insulating layer 166. The landing pad 170 may include an upper portion 170U and a lower portion 170B, and the upper portion 170U of the landing pad 170 may be disposed on an upper surface of the mold structure 130 and the buried insulating layer 166, and the lower portion 170B of the landing pad 170 may be disposed within the landing pad recess space 170R.
[0033] For example, the landing pad recess space 170R may be defined on the top surface of the first portion 140P1 of the active semiconductor layer 140 between the first and second sidewalls 130H1, 130H2 of the mold opening 130H and the gate insulating layer 150. The lower portion 170B of the landing pad 170 may be disposed between the gate insulating layer 150 and the interface insulating layer 138 within the landing pad recess space 170R. A bottom surface of the lower portion 170B of the landing pad 170 may contact the top surface of the first portion 140P1 of the active semiconductor layer 140. The bottom surface of the lower portion 170B of the landing pad 170 may be disposed in the same level as the bottom surface of the cover insulating layer 136 and the bottom surface of the interface insulating layer 138.
[0034] In an exemplary embodiment, landing pad 170 has a T-shaped vertical cross-section such that an upper portion 170U of landing pad 170 is wider than a lower portion 170B of landing pad 170. In an exemplary embodiment, landing pad 170 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or combinations thereof.
[0035] In an exemplary embodiment, the interface insulating layer 138 is disposed to cover the sidewall of the cover insulating layer 136 in the landing pad recess space 170R, so that there is no direct contact between the lower portion 170B of the landing pad 170 and the cover insulating layer 136. For example, as illustrated in FIG. 5, the entire sidewall of the cover insulating layer 136 facing the lower portion 170B of the landing pad 170 may be covered by the interface insulating layer 138.
[0036] In the manufacturing process according to the exemplary embodiment, a recess process may be performed on the upper side of the first portion 140P1 of the active semiconductor layer 140 disposed between the mold structure 130 and the buried insulating layer 166 to lower the height of the first portion 140P1 of the active semiconductor layer 140 to form a landing pad recess space 170R. Then, an oxygen annealing process may be performed through the upper surface of the first portion 140P1 of the active semiconductor layer 140 exposed to the landing pad recess space 170R to passivate oxygen vacancies contained within the active semiconductor layer 140, thereby adjusting the carrier concentration of the active semiconductor layer 140. As a result of performing an oxygen annealing process on the upper surface of the cover insulating layer 136 exposed to the inner wall of the landing pad recess space 170R, an interface insulating layer 138 may be formed on the sidewalls and upper surface of the cover insulating layer 136.
[0037] A landing pad isolation insulating layer 172 covering the landing pads 170 may be disposed on the upper surfaces of the mold structure 130 and the buried insulating layer 166. The landing pad isolation insulating layer 172 fills the spaces between adjacent landing pads 170 and covers the upper surfaces of the landing pads 170, and the landing pad isolation insulating layer 172 has an upper surface disposed at a higher level than the upper surfaces of the landing pads 170. In other embodiments, the landing pad isolation insulating layer 172 may have an upper surface disposed at the same level as the upper surfaces of the landing pads 170.
[0038] A storage node 180 may be disposed on the landing pad isolation insulating layer 172. In some embodiments, the storage node 180 may also be a capacitor type, for example for a DRAM memory cell, and may include, for example, a bottom electrode 182, a capacitor dielectric layer 184, and a top electrode 186. The bottom electrode 182 may be disposed on a top surface of the landing pad 170 and extend in the vertical direction Z. The capacitor dielectric layer 184 may be disposed on a sidewall of the bottom electrode 182, and the top electrode 186 may cover the bottom electrode 182 on the capacitor dielectric layer 184.
[0039] According to the above-described exemplary embodiment, an oxygen annealing process is performed on the upper surface of the active semiconductor layer 140 exposed to the landing pad recess space 170R to adjust the carrier concentration of the active semiconductor layer 140, thereby enabling the semiconductor device 100 to have excellent electrical performance.
[0040] Figures 6 and 7 are cross-sectional views showing a semiconductor device 100A according to an exemplary embodiment, and Figure 8 is an enlarged view of a portion CX1 in Figure 6. In Figures 6 to 8, the same reference numerals as in Figures 1 to 5 denote the same components.
[0041] 6 to 8, the top surface of the active semiconductor layer 140 may be disposed at a higher level than the top surface of the mold insulating layer 134. For example, the top surface of the active semiconductor layer 140 may be disposed at a higher level than the bottom surface of the cover insulating layer 136 and at a lower level than the top surface of the cover insulating layer 136. The landing pad 170A includes an upper portion 170U and a lower portion 170B, and the lower portion 170B of the landing pad 170A may be disposed within the landing pad recess space 170R.
[0042] In an exemplary embodiment, the interface insulating layer 138 is disposed to cover a portion of the sidewall of the cover insulating layer 136 in the landing pad recess space 170R, for example, the lower side of the sidewall of the cover insulating layer 136 is not covered by the interface insulating layer 138 and may be in contact with the upper side of the first portion 140P1 of the active semiconductor layer 140. The upper side of the sidewall of the cover insulating layer 136 is covered by the interface insulating layer 138 and is not in direct contact with the lower portion 170B of the landing pad 170A.
[0043] In a manufacturing process according to an example embodiment, a recess process may be performed on an upper side of the first portion 140P1 of the active semiconductor layer 140 disposed between the mold structure 130 and the buried insulating layer 166 to lower the height of the first portion 140P1 of the active semiconductor layer 140 and form a landing pad recess space 170R. In this case, the etching amount in the recess process may be adjusted so that the upper surface of the active semiconductor layer 140 is disposed at a level lower than the upper surface of the cover insulating layer 136 and higher than the upper surface of the mold insulating layer 134.
[0044] Then, an oxygen annealing process may be performed on the top surface of the first portion 140P1 of the active semiconductor layer 140 exposed to the landing pad recess space 170R to passivate oxygen vacancies contained within the active semiconductor layer 140, thereby adjusting the carrier concentration of the active semiconductor layer 140. At this time, as a result of performing the oxygen annealing process on the top surface and part of the sidewall of the cover insulating layer 136 exposed to the inner wall of the landing pad recess space 170R, a part of the cover insulating layer 136 may be oxidized to form an interface insulating layer 138.
[0045] The sidewall of the interface insulating layer 138 exposed in the landing pad recess space 170R may be aligned with the lower sidewall of the cover insulating layer 136, and the bottom surface of the interface insulating layer 138 may be disposed at a higher vertical level than the bottom surface of the cover insulating layer 136.
[0046] Fig. 9 is a cross-sectional view showing a semiconductor device 100B according to an exemplary embodiment, and Fig. 10 is an enlarged view of a portion CX1 in Fig. 9. In Figs. 9 and 10, the same reference numerals as those in Figs. 1 to 8 denote the same components.
[0047] 9 and 10, the gate insulating layer 150 and the word line WL have an L-shaped vertical cross section, and a second insulating liner 164 covers the sidewalls of the word line WL and the sidewalls of the gate insulating layer 150 and extends downward onto the top surface of the second portion 140P2 of the active semiconductor layer 140.
[0048] According to an exemplary embodiment, within one mold opening 130H, a portion of the active semiconductor layer 140 constituting the first cell transistor CTR1 (see FIG. 2) may be connected to a portion of the active semiconductor layer 140 constituting the second cell transistor CTR2 (see FIG. 2) (e.g., the active semiconductor layer 140 may be shared by the first cell transistor CTR1 and the second cell transistor CTR2), and within one mold opening 130H, a portion of the gate insulating layer 150 constituting the first cell transistor CTR1 may be disposed apart from a portion of the gate insulating layer 150 constituting the second cell transistor CTR2. Also, within one mold opening 130H, a portion of the gate insulating layer 150 constituting the first cell transistor CTR1 may have a mirror symmetric shape with respect to a portion of the gate insulating layer 150 constituting the second cell transistor CTR2.
[0049] 11 is a cross-sectional view showing a semiconductor device 100C according to an exemplary embodiment. In FIG. 11, the same reference numerals as in FIGS. 1 to 10 denote the same components.
[0050] 11, the word lines WL have a rectangular vertical cross section, and the widths of the top and bottom of the word lines WL are substantially the same. Also, the second insulating liner 164 described with reference to FIGS. 1 to 5 may be omitted, and a buried insulating layer 166 may be disposed on the sidewalls and top surface of the first insulating liner 162.
[0051] 12A to 23 are schematic diagrams showing a manufacturing method of the semiconductor device 100 according to an exemplary embodiment, in which 12A, 13A, 14, 15A, 16A, 17 to 21, 22A, and 23 are cross-sectional views taken along the line A1-A1' in FIG. 2, 15B, 16B, and 22B are cross-sectional views taken along the line A2-A2' in FIG. 2, and 12B, 13B, 15C, and 16C are top views of 12A, 13A, 15A, and 16A. In 12A to 23, the same reference numerals as in 1 to 11 indicate the same components.
[0052] 12A and 12B, a lower insulating layer 112 is formed on a substrate 110. Then, a plurality of bit lines BL extending in a second horizontal direction Y and a bit line isolation insulating layer 122 filling spaces between the plurality of bit lines BL may be formed on the lower insulating layer 112.
[0053] In an exemplary embodiment, a plurality of bit lines BL can be formed by forming a bit line isolation insulating layer 122 on a lower insulating layer 112, patterning the bit line isolation insulating layer 122 using a mask pattern (not shown) to form a bit line forming space (not shown), forming a conductive layer in the bit line forming space, and removing an upper side of the conductive layer until an upper surface of the bit line isolation insulating layer 122 is exposed.
[0054] 13A and 13B, a mold stack 130S may be formed on the plurality of bit lines BL and the bit line isolation insulating layer 122. As shown in FIG.
[0055] The mold stack 130S may include an etch stop layer 132, a mold insulating layer 134, and a cover insulating layer 136. For example, the etch stop layer 132 may be formed using silicon nitride, the mold insulating layer 134 may be formed using silicon oxide, and the cover insulating layer 136 may be formed using silicon nitride.
[0056] Then, a mask pattern (not shown) may be formed on the mold stack 130S, and a plurality of mold openings 130H may be formed using the mask pattern as an etching mask. Top surfaces of the bit lines BL and top surfaces of the bit line isolation insulating layers 122 may be exposed at bottoms of the plurality of mold openings 130H. The plurality of mold openings 130H may be arranged to extend in a first horizontal direction X, and each of the plurality of mold openings 130H may include a first sidewall 130H1 and a second sidewall 130H2 that are opposite to each other and extend in the first horizontal direction X.
[0057] Referring to FIG. 14, a preliminary active semiconductor layer 140P may be formed on the mold stack 130S to conformally cover the inner walls of the mold opening 130H.
[0058] In an exemplary embodiment, the preliminary active semiconductor layer 140P may be formed using an oxide semiconductor material. For example, the preliminary active semiconductor layer 140P may be formed using an oxide semiconductor material such as indium gallium zinc oxide (In x Ga y Zinc z O), indium tungsten oxide (In x W y O), indium tin gallium oxide (In x Sn y Ga z O), indium aluminum zinc oxide (In x Al y Zinc z O), indium gallium oxide (In x Ga y O), indium tin zinc oxide (In x Sn y Zinc z O), indium gallium silicon oxide (In x Ga y S z O), indium zinc oxide (In x Zinc y O), indium oxide (In x O), and magnesium aluminum zinc oxide (Mgx Al y Zinc z O), zinc tin oxide (Zn x Sn y O), zirconium zinc tin oxide (Zr x Zinc y Sn z O), gallium zinc tin oxide (Ga x Zinc y Sn z O), aluminum zinc tin oxide (Al x Zinc y Sn z O), and tin oxide (Sn x O) may include at least one of
[0059] In an exemplary embodiment, the preliminary active semiconductor layer 140P may be formed using at least one of a chemical vapor deposition (CVD) process, a low pressure CVD process, a plasma enhanced CVD process, a metal organic CVD (MOCVD) process, and an atomic layer deposition process.
[0060] 15A to 15C, a first mask layer 210 may be formed on the preliminary active semiconductor layer 140P. The first mask layer 210 may be formed to a thickness that is sufficiently large to fill the entire mold opening 130H.
[0061] Then, a mask pattern (not shown) may be formed on the first mask layer 210, and a portion of the preliminary active semiconductor layer 140P may be removed using the mask pattern and the first mask layer 210 as an etching mask. For example, the mask pattern may have a line shape extending in the first horizontal direction X, so that the preliminary active semiconductor layer 140P may also remain on the inner wall of the mold opening 130H and the upper surface of the mold stack 130P to extend along the first horizontal direction X.
[0062] In addition, a portion of the preliminary active semiconductor layer 140P may be removed, so that the upper surface of the bit line isolation insulating layer 122 may be exposed again at the bottom of the mold opening 130H.
[0063] 16A through 16C, the first mask layer 210 may be removed.
[0064] Thereafter, a second mask layer 220 may be formed on the mold stack 130S and the preliminary active semiconductor layer 140P. The second mask layer 220 may be formed to a sufficient thickness to completely fill the mold opening 130H, such that the top surface of the preliminary active semiconductor layer 140P disposed on the top surface of the mold stack 130S may be covered by the second mask layer 220.
[0065] Thereafter, a planarization process may be performed on the upper side of the second mask layer 220 to remove the preliminary active semiconductor layer 140P disposed on the upper surface of the mold stack 130S (e.g., the cover insulating layer 136) and leave the preliminary active semiconductor layer 140P on the inner wall of the mold opening 130H. By removing the preliminary active semiconductor layer 140P disposed on the upper surface of the mold stack 130S (e.g., the upper surface of the cover insulating layer 136), a plurality of active semiconductor layers 140 spaced apart in the first horizontal direction X and the second horizontal direction Y may be defined such that one active semiconductor layer 140 is disposed at a portion where one mold opening 130H and one bit line BL intersect.
[0066] The active semiconductor layer 140 may include a first portion 140P1 disposed on the sidewalls 130H1, 130H2 of the mold opening 130H and a second portion 140P2 disposed on the bottom of the mold opening 130H and contiguously connected to the first portion 140P1. The active semiconductor layer 140 may have a U-shaped vertical cross-section.
[0067] Referring to FIG. 17, the second mask layer 220 may be removed.
[0068] Thereafter, a gate insulating layer 150 may be formed on the preliminary active semiconductor layer 140P.
[0069] In an exemplary embodiment, the gate insulating layer 150 is made of at least one selected from a high-k dielectric material having a dielectric constant higher than silicon oxide and a ferroelectric material. In some embodiments, the gate insulating layer 150 is made of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), or the like. , titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).
[0070] A word line metal layer WLP is formed on the gate insulating layer 150 .
[0071] In exemplary embodiments, the word line metal layer WLP may be formed using Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or combinations thereof.
[0072] 18, a first insulating liner 162 may be formed on the word line metal layer WLP, and an anisotropic etching process may be performed on the word line metal layer WLP and the first insulating liner 162 to remove the word line metal layer WLP portions disposed on the bottoms of the mold openings 130H, leaving the word lines WL on the first sidewalls 130H1 and second sidewalls 130H2 of the mold openings 130H. Meanwhile, the anisotropic etching process may also remove the word line metal layer WLP portions disposed on the upper surface of the mold stack 130P. After the anisotropic etching process, two word lines WL may be disposed spaced apart from each other on the first sidewalls 130H1 and second sidewalls 130H2 of the plurality of mold openings 130H.
[0073] 19, a second insulating liner 164 and a buried insulating layer 166 are formed inside the mold opening 130H. The second insulating liner 164 may be disposed on an upper surface of the active semiconductor layer 140 disposed at the bottom of the mold opening 130H, for example, on a second portion 140P2 of the active semiconductor layer 140, and the buried insulating layer 166 may fill the mold opening 130H on the second insulating liner 164.
[0074] In an exemplary embodiment, buried insulating layer 166 has an upper surface that is disposed in the same bell as the upper surface of mold stack 130S, and the upper surface of first portion 140P1 of active semiconductor layer 140 and the upper surface of gate insulating layer 150 may also be disposed in the same bell as the upper surface of mold stack 130S.
[0075] 20, a portion of an upper portion of the active semiconductor layer 140 may be removed by an etch-back process to form a landing pad recess space 170R. The landing pad recess space 170R refers to a space between the upper surface of the active semiconductor layer 140 and the upper side of the mold stack 130S and the buried insulating layer 166. The upper surface of the active semiconductor layer 140 may be disposed at the bottom of the landing pad recess space 170R.
[0076] In an exemplary embodiment, the landing pad recess space 170R is formed to a depth that exposes the sidewall of the cover insulating layer 136, and the top surface of the first portion 140P1 of the active semiconductor layer 140 may be disposed at the same level as the bottom surface of the cover insulating layer 136.
[0077] 21A and 21B, an oxygen annealing process P200 may be performed on the upper surface of the active semiconductor layer 140 exposed in the landing pad recess space 170R.
[0078] In an exemplary embodiment, the oxygen annealing process P200 may include exposing the upper surface of the active semiconductor layer 140 to an atmosphere containing oxygen. For example, the oxygen annealing process P200 may include supplying at least one of oxygen gas, air, ozone, or oxygen plasma to the active semiconductor layer 140 so that oxygen atoms penetrate through the upper surface of the active semiconductor layer 140 exposed to the landing pad recess space 170R.
[0079] In an exemplary embodiment, the oxygen annealing process P200 may be performed under atmospheric pressure or at increased pressure. In some embodiments, the oxygen annealing process P200 may be performed sequentially under vacuum and atmospheric pressure. In an exemplary embodiment, the oxygen annealing process P200 may be performed at room temperature to an elevated temperature. In an exemplary embodiment, the oxygen annealing process P200 may be performed for several minutes to several hours.
[0080] In an exemplary embodiment, by performing the oxygen annealing process P200, oxygen atoms may penetrate and / or diffuse into the active semiconductor layer 140, passivating oxygen vacancies contained within the active semiconductor layer 140, thereby adjusting the carrier concentration of the active semiconductor layer 140.
[0081] In an exemplary embodiment, an oxygen annealing process P200 may be performed through the upper surface of the active semiconductor layer 140 exposed to the landing pad recess space 170R to provide a sufficient supply of oxygen atoms within the active semiconductor layer 140.
[0082] In an exemplary embodiment, as a result of performing the oxygen annealing process on the top surface of the cover insulating layer 136 exposed to the inner wall of the landing pad recess space 170R, a portion of the cover insulating layer 136 may be oxidized to form an interfacial insulating layer 138. The interfacial insulating layer 138 may be formed on the entire top surface of the cover insulating layer 136 exposed during the oxygen annealing process P200. Also, the interfacial insulating layer 138 may be formed on the sidewalls of the cover insulating layer 136 exposed within the landing pad recess space 170R during the oxygen annealing process P200.
[0083] In an exemplary embodiment, the interface insulating layer 138 formed on the sidewall of the cover insulating layer 136 may have a first thickness t11 (see FIG. 5), and the interface insulating layer 138 formed on the upper surface of the cover insulating layer 136 may have a second thickness t12 (see FIG. 5). In an exemplary embodiment, the first thickness t11 and the second thickness t12 are in the range of several to several tens of angstroms. In some embodiments, the first thickness t11 is substantially the same as the second thickness t12. In some embodiments, the first thickness t11 is thinner than the second thickness t12.
[0084] Here, the structure in which the etch stop layer 132, the mold insulating layer 134, the cover insulating layer 136, and the interface insulating layer 138 are arranged in this order is referred to as a mold structure 130.
[0085] 22, a landing pad 170 may be formed on the mold structure 130 and the buried insulating layer 166. The landing pad 170 may fill the landing pad recess space 170R and contact an upper surface of the first portion 140P1 of the active semiconductor layer 140.
[0086] In an exemplary embodiment, landing pad 170 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or combinations thereof.
[0087] In some embodiments, prior to forming the landing pad 170 in the landing pad recess space 170R, impurity ions may be implanted into an upper surface of the first portion 140P1 of the active semiconductor layer 140 exposed in the landing pad recess space 170R to form a contact region.
[0088] 23, a landing pad isolation insulating layer 172 covering the landing pads 170 may be formed on the mold structure 130 and the buried insulating layer 166. As shown in FIG.
[0089] In an exemplary embodiment, the landing pad isolation insulating layer 172 may be formed using silicon nitride.
[0090] Next, a bottom electrode 182 , a capacitor dielectric layer 184 , and a top electrode 186 may be sequentially formed on the landing pad 170 and the landing pad isolation insulating layer 172 .
[0091] The semiconductor device 100 can be completed by performing the above-mentioned processes.
[0092] According to an example embodiment, the oxygen annealing process P200 may cause oxygen atoms to penetrate and / or diffuse into the active semiconductor layer 140, thereby passivating oxygen vacancies in the active semiconductor layer 140 or adjusting the carrier concentration of the active semiconductor layer 140. As a result, the semiconductor device 100 may have excellent electrical performance.
[0093] In another embodiment, in the process described with reference to FIG. 20, the landing pad recess space 170R is formed to a depth that exposes only the upper portion of the sidewall of the cover insulating layer 136, and the upper surface of the first portion 140P1 of the active semiconductor layer 140A (see FIG. 6) may be disposed at a level higher than the bottom surface of the cover insulating layer 136. In this case, when the oxygen annealing process P200 is performed in the process described with reference to FIG. 21, the interface insulating layer 138 may be formed only on the upper portion of the sidewall of the cover insulating layer 136 exposed by the landing pad recess space 170R. The lower portion of the sidewall of the cover insulating layer 136 is covered by the active semiconductor layer 140A and is not exposed to the oxygen atmosphere, and the interface insulating layer 138 is not formed on the lower portion of the sidewall of the cover insulating layer 136. In this case, the semiconductor device 100A described with reference to FIGS. 6 to 8 may be manufactured.
[0094] As described above, the drawings and the specification disclose exemplary embodiments. Although specific terms are used in the present specification to describe the embodiments, these terms are merely used to describe the technical ideas of the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, a person having ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical ideas of the claims. [Explanation of symbols]
[0095] 110 Substrate 112 Lower insulating layer 122 Bit line isolation insulating layer 130 Mold Structure 130H mold opening 130H1 1st side wall 130H2 2nd side wall 132 Etching stop film 134 Molded insulation layer 136 Cover insulation layer 138 Interface Insulation Layer 140 Active semiconductor layer 140P1 Part 1 140P2 2nd part 150 Gate insulation layer 162 First insulating liner 164 Second insulating liner 166 Buried Insulating Layer 170 Landing Pad 170U Upper 170B Lower 170R Landing pad recess space BL Bit Line WL Word Line t11 1st thickness t12 second thickness CTR1 First cell transistor CTR2 Second cell transistor X 1st horizontal direction
Claims
1. a bit line extending in a first horizontal direction on the substrate; a mold structure including a mold opening extending over the bit line and extending in a second horizontal direction perpendicular to the first horizontal direction, the mold structure including a mold insulating layer, a cover insulating layer disposed on the mold insulating layer, and an interfacial insulating layer disposed on a top surface and on at least a portion of a sidewall of the cover insulating layer; an active semiconductor layer, the active semiconductor layer being disposed on an inner wall of the mold opening of the mold structure, the active semiconductor layer including a first portion extending in a vertical direction perpendicular to an upper surface of the substrate and a second portion connected to a bottom of the first portion and extending in the first horizontal direction, the second portion being disposed on an upper surface of the bit line, the first portion including a first sidewall contacting a sidewall of the mold opening and a second sidewall opposite to the first sidewall; a word line disposed on the second sidewall of the active semiconductor layer and extending in the second horizontal direction; a gate insulating layer interposed between the active semiconductor layer and the word line.
2. a landing pad extending over a top surface of the first portion of the active semiconductor layer; the interfacial insulating layer extends between the landing pad and the cover insulating layer; 2. The semiconductor device according to claim 1, wherein the landing pad is not in direct contact with the cover insulating layer.
3. the active semiconductor layer has a U-shaped vertical cross-section; 2. The semiconductor device according to claim 1, wherein the word line has an L-shaped vertical cross section.
4. a landing pad extending over a top surface of the first portion of the active semiconductor layer; the landing pad includes an upper portion and a lower portion; the lower portion of the landing pad extends within a landing pad recess space defined between the mold structure and the gate insulating layer above an upper surface of the active semiconductor layer; The semiconductor device of claim 1 , wherein the upper portion of the landing pad is disposed on a top surface of the mold structure.
5. the top portion of the landing pad has a first width in the first horizontal direction; 5. The semiconductor device of claim 4, wherein the lower portion of the landing pad has a second width in the first horizontal direction that is narrower than the first width.
6. the interface insulating layer extends from the top surface of the cover insulating layer onto a sidewall of the cover insulating layer disposed within the landing pad recess space; 5. The semiconductor device according to claim 4, wherein a portion of the interface insulating layer extending on the sidewall of the cover insulating layer contacts the landing pad.
7. the first portion of the active semiconductor layer has a top surface disposed at the same level as or lower than a bottom surface of the cover insulating layer; 7. The semiconductor device according to claim 6, wherein the entire sidewall of the cover insulating layer extending within the landing pad recess space is covered by the interface insulating layer.
8. the first portion of the active semiconductor layer has a top surface disposed at a higher level than a bottom surface of the cover insulating layer; an upper side of the sidewall of the cover insulating layer extending within the landing pad recess space is covered by the interface insulating layer; 7. The semiconductor device of claim 6, wherein an underside of the sidewall of the cover insulating layer contacts a sidewall of the first portion of the active semiconductor layer.
9. a buried insulating layer extending over sidewalls of the wordlines and filling the mold openings; 5. The semiconductor device according to claim 4, wherein a part of a bottom surface of the upper portion of the landing pad is disposed on the upper surface of the buried insulating layer.
10. 5. The semiconductor device according to claim 4, wherein a bottom surface of the landing pad is disposed in the same bell as a bottom surface of the interface insulating layer.
11. 2. The semiconductor device according to claim 1, wherein the interfacial insulating layer contains silicon oxynitride or silicon oxide.
12. The active semiconductor layer is made of indium gallium zinc oxide (In ｘ G ｙ Zinc ｚ O), indium tungsten oxide (In ｘ W ｙ O), indium tin gallium oxide (In ｘ Sn ｙ G ｚ O), indium aluminum zinc oxide (In ｘ A ｙ Zinc ｚ O), indium gallium oxide (In ｘ G ｙ O), indium tin zinc oxide (In ｘ Sn ｙ Zinc ｚ O), indium gallium silicon oxide (In ｘ G ｙ S ｚ O), indium zinc oxide (In ｘ Zinc ｙ O), indium oxide (In ｘ O), and magnesium aluminum zinc oxide (Mg ｘ A ｙ Zinc ｚ O), zinc tin oxide (Zn ｘ Sn ｙ O), zirconium zinc tin oxide (Zr ｘ Zinc ｙ Sn ｚ O), gallium zinc tin oxide (Ga ｘ Zinc ｙ Sn ｚ O), aluminum zinc tin oxide (Al ｘ Zinc ｙ Sn ｚ O), and tin oxide (Sn ｘ 10. The semiconductor device according to claim 1, further comprising at least one of the following:
13. a bit line extending in a first horizontal direction on the substrate; a mold structure including a mold opening extending over the bit line and extending in a second horizontal direction perpendicular to the first horizontal direction, the mold structure including a mold insulating layer, a cover insulating layer disposed on the mold insulating layer, and an interfacial insulating layer disposed on a top surface and on at least a portion of a sidewall of the cover insulating layer; an active semiconductor layer including a first portion extending on an inner wall of the mold opening of the mold structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a second portion connected to a bottom of the first portion and extending in the first horizontal direction; a word line extending on a sidewall of the active semiconductor layer and extending in the second horizontal direction; a gate insulating layer extending between the active semiconductor layer and the word line; a landing pad electrically connected to an upper surface of the first portion of the active semiconductor layer, the landing pad including an upper portion extending on the upper surface of the mold structure and a lower portion connected to the upper portion and extending within a landing pad recess space; a bottom surface of the lower portion of the landing pad extends at the same level as a bottom surface of the interfacial insulating layer; the first portion includes a first sidewall in contact with a sidewall of the mold opening and a second sidewall opposite the first sidewall; the second portion extends above an upper surface of the bit line.
14. the interface insulating layer extends from the top surface of the cover insulating layer onto a sidewall of the cover insulating layer disposed within the landing pad recess space; The semiconductor device according to claim 13 , wherein a portion of the interface insulating layer disposed on the sidewall of the cover insulating layer contacts the lower portion of the landing pad.
15. the interface insulating layer extends between the lower portion of the landing pad and the cover insulating layer; The semiconductor device of claim 14 , wherein the lower portion of the landing pad is not in direct contact with the cover insulating layer.
16. the first portion of the active semiconductor layer has a top surface disposed at the same level as or lower than a bottom surface of the cover insulating layer; 14. The semiconductor device according to claim 13, wherein the entire sidewall of the cover insulating layer disposed in the landing pad recess space is covered by the interface insulating layer.
17. a buried insulating layer extending over sidewalls of the wordlines and filling the mold openings; 14. The semiconductor device of claim 13, wherein a portion of a bottom surface of the upper portion of the landing pad extends above an upper surface of the buried insulating layer.
18. the interfacial insulating layer comprises silicon oxynitride or silicon oxide; The semiconductor device according to claim 13 , wherein the cover insulating layer contains silicon nitride.
19. a bit line extending in a first horizontal direction on the substrate; a mold structure including a mold opening extending over the bit line and extending in a second horizontal direction perpendicular to the first horizontal direction, the mold structure including a mold insulating layer, a cover insulating layer disposed on the mold insulating layer, and an interfacial insulating layer disposed on a top surface and on at least a portion of a sidewall of the cover insulating layer; an active semiconductor layer disposed on an inner wall of the mold opening of the mold structure, the active semiconductor layer including a first portion extending in a vertical direction perpendicular to an upper surface of the substrate and a second portion connected to a bottom of the first portion and extending in the first horizontal direction, the second portion extending on an upper surface of the bit line, the first portion including a first sidewall contacting a sidewall of the mold opening and a second sidewall opposite the first sidewall, and having a top surface extending at a level lower than a top surface of the mold structure; a word line extending on the second sidewall of the active semiconductor layer and extending in the second horizontal direction; a gate insulating layer interposed between the active semiconductor layer and the word line; a buried insulating layer extending over sidewalls of the wordlines and filling the mold openings; a landing pad electrically connected to an upper surface of the first portion of the active semiconductor layer, the landing pad including: an upper portion disposed on the upper surface of the mold structure; and a lower portion connected to the upper portion and disposed within a landing pad recess space; a storage node coupled onto the landing pad; The interfacial insulating layer extends from the top surface of the cover insulating layer onto a sidewall of the cover insulating layer that extends within the landing pad recess space.
20. the first portion of the active semiconductor layer has a top surface disposed at the same level as or lower than a bottom surface of the cover insulating layer; the entire sidewall of the cover insulating layer disposed in the landing pad recess space is covered by the interface insulating layer; 20. The semiconductor device of claim 19, wherein the interfacial insulating layer extends between the bottom of the landing pad and the cover insulating layer and does not directly contact the cover insulating layer.