Semiconductor device including interconnect package having embedded capacitor

Abstract

To provide a semiconductor device including an interconnect package capable of fast and efficient power supply to a load.SOLUTION: A semiconductor device includes at least two semiconductor chips arranged laterally, and a semiconductor package is provided that includes a die stack separated from each other by a molding material, and an interconnect package that is arranged above or below the die stack and connects the semiconductor chips to each other. The interconnect package having a lateral width smaller than the die stack is completely covered by the die stack in a vertical direction, and a capacitor is arranged in the interconnect package and is configured to be connected to at least one of the semiconductor chips and to be connected to a voltage source and the ground.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present invention relates to semiconductor devices that include interconnect packages with embedded capacitors. [Background technology]

[0002] Semiconductor packaging technology has been rapidly developing to meet the demands of high component density and performance for integrated circuits. In multi-chip semiconductor packaging, a technical challenge is the design of interconnect structures that connect semiconductor chips in a semiconductor package, taking into account impedance and noise that can adversely affect the performance of semiconductor devices that contain the semiconductor chips.

[0003] The information disclosed in this Background Art is information that was known to the inventors prior to or during the realization of the embodiments of the present invention, or was derived from the inventors, or is technical information obtained during the realization of the embodiments of the present invention, and therefore may include information that does not constitute prior art that is already publicly known. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned conventional technology, and an object of the present invention is to provide a semiconductor device and an electronic device including an interconnect package that can provide a stable power supply to a semiconductor chip in a semiconductor package while reducing the size of the entire semiconductor package. [Means for solving the problem]

[0005] The present invention provides a semiconductor package including at least one interconnect package having at least one capacitor disposed therein and connected to a semiconductor chip, the interconnect package being stacked on a package substrate with a rewiring substrate therebetween. The rewiring substrate includes a plurality of wiring traces connecting the semiconductor chip to other circuit elements within or outside the package substrate. The interconnect package is included in the rewiring substrate. The semiconductor package is a fan-out wafer level package (FOWLP). The capacitor is a decoupling capacitor configured to reduce impedance and noise applied to a load, i.e., the semiconductor chip within the semiconductor package.

[0006] Although decoupling capacitors are generally implemented by die side capacitors (DSC) or land side capacitors (LSC) located on the top or bottom surface of a package substrate, respectively, a semiconductor package according to an embodiment includes at least one capacitor in an interconnect package provided to locally connect semiconductor chips to each other with a small footprint. Thus, at least one of the DSC and LSC can be removed from the semiconductor package, because the capacitor in the interconnect package replaces the removed DSC or LSC as a decoupling capacitor. This capacitor included in the interconnect package is called an integrated stack capacitor (ISC), and has a thickness of a few micrometers or less and a very high capacitance density.

[0007] The interconnect package includes a plurality of dielectric layers and at least one redistribution layer having wiring traces formed thereon, and a capacitor formed on the at least one wiring trace.

[0008] In the interconnect package, a redistribution layer is formed on the top of the interconnect package, and a capacitor is formed in the upper portion of the redistribution layer, so that the capacitor can be located closer to the semiconductor chip for better decoupling performance. Effect of the Invention

[0009] According to the present invention, by embedding a capacitor in a redistribution layer of an interconnect package, the semiconductor package can provide power to a semiconductor chip with low impedance and low noise, and can reduce the footprint of a semiconductor device including the semiconductor package.

[0010] The present invention also provides semiconductor and electronic devices that include interconnect packages that enable fast and efficient power delivery to packaged semiconductor chips. [Brief description of the drawings]

[0011] [Figure 1A] 1 is a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to one embodiment. [Figure 1B] 1B is a schematic cross-sectional view of an interconnect package included in the semiconductor package shown in FIG. 1A. [Figure 2A] 1 is a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to another embodiment. [Figure 2B] 2B is a schematic cross-sectional view of an interconnect package included in the semiconductor package shown in FIG. 2A. [Figure 3A] 1 is a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to yet another embodiment. [Figure 3B] 3B is a schematic cross-sectional view of an interconnect package included in the semiconductor package shown in FIG. 3A. [Figure 4]4 is a flow chart of a method for manufacturing a semiconductor package including an interconnect package and a decoupling capacitor according to an embodiment. [Figure 5A] FIG. 5 shows an intermediate semiconductor package after step 10 shown in FIG. 4. [Figure 5B] FIG. 5 shows an intermediate semiconductor package after step 20 shown in FIG. 4. [Figure 5C] FIG. 5 shows an intermediate semiconductor package after step 30 shown in FIG. 4. [Figure 5D] FIG. 5 illustrates an intermediate semiconductor package after step 40 shown in FIG. 4. [Figure 5E] FIG. 5 illustrates an intermediate semiconductor package after step 50 shown in FIG. 4. [Figure 5F] FIG. 5 illustrates an intermediate semiconductor package after step 60 shown in FIG. 4. [Figure 6] FIG. 2 is a schematic block diagram of an electronic device including at least one of the semiconductor packages shown in FIGS. 2A-2B and / or 3A-3B, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The embodiments of the present invention described herein are exemplary embodiments, and therefore the present invention is not limited thereto and may be realized in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of other examples or other embodiments provided herein or not provided herein but consistent with the present invention. For example, even if a matter described in a particular example or embodiment is not described in a different example or embodiment, the matter may be understood to be related to or combined with the different example or embodiment unless otherwise stated in the description of the example or embodiment. In addition, all descriptions of principles, aspects, examples, and embodiments of the present invention are intended to encompass structural and functional equivalents thereof. Furthermore, these equivalents should be understood to include not only currently known equivalents but also equivalents developed in the future, i.e., all devices invented to perform the same function regardless of their structure. For example, the channel layer, sacrificial layer, and separation layer described herein may take different types or forms as long as the present invention applies.

[0013] When an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "over," "above," "on," "below," "under," "beneath," or "connected to" or "coupled to" another element of a semiconductor device, the element may be directly on, above, on, below, beneath, connected to, or coupled to the other element, or there may be an intervening element(s) therebetween. In contrast, when an element of a semiconductor device is referred to as being "directly over," "directly above," "directly on," "directly below," "directly under," "directly beneath," "directly connected to," or "directly coupled to" another element of the semiconductor device, there are no intervening elements present. Like numbers refer to like elements throughout this specification.

[0014] Spatially relative terms such as "over," "above," "on," "upper," "below," "under," "beneath," "lower," "left," "right," "lower-left," "lower-right," "upper-left," "upper-right," "central," "middle," and the like, may be used herein to describe the relationship of one element to another element(s) as shown in the multiple figures for ease of description. It will be understood that the spatially relative terms are intended to encompass different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the figures were flipped over, elements described as "below" or "beneath" other elements would be oriented "above" the other elements. Thus, the term "below" includes both an orientation of above and below. The semiconductor device may be oriented in other directions (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly. As another example, elements referred to as "left" and "right" elements may become "right" and "left" elements when the device or structure containing these elements is oriented in a different direction. Thus, in the following description, "left" and "right" elements may also be referred to as "first" or "second" elements, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" and "upper" elements may be referred to as "first" and "second" elements, respectively, with any necessary description to distinguish between the two elements.

[0015] In this specification, terms such as "first," "second," "third," "fourth," "fifth," "sixth," etc. may be used to describe various elements, but it is understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element described below could also be named a second element without departing from the teachings of the present invention.

[0016] As used herein, the phrase "at least one," when preceding a list of elements, modifies the entire list of elements and not any individual element of the list. For example, the phrase "at least one of a, b, and c" should be understood to include a alone, b alone, c alone, both a and b, both a and c, both b and c, or all of a, b, and c. When the terms "same" or "equal" are used herein to compare dimensions of two or more elements, the terms may apply to "substantially the same" or "substantially equal" dimensions.

[0017] It will also be understood that when a method of manufacturing a device or structure is described as including multiple steps or operations, even if a step or operation is described as being performed after other steps or operations, the step or operation may be performed before or concurrently with the other steps or operations, unless the other steps or operations are described as being performed prior to the other steps or operations. Additionally, the method may include additional steps or operations not described herein.

[0018] Many embodiments are described herein with reference to cross-sectional views that are schematic illustrations of the embodiments (and intermediate structures). As such, variations in the shapes shown are expected, for example, as a result of manufacturing techniques and / or tolerances. Thus, the embodiments should not be construed as limited to the particular shapes of the regions illustrated herein, and include, for example, deviations in shapes that result from manufacturing. The various regions shown in the figures are schematic in nature, and the shapes are not intended to represent the actual shapes of the regions of the device and are not intended to limit the scope of the invention. Additionally, in the figures, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0019] For the sake of brevity, conventional elements, structures, or layers included in a semiconductor package, including connection pads, adhesive layers, isolation layers, barrier metal patterns, seed layers, etc., may or may not be described in detail herein. For example, certain connection pads of a semiconductor chip that are connected to solder balls or bumps in a semiconductor package may be omitted herein if these structural elements are not related to novel features of the embodiments. Also, descriptions of materials forming well-known structural elements may be omitted herein if these materials are not related to novel features of the embodiments. Herein, the term "connection" between two structures or elements may refer to an electrical connection between them. For example, a connection between a semiconductor chip, a semiconductor package, and / or a semiconductor device may refer to electrically connecting two or more corresponding elements to each other. The terms "coupled" and "connected" have the same meaning and may be used interchangeably herein. Additionally, the term "separation" between two structures or elements relates to electrical insulation or electrical separation between them. For example, separating wiring patterns from each other means that the wiring patterns are not electrically connected to each other.

[0020] Various embodiments of the present invention will now be described with reference to FIGS.

[0021] High-performance semiconductor chips, such as central processing units (CPUs), graphic processing units (GPUs), and artificial intelligence (AI) chips, consume a large amount of power compared to other types of semiconductor chips, such as memory chips. For example, the power consumption of these high-performance chips can reach very high levels (e.g., about 1000W) as thermal design power (TDP). The high power consumption poses challenges in designing power delivery networks (PDNs) for high-performance chips, and there is an increasing need to design low impedance PDNs across multiple frequency ranges when designing and manufacturing semiconductor packages that contain high-performance chips.

[0022] Advances in packaging technology for multiple high-performance semiconductor chips have resulted in sizes up to 3,000 square millimeters (mm), three to four times the size of the reticle. 2 A number of different die-to-die interconnect structures have been introduced, such as silicon interposers, which extend to 1000 MHz to 1000 MHz. The silicon interposer includes a redistribution layer (RDL) in which a number of wiring patterns or traces are formed on one or more dielectric layers to connect semiconductor chips together in a semiconductor package. Therefore, the power supply risk in a multi-chip package including the above interconnect structure is also a consideration factor when designing a semiconductor package. Furthermore, when the interconnect structure includes active elements such as transistors and metal layers, the power consumption increases under a certain switching frequency of the active elements. Therefore, there is a need to reduce the power supply risk or reduce the impedance applied to a multi-chip package in which the interconnect structure connects semiconductor chips together.

[0023] A decoupling capacitor is included in a semiconductor package to control impedance in a power supply path to a semiconductor chip in the semiconductor package and remove noise. As a decoupling capacitor, a conventional semiconductor package includes one or more capacitors such as a multilayer ceramic capacitor (MLCC), a metal-in-metal (MiM) capacitor, a deep trench capacitor (DTC), etc. How to configure one or more decoupling capacitors in a semiconductor package can affect the power supply performance of a semiconductor device including a semiconductor package of various semiconductor chips that require high power.

[0024] FIG. 1A is a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to one embodiment, and FIG. 1B is a schematic cross-sectional view of an interconnect package included in the semiconductor package shown in FIG. 1A according to one embodiment.

[0025] 1A, according to one embodiment, a semiconductor package 10 includes a package substrate 100, a redistribution substrate 200 disposed thereon, and a die stack 300 disposed on the redistribution substrate 200 and having a plurality of connection structures therebetween. The die stack 300 includes a plurality of semiconductor chips 300A-300C that are laterally arranged and separated from one another, and the redistribution substrate 200 includes an interconnect package 400 therein.

[0026] The semiconductor package 10 is a fan-out wafer-level package (FOWLP) characterized by one or more redistribution layers connecting the semiconductor chip or die to the package substrate. The FOWLP allows for smaller package size and improved electrical performance compared to other types of semiconductor packages such as fan-in packages and wirebond packages. In the FOWLP, the lateral edges of the package profile extend in the D1 direction beyond the lateral edges of the semiconductor chips 300A-300C contained in the package, as shown in FIG. 1A. The lateral width WD1 of each of the die stack 300 and the redistribution substrate 200 is smaller than the lateral width WD2 of the package substrate 100. Furthermore, the lateral width WD1 of each of the die stack 300 and the redistribution substrate 200 is larger than the lateral width WD3 of the interconnect package 400.

[0027] Each of the semiconductor chips 300A to 300C may be, but is not limited to, a system on chip (SoC), a microprocessor chip such as a CPU, a GPU, or a neural processing unit (NPU), an AI chip, an application specific integrated circuit (ASIC) chip, an image sensor chip, a power management chip, or a memory chip. The SoC may include a CPU, a GPU, an NPU, or an AI module.

[0028] The package substrate 100 includes a substrate core 100C, a lower build-up layer 100L, and an upper build-up layer 100U. The substrate core 100C provides structural stability to the semiconductor package 10 and is formed of an insulating material such as, but not limited to, epoxy resin or ceramic. The package substrate 100 may be a printed circuit board or a motherboard of an electronic device or an electronic system. Alternatively, the package substrate 100 may be a part of a printed circuit board or a motherboard of an electronic device or an electronic system.

[0029] The lower build-up layer 100L and the upper build-up layer 100U are respectively laminated on the bottom and top surfaces of the substrate core 100C to provide additional connection and wiring space for the semiconductor package 10. The build-up layers 100L and 100U each include one or more dielectric layers, in which a plurality of wiring patterns 100W are formed to be connected to each other or to core vias 100V that vertically penetrate the package substrate 100. Each wiring pattern in the dielectric layer includes at least one line portion and at least one via portion connected to each other to form a damascene structure. The line portion and the via portion are the same as or similar to the line portion L and the via portion V, respectively, included in the interconnect package 400 described below with reference to FIG. 1B. The wiring pattern 100W is also called a wiring trace.

[0030] The wiring pattern 100W and the core via 100V are each formed of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo). The dielectric layer is formed of an organic material such as, but not limited to, a photosensitive polymer, e.g., a photosensitive polyimide. Alternatively or additionally, the dielectric layer is formed of a silicon oxide (e.g., SiO or SiO 2 The dielectric layer is formed of at least one of, but not limited to, silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON), and silicon carbonitride (e.g., SiCN). The dielectric layer has insulating properties so that the wiring patterns 100W are electrically isolated from each other in the dielectric layer.

[0031] Furthermore, a plurality of external terminals 100T such as solder balls or bumps are formed on the bottom surface of the lower buildup layer 100L, which is also the bottom surface of the package substrate 100. The external terminals 100T connect the semiconductor chips 300A-300C to external circuit elements via various connection structures formed in the package substrate 100 and a rewiring substrate 200 described later.

[0032] A plurality of reinforcing members 600 are formed on the peripheral upper surface of the package substrate 100, thereby preventing warping of the package substrate 100 that may occur during the packaging process of the semiconductor package 10 or after the semiconductor package 10 is completed. The reinforcing members 600 may be made of, but are not limited to, metal, ceramic, or a composite material thereof.

[0033] The redistribution substrate 200 includes a first redistribution layer 200L and a second redistribution layer 200U, which are connected to each other via a plurality of first through vias 200V separated from each other by a first mold layer 200M formed of epoxy resin. The first redistribution layer 200L is disposed so as to face the package substrate 100, and the second redistribution layer 200U is disposed so as to face the die stack 300 including the semiconductor chips 300A to 300C.

[0034] The redistribution layers 200L and 200U each include a plurality of wiring traces separated from each other via one or more vertically stacked dielectric layers, and are each connected to the first through via 200V. The wiring traces included in the first redistribution layer 200L are connected to the core via 100V in the package substrate 100 via a plurality of lower connection terminals 200T separated from each other by the first underfill layer 200F. In addition, not only the first through via 200V but also the wiring traces of the redistribution layers 200L and 200U may be formed of metals such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo), but are not limited thereto.

[0035] The wiring traces and dielectric layers of the redistribution layers 200L and 200U are similar or identical in shape, material, function or role to the wiring patterns of the build-up layers 100L and 100U of the package substrate 100. Therefore, duplicated descriptions are omitted in this specification. The first underfill layer 200F is formed of an epoxy resin, but is not limited thereto.

[0036] A die stack 300 including semiconductor chips 300A-300C, each of which is a high-performance chip such as a system on chip (SoC) or a memory chip, is disposed on the second redistribution layer 200U. The semiconductor chips 300A-300C are connected to wiring traces in the second redistribution layer 200U via upper connection terminals 300T separated from each other by a second underfill layer 300F, which may be formed of the same or similar material as the first underfill layer 200F (e.g., epoxy resin).

[0037] For example, but not limited to, semiconductor chips 300A and 300C may be high bandwidth memories (HBM) and semiconductor chip 300B may be a system on a chip (SoC). A second molding layer 300M, for example including an epoxy resin, is formed on the sides of the chips to laterally separate each chip from the other chips.

[0038] In addition, the upper connection terminals 300T and the lower connection terminals 200T may be solder balls or bumps, like the external terminals 100T, and both may be formed from metal materials such as copper (Cu), tin (Sb), lead (Pb), silver (Ag), etc., or composite materials thereof, but are not limited to these.

[0039] The semiconductor package 10 may include multiple interconnect packages 400 in the redistribution substrate 200 below the second redistribution layer 200U, which are used to connect or bridge the semiconductor chips 300A-300C to one another.

[0040] For example, one of the interconnect packages 400 is embedded in the redistribution substrate 200 under the boundary of the adjacent semiconductor chips 300A and 300B in the second mold layer 300M and is at least partially covered by each of the two chips to shorten the connection length between the two semiconductor chips. Furthermore, the lateral width WD3 of the interconnect package 400 is smaller than the lateral width WD1 of each of the redistribution substrate 200 and the die stack 300. Therefore, the entire lateral width of each of the die stack 300 and the redistribution substrate 200 does not vertically overlap the entire lateral width of the interconnect package 400 in the vertical direction, i.e., in the D3 direction where the D1 direction and the D2 direction intersect.

[0041] 1A and 1B, the interconnect package 400 includes a third redistribution layer 400R and a support layer 400S, and the support layer 400S is attached to the first redistribution layer 200L of the redistribution substrate 200 via a die attach film (DAF) 400F. The third redistribution layer 400R includes a dielectric layer 400D and a plurality of wiring traces 400W formed therein. The wiring traces 400W locally connect the two semiconductor chips 300A and 300B to each other, and are connected to a voltage source for supplying power to the semiconductor chips 300A and 300B via the second redistribution layer 200U and the upper connection terminals 300T connected thereto.

[0042] As shown in FIG. 1B, the dielectric layer 400D of the interconnect package 400 includes a plurality of dielectric layers D1-D4 vertically stacked on the support layer 400S. Furthermore, the wiring trace 400W includes one or more power wiring traces W1 and one or more signal wiring traces W2 embedded in the dielectric layers D1-D4. The power wiring trace W1 may include a power line and a ground line for power supply through the second redistribution layer 200U. The signal wiring trace W2 connects the two semiconductor chips 300A and 300B to each other. Each of the wiring traces W1 and W2 includes at least one line portion L and at least one via portion V connected to each other across the plurality of dielectric layers D1-D4 forming the dielectric layer 400D of the interconnect package 400.

[0043] In this embodiment, the dielectric layer 400D includes four dielectric layers D1 to D4. However, the present invention is not limited thereto, and in some embodiments, the dielectric layer 400D may include more or less than the four dielectric layers D1 to D4. For example, the dielectric layer 400D may be a single dielectric layer.

[0044] Similarly, another interconnect package 400 is disposed below the boundary between adjacent semiconductor chips 300B and 300C in the second molding layer 300M and connects the semiconductor chips 300B and 300C to each other via wiring traces 400W, wiring traces of the second redistribution layer 200U, and top connection terminals 300T. Although not shown in the drawings, each of the semiconductor chips 300A-300C includes connection pads on its bottom surface, which are connected to the top connection terminals 300T.

[0045] The wiring traces 400W and the dielectric layer 400D in the third redistribution layer 400R are formed of the same material as the wiring traces and the dielectric layers included in the first redistribution layer 200L and the second redistribution layer 200U. Therefore, a duplicated description of these is omitted in this specification. The support layer 400S supporting the upper dielectric layer 400D may be formed of, for example, but is not limited to, silicon, glass, or ceramic.

[0046] Furthermore, the semiconductor package 10 includes a plurality of land side capacitors (LSC) 500L and a plurality of die side capacitors (DSC) 500D disposed on the bottom and top surfaces, respectively, of the package substrate 100. Each of the LSC 500L and the DSC 500D is a decoupling capacitor that controls impedance and noise applied to the semiconductor chips 300A-300C and other active elements (if any) included in the semiconductor package 10. Each of the LSC 500L and the DSC 500D is implemented by a multilayer ceramic capacitor (MLCC), a metal-in-metal (MiM) capacitor, or a deep trench capacitor (DTC).

[0047] Therefore, stable power supply to the semiconductor chips 300A to 300C and other active elements is possible via these decoupling capacitors 500L and 500D.

[0048] However, at least one of the semiconductor chips 300A to 300C may be an SoC, which may include high-performance components such as a CPU, a GPU, an NPU, or an AI module that consumes more power. Therefore, the semiconductor package 10 including the semiconductor chips 300A to 300C may require additional decoupling capacitors.

[0049] FIG. 2A is a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to another embodiment, and FIG. 2B is a schematic cross-sectional view of an interconnect package included in the semiconductor package shown in FIG. 2A according to one embodiment.

[0050] 2A, semiconductor package 20 includes the same structural elements in the same structural arrangement as semiconductor package 10 shown in FIG 1A, but differs in that each of interconnection packages 400 includes a capacitor 700 in the third redistribution layer 400R. Therefore, the following will describe the differences between semiconductor package 20 and semiconductor package 10, but overlapping descriptions may be omitted.

[0051] Capacitor 700 is a capacitor referred to as, but not limited to, an integrated stack capacitor (ISC) embedded in interconnect package 400 and functions as a decoupling capacitor, similar to DSC500D and LSC500L disposed on package substrate 100 as described with reference to FIG. 1A.

[0052] As shown in FIG 2B, the vertical thickness TH1 of the capacitor 700 is less than the vertical thickness of the third redistribution layer 400R and less than the vertical thickness TH2 of one of the dielectric layers D1-D4 of the dielectric layer 400D (e.g., D4 as shown in FIG 2B). Thus, the capacitor 700 is embedded in one of the dielectric layers D1-D4 such that the vertical thickness TH1 of the capacitor 700 is included in or within the vertical thickness TH2 of the single dielectric layer.

[0053] For example, the ISC, which is the capacitor 700, takes the form of a vertical cylinder array including multiple capacitive vias between two or more connection terminals and has a very low profile, e.g., about 2.0×2.0×2.0 μm, while the DSC500D or LSC500C, which is an MLCC, has a size of several hundred micrometers (μm), e.g., about 1.0×0.5×0.35 mm for a 0402 MLCC. The vertical thickness of the ISC in the D3 direction is about 2.0 micrometers, while the vertical thickness of each of the dielectric layers D1-D4 of the dielectric layer 400D in the D3 direction is in the range of 3.0-10.0 micrometers. Furthermore, the ISC has a high capacitance density similar to that of an MLCC. For example, the ISC has a capacitance density of several hundred nanofarads per square millimeter (nF / mm2 ) capacitance value, e.g. 1100nF / mm 2 has.

[0054] Due to the low profile and high capacitance density discussed above, the capacitor 700 is embedded within the third redistribution layer 400R at the desired location for the same functional purpose as the DSC 500D and LSC 500L.

[0055] For example, the capacitor 700 is formed in an upper portion of the third redistribution layer 400R arranged to be adjacent to the semiconductor chips 300A and 300B. When arranged to be adjacent to the semiconductor chips 300A and 300B, the capacitor 700 performs better in controlling impedance and noise applied to the semiconductor chips 300A and 300B than the DSC500D and LSC500L arranged at a position away from the semiconductor chips 300A and 300B. As another example, the capacitor 700 is formed in an upper portion of the power supply wiring trace W1 of the wiring trace 400W, connected to the power supply wiring trace W1 in the third redistribution layer 400R, and connected to the wiring trace of the second redistribution layer 200U directly below the semiconductor chips 300A and 300B.

[0056] By placing the capacitor 700 closer to the load, i.e., the semiconductor chips 300A and 300B, the overall length of the wiring traces between the capacitor 700 and the load is reduced, providing a low impedance path for high frequency currents and minimizing parasitic inductance, thus allowing for faster and more efficient power delivery to the load.

[0057] Capacitor 700 in interconnect package 400 provides at least additional impedance and noise control performance to semiconductor package 20, although DSC500D and LSC500L are disposed on package substrate 100 for the same purpose. However, by design choice, semiconductor package 20 can do without DSC500D and LSC500L since capacitor 700 is included in interconnect package 400 directly underneath semiconductor chips 300A and 300B.

[0058] Furthermore, the semiconductor package 20 can omit at least one of the DSC 500D and the LSC 500L, thereby reducing the overall size of the semiconductor package 20. For example, the external terminals 100T, which are solder balls or bumps, form a ball grid array (BGA) of the semiconductor package 20, but by removing the LSC 500L formed between the external terminals 100T on the bottom surface of the package substrate 100 as shown in FIG. 2A, the constraints on the package design, including the ball design of the BGA semiconductor package 20, can be reduced. For example, the external terminals 100T can be formed by smaller sized solder balls or bumps with a smaller pitch and profile, which helps to reduce the overall stack-up height of the semiconductor package 20.

[0059] The above embodiment of embedding capacitor 700 in interconnect package 400 may also be applied to land grid array (LGA) semiconductor packages, i.e., semiconductor packages 20 without external terminals 100T (solder balls or bumps), in which case removing LSC 500L from the bottom surface of package substrate 100 may eliminate the need for a cavity in the original equipment manufacturer (OEM) socket and improve structural integrity with the OEM socket.

[0060] Meanwhile, the interconnect package 400 including the capacitor 700 is not limited to the structure as shown in FIG. 2A above. According to an embodiment, the interconnect package 400 may include one or more active elements such as transistors therein. For example, FIG. 2B shows that transistors TR, such as field effect transistors, are formed in the support layer 400S and connected to the wiring traces 400W. In this case, the capacitor 700 also serves to reduce the impedance and noise applied to these transistors. Furthermore, the support layer 400S, which structurally supports the third redistribution layer 400R, may have a different configuration as described below.

[0061] FIG. 3A is a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to yet another embodiment, and FIG. 3B is a schematic cross-sectional view of an interconnect package included in the semiconductor package shown in FIG. 3A according to one embodiment.

[0062] 3A and 3B, semiconductor package 30 includes the same structural elements under the same structural configuration as semiconductor package 20, but differs in that interconnect package 400 has one or more second through vias 400V formed therein. Therefore, the differences between semiconductor package 30 and semiconductor package 20 will be described below, and overlapping descriptions may be omitted.

[0063] The second through via 400V is formed to penetrate the support layer 400S and the die attach film 400F and connect the wiring trace 400W of the third redistribution layer 400R to the wiring trace formed in the first redistribution layer 200L. The second through via 400V can be connected to the capacitor 700 to extend the impedance control function of the capacitor 700 to other circuit elements in the semiconductor package 30, including an active element (transistor TR) that may be embedded in the interconnect package 400, as described above in FIG. 2B. Thus, the second through via 400V connects the capacitor to the active element. The second through via 400V is formed of the same or similar metal as the core via 100V and the first through via 200V.

[0064] In the above embodiment, each of the semiconductor packages 20 and 30 is described as including two interconnect packages 400 for connecting three semiconductor chips 300A-300C, and each of the interconnect packages 400 is described as including one capacitor 700, an ISC, embedded therein. However, the invention is not so limited. According to an embodiment, in each of the semiconductor packages 20 and 30, more or less than three semiconductor chips may be disposed on the redistribution substrate 200, and each of the interconnect packages 400 may include multiple capacitors embedded therein for the same or similar purposes as described above for the capacitor 700 in the interconnect package 400.

[0065] In the above embodiment, one interconnect package, i.e., interconnect package 400, is formed below the boundary between two adjacent semiconductor chips 300A and 300B, or 300B and 300C, in each of semiconductor packages 20 and 30. However, one or more additional interconnect packages may be formed below the boundary to provide additional signal routing paths between the two semiconductor chips in semiconductor package 20 or 30. Furthermore, according to an embodiment, one or more capacitors, such as capacitor 700, may be formed in semiconductor package 20 or 30 to further reduce impedance and noise applied to the two semiconductor chips.

[0066] In the above embodiment, each of the semiconductor packages 20 and 30 is formed with one redistribution substrate, i.e., the redistribution substrate 200 having the interconnection package 400 including the capacitor 700. However, according to the embodiment, one or more additional redistribution substrates with or without the interconnection package 400 may be formed above, below, or to the side of the redistribution substrate 200 in the semiconductor package 20 or 30, thereby providing at least one additional redistribution path to the semiconductor chips 300A-300C. For example, one of the semiconductor chips 300A-300C may be connected to another circuit element or semiconductor chip in another semiconductor package or device via the additional redistribution path provided by the additional redistribution substrate in the semiconductor package 20 or 30. Here, the additional redistribution path may be a power supply path or a signal routing path from or to the semiconductor package 20 or 30.

[0067] In the above embodiment, the interconnect package 400 is formed in the redistribution substrate 200 below the semiconductor chips 300A-300C and located above the package substrate 100. However, according to an embodiment, at least one of the interconnect packages 400 may be formed above the semiconductor chips 300A-300C with corresponding connection structures, and the capacitors 700 may be embedded therein. When the interconnect package 400 is formed above the semiconductor chips 300A-300C, the third redistribution layer 400R is formed below the support layer 400S, so that the capacitors 700 formed on the wiring traces 400W in the third redistribution layer 400R can be located near the semiconductor chips 300A-300C.

[0068] Hereinafter, a method for manufacturing a semiconductor package including an interconnect package and a decoupling capacitor according to an embodiment will be described with reference to FIG. 4 and FIGS. 5A to 5F.

[0069] Figure 4 is a flowchart of a method for manufacturing a semiconductor package including an interconnect package and a decoupling capacitor, according to some embodiments. Figures 5A-5F are diagrams illustrating intermediate semiconductor packages after respective steps of manufacturing a semiconductor package including an interconnect package and a decoupling capacitor according to the flowchart shown in Figure 4, according to some embodiments.

[0070] Since the semiconductor package manufactured by the following method is identical to or corresponds to the semiconductor package 20 shown in Figures 2A and 2B, duplicated descriptions will be omitted and the same reference numbers as those used below to refer to the structural elements of the semiconductor package 20 will be used.

[0071] In step S10, as shown in FIG. 5A, the first redistribution layer 200L is disposed on the carrier substrate 101, and the interconnect package 400 and the first through vias 200V are formed on the first redistribution layer 200L.

[0072] The first redistribution layer 200L, which includes one or more dielectric layers and a plurality of wiring traces embedded therein, is bonded to the carrier substrate 101 by adhesive bonding, for example, but not limited to, using an epoxy adhesive. When the first redistribution layer 200L is formed of a plurality of dielectric layers, these dielectric layers are stacked one after the other in a vertical direction, and the wiring traces having line portions and via portions are formed across the dielectric layers and separated from each other.

[0073] The first through vias 200V are formed, for example, through a first photolithography / masking / etching / deposition operation including electroplating, and are connected to the wiring traces in the first redistribution layer 200L, and the interconnect packages 400 are laterally disposed on the first redistribution layer 200L and between the first through vias 200V. Each of the interconnect packages 400 is laterally disposed between the first through vias 200V above a position where an interface of two semiconductor chips that are connected to each other via the interconnect package is located.

[0074] The interconnect package 400 includes a support layer 400S and a third redistribution layer 400R, each on a die attach film 400F, and is bonded to the first redistribution layer 200L by adhesive bonding using, for example, an epoxy adhesive, in a manner similar to the adhesive operation used to form the first redistribution layer 200L on the carrier substrate 101. The third redistribution layer 400R includes a dielectric layer 400D and wiring traces 400W embedded therein. Additionally, the third redistribution layer 400R includes a capacitor 700 in an upper portion thereof, for example, in an upper portion of the wiring traces 400W in the third redistribution layer 400R.

[0075] In step 20, the intermediate semiconductor package obtained in the previous step is overmolded such that the space between the first through vias 200V and the interconnect package 400 is filled with epoxy resin, and the top surfaces of the first mold layer 200M, the first through vias 200V, and the interconnect package 400 are horizontally aligned or flush with each other, see FIG. 5B.

[0076] In step 30, the second redistribution layer 200U is disposed on the intermediate semiconductor package obtained in the previous step, for example by adhesive bonding using an epoxy adhesive, thereby completing the redistribution substrate 200. Furthermore, the upper connection terminals 300T are formed on the second redistribution layer 200U by a second photolithography / masking / etching / deposition operation, for example including electroplating, and are overmolded, for example, by epoxy resin, to form a second underfill layer 300F that isolates the upper connection terminals 300T from each other. The upper connection terminals 300T and the second underfill layer 300F are disposed such that the upper surfaces of the upper connection terminals 300T and the second underfill layer 300F are horizontally aligned or flush with each other. See FIG. 5C.

[0077] Similar to the first redistribution layer 200L, the second redistribution layer 200U also includes one or more dielectric layers and a plurality of wiring traces embedded therein. The second redistribution layer 200U is formed such that the wiring traces included therein are respectively connected to the first through vias 200V and the wiring traces 400W of each interconnect package 400. Furthermore, the upper connection terminals 300T are respectively connected to the wiring traces included in the second redistribution layer 200U.

[0078] In step S40, the semiconductor chips 300A-300C are respectively disposed on and connected to the upper connection terminals 300T, and then overmolded using, for example, epoxy resin, thereby forming a second molding layer 300M between the semiconductor chips 300A-300C and laterally isolating the semiconductor chips 300A-300C, see FIG. 5D.

[0079] The semiconductor chips 300A and 300C may be high bandwidth memories (HBM) and the semiconductor chip 300B may be a system on a chip (SoC), but is not limited thereto.

[0080] In step S50, the carrier substrate 101 is removed, for example by mechanical polishing, and the bottom connection terminals 200T are formed on the bottom surface of the second redistribution layer 200L, for example via soldering, so that the wiring traces in the second redistribution layer 200L are respectively connected to the bottom connection terminals 200T, see FIG. 5E.

[0081] In step S60, the intermediate semiconductor package obtained in the previous step is attached to the package substrate 100 via the lower connection terminals 200T, which are solder balls or bumps, and the lower connection terminals 200T are molded to be separated from each other by the first underfill layer 200F. Surface mount technology (SMT) is applied to attach the intermediate semiconductor package to the package substrate 100, which includes the substrate core 100C, the lower build-up layer 100L, and the upper build-up layer 100U. See FIG. 5F.

[0082] The lower connection terminal 200T is disposed above a core via 100V included in the package substrate 100, and thus the lower connection terminal 200T is connected to an external terminal 100T formed on the lower surface of the package substrate 100.

[0083] Furthermore, the LSC500L and DSC500D may be integrated into the package substrate 100, and the reinforcement member 600 is formed on the peripheral upper surface of the package substrate 100 to prevent warping of the package substrate 100 that may occur at least during subsequent packaging processes.

[0084] FIG. 6 is a schematic diagram of an electronic device including at least one of the semiconductor packages shown in FIGS. 2A-2B and / or 3A-3B, according to one embodiment.

[0085] 6, the electronic device 1000 includes a printed circuit board (PCB) or motherboard 1010 on which a number of semiconductor packages 1011-1015 are mounted. The electronic device 1000 also includes a number of other components 1020.

[0086] The semiconductor package 1011 includes multiple chips such as an SoC and memory chips. The SoC includes at least one of a CPU, a GPU, an AI module, a modem, one or more memory units, a power management unit, etc., and controls the overall operation of the electronic device 1000. The memory chip included in the semiconductor package 1011 may be one or more flash memories, static random access memories (SRAMs), read-only memories (ROMs), etc. The other semiconductor packages 1012-1015 each include a dynamic random access memory (DRAM) chip, various other processor chips, a communication chip, and an interface chip. The communication chip included in the semiconductor package 1014 is configured to perform wireless or wired communication functions in association with the SoC. At least one of the semiconductor packages 1011-1015 may be implemented by the semiconductor package 20 or 30 shown in FIG. 2A and FIG. 3A.

[0087] Other components 1020 included in the electronic device 1000 include storage, a camera module, a speaker, a microphone, a display, a battery, etc. The storage is configured to store user data. The storage may be an embedded multimedia card (eMMC), a solid-state drive (SSD), a universal flash storage (UFS) device, etc. The display is implemented to display data processed by the SoC and / or to receive data via a touch screen panel of the display.

[0088] The above illustrates exemplary embodiments and should not be construed as limiting the present invention. Although several exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the above embodiments without departing from the scope of the present invention. [Explanation of symbols]

[0089] 10, 20, 30 Semiconductor Packages 100 Package Substrate 100C PCB core 100L Lower build-up layer 100U Top Build-up Layer 200 Rewiring board 200F 1st underfill layer 200L 1st redistribution layer 200M 1st mold layer 200T Lower connection terminal 200U 2nd redistribution layer 200V First through via 300 Dice Stack 300F 2nd Underfill Layer 300M 2nd mold layer 300T upper connection terminal 400 Interconnect Package 500D Die Side Capacitor (DSC) 500L Land Side Capacitor (LSC) 600 Reinforcement member 700 Capacitor 1000 Electronic Devices 1010 Motherboard 1020 Components

Claims

1. 1. A semiconductor device comprising: an interconnect package including at least one dielectric layer and at least one first wiring trace formed in the at least one dielectric layer, the interconnect package being configured to connect a plurality of semiconductor chips via the at least one first wiring trace, The semiconductor device, wherein the interconnect package further includes a capacitor on the at least one first wiring trace, the capacitor being coupled to the at least one first wiring trace.

2. 2. The semiconductor device of claim 1, wherein the semiconductor chip is disposed in a first direction above the interconnect package.

3. further comprising a rewiring substrate on which the interconnect package is included; 2. The semiconductor device of claim 1, wherein the redistribution substrate has a greater lateral width in a second direction intersecting the first direction than the interconnect package.

4. further comprising a rewiring substrate on which the interconnect package is included; the semiconductor chip is disposed above the rewiring substrate in a first direction; the redistribution substrate includes at least one redistribution layer having at least one second wiring trace formed thereon; 2. The semiconductor device of claim 1, wherein the at least one second wiring trace connects the at least one first wiring trace to the semiconductor chip.

5. The rewiring substrate further includes a package substrate disposed below the rewiring substrate, the package substrate includes a plurality of connection structures therein and a plurality of connection terminals on a first surface and a second surface of the package substrate, the second surface being opposite the first surface; The connection structures are respectively connected to the connection terminals, 5. The semiconductor device of claim 4, wherein at least one of the connection terminals is connected to the at least one first wiring trace via the at least one second wiring trace.

6. at least one additional capacitor on the first surface of the package substrate or on the second surface opposite the first surface; 6. The semiconductor device of claim 5, wherein said at least one additional capacitor has a size larger than said capacitor in said interconnect package.

7. the semiconductor chip is disposed in a first orientation above the interconnect package; 2. The semiconductor device of claim 1, wherein the capacitor is located in an upper portion of the interconnect package closer to the semiconductor chip than a lower portion of the interconnect package.

8. the at least one dielectric layer comprises a plurality of dielectric layers; 2. The semiconductor device of claim 1, wherein the thickness of the capacitor is less than the thickness of one of the dielectric layers in a first direction.

9. The at least one first wiring trace comprises: a power trace on which the capacitor is disposed and configured to connect at least one of the semiconductor chips to a voltage source; 10. The semiconductor device of claim 1, further comprising: signal wiring traces configured to connect said semiconductor chips.

10. The semiconductor chip; a rewiring substrate disposed below the semiconductor chip in a first direction; a package substrate disposed below the rewiring substrate in the first direction, 2. The semiconductor device of claim 1, wherein the rewiring substrate includes the interconnect package, the package substrate being connected to the rewiring substrate.

11. the interconnect package further includes a support layer on which the at least one dielectric layer is disposed; the support layer is made of at least one of silicon, ceramic, and glass; 11. The semiconductor device of claim 10, wherein at least one transistor is included in the support layer.

12. the interconnect package further includes at least one through via formed in the support layer; 12. The semiconductor device of claim 11, wherein the at least one through via connects the capacitor to the at least one transistor.

13. a die stack including at least two semiconductor chips; an interconnect package disposed below the die stack in a first direction and connecting the semiconductor chips; a capacitor disposed within the interconnect package, connected to at least one of the semiconductor chips, and configured to be connected to a voltage source, The electronic device, wherein the interconnect package has a width in a second direction intersecting the first direction that is smaller than a width of the die stack.

14. The interconnect package includes: a power supply trace coupled to the capacitor; 14. The electronic device of claim 13, further comprising: signal wiring traces connecting said semiconductor chips.

15. 14. The electronic device of claim 13, wherein the interconnect package is disposed in the first direction below a boundary of the semiconductor chip.

16. The interconnect package includes: a dielectric layer on which the capacitor is disposed; 14. The electronic device of claim 13, further comprising: a support layer below the dielectric layer and including at least one transistor connected to the capacitor.

17. a substrate including a plurality of connection terminals on at least one of a first surface and a second surface, the second surface being opposite the first surface; at least one semiconductor package including a plurality of semiconductor chips and at least one interconnect package, At least one of the semiconductor chips is connected to at least one of the connection terminals of the substrate; The at least one interconnect package comprises: at least one dielectric layer; at least one first wiring trace included in the at least one dielectric layer connecting the semiconductor chips; at least one capacitor coupled to the at least one first wiring trace.

18. 20. The electronic system of claim 17, wherein the semiconductor chip comprises a system on a chip (SoC) and a memory chip.

19. The at least one first wiring trace comprises: a power supply trace coupled to the at least one capacitor; 20. The electronic system of claim 17, further comprising signal wiring traces connecting said semiconductor chips.

20. 20. The electronic system of claim 17, wherein the at least one capacitor is configured to be connected to a voltage source.

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