Game machine

Abstract

To provide a game machine capable of efficiently performing control pertaining to a performance image.SOLUTION: A game machine can execute processing for switching mutual functions between a drawing output destination buffer and a frame buffer, and includes registration means capable of registering image information in the drawing output destination buffer and performance image display control means for controlling a performance image on the basis of the registered image information. When image information stored in the frame buffer switched from the drawing output destination buffer is temporary stop image information, temporary stop image information is registered in the drawing output destination buffer switched from the frame buffer. Image information can be controlled by display control corresponding to priority, determination regarding a reproduction mode can be performed when image information is not registered in the drawing output destination buffer, and control can be performed so as to reproduce from the beginning regarding loop reproduction when image information is not registered in the drawing output destination buffer.SELECTED DRAWING: Figure 52

Description

[Technical Field]

[0001] The present invention relates to a gaming machine such as a pachinko machine. [Background technology]

[0002] In a conventional gaming machine such as a pachinko machine, when a game ball enters a starting hole, a lottery is held, and based on the result of this lottery, an effect image is displayed on a display device, etc. If the result of the lottery is a jackpot, a jackpot game begins.

[0003] One known gaming machine of this type is one that decodes compressed image data, converts the decoded image data appropriately, stores it in a frame buffer, and outputs it to a display device (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-87402 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, the variety of effect images displayed on display devices has increased, and control of the effect images has become more complex. In such cases, it is desirable to efficiently control the effect images.

[0006] The present invention has been made in view of the above points, and its object is to provide a gaming machine that can efficiently control the effect images. [Means for solving the problem]

[0007] The gaming machine according to the present invention comprises: A gaming machine capable of executing a process (for example, bank flip) for switching between a drawing output buffer in which a drawing result is stored and a frame buffer used for display, A registration means (for example, a display control circuit 230 capable of executing steps S448 and S457) capable of registering image information (for example, composition) relating to a performance image to be displayed on a predetermined display means in the drawing output destination buffer; After the drawing output destination buffer is switched to the frame buffer (for example, after the processing of step S446 is performed), a performance image display control means (for example, a display control circuit 230) controls the predetermined display means to display a performance image based on the image information registered by the registration means; Equipped with When the image information stored in the frame buffer switched from the drawing output destination buffer is pause image information for temporarily stopping an image (for example, when the determination in step S447 is YES), pause image information can be registered in the drawing output destination buffer switched from the frame buffer, The image information can be controlled by display control according to priority, When the image information is not registered in the drawing output destination buffer by the registration means (for example, when step S444 is determined to be NO), a determination regarding the playback mode can be made. When the image information is not registered in the drawing output destination buffer by the registration means (for example, when step S444 is judged as NO), it is possible to control loop playback so that playback starts from the beginning. It is characterized by: [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a gaming machine that can efficiently control the effect images. [Brief explanation of the drawings]

[0009] [Figure 1]1 is a diagram showing a functional flow of a pachinko gaming machine according to one embodiment of the present invention. [Figure 2] 1 is an external perspective view of a pachinko gaming machine according to one embodiment of the present invention; [Figure 3] 1 is an exploded perspective view of a pachinko gaming machine according to one embodiment of the present invention. [Figure 4] 1 is a front view showing the configuration of a game board of a pachinko game machine according to one embodiment of the present invention. [Figure 5] 1 is a block diagram showing the circuit configuration of a pachinko gaming machine according to one embodiment of the present invention; [Figure 6] 1 is a block diagram showing the internal configuration of a sub-control circuit of a pachinko gaming machine according to one embodiment of the present invention. [Figure 7] 1 is a block diagram showing the internal configuration of a sound and LED control circuit of a pachinko gaming machine according to one embodiment of the present invention. [Figure 8] 10 is a diagram for explaining an example of an output signal of a sound / LED control circuit in a pachinko gaming machine according to one embodiment of the present invention. FIG. [Figure 9] 1 is a control block diagram for explaining an example of volume control by a host control circuit in a pachinko gaming machine according to one embodiment of the present invention. FIG. [Figure 10] 1 is a schematic diagram of the connection configuration between the built-in relay board and the speaker of a pachinko gaming machine according to one embodiment of the present invention. [Figure 11] 1 is a block diagram showing the internal configuration of a display control circuit of a pachinko gaming machine according to one embodiment of the present invention; [Figure 12] 1 is a schematic diagram of a connection configuration between a sub-board and a CGROM board (NOR type) of a pachinko gaming machine according to one embodiment of the present invention. [Figure 13] 1 is a schematic diagram of a connection configuration between a sub-board and a CGROM board (NAND type) of a pachinko gaming machine according to one embodiment of the present invention. [Figure 14] 10 is a truth table for explaining the operation of an AND circuit provided on a sub-board of a pachinko gaming machine according to one embodiment of the present invention. [Figure 15]1 is a truth table for explaining the operation of a bidirectional balanced transceiver provided on a sub-board of a pachinko gaming machine according to one embodiment of the present invention. [Figure 16] 1 is a diagram showing an example of a jackpot random number determination table (when winning at the first starting port) in a pachinko gaming machine according to one embodiment of the present invention. FIG. [Figure 17] 1 is a diagram showing an example of a jackpot random number determination table (when winning at the second starting port) in a pachinko gaming machine according to one embodiment of the present invention. FIG. [Figure 18] 1 is a diagram showing an example of a symbol determination table (when winning at the first starting slot) in a pachinko gaming machine according to one embodiment of the present invention. FIG. [Figure 19] 10 is a diagram showing an example of a symbol determination table (when winning at the second starting slot) in the pachinko gaming machine according to one embodiment of the present invention. FIG. [Figure 20] 1 is a diagram showing an example of a jackpot type determination table (part 1) in a pachinko gaming machine according to one embodiment of the present invention. FIG. [Figure 21] FIG. 10 is a diagram showing an example of a jackpot type determination table (part 2) in the pachinko gaming machine according to one embodiment of the present invention. [Figure 22] FIG. 10 is a diagram showing an example of a jackpot type determination table (part 3) in a pachinko gaming machine according to one embodiment of the present invention. [Figure 23] FIG. 10 is a diagram showing an example of a jackpot type determination table (part 4) in the pachinko gaming machine according to one embodiment of the present invention. [Figure 24] 1 is a diagram showing an example of a winning effect information determination table in a pachinko gaming machine according to one embodiment of the present invention; [Figure 25] 1 is a diagram showing an example of a variable presentation pattern determination table in a pachinko gaming machine according to one embodiment of the present invention. FIG. [Figure 26] FIG. 1 is a diagram showing an example of a variable effect table in a pachinko gaming machine according to one embodiment of the present invention. [Figure 27] 1 is a diagram for explaining an overview of the drawing process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 28]3 is a flowchart showing an example of main control processing executed by a main CPU in a pachinko gaming machine according to one embodiment of the present invention. [Figure 29] 10 is a flowchart showing an example of a special symbol control process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 30] 10 is a flowchart showing an example of a special symbol memory check process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 31] 10 is a flowchart showing an example of a special symbol display time management process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 32] 10 is a flowchart showing an example of a jackpot end interval process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 33] 10 is a flowchart showing an example of a system timer interrupt process executed by a main CPU in a pachinko gaming machine according to one embodiment of the present invention. [Figure 34] 10 is a flowchart showing an example of a switch input detection process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 35] 10 is a flowchart showing an example of a start-hole winning detection process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 36] 10 is a flowchart showing an example of a sub-control main process executed by a host control circuit (sub-control circuit) in a pachinko gaming machine according to one embodiment of the present invention. [Figure 37] 4 is a flowchart showing an example of a timer interrupt process executed by a host control circuit (sub-control circuit) in a pachinko gaming machine according to one embodiment of the present invention. [Figure 38] 10 is a diagram illustrating an example of sub-device input discrimination information created in a pachinko gaming machine according to one embodiment of the present invention. FIG. [Figure 39] 10 is a flowchart showing an example of a sub-device input process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 40]10 is a flowchart showing an example of a sub-device input ON edge information (with repeat function) process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 41] 41 is a flowchart continuing from FIG. 40 showing an example of a sub-device input ON edge information (with repeat function) process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 42] 1 is a diagram for conceptually explaining backlight control processing in a pachinko gaming machine according to one embodiment of the present invention. [Figure 43] 10 is a flowchart showing an example of a backlight control process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 44] 10 is a flowchart showing an example of a timer interrupt process associated with a modified example of the backlight control process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 45] 10 is a flowchart showing a modified example of the backlight control process in the pachinko gaming machine according to one embodiment of the present invention. [Figure 46] 10 is a flowchart showing an example of a timer interrupt process showing a backlight control process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 47] 1 is a sub-control main process (overall flow) executed by a host control circuit to explain a first example of the process for adjusting the brightness of the backlight and various LEDs in a pachinko gaming machine according to one embodiment of the present invention. [Figure 48] This is a sub-control main processing (overall flow) executed by a host control circuit to explain a second example of the processing for adjusting the brightness of the backlight and various LEDs in a pachinko gaming machine according to one embodiment of the present invention. [Figure 49] This is a sub-control main processing (overall flow) executed by a host control circuit to explain a third example of the processing for adjusting the brightness of the backlight and various LEDs in a pachinko gaming machine according to one embodiment of the present invention. [Figure 50]10 is a flowchart showing an example of an RTC acquisition process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 51] 10 is a flowchart showing an example of animation control main processing in a pachinko gaming machine according to one embodiment of the present invention. [Figure 52] 10 is a flowchart showing an example of a composition playback control process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 53] 10 is a flowchart showing an example of a sound amplifier check process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 54] 10 is a flowchart showing an example of a normal amplifier check process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 55] 10 is a flowchart showing an example of a deep bass amplifier check process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 56] 10 is a flowchart showing an example of a sound amplifier check process for performing a normal amplifier / deep bass amplifier (collectively) check process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 57] 10 is a flowchart showing an example of a more preferable form of sound amplifier check processing in a pachinko gaming machine according to one embodiment of the present invention. [Figure 58] 10 is a flowchart showing an example of a more preferred form of normal amplifier / deep bass amplifier check processing in a pachinko gaming machine according to one embodiment of the present invention. [Figure 59] 58 shows a flowchart continuing from FIG. 58, showing an example of a more preferable form of the normal amplifier / deep bass amplifier check processing in a pachinko gaming machine according to one embodiment of the present invention. [Figure 60] 10 is a flowchart showing an example of a sound request control process when there are multiple sound requests for the same channel in a pachinko gaming machine according to one embodiment of the present invention. [Figure 61]10 is a flowchart showing a first example of a sound request control process when volume adjustment is performed in a pachinko gaming machine according to one embodiment of the present invention. [Figure 62] 10 is a flowchart showing a second example of a sound request control process when a volume adjustment is performed in a pachinko gaming machine according to one embodiment of the present invention. [Figure 63] 10 is a flowchart showing a third example of a sound request control process when volume adjustment is performed in a pachinko gaming machine according to one embodiment of the present invention. [Figure 64] 10 is a flowchart showing a fourth example of a sound request control process when volume adjustment is performed in a pachinko gaming machine according to one embodiment of the present invention. [Figure 65] 10 is a flowchart showing a fifth example of a sound request control process when volume adjustment is performed in a pachinko gaming machine according to one embodiment of the present invention. [Figure 66] 10 is an attenuation table showing an example of brightness attenuation values ​​of each color (red, green, blue) according to strong, medium, and weak LED light emission intensities in a pachinko gaming machine according to one embodiment of the present invention. [Figure 67] 1 is a block diagram showing an example of a connection state between an LED port, an LED, and a solenoid in a pachinko gaming machine according to one embodiment of the present invention. FIG. [Figure 68] 10 is a flowchart showing an example of a data loading process executed by a host control circuit as one of various initialization processes in a pachinko gaming machine according to one embodiment of the present invention. [Figure 69] 10 is a flowchart showing an example of a random number initialization process executed by a host control circuit as one of various initialization processes in a pachinko gaming machine according to one embodiment of the present invention. [Figure 70] 10 is a flowchart showing an example of a random number periodic update process in a pachinko gaming machine according to one embodiment of the present invention. [Figure 71](a) A flowchart showing an example of random number 1 acquisition processing, (b) a flowchart showing an example of random number 2 acquisition processing, (c) a flowchart showing an example of random number 3 acquisition processing, and (d) a flowchart showing an example of random number 4 acquisition processing in a pachinko gaming machine according to one embodiment of the present invention. [Figure 72] 10 is a flowchart showing an example of a random number acquisition process executed when a random number is used in a pachinko gaming machine according to one embodiment of the present invention. [Figure 73] 10 is a sub-control main process (overall flow) executed by a host control circuit to explain a modified example of sub-random number processing in a pachinko gaming machine according to one embodiment of the present invention. [Figure 74] 10 is a flowchart showing an example of a reception interrupt process executed by a host control circuit in a pachinko gaming machine according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, the configuration and various operations of a pachinko gaming machine (gaming machine) according to one embodiment of the present invention will be described with reference to the drawings.

[0011] <Function flow> First, the functions of the pachinko gaming machine according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing the functional flow of the pachinko gaming machine according to this embodiment.

[0012] As shown in Figure 1, a pachinko game is a game in which a game ball is shot by a user's operation, and a payout control process for the game ball is performed when the game ball wins various prizes. Pachinko games also include special symbol games that use special symbols and normal symbol games that use normal symbols. When a "jackpot" occurs in a special symbol game or a "win" occurs in a normal symbol game, the possibility of the game ball winning a prize increases relatively, and the payout control process for the game ball becomes easier to perform.

[0013] In addition, the various types of winning include a special pattern starting winning, which is one of the conditions for the variable display of special patterns in a special pattern game, and a normal pattern starting winning, which is one of the conditions for the variable display of normal patterns in a normal pattern game.

[0014] In this specification, the term "variable display" refers to a concept of a display that can be changed, and it allows, for example, a "variable display" that actually changes and is displayed, and a "stopped display" that actually stops and is displayed. Furthermore, the "variable display" can also provide a "derived display" in which a special symbol (identification information) is displayed as the result of a special symbol game. In other words, in this specification, the operation from the start of the "variable display" to the "derived display" is referred to as one "variable display." Furthermore, in this specification, the term "identification information" may include symbols used in pachinko games, such as special symbols, normal symbols, decorative symbols, and identification symbols, as well as symbols used in pachislot or slot games to indicate or suggest the outcome of a game, and may also include various symbols in the embodiments and various modifications described below.

[0015] An outline of the processing flow for the special symbol game and the normal symbol game will be explained below.

[0016] (1) Special symbol game When a special pattern start winning occurs in a special pattern game, random numbers (random number for determining a jackpot and random number for determining a pattern) are extracted from the counter for determining a jackpot and the counter for determining a pattern, respectively, and each extracted random number value is stored (see the flow of the special pattern start winning processing during the special pattern game shown in Figure 1).

[0017] 1, in the special symbol control process during the special symbol game, it is first determined whether or not the condition for starting the variable display of the special symbol is met. In this determination process, it is determined whether or not a random number value has been stored due to the special symbol start winning, and if a random number value has been stored, it is determined that the condition for starting the variable display of the special symbol is met.

[0018] Next, when the variable display of the special symbols is started, the random number value for determining a jackpot extracted from the jackpot determination counter is referenced, and a jackpot determination is made as to whether or not a "jackpot" has occurred. After that, a process for determining the symbols to be stopped is carried out. In this process, the random number value for determining the symbols extracted from the symbol determination counter and the result of the jackpot determination described above are referenced, and the special symbols to be stopped and displayed are determined.

[0019] Next, a variation pattern determination process is carried out. In this process, a random number is extracted from the variation pattern determination counter, and the random number, the result of the jackpot determination, and the special symbols to be stopped and displayed are referenced to determine the variation pattern of the special symbols.

[0020] Next, a presentation pattern determination process is carried out. In this process, a random number is extracted from the presentation pattern determination counter, and the random number, the result of the jackpot determination, the special symbols to be stopped and displayed, and the variation pattern of the special symbols are referenced to determine the presentation pattern to be executed in accordance with the variable display of the special symbols.

[0021] Next, based on the result of the determined jackpot determination, the special pattern to be displayed in a stopped state, the variation pattern of the special pattern, and the presentation pattern associated with the variable display of the special pattern are referenced, and a variable display control process that controls the variable display of the special pattern and a presentation control process that performs a predetermined presentation are executed.

[0022] Then, when the variable display control process and the effect display control process are completed, it is determined whether or not a "jackpot" has been achieved. If it is determined in this determination process that a "jackpot" has been achieved, a jackpot game control process is executed to play a jackpot game. Note that in a jackpot game, the possibility of winning the various prizes mentioned above increases. On the other hand, if it is determined that a "jackpot" has not been achieved, the jackpot game control process is not executed.

[0023] If it is determined that a "jackpot" has not been reached, or if the jackpot game control process has ended, a game state transition control process is performed to transition the game state. This game state transition control process manages a normal game state that is different from the jackpot game state. Examples of normal game states include a game state in which the probability of a "jackpot" being determined increases in the above-mentioned jackpot determination (hereinafter referred to as a "probable variable game state"), and a game state in which a special symbol start winning is more likely to be obtained (hereinafter referred to as a "time-saving game state"). After that, a determination process is performed again to determine whether or not to start the variable display of the special symbol, and then the various processes of the above-mentioned special symbol control process are repeated.

[0024] In the pachinko gaming machine of this embodiment, if a gaming ball makes a start-up winning entry while a special symbol is being displayed in a variable manner, various data acquired at the time of the start-up winning entry (random number value for determining a jackpot, random number value for determining a symbol, etc.) are reserved. In other words, if a gaming ball makes a start-up winning entry while a special symbol is being displayed in a variable manner, the variable display (variable display) of the special symbol corresponding to the start-up winning entry is reserved, and the variable display of the reserved special symbol begins after the variable display of the currently executed special symbol has ended. Hereinafter, the variable display of the reserved special symbol is also referred to as a "reserved ball."

[0025] In addition, in the pachinko gaming machine of this embodiment, as will be described later, two types of special symbol start winnings are possible. (First start opening prize and second start opening prize) are set up, and a maximum of four reserved balls can be acquired for each special symbol start winning. In other words, in this embodiment, a maximum of eight reserved balls can be acquired.

[0026] Furthermore, although not shown in Figure 1, the pachinko gaming machine of this embodiment also has a function to determine whether the reserved balls have won (whether or not they have won a "jackpot") based on the information about the reserved balls described above, and to perform a predetermined presentation based on the results of that determination, i.e., a predictive presentation function.

[0027] (2) Regular symbol game When a normal symbol start winning occurs in a normal symbol game, a random number value is extracted from the winning determination counter and stored (see the flow of the normal symbol start winning processing in the normal symbol game shown in Figure 1).

[0028] 1, in the normal symbol control process during the normal symbol game, it is first determined whether or not the condition for starting the variable display of the normal symbol is met. In this determination process, it is referenced whether or not a random number value has been stored due to the normal symbol start winning, and it is determined that the condition for starting the variable display of the normal symbol is met if a random number value has been stored.

[0029] Next, when variable display of normal symbols is started, the random number extracted from the winning judgment counter is referenced, and a win judgment is made as to whether or not it is a "win." After that, a variation pattern determination process is performed. In this process, the result of the win judgment is referenced, and the variation pattern of the normal symbols is determined.

[0030] Next, the result of the determined winning judgment and the variation pattern of the normal symbol are referenced, and a variable display control process that controls the variable display of the normal symbol and a presentation control process that performs a predetermined presentation are executed.

[0031] When the variable display control process and the effect display control process are completed, it is determined whether or not a "win" has occurred. If it is determined in this determination process that a "win" has occurred, a win game control process is executed in which a win game is played. In the win game control process, the possibility of the various wins described above, particularly the possibility of the game ball starting a special pattern win in the special pattern game, increases. On the other hand, if it is determined that a "win" has not occurred, the win game control process is not executed. Thereafter, a determination process is again performed as to whether or not to start the variable display of the normal pattern, and then the various processes of the normal pattern control process described above are repeated.

[0032] As mentioned above, in pachinko games, the ease with which the payout control process for game balls can be carried out varies depending on conditions such as whether or not a "jackpot" occurs in a special pattern game, the transition status of the game state, and whether or not a "win" occurs in a normal pattern game.

[0033] In this embodiment, a software random number system that generates random numbers by executing a program is used as a system for extracting various random number values. However, the present invention is not limited to this system. For example, if a pachinko gaming machine is equipped with a random number generator that updates random numbers at a predetermined cycle, a hard random number system that extracts random numbers from a counter (so-called ring counter) in the random number generator may be used as a system for extracting the various random number values ​​described above. When using the hard random number system, the initial value of the random number value is determined at a timing different from the predetermined cycle, thereby preventing the same random number value from being extracted at the same cycle.

[0034] <Pachinko machine structure> Next, the structure of the pachinko gaming machine in this embodiment will be described with reference to Figures 2 and 3. Figure 2 is a perspective view showing the appearance of the pachinko gaming machine, and Figure 3 is an exploded perspective view of the pachinko gaming machine.

[0035] As shown in FIGS. 2 and 3, the pachinko gaming machine 1 includes a main body 2, a base door 3 attached to the main body 2 so as to be able to open and close freely, and a glass door 4 attached to the base door 3 so as to be able to open and close freely.

[0036] [Main unit] The main body 2 is made of a frame-shaped member having a rectangular opening 2a (see FIG. 3). The main body 2 is made of a material such as wood.

[0037] [Base Door] The base door 3 is made of a plate-like member having a rectangular outer shape that is approximately the same as the outer shape of the main body 2. The base door 3 is disposed in front of the main body 2 (on the front side of the pachinko gaming machine 1), and the opening 2a of the main body 2 is opened and closed by rotating the base door 3 around an end of one side edge of the main body 2 as an axis. As shown in FIG. 3, the base door 3 is provided with a rectangular opening 3a. This opening 3a is formed from approximately the center of the base door 3 to the upper region, and is formed in a size that occupies most of that region.

[0038] In addition, a speaker 11, a game board 12, a display device 13, a tray unit 14, a launching device 15, a payout device 16, and a board unit 17 are attached to the base door 3.

[0039] The speaker 11 is disposed at the top (near the upper end) of the base door 3. The game board 12 is disposed in front of the base door 3 (on the front side of the pachinko gaming machine 1) so as to cover the opening 3a of the base door 3.

[0040] The game board 12 is made of a plate-shaped resin member that is light-transmitting. Examples of light-transmitting resin that can be used include acrylic resin, polycarbonate resin, and methacrylic resin.

[0041] Furthermore, a play area 12a is formed on the front surface of the play board 12 (the surface on the front side of the pachinko game machine 1) in which game balls launched from the launcher 15 roll. This play area 12a is an area surrounded by a guide rail 41 (specifically, an outer rail 41a shown in FIG. 4 described later), and its outer periphery is substantially circular. Furthermore, a plurality of play nails (see FIG. 4 described later) are driven into the play area 12a. The configuration of the play board 12 (play area 12a) will be described in detail later with reference to FIG. 4 described later.

[0042] The display device 13 is attached to the rear side of the game board 12 (opposite the front side of the pachinko game machine 1). The display device 13 has a display area 13a for displaying images. The size of the display area 13a is set so as to occupy all or part of the surface of the game board 12. Various images such as identification symbols for effects, effect images, and decorative images (decorative symbols) are displayed in the display area 13a of the display device 13 based on the results of a lottery process for special symbols, which will be described later. The player can view the various images displayed in the display area 13a of the display device 13 through the game board 12.

[0043] In this embodiment, a liquid crystal display device is used as the display device 13. However, the present invention is not limited to this, and the display device 13 may be, for example, a display device such as a plasma display, a rear projection display, or a CRT (Cathode Ray Tube) display.

[0044] Furthermore, a spacer 19 is provided on the rear side of the game board 12 (the side opposite to the front side of the pachinko game machine 1). This spacer 19 is provided between the rear side of the game board 12 (the surface on the rear side of the pachinko game machine 1) and the front side of the display device 13 (the surface on the front side of the pachinko game machine 1), and forms a space that serves as a flow path for game balls rolling in the game area 12a of the game board 12. The spacer 19 is made of a light-transmitting material. However, the present invention is not limited to this, and the spacer 19 may, for example, be partially made of a light-transmitting material, or may be made of a material that does not have light transparency.

[0045] The tray unit 14 is disposed below the gaming board 12. This tray unit 14 has an upper tray 21 and a lower tray 22 disposed below it. As shown in FIG. 2, the upper tray 21 and the lower tray 22 are formed with a payout opening 21a and a payout opening 22a, respectively, for lending gaming balls and paying out gaming balls (prize balls). When a predetermined payout condition is met, gaming balls are discharged from the payout opening 21a and the payout opening 22a and stored in the upper tray 21 and the lower tray 22, respectively. In addition, the gaming balls stored in the upper tray 21 are launched into the gaming area 12a by the launching device 15.

[0046] In addition, the tray unit 14 is provided with an effect button 23. This effect button 23 is attached on the upper tray 21. In addition, a dial operation unit (jog dial) 24 is attached to the periphery of the effect button 23 so as to be rotatable relative to the effect button 23. The pachinko gaming machine 1 of this embodiment has a predetermined effect function performed using the effect button 23 and / or the dial operation unit 24, and when performing the predetermined effect, an image prompting the player to operate the effect button 23 and / or the dial operation unit 24 is displayed in the display area 13a of the display device 13.

[0047] The launching device 15 is located in the lower right area (near the lower right corner) on the front of the base door 3. The launching device 15 includes a launching handle 25 that can be operated by a player, and a panel body 26 that engages with the lower right part of the tray unit 14. The launching handle 25 is located on the front side of the panel body 26 and is rotatably supported by the panel body 26.

[0048] Although not shown in Figures 2 and 3, a solenoid actuator (drive device) that controls the launching operation of the game balls is provided on the back side of panel body 26. Also, although not shown in Figures 2 and 3, a touch sensor is provided on the periphery of launch handle 25, and a launch volume is provided inside launch handle 25. The launch volume changes its resistance value according to the amount of rotation of launch handle 25, thereby changing the power supplied to the solenoid actuator.

[0049] In the pachinko gaming machine 1 of this embodiment, when a player's hand touches the touch sensor of the launching handle 25, the touch sensor outputs a detection signal. This detects that the player has gripped the launching handle 25, enabling the solenoid actuator to launch game balls. When the player grips the launching handle 25 and turns it clockwise (right-handed as seen from the player's perspective), the resistance value of the launch volume changes according to the angle of rotation of the launching handle 25, and power corresponding to that resistance value is supplied to the solenoid actuator. As a result, the game balls stored in the upper tray 21 are launched one after another, and the launched game balls are guided by a guide rail 41 (see FIG. 4 described below) and released into the game area 12a of the game board 12.

[0050] 2 and 3, a launch stop button is provided on the side of the launch handle 25. The launch stop button is a button provided to stop the launch of game balls by the solenoid actuator. When a player presses the launch stop button, the launch of game balls is stopped even if the launch handle 25 is being gripped and rotated.

[0051] The payout device 16 and the base unit 17 are arranged on the back side of the base door 3. Gaming balls are supplied to the payout device 16 from a storage unit (not shown). The payout device 16 pays out a predetermined number of gaming balls from the gaming balls supplied from the storage unit to the upper tray 21 or the lower tray 22 based on the establishment of payout conditions. The base unit 17 has various control boards. The various control boards are provided with a main control circuit 70 and a sub-control circuit 200, which will be described later (see Figure 5, which will be described later).

[0052] [Glass door] The glass door 4 is made of a plate-like member with a substantially rectangular surface. The glass door 4 is placed on the front side of the game board 12 and is large enough to cover the game board 12. A speaker cover 29 is provided on the front side of the glass door 4 in an upper area facing the speaker 11.

[0053] Furthermore, an opening 4a of a size large enough to expose at least the playing area 12a is formed in the center of the glass door 4 in an area facing the playing area 12a of the gaming board 12. A light-transmitting protective glass 28 is attached to the opening 4a of the glass door 4, thereby closing the opening 4a. Therefore, when the glass door 4 is closed against the base door 3, the protective glass 28 is positioned so as to face at least the playing area 12a of the gaming board 12.

[0054] [Game board] Next, the configuration of the game board 12 will be described with reference to Fig. 4. Fig. 4 is a front view showing the configuration of the game board 12.

[0055] 4, a guide rail 41, a ball passage detector 43, a first start opening 44, a second start opening 45 (start area), and a normal electric device 46 are provided on the front surface of the game board 12. Also provided on the front surface of the game board 12 are general winning openings 51 and 52, a first large winning opening 53 (variable winning device), a second large winning opening 54 (variable winning device), an outlet opening 55, and a plurality of game pins 56. Furthermore, on the front surface of the game board 12, above the display area 13a of the display device 13 located approximately in the center thereof, a special symbol display device 61, a normal symbol display device 62, a normal symbol reserve display device 63, a first special symbol reserve display device 64, and a second special symbol reserve display device 65 are provided.

[0056] Although not shown in Fig. 4, a seven-segment counter for effect is also provided on the front of the gaming board 12. The seven-segment counter for effect is configured as a display counter that can display two-digit numbers or two English letters. In this embodiment, an indicator LED (Light Emitting Diode) that lights up when the result of the stopped display of the special pattern is a "jackpot," and a round number display LED that displays the number of rounds during a jackpot game may also be provided.

[0057] [Various components in the entertainment field] The guide rail 41 is composed of an outer rail 41a extending in an arc shape that defines the play area 12a, and an inner rail 41b extending in an arc shape that is located inside (on the inner periphery of) the outer rail 41a. The play area 12a is formed inside the outer rail 41a. The outer rail 41a and the inner rail 41b are located opposite each other near the left end of the play area 12a when viewed from the player's side, and a guide path 41c is formed between the outer rail 41a and the inner rail 41b that guides game balls launched by the launching device 15 to the top of the play area 12a.

[0058] At the tip of the inner rail 41b located at the upper left side of the playing area 12a, a ball discharge port 41d is formed by the tip of the inner rail 41b and a part of the outer rail 41a facing it. A ball return prevention piece 42 is provided at the tip of the inner rail 41b so as to close the ball discharge port 41d. This ball return prevention piece 42 prevents game balls discharged from the ball discharge port 41d into the playing area 12a from passing through the ball discharge port 41d again and entering the guide path 41c.

[0059] The game balls released from the ball release port 41d flow down from the top to the bottom of the game area 12a. At this time, the game balls collide with various components provided in the game area 12a, such as the multiple game nails 56, the first start port 44, the second start port 45, etc., and flow down from the top to the bottom of the game area 12a while changing their direction of travel.

[0060] A display area 13a of the display device 13 is provided in approximately the center of the game area 12a. An obstacle 13b is provided at the upper end of this display area 13a. By providing the obstacle 13b, the game ball does not pass over the area in the game area 12a that overlaps with the display area 13a.

[0061] The ball passing detector 43 is disposed near the right end of the display area 13a when viewed from the player's side. The ball passing detector 43 is provided with a passing ball sensor 43a (see FIG. 5 described later) for detecting a gaming ball passing through the ball passing detector 43. When a gaming ball passes through the ball passing detector 43, a lottery is held to determine whether or not there is a "win," and the variable display of the normal symbols starts based on the result of the lottery.

[0062] The first start hole 44 is disposed below the display area 13a, and the second start hole 45 is disposed below the first start hole 44. The first start hole 44 and the second start hole 45 are composed of members capable of receiving game balls. Hereinafter, the entry or passage of a game ball through the first start hole 44 or the second start hole 45 is referred to as a "winning." When a game ball enters the first start hole 44 or the second start hole 45, a first predetermined number of game balls (three in this embodiment) are paid out. When a game ball enters the first start hole 44, a lottery is held to determine whether the result is a "jackpot" or a "minor jackpot," and the variable display of special symbols is initiated based on the result of the lottery. When a game ball enters the second start hole 45, a lottery is held to determine whether the result is a "jackpot," and the variable display of special symbols is initiated based on the result of the lottery.

[0063] The first start opening 44 is provided with a first start opening winning ball sensor 44a (see FIG. 5 described later) for detecting a game ball that has entered the first start opening 44. The second start opening 45 is provided with a second start opening winning ball sensor 45a (see FIG. 5 described later) for detecting a game ball that has entered the second start opening 45. The game balls that have entered the first start opening 44 and the second start opening 45 pass through a recovery port (not shown) provided in the game board 12 and are transported to a game ball recovery section (not shown).

[0064] The normal electric device 46 is provided in the second starting hole 45. The normal electric device 46 has a pair of blade members rotatably attached to both sides of the second starting hole 45, and a normal electric device solenoid 46a (see FIG. 5 described later) that drives the pair of blade members. This normal electric device 46 is driven by the normal electric device solenoid 46a and generates one of two states: an open state in which the pair of blade members are spread to make it easier for a game ball to enter the second starting hole 45, and a closed state in which the pair of blade members are closed to make it impossible for a game ball to enter the second starting hole 45. Note that in this embodiment, when the normal electric device 46 is in the closed state, the opening shape of the pair of blade members may be a shape that makes it difficult for a game ball to enter, rather than a shape that makes it impossible for a game ball to enter.

[0065] The general winning opening 51 is located near the lower left of the game area 12a as viewed from the player's side. The general winning opening 52 is located below the ball passage detector 43 and is located near the lower right of the game area 12a as viewed from the player's side. The general winning opening 51 and the general winning opening 52 are made of a member capable of receiving game balls. Hereinafter, the entry or passage of a game ball into the general winning opening 51 or the general winning opening 52 is also referred to as "winning." When a game ball enters the general winning opening 51 or the general winning opening 52, a second predetermined number of game balls (10 in this embodiment) are paid out.

[0066] The general winning opening 51 is provided with a general winning ball sensor 51a (see FIG. 5 described later) for detecting a gaming ball that has won the general winning opening 51. The general winning opening 52 is provided with a general winning ball sensor 52a (see FIG. 5 described later) for detecting a gaming ball that has won the general winning opening 52.

[0067] The first large prize opening 53 and the second large prize opening 54 are located below the ball passage detector 43 and between the first start opening 44 and the general prize opening 52. The first large prize opening 53 and the second large prize opening 54 are located vertically along the flow path of the gaming balls, with the first large prize opening 53 being located above the second large prize opening 54. The first large prize opening 53 and the second large prize opening 54 are both so-called attacker-type opening and closing devices, and have openable and closable shutters 53a and 54a, and solenoid actuators (first large prize opening solenoid 53b and second large prize opening solenoid 54b in FIG. 5 described below) that drive the shutters.

[0068] Each of the first large prize opening 53 and the second large prize opening 54 accepts game balls when the corresponding shutter is open (open state), and does not accept game balls when the shutter is closed (closed state). Hereinafter, the entry or passage of a game ball into the first large prize opening 53 or the second large prize opening 54 is also referred to as "winning." When a game ball enters the first large prize opening 53, a third predetermined number of game balls (10 in this embodiment) are paid out. On the other hand, when a game ball enters the second large prize opening 54, a fourth predetermined number of game balls (15 in this embodiment) are paid out.

[0069] In addition, the first major prize opening 53 is provided with a count sensor 53c (see FIG. 5 described later) for counting the number of game balls that have entered the first major prize opening 53. Furthermore, the second major prize opening 54 is provided with a count sensor 54c (see FIG. 5 described later) for counting the number of game balls that have entered the second major prize opening 54.

[0070] The outlet 55 is provided at the bottom of the game area 12a. The outlet 55 receives game balls that have not won in any of the first start opening 44, the second start opening 45, the general prize opening 51, the general prize opening 52, the first big prize opening 53, and the second big prize opening 54.

[0071] In this embodiment, when the various components in the game area 12a are arranged as shown in FIG. 4, if a player hits a game ball into the right area of ​​the game area 12a (if the player hits from the right), the game ball is guided to the second starting hole 45 by the game pins 56, etc. In this case, there is almost no chance of the game ball winning in the first starting hole 44. In this embodiment, as will be described later, if the game ball wins in the second starting hole 45, the player is more likely to win a "jackpot," which is advantageous to the player, than if the game ball wins in the first starting hole 44. Therefore, in the "time-saving game state" described later, in which it is relatively easy to win in the second starting hole 45, hitting from the right can reduce the chance of the game ball winning in the first starting hole 44 (the chance of a game state disadvantageous to the player).

[0072] [Special pattern display device] The special symbol display device 61 is disposed approximately in the center of the upper part of the display area 13a of the display device 13, as shown in FIG.

[0073] The special symbol display device 61 is a display device that variably displays (variably displays and statically displays) special symbols in a special symbol game. In this embodiment, as shown in FIG. 4, the special symbol display device 61 is configured by a device that displays special symbols as symbols consisting of numbers, symbols, etc. Note that the present invention is not limited to this, and the special symbol display device 61 may be configured by, for example, a plurality of LEDs. In this case, a display pattern configured by the lighting and extinguishing of a plurality of LEDs is represented as a special symbol.

[0074] The special symbol display device 61 displays a winning symbol when the game ball enters the first starting hole 44 or the second starting hole 45. When the special symbol start winning is triggered, the special symbol (identification information) is displayed in a variable manner. Then, the special symbol display device 61 displays the variable special symbol for a predetermined time, and then displays the static special symbol. Hereinafter, the special symbol displayed in a variable manner on the special symbol display device 61 when the gaming ball enters the first start hole 44 is referred to as the first special symbol. Also, the special symbol displayed in a variable manner on the special symbol display device 61 when the gaming ball enters the second start hole 45 is referred to as the second special symbol.

[0075] When the first special symbol or the second special symbol displayed in a stopped state is in a specific mode (a "jackpot" mode) on the special symbol display device 61, the game state transitions from the normal game state to a jackpot game state, which is advantageous to the player. In other words, when the first special symbol or the second special symbol is displayed in a stopped state on the special symbol display device 61 in a mode that transitions to the jackpot game state, this is a "jackpot."

[0076] In a jackpot game state, the first large prize opening 53 or the second large prize opening 54 is in an open state. Specifically, in this embodiment, when a gaming ball enters the first starting opening 44 and the first special symbol is stopped and displayed in a specific manner on the special symbol display device 61, the first large prize opening 53 is in an open state. On the other hand, when a gaming ball enters the second starting opening 45 and the second special symbol is stopped and displayed in a specific manner on the special symbol display device 61, the second large prize opening 54 is in an open state.

[0077] The open state of each big prize opening is maintained until a predetermined number of game balls enter or until a certain period of time (for example, 30 seconds) has passed. When the period during which each big prize opening remains open meets either of these conditions, the big prize opening that was open will be closed.

[0078] Hereinafter, a game in which the first major prize opening 53 or the second major prize opening 54 is in a state (open state) in which it is easy to receive game balls is referred to as a round game. Between round games, the major prize opening is in a closed state. Furthermore, round games are counted as one round, two rounds, etc. For example, the first round game is referred to as the first round, and the second round game is referred to as the second round.

[0079] In addition, when the special symbol displayed in a stopped state on the special symbol display device 61 is in a state other than the specific state (a "miss" state), the game state does not change unless the player wins the falling lottery. In other words, the special symbol game is a game in which the special symbol is displayed variably by the special symbol display device 61, and then the special symbol is displayed in a stopped state, and the game state changes or is maintained depending on the result.

[0080] In addition, in the pachinko game machine 1 of this embodiment, when the game ball enters the first starting hole 44 during the variable display of the first special symbol or the second special symbol, the variable display of the first special symbol corresponding to the winning is (Reserved balls) are reserved. Then, when the first special symbol or second special symbol currently being displayed in a variable manner is stopped and displayed, the variable display of the reserved first special symbol begins. In this embodiment, the number of variable displays of the reserved first special symbol (so-called "reserved number (reserved balls)") is set to a maximum of four times (pieces).

[0081] Furthermore, in this embodiment, if a gaming ball enters the second starting hole 45 while the first special symbol or the second special symbol is being displayed in a variable manner, the variable display (reserved ball) of the second special symbol corresponding to the winning symbol is reserved. Then, when the first special symbol or the second special symbol currently being displayed in a variable manner is displayed in a static manner, the variable display of the reserved second special symbol begins. In this embodiment, the number of reserved variable displays of the reserved second special symbol (reserved number) is set to a maximum of four times (number). Therefore, in this embodiment, the maximum number of reserved variable displays of special symbols is eight in total.

[0082] In this embodiment, when reserved balls of the first special pattern and reserved balls of the second special pattern are mixed, the variable display of one special pattern is executed with priority over the variable display of the other special pattern. Note that the present invention is not limited to this, and when reserved balls of the first special pattern and reserved balls of the second special pattern are mixed, the variable display of the special patterns may be executed in the order in which they were reserved.

[0083] [Normal pattern display device] 4, the normal symbol display device 62 is disposed approximately in the center of the upper part of the display area 13a of the display device 13. In this embodiment, the normal symbol display device 62 is disposed to the right of the special symbol display device 61 as viewed from the player's side.

[0084] The normal symbol display device 62 is a display device that variably displays (variable display and stationary display) normal symbols in a normal symbol game. In this embodiment, as shown in Fig. 4, the normal symbol display device 62 is configured with two LEDs (normal symbol display LEDs) arranged in a vertical direction. Then, in the normal symbol display device 62, a display pattern configured by the lighting and extinguishing of each normal symbol display LED is displayed as a normal symbol.

[0085] The normal pattern display device 62 alternately turns on and off two normal pattern display LEDs to display a variable normal pattern when the gaming ball passes through the ball passage detector 43. Then, the normal pattern display device 62 displays a variable normal pattern for a predetermined time, and then displays a stationary normal pattern.

[0086] When the stopped normal symbol displayed on the normal symbol display device 62 is in a predetermined state (a "win" state), the normal electric device 46 changes from a closed state to an open state for a predetermined period of time. On the other hand, when the stopped normal symbol displayed is in a state other than the predetermined state (a "lose" state), the normal electric device 46 maintains the closed state. In other words, the normal symbol game is a game in which the normal symbol is variably displayed by the normal symbol display device 62, and then the normal symbol is stopped and displayed, and the normal electric device 46 operates according to the result.

[0087] If the gaming ball passes through the ball passage detector 43 while the normal symbol is being displayed variably, the variable display of the normal symbol is put on hold. Then, when the normal symbol currently being displayed variably is displayed stationary, the variable display of the reserved normal symbol is started. In this embodiment, the number of reserved variable displays of the normal symbol (i.e., the "reserved number") is set to a maximum of four times (pieces).

[0088] [Normal symbol reserved display device] 4, the normal symbol reservation display device 63 is disposed approximately in the center of the upper part of the display area 13a of the display device 13. In this embodiment, the normal symbol reservation display device 63 is disposed below the special symbol display device 61 and the normal symbol display device 62.

[0089] The normal symbol reserved display device 63 is a device that displays the number of reserved variable displays of normal symbols. In this embodiment, as shown in Figure 4, the normal symbol reserved display device 63 is configured with four LEDs (normal symbol reserved display LEDs) arranged in the left-right direction. The normal symbol reserved display device 63 displays the number of reserved variable displays of normal symbols by turning on and off each normal symbol reserved display LED.

[0090] Specifically, when the number of reserved normal symbol variable displays is one, the normal symbol reserved indicator LED located on the far left as viewed from the player (the first normal symbol reserved indicator LED from the left) lights up, and the other normal symbol reserved indicator LEDs go out. When the number of reserved normal symbol variable displays is two, the first and second normal symbol reserved indicator LEDs from the left light up, and the other normal symbol reserved indicator LEDs go out. When the number of reserved normal symbol variable displays is three, the first to third normal symbol reserved indicator LEDs from the left light up, and the other normal symbol reserved indicator LEDs go out. And when the number of reserved normal symbol variable displays is four, all normal symbol reserved indicator LEDs go out.

[0091] [First special symbol reserved display device] As shown in FIG. 4, the first special symbol reserved display device 64 is disposed in the upper part of the display area 13a of the display device 13, on the left side of the special symbol display device 61 when viewed from the player's side.

[0092] The first special symbol reserved display device 64 is a device that displays information related to the variable display of the reserved first special symbol (reserved ball of the first special symbol). In this embodiment, as shown in Fig. 4, the first special symbol reserved display device 64 is composed of a first special symbol reserved number display section 64a and a first special symbol reserved information display section 64b. The first special symbol reserved information display section 64b is disposed on the left side of the special symbol display device 61, and the first special symbol reserved number display section 64a is disposed on the left side of the first special symbol reserved information display section 64b.

[0093] The first special symbol reserved number display unit 64a has four LEDs (first special symbol reserved display LEDs) arranged in the left-right direction. The display mode of the first special symbol reserved number display unit 64a is the same as the display mode of the normal symbol reserved display device 63. That is, when the variable display of the first special symbol is reserved, the first special symbol reserved display LEDs from the first special symbol reserved display LED located on the far left as seen from the player's side to the reserved number are lit up.

[0094] Furthermore, the first special pattern reserved information display unit 64b displays information about reserved balls of the first special pattern. For example, the first special pattern reserved information display unit 64b displays information (identification information) about reserved balls of the first special pattern that will be variably displayed next, using a pattern consisting of numbers, symbols, etc. The configuration of the first special pattern reserved display device 64 is not limited to the example shown in Fig. 4, and can be configured arbitrarily as long as it is capable of displaying at least the number of reserved balls of the variably displayed first special pattern.

[0095] [Second special symbol reserved display device] As shown in FIG. 4, the second special symbol reserved display device 65 is disposed in the upper part of the display area 13a of the display device 13, on the right side of the normal symbol display device 62 when viewed from the player side.

[0096] The second special symbol reserved display device 65 is a device that displays information about the variable display of the reserved second special symbol (reserved ball of the second special symbol). In this embodiment, as shown in Fig. 4, the second special symbol reserved display device 65 is composed of a second special symbol reserved number display unit 65a and a second special symbol reserved information display unit 65b. The second special symbol reserved information display unit 65b is disposed to the right of the normal symbol display device 62, and the second special symbol reserved number display unit 65a is disposed to the right of the second special symbol reserved information display unit 65b.

[0097] The second special symbol reserved number display unit 65a has four LEDs (second special symbol reserved display LEDs) arranged in the left-right direction. The display mode of the second special symbol reserved number display unit 65a is the same as the display mode of the normal symbol reserved display device 63. That is, when the variable display of the second special symbol is reserved, the second special symbol reserved display LEDs from the second special symbol reserved display LED located on the far left as seen from the player's side to the reserved number are lit up.

[0098] Also, the second special pattern reserved information display unit 65b displays information about reserved balls of the second special pattern. For example, the second special pattern reserved information display unit 65b displays information (identification information) about reserved balls of the second special pattern that will be variably displayed next, using a pattern consisting of numbers, symbols, etc. The configuration of the second special pattern reserved display device 65 is not limited to the example shown in Fig. 4, and can be configured arbitrarily as long as it is capable of displaying at least the number of reserved balls of the variably displayed second special pattern.

[0099] [Display device] The display device 13 is configured as a liquid crystal display device as described above, and performs various image display effects in its display area 13a.

[0100] Specifically, in this embodiment, an effect image related to the special symbol displayed on the special symbol display device 61 is displayed in the display area 13a. At this time, for example, when a special symbol is being variably displayed on the special symbol display device 61, a plurality of effect identification symbols (decorative symbols) consisting of, for example, numbers from 1 to 8 and various characters are variably displayed in the display area 13a, except in specific cases. Then, when a special symbol is stopped and displayed on the special symbol display device 61, a plurality of decorative symbols (such as a jackpot symbol described later) corresponding to the special symbol are also stopped and displayed in the display area 13a.

[0101] Then, when the special symbol displayed in a stopped state on the special symbol display device 61 is in a specific pattern (the result of the stopped display is a "jackpot"), an effect image for making the player understand that it is a "jackpot" is displayed in the display area 13a. As an effect for making the player understand that it is a "jackpot", for example, first, a plurality of decorative symbols displayed in a stopped state assume a specific pattern (for example, a pattern in which the same decorative symbols are lined up in a predetermined direction), and then an image announcing the "jackpot" is displayed.

[0102] In this embodiment, the display area 13a of the display device 13 displays effect images related to the display contents of the first special symbol reserved display device 64 and the second special symbol reserved display device 65. For example, the display area 13a displays reserved information notifying the reserved number of variable displays of special symbols (for example, reserved symbols in the same number as the reserved number). In addition, for example, in the pachinko gaming machine 1 of this embodiment, a pre-reading effect is performed based on information on reserved balls of special symbols, and the advance notice at this time is also displayed in the display area 13a.

[0103] In addition, in this embodiment, a function may be further provided to display a presentation image in the display area 13a of the display device 13 to inform the player of the information when the normal pattern displayed in a stopped state on the normal pattern display device 62 is in a predetermined form.

[0104] <Circuit configuration of a pachinko machine> Next, the configuration of various circuits provided in the pachinko gaming machine 1 of this embodiment will be described with reference to Fig. 5. Fig. 5 is a block diagram showing the circuit configuration of the pachinko gaming machine 1.

[0105] As shown in Figure 5, the pachinko game machine 1 has a main control circuit 70 that mainly controls game operations, a payout / launch control circuit 123, and a sub-control circuit 200 that controls presentation operations according to the progress of the game.

[0106] [Main control circuit] The main control circuit 70 includes a one-chip microcomputer 77, a clock generating circuit 74, and an initial reset circuit 75. As described above, in this embodiment, a lottery process for a special symbol is performed when the first start slot 44 or the second start slot 45 is won, and this process is controlled by the main control circuit 70. In other words, the main control circuit 70 also serves as a means (lottery means) for performing a lottery process to determine whether or not to transition the gaming state to a state advantageous to the player.

[0107] The one-chip microcomputer 77 is configured with a main CPU (Central Processing Unit) 71, a main ROM (Read Only Memory) 72, a main RAM (Random Access Memory) 73, and a serial communication unit 76. Note that the main CPU 71, the main ROM 72, the main RAM 73, and the serial communication unit 76 may each be provided separately.

[0108] In addition, in this embodiment, a configuration in which the main ROM 72 is built into the board of the main control circuit 70 is described, but the present invention is not limited to this. For example, a ROM board on which the main ROM 72 is mounted may be connected to the board of the main control circuit 70. Furthermore, in this embodiment, the various circuits in the main control circuit 70 may be formed integrally or separately. Furthermore, the main ROM 72 does not have to be configured to be installed in the gaming machine, and may be configured to be able to communicate with the gaming machine.

[0109] A clock generating circuit 74 and an initial reset circuit 75 are connected to the one-chip microcomputer 77. The main ROM 72 stores various programs (see Figures 28 to 35 described later) for the main CPU 71 to control the operation of the pachinko gaming machine 1, various data tables (see Figures 16 to 26 described later), and the like.

[0110] The main CPU 71 executes various processes in accordance with programs stored in the main ROM 72. The main RAM 73 acts as a temporary storage area when the main CPU 71 executes various processes, and stores various flags and variable values ​​required for the various processes by the main CPU 71. Note that, although the main RAM 73 is used as the temporary storage area for the main CPU 71 in this embodiment, the present invention is not limited to this, and any readable and writable storage medium can be used as the temporary storage area.

[0111] The clock generation circuit 74 generates a clock pulse at a predetermined period (e.g., 2 msec) to execute the system timer interrupt process described later. The initial reset circuit 75 generates a reset signal when the power is turned on. The serial communication unit 76 then supplies a command to the sub-control circuit 200.

[0112] Furthermore, as shown in FIG. 5, various devices that operate in response to output signals sent from the main control circuit 70 are connected to the main control circuit 70.

[0113] Specifically, the main control circuit 70 is connected to a special symbol display device 61, a normal symbol display device 62, a normal symbol reserved display device 63, a first special symbol reserved display device 64, and a second special symbol reserved display device 65. Each of these devices performs a predetermined operation based on an output signal sent from the main control circuit 70. For example, when a predetermined output signal is sent from the main control circuit 70 to the special symbol display device 61, the special symbol display device 61 performs operation control of the variable display of special symbols in the special symbol game based on the output signal.

[0114] Furthermore, the normal electric prize device solenoid 46a, first large prize opening solenoid 53b, and second large prize opening solenoid 54b are connected to the main control circuit 70. The main control circuit 70 drives and controls the normal electric prize device solenoid 46a to open or close the pair of blade members of the normal electric prize device 46. The main control circuit 70 also drives and controls the first large prize opening solenoid 53b and second large prize opening solenoid 54b, respectively, to open or close the first large prize opening 53 and second large prize opening 54.

[0115] 5, the main control circuit 70 is connected to various sensors and receives output signals from the various sensors. Specifically, the main control circuit 70 is connected to count sensors 53c, 54c, general winning ball sensors 51a, 52a, passing ball sensor 43a, first start opening winning ball sensor 44a, second start opening winning ball sensor 45a, backup clear switch 121, etc.

[0116] The count sensor 53c counts the number of gaming balls that have entered the first large winning opening 53, and outputs a predetermined output signal indicative of the result to the main control circuit 70. The count sensor 54c counts the number of gaming balls that have entered the second large winning opening 54, and outputs a predetermined output signal indicative of the result to the main control circuit 70. The general winning ball sensor 51a outputs a predetermined detection signal to the main control circuit 70 when a gaming ball has entered the general winning opening 51, and the general winning ball sensor 52a outputs a predetermined detection signal to the main control circuit 70 when a gaming ball has entered the general winning opening 52.

[0117] Furthermore, the passing ball sensor 43a outputs a predetermined detection signal to the main control circuit 70 when a gaming ball passes through the ball passing detector 43. The first start port winning ball sensor 44a outputs a predetermined detection signal to the main control circuit 70 when a gaming ball enters the first start port 44. The second start port winning ball sensor 45a outputs a predetermined detection signal to the main control circuit 70 when a gaming ball enters the second start port 45. Furthermore, the backup clear switch 121 outputs a predetermined detection signal to the main control circuit 70 and the payout / launch control circuit 123 when the backup data is cleared in response to an operation by the gaming parlor manager or the like in the event of a power outage or the like.

[0118] Furthermore, a payout / launch control circuit 123 is connected to the main control circuit 70. The payout / launch control circuit 123 and the various peripheral devices connected thereto will be described in detail later.

[0119] [Dispensing and firing control circuit and its peripheral devices] The payout / launch control circuit 123 is connected to the prize ball case unit 170, the payout status notification display device 178, the lower tray full switch 179, the launch device 15, the external terminal board 140, and the card unit 150. In addition, the external terminal board 140 is connected to the data display device 141, and the card unit 150 is connected to the lending operation unit 151.

[0120] The payout / launch control circuit 123 inputs and outputs signals to and from these peripheral devices, and controls the operation of each peripheral device, based on various commands sent from the main control circuit 70. For example, the payout / launch control circuit 123 receives a prize ball control command sent from the main control circuit 70 and a dispensing ball control signal (described below) sent from the card unit 150, and sends a predetermined signal to the prize ball case unit 170. This causes the prize ball case unit 170 to pay out gaming balls.

[0121] The prize ball case unit 170 is a device that dispenses game balls, and includes a first 15-ball security switch 172a, a second 15-ball security switch 172b, a first counting switch 181a, a second counting switch 181b, and a payout motor 174. These components included in the prize ball case unit 170 are each connected to a payout / launch control circuit 123.

[0122] Although not shown here, two ball supply passages are provided inside the prize ball case unit 170. The first 15-ball security switch 172a detects game balls supplied to one of the ball supply passages and outputs a predetermined output signal indicating the detection result to the payout / launch control circuit 123. The second 15-ball security switch 172b detects game balls supplied to the other ball supply passage and outputs a predetermined output signal indicating the detection result to the payout / launch control circuit 123.

[0123] Furthermore, although not shown here, two payout passages are provided inside the prize ball case unit 170. The first counting switch 181a detects gaming balls paid out to one of the payout passages and outputs a predetermined output signal indicative of the detection result to the payout / launch control circuit 123. The second counting switch 181b detects gaming balls paid out to the other payout passage and outputs a predetermined output signal indicative of the detection result to the payout / launch control circuit 123.

[0124] The payout motor 174 is composed of a stepping motor, and is driven in response to a control signal input from the payout / launch control circuit 123. The payout motor 174 rotates a sprocket (rotating member) (not shown) provided in the prize ball case unit 170. The rotation of this sprocket moves the game balls accumulated in each ball supply path one by one to the corresponding payout path.

[0125] The payout status notification display device 178 is a device for notifying the type of abnormality when an abnormality occurs in the payout of game balls, and is configured with a 7-segment display. The payout status notification display device 178 is attached in a position visible only to the manager of the gaming parlor (game center), for example, attached to a predetermined location on the back of the pachinko gaming machine 1.

[0126] The lower tray full switch 179 detects when the gaming balls stored in the lower tray 22 become full, and outputs the detection result to the payout / launch control circuit 123.

[0127] When a signal indicating that the lower tray is full is input from the lower tray full switch 179, the payout / launch control circuit 123 notifies the fact that the lower tray is full using the payout status notification display device 178, and outputs a signal indicating that the lower tray is full to the main control circuit 70. After that, when a performance control command is sent from the main control circuit 70 to the sub-control circuit 200, the sub-control circuit 200 notifies that the lower tray 22 is full using, for example, the speaker 11, the lamp group 18, the display device 13, etc.

[0128] The launching device 15 has a launching handle 25 that can be rotated by a player when launching gaming balls stored in the upper tray 21 into the gaming area 12a. When the launching handle 25 is gripped by a player and rotated clockwise, the payout / launching control circuit 123 supplies power to a solenoid actuator (not shown) of the launching device 15 in accordance with the rotation angle. This causes the launching device 15 to launch gaming balls. Note that a motor may be used instead of a solenoid actuator as the driving means for the launching device 15.

[0129] The external terminal board 140 is used to transmit data to the hall computer that manages all the pachinko machines in the gaming parlor. The data display 141 is installed, for example, on top of the pachinko gaming machine 1 as ancillary equipment of the gaming parlor, and has the functions of calling a hall attendant and displaying the number of wins.

[0130] When operated by a player, the dispensing operation unit 151 outputs a signal requesting the dispensing of game balls to the card unit 150. The card unit 150 determines the number of game balls to be dispensed (number of dispensed balls) via the prize ball case unit 170 based on the signal requesting the dispensing of game balls output from the dispensing operation unit 151. Then, when the card unit 150 receives a signal requesting the dispensing of game balls from the dispensing operation unit 151, it transmits a dispensed ball control signal including information on the determined number of dispensed balls to the dispensing / launching control circuit 123.

[0131] [Sub-control circuit] The sub-control circuit 200 is connected to the serial communication unit 76 of the main control circuit 70. The sub-control circuit 200 (the host control circuit 210, described later) controls the entire sub-control circuit 200 in accordance with various commands (information related to the progress of the game) transmitted from the main control circuit 70. Based on the various commands transmitted from the main control circuit 70, the sub-control circuit 200 controls the audio playback operation of the speaker 11, the image display operation of the display device 13, the lamp on / off operation of the lamp group 18 including LEDs, and the performance operation of the accessory 20 (decorative member). In other words, the sub-control circuit 200 controls various performance devices based on instructions from the main control circuit 70, and executes various performances according to the progress of the game. Note that in this embodiment, the sub-control circuit 200 is configured not to supply signals to the main control circuit 70, but the present invention is not limited to this, and the sub-control circuit 200 may be configured to transmit signals to the main control circuit 70.

[0132] Next, the internal configuration of the sub-control circuit 200 will be described in more detail with reference to Fig. 6. Fig. 6 is a block diagram showing the internal circuit configuration of the sub-control circuit 200 and the connections between the sub-control circuit 200 and various peripheral devices.

[0133] As shown in FIG. 6, the sub-control circuit 200 includes a relay board 201, a sub-board 202 (first board), a control ROM board 203, and a CGROM (Character Generator ROM) board 204. The sub-substrate 202 is connected to the relay substrate 201, the control ROM substrate 203, and the CGROM substrate 204. Within the sub-control circuit 200, the sub-substrate 202 and the various ROM substrates (the control ROM substrate 203 and the CGROM substrate 204) are connected via board-to-board connectors (not shown).

[0134] The relay board 201 is a relay board for receiving commands transmitted from the main control circuit 70 and transmitting the received commands to the sub-board 202 .

[0135] The sub-board 202 is provided with a host control circuit 210, an audio / LED control circuit 220, a display control circuit 230, an SDRAM (Synchronous Dynamic RAM) 250, and an internal relay board 260. Of these, at least the host control circuit 210, the audio / LED control circuit 220, and the display control circuit 230 are configured as a single board.

[0136] The host control circuit 210 is a circuit that controls the operation of the entire sub-control circuit 200 based on various commands sent from the main control circuit 70, and is composed of a CPU processor, a sub-work RAM 210a, an SRAM 210b, an RTC (real-time clock), and a watchdog timer. The host control circuit 210 is connected to the audio / LED control circuit 220, the display control circuit 230, and the built-in relay board 260 within the sub-board 202. The host control circuit 210 is also connected to the control ROM board 203.

[0137] The host control circuit 210 also has a sub-work RAM 210a and an SRAM (Static RAM) 210b. The sub-work RAM 210a is a storage device that functions as a temporary working storage area when the host control circuit 210 executes various processes, and stores various flags and variable values ​​required when the host control circuit 210 executes various processes. The SRAM 210b is a storage device that backs up predetermined data in the sub-work RAM 210a. Note that, although RAM is used as the temporary storage area of ​​the host control circuit 210 in this embodiment, the present invention is not limited to this, and any readable and writable storage medium may be used as the temporary storage area.

[0138] The audio / LED control circuit 220 is connected to the speaker 11 and the lamp group 18 via the built-in relay board 260, and is a circuit that controls the audio playback operation by the speaker 11 and the light emission operation by the lamp group 18 based on control signals (sound request and lamp request, described below) input from the host control circuit 210. Therefore, functionally, the audio / LED control circuit 220 has an audio controller 220a and a lamp controller 220b. The audio controller 220a and the lamp controller 220b are substantially included in a sound / lamp control module 226, described below. The internal configuration of the audio / LED control circuit 220 will be described in detail later with reference to the drawings.

[0139] In this embodiment, when the control signals and data (such as LED data described below) output from the audio / LED control circuit 220 are transmitted to the lamp group 18 via the built-in relay board 260, communication between the audio / LED control circuit 220 and the lamp group 18 is performed using the SPI (Serial Peripheral Interface) communication method (a type of serial communication method). Also, in this embodiment, the lamp group 18 includes one or more LEDs and one or more LED drivers for controlling each LED.

[0140] The display control circuit 230 is connected to the display device 13, and is a circuit for controlling various processing operations when images related to effects (decorative pattern images, background images, images for effects, etc.) are displayed on the display device 13 based on control signals (drawing requests) input from the host control circuit 210. The display control circuit 230 has display controllers (a first display controller 238 and a second display controller 239, which will be described later) and an internal VRAM (Video RAM) 237.

[0141] The display control circuit 230 is connected to the SDRAM 250 in the sub-substrate 202. The display control circuit 230 is further connected to the CGROM substrate 204. The display controller in the display control circuit 230 is directly connected to the display device 13 without going through an intermediate substrate. The internal configuration of the display control circuit 230 will be described in detail later with reference to the drawings.

[0142] The SDRAM 250 is configured with DDR2 (Double-Data Rate 2) SDRAM. The SDRAM 250 also includes various buffers for temporarily storing various types of image data in the rendering process of images (moving images and still images) displayed by the display device 13. Specifically, the SDRAM 250 includes, for example, a texture buffer, a movie buffer, a blend buffer, two frame buffers (a first frame buffer and a second frame buffer), a motion buffer, and the like.

[0143] The built-in relay board 260 is a relay board that receives various signals and data output from the host control circuit 210 and the audio / LED control circuit 220, and transmits the received various signals and data to the speaker 11, the lamp group 18, and the props 20.

[0144] Furthermore, the built-in relay board 260 has an I2C (Inter-Integrated Circuit) controller 261 and a digital audio power amplifier 262 (amplifying means). Note that, although the present embodiment shows an example in which the I2C controller 261 and the digital audio power amplifier 262 are mounted on the same relay board, the present invention is not limited to this, and the relay board on which the I2C controller 261 is mounted may be provided separately from the relay board on which the digital audio power amplifier 262 is mounted.

[0145] The I2C controller 261 is connected to the host control circuit 210 and the motor controller 270 of the accessory 20. That is, the host control circuit 210 is connected to the accessory 20 via the I2C controller 261 and the motor controller 270. Then, the control signals and data (for example, excitation data, etc., described below) output from the host control circuit 210 are input to the accessory 20 via the I2C controller 261 and the motor controller 270.

[0146] In this embodiment, communication between the I2C controller 261 and the motor controller 270 is performed using an I2C communication method (a type of serial communication method). In this embodiment, the accessory 20 includes one or more motors, and the motor controller 270 includes one or more motor drivers for driving each motor. While Fig. 6 shows an example in which only one accessory 20 is provided, the present invention is not limited to this, and multiple accessory 20 may be provided.

[0147] Furthermore, in the configuration of this embodiment, the host control circuit 210 may directly drive the motor of the accessory 20 without using the motor controller 270, or a separate control circuit for motor control may be provided. Furthermore, in this embodiment, one control circuit controls multiple motor drivers (motors), but the present invention is not limited to this. In this embodiment, one or more control circuits may be configured to control one or more motors (motor drivers), one or more control circuits may be configured to control one motor (motor driver), or one control circuit may be configured to control one motor (motor driver).

[0148] Furthermore, the digital audio power amplifier 262 is connected to the audio / LED control circuit 220 and the speaker 11. That is, the audio / LED control circuit 220 is connected to the speaker 11 via the digital audio power amplifier 262. Therefore, audio signals and the like output from the audio / LED control circuit 220 are input to the speaker 11 via the digital audio power amplifier 262.

[0149] The control ROM board 203 is provided with a sub-main ROM 205. The sub-main ROM 205 stores various programs and various data tables (see, for example, FIG. 26 described later) for controlling the performance operations of the pachinko gaming machine 1 by the host control circuit 210. The host control circuit 210 then executes various processes in accordance with the programs stored in the sub-main ROM 205.

[0150] In this embodiment, the sub-main ROM 205 is used as storage means for storing programs and various tables used by the host control circuit 210, but the present invention is not limited to this. As such storage means, other storage media readable by a computer equipped with control means may be used, such as a hard disk drive, a CD-ROM, a DVD-ROM, or a ROM cartridge. Also, each program may be recorded on a separate storage medium. Furthermore, the programs may be pre-recorded on a recording medium, or may be downloaded from an external source after power is turned on and recorded on the sub-main ROM 205.

[0151] A CGROM 206 is provided on the CGROM substrate 204. The CGROM 206 is configured by a NOR or NAND type flash memory. The CGROM 206 also stores, for example, image data to be displayed on the display device 13 and audio data (sometimes referred to as sound data in this specification) to be played back by the speaker 11. At this time, various data are compressed (encoded) and stored in the CGROM 206, but the present invention is not limited to this, and various data may also be stored in the CGROM 206 without being compressed.

[0152] In the present embodiment, the sub-control circuit 200 is configured such that the various ROM boards (control ROM board 203 and CGROM board 204) and the sub-board 202 are connected via board-to-board connectors. However, the present invention is not limited to this. For example, the various ROMs may be directly inserted into ports such as sockets on the sub-board 202, thereby constituting the sub-board 202 with a single board that has ROM functions or the ROM itself. That is, the sub-board 202 and the various ROMs may be integrally configured. Furthermore, when the sub-board 202 is configured with a single board that has ROM functions or the ROM itself, the sub-control circuit 200 may be provided with switching means that physically or electrically switches the circuit on the sub-board to be used depending on the type of memory used as the CGROM, or switching means that switches the information on the circuit on the sub-board to be used depending on the type of memory.

[0153] In addition, in this embodiment, the relationship in magnitude of data communication speed between each of the various storage means (sub-main ROM 205, CGROM 206, internal VRAM 237, SDRAM 250) and the corresponding control circuit is internal VRAM 237 > SDRAM 250 > sub-main ROM 205 ≈ CGROM 206. That is, in this embodiment, the communication speed between the internal VRAM 237 and the various circuits in the display control circuit 230 is the fastest, followed by the communication speed between the SDRAM 250 and the display control circuit 230. The communication speed between the sub-main ROM 205 and the host control circuit 210 and the communication speed between the CGROM 206 and the display control circuit 230 are the slowest. However, the present invention is not limited to this, and the relationship in magnitude of communication speed between each of the various storage means and the corresponding control circuit can be set arbitrarily. For example, the relationship in magnitude of communication speed between each of the various storage means and the corresponding control circuit may be different from that in this embodiment, or the communication speed between each storage means and the corresponding control circuit may all be the same.

[0154] Here, possible configurations of the various storage means mentioned above will be explained. In this embodiment, an example configuration has been described in which the storage means for information related to image data (compressed (encoded) image data) is the same as the storage means (CGROM 206) for information related to transparency data (an alpha table described later) that can be used when setting transparency for image data. That is, an example configuration has been described in which the "first information storage means" is physically the same as the "second information storage means." However, the present invention is not limited to this. For example, the "first information storage means" may be configured as a storage means (storage medium) that is physically different from the "second information storage means."

[0155] Furthermore, the term "information storage means" as used herein may refer not only to storage means such as CGROM 206, but also to tables stored in the storage means, data storage areas within the storage means, etc. Therefore, for example, the "first information storage means" and the "second information storage means" may be different data storage areas, different tables, or different register addresses within the same storage means. In other words, "different information storage means" as used herein refers not only to different physical storage means (storage media), but also to different data areas (storage areas distinguished by addresses, registers, tables, structures, etc.) within the same physical storage means (e.g., ROM, RAM, etc.).

[0156] The meaning of "information storage means" in this specification can also be applied to the "third information storage means" (SDRAM 250) and "fourth information storage means" (built-in VRAM 237). Therefore, for example, the "first information storage means" to the "fourth information storage means" may be configured as physically different storage means (storage media), or the "first information storage means" to the "fourth information storage means" may be configured as different data areas (storage areas distinguished by addresses, registers, tables, structures, etc.) within a single storage means.

[0157] In addition, in this embodiment, an example has been described in which the "first information storage means" and the "second information storage means" are configured as different data areas within one storage means (CGROM206), the "third information storage means" is configured as a storage means (SDRAM250) physically different from the storage means (CGROM206) including the "first information storage means" and the "second information storage means", and the "fourth information storage means" is configured as a storage means (built-in VRAM237) physically different from the storage means (CGROM206) including the "first information storage means" and the "second information storage means" and the "third information storage means" (SDRAM250), but the present invention is not limited to this. Whether the "information storage means" is configured as a data area or a storage means, and what form to use for combining the "information storage means" defined as a data area and the "information storage means" defined as a storage means, depend on the configuration of the storage means provided in the gaming machine, for example. It can be set appropriately depending on the number, type, etc. For example, in this embodiment, the "first information storage means" to the "third information storage means" may be configured as different data areas in one storage means, and the "fourth information storage means" may be configured as a storage means physically different from the storage means including the "first information storage means" to the "third information storage means".

[0158] [Audio and LED control circuit] Next, the internal configuration of the audio / LED control circuit 220 will be described with reference to Fig. 7. Fig. 7 is a block diagram showing the internal circuit configuration of the audio / LED control circuit 220 and the connection relationship between the audio / LED control circuit 220 and various peripheral devices and peripheral circuit sections. Note that, in Fig. 7, for the sake of simplicity, relay boards and the like provided between the audio / LED control circuit 220 and various peripheral devices and circuit sections are not shown.

[0159] 7, the sound / LED control circuit 220 includes an LSI (Large-Scale Integration) interface 221, a memory interface 222, a digital audio interface 223, a peripheral interface 224, a command register 225, a sound / lamp control module 226, a main generator 227, and a multi-effector 228. The connections between the various parts in the sound / LED control circuit 220 are as follows:

[0160] Within the sound and LED control circuit 220, the sound and lamp control module 226 is connected to the memory interface 222, the peripheral interface 224, the command register 225, the main generator 227, and the multi-effector 228. The command register 225 is connected to the LSI interface 221 in addition to the sound and lamp control module 226. The main generator 227 is connected to the memory interface 222 and the multi-effector 228 in addition to the sound and lamp control module 226. The multi-effector 228 is connected to the memory interface 222 and the digital audio interface 223 in addition to the sound and lamp control module 226 and the main generator 227.

[0161] Next, the configuration of each part in the audio / LED control circuit 220 will be described.

[0162] The LSI interface 221 is an interface circuit used when performing input / output operations of control signals and the like (for example, sound requests, lamp requests, etc.) between the host control circuit 210 and the command register 225. In other words, the command register 225 is connected to the host control circuit 210 via the LSI interface 221.

[0163] The memory interface 222 is an interface circuit used when performing input / output operations of audio data and the like between the sub-main ROM 205 and each of the sound / lamp control module 226, the main generator 227, and the multi-effector 228.

[0164] The digital audio interface 223 is an interface circuit used when outputting an audio signal or the like from the multi-effector 228 to the speaker 11. The digital audio interface 223 also outputs an audio input signal to the multi-effector 228.

[0165] The peripheral interface 224 is an interface circuit used when inputting and outputting lamp signals and the like (such as LED data, which will be described later) between the lamp group 18 and the sound and lamp control module 226. The peripheral interface 224 is provided with three physical systems (SPI channels) for outputting data to the LED drivers included in the lamp group 18. In this embodiment, as will be described later, two physical systems (physical system 0 (SPI channel 0) and physical system 1 (SPI channel 1)) are used.

[0166] The command register 225 is composed of a large number of registers (for example, a large number of audio control registers) that are accessed by the host control circuit 210. The command register 225 sets the function control of the sound / lamp control module 226, the main generator 227, and the multi-effector 228. The command register 225 also sets the operating conditions of each interface (LSI interface 221, memory interface 222, digital audio interface 223, and peripheral interface 224).

[0167] Each register that makes up the command register 225 is equipped with an integrated circuit (IC), and each register is made up of a memory chip that stabilizes operation through memory access control. When registers with this configuration are used, the load on the signal bus to which each register is connected is reduced, so the capacity per memory module (the capacity of the command register 225) can be easily increased by increasing the number of memory chips (registers).

[0168] The sound / lamp control module 226 comprehensively controls audio playback operations and the like, and controls the operation of each component (each block) in the audio / LED control circuit 220 according to the settings of the command register 225. As shown in Fig. 7, the sound / lamp control module 226 has a simple access controller 226a, a sequencer 226b, a lamp control unit 226c, and a peripheral control unit 226d.

[0169] The simple access controller 226a is a circuit unit that processes commands in bulk. The sequencer 226b has various sequencers (automatic playback function units) for controlling automatic playback operations such as lamp lighting and audio. Each sequencer controls various operations according to timers and step conditions (for example, conditions set for each step during sequence playback such as LED animation and audio, which will be described later).

[0170] The lamp control unit 226c calculates the brightness values ​​to be set for all channels (eight channels) for which LED data (described later) can be set, and transmits the calculation results to the outside (LED driver). The peripheral control unit 226d also performs physical transmission control when transmitting the calculation result data output from the lamp control unit 226c to the LED driver.

[0171] The main generator 227 is a circuit unit that generates an audio signal. Specifically, the main generator 227 acquires predetermined audio data stored in the CGROM 206 based on a control signal input from the sound / lamp control module 226, and converts the acquired audio data into a predetermined audio signal. The main generator 227 includes a decoder 227a that reproduces compressed data divided into reproduction channels CH1 to CH32, channel volumes 227b (V1 to V4) that adjust the volume, a channel mix unit 227c that mixes the reproduced sounds of the decoder 227a, and a remix unit 227d that performs the final mixing operation.

[0172] The multi-effector 228 has a mixer that mixes the audio signal input from the main generator 227 with the audio input signal input from the digital audio interface 223, and various effectors that apply various sound effects to the audio. The multi-effector 228 outputs the audio signal mixed by the mixer, the output signal from the effector, etc. to the speaker 11 via the digital audio interface 223.

[0173] Figure 8 is a diagram explaining the output signals of the sound and LED control circuit. The CGROM 206 stores up to 8192 types of sequence code groups and up to 8192 types of SAC data groups. The sequence code and SAC data are specified by a 13-bit sequence code number and SAC number, respectively, and 8192 = 2 13 are in a relationship.

[0174] In this embodiment, the sequencer 226b is provided with 16 systems (SQ0 to SQ15) that operate in parallel, and the simple accelerator controller 226a is provided with 4 systems (SAC0 to SAC3) that operate in parallel. Corresponding to this configuration, the command register 225 is provided with a voice control register RGj2 for controlling the sequencers (SQ0 to SQ15) and a voice control register RGj1 for controlling the SACs (SAC0 to SAC3).

[0175] Then, when the host control circuit 210, which is configured by a CPU processor, writes the SAC number and its associated information to a predetermined voice control register RGj1 for SAC control based on the transmission operation of a voice command, the corresponding simple access controller 226a starts functioning, and the simple access controller 226a writes a group of setting data specified by the SAC number to a group of voice control registers specified by the SAC data. In this embodiment, the complicated setting operation can be completed by transmitting one SAC number and its associated information.

[0176] On the other hand, when the host control circuit 210, which is composed of a CPU processor, writes a sequence code number and its associated information to a predetermined voice control register RGj2 for controlling the sequencer 226b (SQ0 to SQ7) based on the sending operation of a voice command, the corresponding sequencer SQi starts functioning and writes a group of setting data specified by the sequence code to a group of voice control registers indicated by the sequence code.

[0177] Here, the predetermined sound control register RGj2 for controlling the sequencers (SQ0 to SQ7) can be written with multiple (up to eight) sequence code numbers and loop information for the effects of each sequence code number for any sequencer SQi. Therefore, for example, if n+1 sequence code numbers (X0, X1, . . . , Xn) are specified for sequencer SQi, the setting operation for sequence code number X0 → setting operation for sequence code number X1 → . . . setting operation for sequence code number Xn will be executed in this order, and the sound effects corresponding to the setting operations will be executed.

[0178] In addition, loop information such as the number of repetitions can be specified for each sequence code number, so that after repeating the audio performance specified by the sequence code number a predetermined number of times, it is possible to move on to the audio performance specified by the next sequence code number.

[0179] As described above, a wide variety of data needs to be set in the sequencer SQi, and these sequence code numbers and associated data must be appropriately set in the voice control register RGj2 for controlling the sequencer. Therefore, in this embodiment, the entire sequence code number and associated data are divided into 1-byte units, and a group of SAC data, each consisting of a divided 1-byte data and a register address of the sequencer control register RGj2 to which this 1-byte data should be set, is secured in the CGROM 206 (hereinafter, this is referred to as sequencer startup SAC data).

[0180] The host control circuit 210 then starts the simple access controller 226a by specifying a specific SAC number in the audio control register RGj1 for SAC control. Here, the SAC number naturally identifies the SAC data for starting the sequencer. Then, based on the operation of the SAC (Simple Access Controller), the necessary data is loaded into the sequencer control register RGj2. Therefore, the operation of setting the start-up data for the sequencers SQ0 to SQ15 is easy.

[0181] As explained above with reference to Figure 8, a group of sequence codes identified by one sequence code number contains multiple operation units (sequence steps) separated by step end codes (FFFEH), so that after all the multiple sequence steps identified by one sequence code number are executed, the multiple sequence steps identified by the next sequence code number are executed.

[0182] A standby time can also be set for each sequencer, so that the first sequence step (writing operation of a group of setting data) starts after the standby time specified by the host control circuit 210 configured by the CPU processor, and when it is executed up to the step end code (FFFEH), the next group of setting data is written to a group of audio control registers after the standby time. Note that a single time information can be set for the standby time for each sequencer (SQ0 to SQ7), but the standby time for each sequence step can be set arbitrarily, for example, by setting a standby time to be applied to the subsequent sequence step in the preceding sequence step.

[0183] Continuing with the explanation of the internal configuration of the audio / LED control circuit 220, as shown in Figure 7, the six-channel output signals (mixed L0, mixed R0, mixed L1, mixed R1, mixed SUB0, mixed SUB1) of the channel mix section 227c are digitally filtered in the multi-effector 228 based on the operating parameters specified in a predetermined audio control register of the command register 225, and then supplied to the total volume 229 (TV0 to TV3) and amplified based on the total volume value TV.

[0184] The total volume value TV is determined by the operating parameters written to the corresponding audio control register. As explained above, in this embodiment, these operating parameters are determined based on the setting switch (hardware switch) operated by the attendant. However, if the player operates the volume switch (screen operation) during game play (but while audio effects are waiting), the total volume TV is determined (changed) based on the set value. Note that when the player operates the volume switch, instead of or in addition to the total volume TV being determined based on the set value, the channel volume 227b (V1 to V4) may be determined (changed).

[0185] [Speaker volume control] Next, the volume control of each speaker 11 executed by the host control circuit 210 will be described with reference to Fig. 9. Fig. 9 is a control block diagram for explaining an example of volume control by the host control circuit.

[0186] The volume of the game sounds and other sounds output from each speaker 11 (L0 / R0 / L1 / R1, SUB0, SUB1) is controlled by a volume transition operation that gradually transitions the volume value of the audio signal by multiplying the audio signal of the total volume TV0 to 3 output to all channels with the audio signal of each playback channel output to each individual channel among all channels.

[0187] Note that the "audio signal" has volume information (such as information on wattage) and can also be simply called "volume." For example, in this specification, the "audio signal for each playback channel" may be referred to as the "volume for each playback channel."

[0188] The audio signals of the total volumes TV0 to 3 are determined by multiplying the total value of the audio signals output by volume control 281 using a hardware switch and user volume control 282 using the volume setting screen by the audio signal output by debug volume control 283 during debugging. The host control circuit 210 that executes volume control 281 using a hardware switch, user volume control 282 using the volume setting screen, and debug volume control 283 during debugging corresponds to the "first volume control means" of the present invention.

[0189] The volume for each playback channel is determined by multiplying the audio signal for the primary volume by the audio signal for the secondary volume. The audio signal for the primary volume is determined by the combined value of the audio signal output by the first playback channel primary control 284, which is affected by volume adjustment, and the audio signal output by the second playback channel primary control 285, which is not affected by volume adjustment. The first playback channel primary control 284 controls the volume of normal game sounds (i.e., audio signals (hereinafter the same)) based on, for example, a volume change operation performed by a player. The second playback channel primary control 285 controls the output of specific game sounds (e.g., error sounds or warning sounds for illegal activity) at a constant volume, regardless of whether a volume change operation has been performed. This constant volume may always be maximum volume. In this way, the second playback channel primary control 285, which is not affected by volume adjustment, controls the output of specific game sounds at a constant volume, making it possible to control the volume of specific game sounds to be constant only on specific playback channels, rather than across the entire system. The audio signal of the secondary volume is the volume incorporated in the audio data specified by the SAC number, and is output by volume controls 286, 287, and 288. The first playback channel primary control 284, the second playback channel primary control 285, and the host control circuit 210 that executes the volume controls 286, 287, and 288 incorporated in the audio data correspond to the "second volume control means" of the present invention.

[0190] In this way, the sound output from each speaker 11 (L0 / R0 / L1 / R1, SUB0, SUB1) is determined by multiplying the volume of the total volumes TV0-3 by the volume of the primary volume and the secondary volume, which are the volumes for each playback channel, making it possible to provide diversity in the volume of the game sounds. In particular, the volume of the total volumes TV0-3 is also determined by the volume output by the debug volume control 283 during debugging, so that during debugging, the game sound data used in the game can be used as is, thereby improving work efficiency during debugging.

[0191] Furthermore, the volume of normal game sounds can be changed based on whether a player or other user has performed an operation to change the volume, but for specific game sounds such as error sounds and warning sounds for illegal activity, a fixed volume is output by the second playback channel primary control 285 regardless of whether a volume change operation has been performed. This makes it impossible to hide the occurrence of an error or illegal activity, thereby improving security.

[0192] In the pachinko gaming machine 1 of this embodiment, the volume control 281 by the hardware switch has three levels, for example, large, medium, and small. Also, the user volume control 282 by the volume setting screen has seven levels, which are linked to the hardware switch: [Small] = [1], [Medium] = [4], and [Large] = [7].

[0193] As described above, in the pachinko gaming machine 1 of this embodiment, for example, the volume of a specific sound such as an error sound can be maintained only by the control by the second playback channel primary control 285, so that it is possible to easily perform volume control such that the volume of the specific sound is maintained while the volume of other normal sounds is changed according to the volume adjustment. Note that the processing by the host control circuit 210 when the volume adjustment is performed will be described later with reference to Figures 61 to 65.

[0194] [Connection configuration between digital audio power amplifier and speaker] Next, the connection configuration between the digital audio power amplifier 262 and its peripheral circuits provided in the built-in relay board 260 and the speaker 11 will be described with reference to Fig. 10. Fig. 10 is a diagram showing the connection configuration between the built-in relay board 260 and the speaker 11. Note that Fig. 10 shows a state in which the speaker 11 is not connected to the built-in relay board 260 in order to clarify the configuration of the connection portion.

[0195] In the pachinko gaming machine 1 of this embodiment, a speaker box 11a in which a speaker 11 is provided is connected to a built-in relay board 260 via a harness 300, as shown in FIG.

[0196] The built-in relay board 260 has a digital audio power amplifier 262, an LC circuit 263, a connection terminal group 264 including four connection terminals (first connection terminal to fourth connection terminal), two resistors 265 and 266, a capacitor 267, and a NOT circuit (logic circuit) 268.

[0197] The digital audio power amplifier 262 amplifies the input audio signal (audio data) and outputs the amplified audio signal to the speaker 11 to drive the speaker 11. The LC circuit 263 is configured as a resonant circuit including a coil and a capacitor. The NOT circuit 268 is a logic circuit that inverts the level of the input signal and outputs it.

[0198] The clock input terminal (MCK) and data input terminal (SDATA) of the digital audio power amplifier 262 are connected to the audio / LED control circuit 220. The clock input terminal (MCK) of the digital audio power amplifier 262 receives as input a clock signal (master clock signal) output from the audio / LED control circuit 220, and the data input terminal (SDATA) receives as input an audio signal (audio data) output from the audio / LED control circuit 220.

[0199] Furthermore, the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 are connected to the first connection terminal and the second connection terminal in the connection terminal group 264 of the built-in relay board 260, respectively, via the LC circuit 263. Note that, although the present embodiment shows an example in which the digital audio power amplifier 262 is provided with two output terminals, the present invention is not limited to this and can be modified as appropriate depending on, for example, the functions and specifications of the speaker 11.

[0200] Furthermore, the digital audio power amplifier 262 has a mute terminal (MUTE: audio output control terminal). The digital audio power amplifier 262 has a function (hereinafter referred to as a mute function) of stopping the output of audio signals from the first output terminal (OUTM1) and the second output terminal (OUTM2) or grounding these output terminals via high resistances when the level (amplitude value) of the voltage signal applied to the mute terminal is low. That is, the digital audio power amplifier 262 has a function of generating a state in which the output of audio signals from the first output terminal (OUTM1) and the second output terminal (OUTM2) to the first connection terminal and the second connection terminal of the built-in relay board 260 is stopped when the level of the voltage signal applied to the mute terminal is low.

[0201] On the other hand, when the level (amplitude value) of the voltage signal applied to the mute terminal (MUTE) is at a HIGH level, the digital audio power amplifier 262 outputs an audio signal from the first output terminal (OUTM1) and the second output terminal (OUTM2).

[0202] A third connection terminal in connection terminal group 264 of built-in relay substrate 260 is connected to an input terminal of NOT circuit 268 via resistor 266. An output terminal of NOT circuit 268 is connected to a mute terminal (MUTE) of digital audio power amplifier 262. A signal wiring between the third connection terminal of built-in relay substrate 260 and resistor 266 is connected to a power supply voltage (+5V) terminal provided in built-in relay substrate 260 via resistor 265. A signal wiring between the input terminal of NOT circuit 268 and resistor 266 is connected (grounded) to a ground (GND) terminal provided in built-in relay substrate 260 via capacitor 267. A fourth connection terminal of built-in relay substrate 260 is connected to the ground (GND) terminal.

[0203] As shown in Fig. 10, the speaker 11 is attached to a speaker box 11a made of a wooden frame. The speaker box 11a is provided with a connection terminal group 11b including four connection terminals (first to fourth connection terminals). The first and second connection terminals of the speaker box 11a are connected to the speaker 11 via signal wiring. The third connection terminal (specific connection terminal) of the speaker box 11a is electrically connected to the fourth connection terminal by a signal wiring W1.

[0204] 10 , the harness 300 is configured by bundling four signal wires. Four connection terminals (first to fourth connection terminals) on one side of the four signal wires are connected to the first to fourth connection terminals of the built-in relay substrate 260, respectively. Meanwhile, four connection terminals (fifth to eighth connection terminals) on the other side of the four signal wires are connected to the first to fourth connection terminals of the speaker box 11a, respectively. That is, the first connection terminal of the built-in relay substrate 260 and the first connection terminal of the speaker box 11a are connected by a signal wiring between the first and fifth connection terminals in the harness 300, and the second connection terminal of the built-in relay substrate 260 and the second connection terminal of the speaker box 11a are connected by a signal wiring between the second and sixth connection terminals in the harness 300. Furthermore, the third connection terminal of the built-in relay board 260 and the third connection terminal of the speaker box 11a are connected by a signal wiring between the third connection terminal and the seventh connection terminal in the harness 300, and the fourth connection terminal of the built-in relay board 260 and the fourth connection terminal of the speaker box 11a are connected by a signal wiring between the fourth connection terminal and the eighth connection terminal in the harness 300. In this way, the speaker 11 is connected to the built-in relay board 260 via the harness 300.

[0205] The number of signal wires included in the harness 300 is not limited to four and may be changed as appropriate depending on, for example, the specifications of the digital audio power amplifier 262 and the speaker 11, the connection configuration between them, etc. The harness 300 only needs to include at least a signal wire for connecting the output terminal of the digital audio power amplifier 262 to the speaker 11, and a signal wire for grounding the mute terminal of the digital audio power amplifier 262 via the speaker box 11a.

[0206] When the built-in relay board 260 and the speaker 11 are connected via the harness 300 as described above, the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 are connected to the speaker 11 via the harness 300. In addition, the mute terminal (MUTE) of the digital audio power amplifier 262 is grounded via the NOT circuit 268, the harness 300, and the signal wiring W1 between the third connection terminal and the fourth connection terminal of the speaker box 11a.

[0207] As a result, when the speaker 11 is connected to the built-in relay board 260 (digital audio power amplifier 262) via the harness 300, a LOW level voltage signal is input to the NOT circuit 268, and the mute terminal of the digital audio power amplifier 262 The level (amplitude value) of the voltage signal input to (MUTE) becomes HIGH. In this case, an audio signal is output to the speaker 11 from the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262.

[0208] On the other hand, when the speaker 11 is not connected to the built-in relay board 260 (digital audio power amplifier 262), the third connection terminal of the built-in relay board 260 is in an open state. In this case, the power supply voltage (+5V) is input to the NOT circuit 268, so that the level (amplitude value) of the voltage signal input to the mute terminal (MUTE) of the digital audio power amplifier 262 becomes a LOW level, and the above-mentioned mute function of the digital audio power amplifier 262 is activated.

[0209] That is, when the speaker 11 is detached from the built-in relay board 260 (digital audio power amplifier 262), a state is created in which the output of audio signals from the first output terminal (OUTM1) and second output terminal (OUTM2) of the digital audio power amplifier 262 to the first connection terminal and second connection terminal of the built-in relay board 260 is stopped. As a result, the occurrence of a resonance phenomenon between the digital audio power amplifier 262 (output terminal) and the first and second connection terminals of the built-in relay board 260 is suppressed, and it is possible to prevent malfunctions such as breakdowns of the digital audio power amplifier 262.

[0210] As described above, in this embodiment, the mute function of the digital audio power amplifier 262 can be activated regardless of software control by the host control circuit 210 and the audio / LED control circuit 220. Therefore, for example, when the speaker 11 is detached from the built-in relay board 260, the host control circuit 210 and the audio / LED control circuit 220 recognize that they are controlling the output of an audio signal to stop, but an audio signal is erroneously output due to a program bug (malfunction) or the like. In a pachinko gaming machine 1 that is designed so that the game board cannot be replaced unless the speaker 11 is detached from the harness 300, the door is accidentally closed after the game board has been replaced, and audio output is started without connecting the speaker 11 to the harness 300. Even in such a case, the mute function of the digital audio power amplifier 262 is activated by hardware. In this case, the digital audio power amplifier 262 can be reliably protected, thereby improving the safety of the pachinko gaming machine 1.

[0211] Furthermore, in this embodiment, as described above, the third connection terminal of built-in relay board 260 is connected to a ground (GND) terminal provided within built-in relay board 260 via harness 300 and signal wiring W1 between the third connection terminal and the fourth connection terminal of speaker box 11a. In this configuration, when the signal level of the third connection terminal of built-in relay board 260 is LOW, it can be determined by measuring the signal level of the fourth connection terminal of built-in relay board 260 whether this is due to the fourth connection terminal of built-in relay board 260 being grounded, and therefore digital output operation from digital audio power amplifier 262 can be managed more accurately.

[0212] [Display control circuit] Next, the internal configuration of the display control circuit 230 will be described with reference to Fig. 11. Fig. 11 is a block diagram showing the internal circuit configuration of the display control circuit 230 and the connection relationship between the display control circuit 230 and various peripheral devices and peripheral circuit sections.

[0213] 11, the display control circuit 230 includes a memory controller 231, a command memory 232, a command parser 233, a video decoder 234, a still image decoder 235, an SDRAM controller 236, an internal VRAM 237, a first display controller 238, a second display controller 239, a 3D (Dimension) geometry engine 240, and a rendering engine 241. The connections between the various components within the display control circuit 230 and the connections between the display control circuit 230 and its various peripheral devices and circuits are as follows.

[0214] Within the display control circuit 230, the memory controller 231 is connected to a command parser 233, a video decoder 234, and a still image decoder 235. The command parser 233 is connected to the command memory 232, the video decoder 234, the still image decoder 235, and the 3D geometry engine 240 in addition to the memory controller 231. The video decoder 234 is connected to an SDRAM controller 236 in addition to the memory controller 231 and command parser 233. The still image decoder 235 is connected to an internal VRAM 237 in addition to the memory controller 231 and command parser 233.

[0215] Furthermore, within the display control circuit 230, the SDRAM controller 236 is connected to the video decoder 234 as well as to an internal VRAM 237, a first display controller 238, and a second display controller 239. The internal VRAM 237 is connected to the still image decoder 235 and the SDRAM controller 236 as well as to the first display controller 238, the second display controller 239, and a rendering engine 241. Furthermore, the 3D geometry engine 240 is connected to the rendering engine 241 as well as to the command parser 233.

[0216] The SDRAM 250 is connected to a memory controller 231 and an SDRAM controller 236 in the display control circuit 230. The CGROM board 204 is connected to the memory controller 231 in the display control circuit 230. The host control circuit 210 is connected to the memory controller 231 and a command memory 232 in the display control circuit 230. The display device 13 is connected to a first display controller 238 and a second display controller 239 in the display control circuit 230.

[0217] Next, the configuration of each part in the display control circuit 230 will be described.

[0218] The memory controller 231 mainly controls communication between various external memories (CGROM board 204 and SDRAM 250) and the display control circuit 230. For example, the memory controller 231 performs processes such as sending and receiving address specification signals for the external memory to be controlled, managing the ready and busy states of the memory, and acquiring data (performance data, command data, etc.) stored at addresses specified for the various memories.

[0219] The command memory 232 is an internal memory that stores the command list. Note that the command list can also be stored in the SDRAM 250 or the CGROM board 204 (CGROM 206) in addition to the command memory 232.

[0220] The command parser 233 acquires the command list from the specified memory (command memory 232, SDRAM 250, or CGROM 206). Specifically, in this embodiment, the host control circuit 210 sets the type of memory (command memory 232, SDRAM 250, or CGROM 206) in which the command list is located and its start address in a system control register (not shown) in the display control circuit 230. Then, the command parser 233 accesses the start address in the memory specified in the system control register (not shown) to acquire the command list.

[0221] Furthermore, the command parser 233 analyzes the acquired command list to generate specific control codes, and outputs the control codes to the video decoder 234, the still image decoder 235, and the 3D geometry engine 240. In this embodiment, each image processing module in the display control circuit 230 operates based on the control codes output by the command parser 233.

[0222] The video decoder 234 decodes the compressed video data acquired from the CGROM board 204 or the SDRAM 250. Then, the video decoder 234 outputs the decoded video data to the SDRAM 250 (external RAM). The video data (decoded result) output from the video decoder 234 is stored in a movie buffer provided in the SDRAM 250.

[0223] The still image decoder 235 decodes compressed still image data acquired from the CGROM board 204 or SDRAM 250. Then, the still image decoder 235 outputs the decoded still image data to the built-in VRAM 237. The still image data (decoded result) output from the still image decoder 235 is temporarily stored in a sprite buffer (described later) provided in the built-in VRAM 237.

[0224] The SDRAM controller 236 is a controller that controls operations such as the process of storing decoded moving image data and still image data in RAM, and the process of transferring image data between the built-in VRAM 237 and the CGROM board 204 or SDRAM 250 .

[0225] The built-in VRAM 237 operates as a work RAM when various processes such as decoding and rendering are executed in the drawing process by the display control circuit 230. In addition, various image data are temporarily stored in the built-in VRAM 237 in the process of transferring image data between the built-in VRAM 237 and the CGROM board 204 or the SDRAM 250, which is executed in each process step of the drawing process described below.

[0226] Each of the first display controller 238 and the second display controller 239 acquires the rendering result (drawing result) generated by the rendering engine 241 and outputs the rendering result to the display device 13. As a result, a predetermined image is displayed on the display screen of the display device 13. When two display controllers are provided as in the pachinko gaming machine 1 of this embodiment, one display control circuit 230 (one chip) can provide two screens on the display device 13 and control each screen independently.

[0227] The 3D geometry engine 240 performs processing to convert three-dimensional information into two-dimensional information (projection transformation processing) and affine transformation (graphic transformation) processing such as enlarging, reducing, rotating, and moving a graphic, based on the control code input from the command parser 233. Then, the 3D geometry engine 240 outputs the result of the transformation processing to the rendering engine 241.

[0228] The rendering engine 241 refers to a texture source (SDRAM 250 in this embodiment) in which the decompressed still image data and video data are stored, and performs rendering (drawing) processing on the image data. Then, the rendering engine 241 writes the rendering result to a rendering target (built-in VRAM 237 or SDRAM 250 in this embodiment).

[0229] In this specification, "rendering (drawing)" refers to editing decoded data in accordance with designated information such as scaling and rotation of the video (information output from the 3D geometry engine 240 in this embodiment). The "rendering engine" here also includes, for example, a "rasterizer" and a "pixel shader." Therefore, similar to a pixel shader, the rendering engine 241 also performs calculations on image data on a pixel-by-pixel basis to calculate ARGB values ​​(A: alpha value indicating transparency (opacity), R: luminance value of the red component, G: luminance value of the green component, B: luminance value of the blue component).

[0230] [Connection between display control circuit and CGROM] The pachinko gaming machine 1 of this embodiment has a configuration that can handle different types (NOR type or NAND type) of CGROM connected to the display control circuit 230. Here, with reference to Figures 12 and 13, the connection configuration between the display control circuit 230 and its peripheral circuits provided in the sub-substrate 202 and the CGROM mounted on the CGROM substrate will be described.

[0231] Fig. 12 is a diagram showing the connection between the sub-substrate 202 and the CGROM substrate 204a when the CGROM is a NOR-type CGROM 206a (NOR-type flash memory). Fig. 13 is a diagram showing the connection between the sub-substrate 202 and the CGROM substrate 204b when the CGROM is a NAND-type CGROM 206b (NAND-type flash memory). Note that Figs. 12 and 13 show the CGROM substrate detached from the sub-substrate 202 to clarify the configuration of the connection portion, but in reality, the two substrates are connected via a board-to-board connector.

[0232] (1) Sub-board configuration First, we will explain the internal configuration of the sub-board 202. As is clear from a comparison between Figures 12 and 13, the configuration of the sub-board 202 when a NOR-type CGROM 206a is mounted on a CGROM board 204a is the same as that when a NAND-type CGROM 206b is mounted on a CGROM board 204b.

[0233] 12 and 13, the sub-substrate 202 is provided with a display control circuit 230, and is also provided with a bidirectional balanced transceiver 301 and an AND circuit 302 (AND gate) as its peripheral circuits. The sub-substrate 202 is also provided with various signal wiring (buses) and a terminal group 303 including a plurality of connection terminals directly or indirectly connected to the display control circuit 230 via the various buses.

[0234] The bidirectional balanced transceiver 301 has four input / output terminals (terminals A0 to A3 in FIG. 12) on one side and four input / output terminals (terminals B0 to B3 in FIG. 12) connected to the four input / output terminals (terminals A0 to A3) on the other side. The bidirectional balanced transceiver 301 also has two control terminals (terminals OE and DIR in FIG. 12) for switching and controlling the communication direction of signals between the input / output terminals A0 to A3 and the input / output terminals B0 to B3.

[0235] The bidirectional balanced transceiver 301 switches the communication direction of signals between the input / output terminals A0 to A3 and the input / output terminals B0 to B3 according to the combination of the signal levels of the voltage signals applied to the control terminal OE and the control terminal DIR, respectively. This ensures the safety of the communication operation between the display control circuit 230 and the CGROM even if a mismatch in the communication direction (communication operation) occurs for some reason. The communication direction switching control operation of the bidirectional balanced transceiver 301 will be described in detail later. The bidirectional balanced transceiver 301 used in this embodiment is also compatible with systems having two power supplies of 3.3V and 5V.

[0236] The display control circuit 230 is provided with four input / output terminals (terminals GMA31 / GRB3 to terminals GMA28 / GRB0 in FIG. 12). These input / output terminals GMA31 / GRB3 to input / output terminals GMA28 / GRB0 act as output terminals for the address bus when the CGROM is a NOR-type CGROM 206a, and act as input terminals for ready / busy signals when the CGROM is a NAND-type CGROM 206b. The display control circuit 230 is also provided with 26 output terminals (terminals GMA27 to GMA2 in FIG. 12) that act as output terminals for data related to addresses of data storage areas in the CGROM (address specification data, etc.).

[0237] The display control circuit 230 is also provided with two CG memory chip enable output terminals (terminals GCE_0 and GCE_1 in FIG. 12). In this embodiment, the display control circuit 230 has two memory spaces corresponding to the two CG memory chip enable output terminals (GCE_0 and GCE_1: specific output terminals), and information such as memory type, bus width, and access timing is set in each memory space. However, in this embodiment, the display control circuit 230 cannot cope with a case where synchronous mode ROM and asynchronous mode ROM are mixed. It is configured in a way that makes it unusable.

[0238] Furthermore, the display control circuit 230 is provided with a plurality of data bus input terminals for acquiring image data (compressed data of moving images / still images) from the CGROM via a data bus.

[0239] The electrical connections of the above components provided on the sub-board 202 are as follows.

[0240] 12 and 13, the input / output combined terminal GMA31 / GRB3 to the input / output combined terminal GMA28 / GRB0 of the display control circuit 230 are connected to the input / output terminal B0 to the input / output terminal B3, respectively, of the bidirectional balanced transceiver 301. The input / output terminals A0 to A3 of the bidirectional balanced transceiver 301 are connected to the first connection terminal to the fourth connection terminal, respectively, of the terminal group 303. That is, the input / output combined terminal GMA31 / GRB3 to the input / output combined terminal GMA28 / GRB0 of the display control circuit 230 are connected to the first connection terminal to the fourth connection terminal, respectively, of the terminal group 303 via the bidirectional balanced transceiver 301.

[0241] Moreover, the output terminals GMA27 to GMA2 of the display control circuit 230 are connected to the 9th to 34th connection terminals of the terminal group 303, respectively, and the CG memory chip enable output terminals GCE_0 and GCE_1 are connected to the 35th and 36th connection terminals of the terminal group 303, respectively. Furthermore, the multiple data bus input terminals of the display control circuit 230 are connected to the corresponding connection terminals of the terminal group 303 from the 37th connection terminal onwards.

[0242] A control terminal DIR of the bidirectional balanced transceiver 301 is connected to a fifth connection terminal of the terminal group 303, and a control terminal OE is connected to an output terminal of the AND circuit 302. One input terminal of the AND circuit 302 is connected to a CG memory chip enable output terminal GCE_0, and the other input terminal of the AND circuit 302 is connected to a CG memory chip enable output terminal GCE_1. In addition, a sixth and seventh connection terminal of the terminal group 303 of the sub-substrate 202 are connected to a power supply voltage (+3.3V) terminal provided on the sub-substrate 202, and an eighth connection terminal is connected to a ground (GND) terminal provided on the sub-substrate 202.

[0243] (2) CGROM board (NOR type) configuration Next, the internal configuration of the CGROM board 204a on which the NOR type CGROM 206a is mounted will be described with reference to FIG.

[0244] When a NOR type CGROM 206a is mounted on a CGROM substrate 204a, the CGROM substrate 204a is provided with the NOR type CGROM 206a, as well as various signal wiring (buses) and a terminal group 311 including multiple connection terminals connected to the CGROM 206a via various buses.

[0245] The first to fourth connection terminals and the ninth and subsequent connection terminals in the terminal group 311 provided on the CGROM substrate 204a are connected to the CGROM 206a.

[0246] 12, since the CGROM 206a is a NOR flash memory (random access flash memory), the first to fourth connection terminals and the ninth to thirty-fourth connection terminals in the terminal group 311 are connected to input terminals (not shown) of the address bus of the CGROM 206a. The thirty-fifth and thirty-sixth connection terminals in the terminal group 311 are connected to CG memory chip enable input terminals (not shown) of the CGROM 206a, and the thirty-seventh and subsequent connection terminals are connected to data output terminals of the CGROM 206a that are used when the display control circuit 230 acquires image data (compressed data of moving images / still images) from the CGROM 206a.

[0247] Furthermore, the fifth connection terminal (predetermined connection terminal) in the terminal group 311 provided on the CGROM substrate 204a is connected to the eighth connection terminal via a signal wiring W2, and the eighth connection terminal is connected to a ground (GND) terminal provided on the CGROM substrate 204a. That is, if the CGROM 206a is a NOR flash memory, the fifth connection terminal is grounded via the signal wiring W2. Furthermore, the sixth and seventh connection terminals in the terminal group 311 are connected to a power supply voltage (+3.3V) terminal provided on the CGROM substrate 204a.

[0248] The number of connection terminals included in terminal group 311 is the same as the number of connection terminals in terminal group 303 for connecting a CGROM substrate, which is provided on sub-substrate 202. When connecting (mounting) CGROM substrate 204a to sub-substrate 202, the two substrates are connected so that the connection terminals of CGROM substrate 204a are connected to the connection terminals of sub-substrate 202 having the same terminal numbers. That is, as shown in Figure 12, the first connection terminal, second connection terminal, ..., 37th connection terminal, ... of CGROM substrate 204a are connected to the first connection terminal, second connection terminal, ..., 37th connection terminal, ... of sub-substrate 202, respectively.

[0249] (3) CGROM board (NAND type) configuration Next, the internal configuration of a CGROM substrate 204b equipped with a NAND-type CGROM 206b will be described with reference to Fig. 13. In the configuration of the CGROM substrate 204b shown in Fig. 13, the same components as those of the CGROM substrate 204a equipped with a NOR-type CGROM 206a shown in Fig. 12 are denoted by the same reference numerals.

[0250] When a NAND-type CGROM 206b is mounted on the CGROM substrate 204b, the CGROM substrate 204b is provided with the NAND-type CGROM 206b and a transistor circuit 312 as its peripheral circuit. The CGROM substrate 204b is also provided with various signal wirings (buses) and a terminal group 311 including a plurality of connection terminals directly or indirectly connected to the CGROM 206b via the various buses.

[0251] The first to fourth connection terminals in the terminal group 311 of the CGROM substrate 204b are connected to the drain terminal of the transistor circuit 312. The gate terminal of the transistor circuit 312 is connected to the CGROM 206b, and the source terminal is connected to a ground (GND) terminal provided on the CGROM substrate 204b. That is, the first to fourth connection terminals are connected to the CGROM 206b via the transistor circuit 312.

[0252] In the example shown in FIG. 13, since CGROM 206b is a NAND-type flash memory (sequential access flash memory), the gate terminal of the transistor circuit 312, i.e., the first to fourth connection terminals in the terminal group 311, are connected to a ready / busy output terminal (not shown) provided in CGROM 206b.

[0253] Furthermore, the fifth connection terminal (predetermined connection terminal) in the terminal group 311 of the CGROM substrate 204b is connected to the sixth and seventh connection terminals via the signal wiring W3, and the sixth and seventh connection terminals are connected to a power supply voltage (+3.3V) terminal provided on the CGROM substrate 204b. That is, if the CGROM 206b is a NAND-type flash memory, the fifth connection terminal is connected to the power supply voltage (+3.3V) terminal via the signal wiring W3.

[0254] Furthermore, the eighth connection terminal in the terminal group 311 of the CGROM substrate 204b is connected to a ground (GND) terminal provided on the CGROM substrate 204b.

[0255] Furthermore, the ninth connection terminal and subsequent connection terminals in the terminal group 311 of the CGROM substrate 204b are connected to the CGROM 206b. In this case, the ninth connection terminal to the thirty-fourth connection terminal are connected to input terminals (not shown) for address-related data provided in the CGROM 206b, and the thirty-fifth and thirty-sixth connection terminals are connected to CG memory chip enable input terminals provided in the CGROM 206b. In addition, the thirty-seventh connection terminal and subsequent connection terminals are connected to data output terminals (not shown) of the CGROM 206b used when the display control circuit 230 acquires image data (compressed data of moving images / still images) from the CGROM 206b.

[0256] Note that even when a NAND-type CGROM 206b is mounted on the CGROM substrate 204b, the number of connection terminals included in the terminal group 311 of the CGROM substrate 204b is the same as the number of connection terminals in the terminal group 303 for connecting the CGROM substrate provided on the sub-substrate 202. When connecting (mounting) the CGROM substrate 204b to the sub-substrate 202, the two substrates are connected so that the connection terminals of the CGROM substrate 204b are connected to the connection terminals of the sub-substrate 202 having the same terminal numbers. That is, as shown in Fig. 13, the first connection terminal, the second connection terminal, ..., the 37th connection terminal, ... of the CGROM substrate 204b are connected to the first connection terminal, the second connection terminal, ..., the 37th connection terminal, ... of the sub-substrate 202, respectively.

[0257] [Communication between the display control circuit and CGROM] Next, the operation of the display control circuit 230 when acquiring image data (compressed data of moving images / still images) from the CGROM will be described with reference to Figures 12 to 15. Note that Figure 14 is a truth table showing the correspondence between input signals and output signals in the AND circuit 302 provided on the sub-substrate 202, and Figure 15 is a truth table showing the correspondence between the signal levels applied to the control terminals OE and DIR of the bidirectional balanced transceiver 301 provided on the sub-substrate 202 and the communication direction.

[0258] (1) Operation of AND circuit and bidirectional balanced transceiver As shown in FIG. 14, the AND circuit 302 outputs a HIGH level signal to the control terminal OE of the bidirectional balanced transceiver 301 only when a HIGH level signal (voltage signal) is input to both input terminals, and outputs a LOW level signal to the control terminal OE under other input conditions.

[0259] 15, when a LOW level signal (voltage signal) is input to the control terminal OE and a LOW level signal is input to the control terminal DIR, the bidirectional balanced transceiver 301 causes the input / output terminals A0 to A3 of the bidirectional balanced transceiver 301 to function as output terminals and the input / output terminals B0 to B3 to function as input terminals. In this case, the communication direction between the display control circuit 230 and the CGROM is from the display control circuit 230 to the CGROM.

[0260] Furthermore, when a LOW level signal is input to the control terminal OE and a HIGH level signal is input to the control terminal DIR, the bidirectional balanced transceiver 301 causes the input / output terminals A0 to A3 of the bidirectional balanced transceiver 301 to function as input terminals and the input / output terminals B0 to B3 to function as output terminals. In this case, the communication direction between the display control circuit 230 and the CGROM is from the CGROM to the display control circuit 230.

[0261] Note that if the combination of the signal level input to the control terminal OE of the bidirectional balanced transceiver 301 and the signal level input to the control terminal DIR is other than the above combination, When a HIGH level signal is input to the control terminal OE of the bidirectional balanced transceiver 301, the input / output terminals A0 to A3 and the input / output terminals B0 to B3 of the bidirectional balanced transceiver 301 are in a HIGH impedance state ("Z" in FIG. 15), i.e., a state equivalent to an open state, and no communication takes place between the display control circuit 230 and the CGROM.

[0262] (2) Communication between the display control circuit and CGROM (NOR type) First, consider the case where a CGROM board 204a on which a NOR type CGROM 206a is mounted is connected (mounted) to the sub-board 202.

[0263] In this case, in this embodiment, a LOW level signal is output from at least one of the two CG memory chip enable output terminals GCE_0, GCE_1 of the display control circuit 230, and therefore a LOW level signal is input to the control terminal OE of the bidirectional balanced transceiver 301. Note that the signal levels of the CG memory chip enable output terminals GCE_0, GCE_1 are set in the hardware initialization process (see FIG. 38 described later).

[0264] In this embodiment, the amplitude value of the output signal from the CG memory chip enable output terminals GCE_0, GCE_1 (specific terminals), which is set in advance by the sub-control circuit 200, differs depending on the type of CGROM, and therefore the amplitude value of the signal output from the CG memory chip enable output terminals GCE_0, GCE_1 provided in the display control circuit 230 changes depending on the type of storage means. However, the aspect in which "the amplitude value of the output signal changes depending on the type of CGROM" is not limited to this aspect. As will be described in Modification 7 below, the display control circuit 230 may detect the type of storage means connected and set the amplitude value of the signal output from the CG memory chip enable output terminals GCE_0, GCE_1 (specific terminals) based on the detection result.

[0265] In addition, the fifth connection terminal of the sub-board 202, to which the control terminal DIR of the bidirectional balanced transceiver 301 is connected, is grounded via the fifth connection terminal of the CGROM board 204a and the signal wiring W2, as shown in Figure 12, so that a LOW level signal is input to the control terminal DIR.

[0266] Therefore, when the CGROM board 204a equipped with the NOR type CGROM 206a is connected to the sub-board 202, the input / output terminals A0 to A3 of the bidirectional balanced transceiver 301 function as output terminals, and the input / output terminals B0 to B3 function as input terminals, as shown in Fig. 15. That is, the communication direction between the display control circuit 230 and the CGROM 206a in the bidirectional balanced transceiver 301 is from the display control circuit 230 to the CGROM 206a.

[0267] In this case, the signal wiring connected via the first to fourth connection terminals of the sub-substrate 202 and the first to fourth connection terminals of the CGROM substrate 204a can be used as an address bus, and the display control circuit 230 can properly perform memory addressing operations on the NOR type CGROM 206a. As a result, the display control circuit 230 can directly perform addressing via the address bus and perform data read operations.

[0268] (3) Communication between the display control circuit and CGROM (NAND type) Next, a case where a CGROM board 204b on which a NAND type CGROM 206b is mounted is connected (mounted) to the sub-board 202 will be considered.

[0269] Even in this case, in this embodiment, a LOW-level signal is output from at least one of the two CG memory chip enable output terminals CGE_0, CGE_1 of the display control circuit 230, and therefore a LOW-level signal is input to the control terminal OE of the bidirectional balanced transceiver 301. That is, in this embodiment, whether the CGROM type is NOR type or NAND type, a LOW-level signal is input to the control terminal OE of the bidirectional balanced transceiver 301. Furthermore, the fifth connection terminal of the sub-substrate 202 to which the control terminal DIR of the bidirectional balanced transceiver 301 is connected is connected to the power supply voltage (+3.3V) terminal via the fifth connection terminal of the CGROM substrate 204b and the signal wiring W3, as shown in FIG. 13, and therefore a HIGH-level signal is input to the control terminal DIR.

[0270] Therefore, when a CGROM board 204b equipped with a NAND-type CGROM 206b is connected to the sub-board 202, the input / output terminals A0 to A3 of the bidirectional balanced transceiver 301 function as input terminals, and the input / output terminals B0 to B3 function as output terminals, as shown in Fig. 15. That is, the communication direction between the display control circuit 230 and the CGROM 206b in the bidirectional balanced transceiver 301 is from the CGROM 206b to the display control circuit 230.

[0271] In this case, the signal wiring connected via the first to fourth connection terminals of the sub-substrate 202 and the first to fourth connection terminals of the CGROM substrate 204b can be used as communication wiring for ready / busy signals. That is, in this case, it becomes possible to execute a process of transmitting the ready / busy signal, which the display control circuit 230 references when reading data from the NAND-type CGROM 206b using the sequential access method, from the CGROM 206 to the display control circuit 230. As a result, the display control circuit 230 can properly execute an operation of acquiring the memory status (ready / busy status) of the NAND-type CGROM 206b.

[0272] As described above, in this embodiment, even if the type of CGROM is changed, communication between the display control circuit 230 and the CGROM can be performed normally without changing the configuration of the sub-board 202. Therefore, in this embodiment, the optimal CGROM can be selected taking into consideration, for example, data capacity, communication speed, price, etc. Furthermore, for example, when manufacturing a new pachinko gaming machine 1, it is possible to easily accommodate a case where the sub-board 202 used in a previously manufactured pachinko gaming machine is reused and only the type of CGROM is changed based on conditions such as data capacity and communication speed. In other words, in the pachinko gaming machine 1 of this embodiment, it is possible to select a CGROM according to the implementation, thereby ensuring the expandability of the pachinko gaming machine 1.

[0273] Furthermore, in this embodiment, by using bidirectional balanced transceiver 301, the first to fourth connection terminals in terminal group 303 of sub-substrate 202 and the first to fourth connection terminals in terminal group 311 of CGROM substrate 204 can be used as data input / output terminals. In this case, there is no need to separately provide data input and output terminals corresponding to the first to fourth connection terminals of sub-substrate 202 and CGROM substrate 204, and space saving of sub-substrate 202 and CGROM substrate 204 can be achieved.

[0274] As described above, in this embodiment, the "communication format" between the display control circuit 230 and the CGROM can be switched depending on the type of CGROM by the bidirectional balanced transceiver 301. However, in this specification, the "communication format" between the display control circuit 230 and the CGROM refers to the overall manner in which various types of information are transmitted and received between the display control circuit 230 and the CGROM.

[0275] For example, the "communication format" between the display control circuit 230 and the CGROM in this specification includes data (image data) required for displaying information about performance actions on the display device 13. This not only refers to the manner in which data (compressed data of moving images / still images) is transmitted and received between the display control circuit 230 and the CGROM, but also includes the manner in which information specifying the address of the data stored in the CGROM is communicated between the display control circuit 230 and the CGROM, and the manner in which the display control circuit 230 receives a ready / busy signal from the CGROM. Note that the present invention is not limited to this, and the "communication form" referred to in this specification may refer only to the communication form of the part in which the manner in which information is transmitted and received changes depending on the type of CGROM.

[0276] <Type of game state> Next, the types of game states controlled and managed by the main CPU 71 will be described.

[0277] In this embodiment, the types of game states controlled and managed by the main CPU 71 include a "jackpot game state" (special game state) and a "small jackpot game state" (specific game state), which have different expectations for winning prize balls. The "jackpot game state" is a game state in which a round game occurs in which the shutter of the first large prize opening 53 or the second large prize opening 54 is open for a long period (i.e., the period of one round) (e.g., 30 seconds), and is a game state in which the player can expect to win a large prize ball. In other words, in the "jackpot game state," the repeated open and closed states of the shutter of the large prize opening are advantageous to the player.

[0278] On the other hand, the "small win game state" is a game state in which round games occur with a shorter duration (for example, 1.8 seconds) than the "big win game state," and is a game state in which the player cannot expect to win a large prize ball. In other words, in the "small win game state," the repeated opening and closing of the shutter of the big prize opening puts the player in a disadvantageous state.

[0279] In addition, in this embodiment, the types of game states controlled and managed by the main CPU 71 include a "high probability game state" (high probability game state) and a "normal game state" (low probability game state), which have different probabilities of winning a "jackpot."

[0280] The "probability variable game state" is a game state in which the probability of winning a "jackpot" (1 / 131 in this embodiment) is high. On the other hand, the "normal game state" is a game state in which the probability of winning a "jackpot" (1 / 392 in this embodiment) is lower than that in the "probability variable game state."

[0281] Furthermore, in this embodiment, the types of game states controlled and managed by the main CPU 71 include a "time-saving game state" (high prize game state) and a "non-time-saving game state" (low prize game state), which have different winning probabilities for normal symbols (probability that a normal symbol will become a "win").

[0282] As used herein, the term "time-saving game state" refers to a game state in which the probability of winning a normal symbol is high. In other words, the "time-saving game state" is a game state in which the normal electric device 46 (the blade member) installed in the second starting hole 45 is likely to open (a game state in which a second starting hole win is likely to occur), and is therefore advantageous to the player. The "time-saving game state" ends when a "jackpot" is determined or when the variable display of special symbols has been executed a predetermined number of times for the time-saving game, as described below. Furthermore, in the time-saving game state, the variable display time for the variable display of special symbols executed during the time-saving game state may be controlled so that a variable time shorter than the variable time selected during the normal game state is more likely to be selected. By using such control, the variable time during the time-saving game state may be shortened compared to the normal game state, thereby increasing the number of games per unit time and providing a game state advantageous to the player.

[0283] On the other hand, the "non-time-saving (no time-saving) game state" is a game state in which the probability of winning a normal symbol is lower than in the "time-saving game state." Therefore, the "non-time-saving game state" is a game state in which the normal electric device 46 (the blade member) is unlikely to be opened (a game state in which the second starting hole winning is unlikely to occur), and is a game state that is disadvantageous to the player.

[0284] In this embodiment, various combinations of the above-mentioned game states other than the "big win game state" and the "small win game state" are provided. Specifically, in this embodiment, a game state in which the "probability variable game state" and the "time-shortened game state" occur simultaneously (hereinafter referred to as a "state with high probability time-shortened"), and a game state in which the "probability variable game state" and the "non-time-shortened game state" occur simultaneously are provided. (hereinafter referred to as a "state without high-probability time reduction") is provided. In the "state without high-probability time reduction", it is difficult for the player to determine whether the gaming state is a "probability variable gaming state", so here, such a gaming state is also referred to as a "potentially probable gaming state". In addition, in this embodiment, a gaming state in which a "normal gaming state" and a "non-time-reduction gaming state" occur simultaneously (hereinafter referred to as a "state without low-probability time reduction"), and a gaming state in which a "normal gaming state" and a "time-reduction gaming state" occur simultaneously (hereinafter referred to as a "state with low-probability time reduction") are also provided.

[0285] <Data table configuration stored in main ROM> Next, the configurations of various data tables stored in the main ROM 72 of the main control circuit 70 will be described with reference to FIGS.

[0286] [Jackpot Random Number Judgment Table (When the first starting gate is entered)] First, the jackpot random number determination table (when the first starting hole is entered) will be described with reference to Fig. 16. The jackpot random number determination table (when the first starting hole is entered) is a table in which the game ball enters the first starting hole 44. This is a table that is referenced when determining by lottery whether a prize is awarded based on the random number value for determining a jackpot obtained when the prize is awarded.

[0287] The random number value for determining a jackpot is a random number value for determining the result of a lottery that is held when a winning jackpot is entered into the starting slot, and more specifically, is a random number value that indicates the result of a lottery for special symbols (first special symbol and second special symbol). In this embodiment, the random number value for determining a jackpot (random number value for a lottery for special symbols) is selected from 0 to 65535 (65536 types).

[0288] In this embodiment, when a gaming ball enters the first starting slot 44, a "jackpot," a "small jackpot," or a "miss" is determined by lottery. Therefore, as shown in FIG. 16, the jackpot random number determination table (when the ball enters the first starting slot) defines the relationship between the range of jackpot determination random numbers for determining whether a "jackpot," a "small jackpot," or a "miss" is won, and the corresponding determination value data (either "jackpot determination value data," "small jackpot determination value data," or "miss determination value data") for each value of the probability variable flag ("0 (= off)" or "1 (= on)"). The probability variable flag is one of the management flags stored in the main RAM 73 and is a flag for managing whether the gaming state is a "probability variable gaming state." When the gaming state is a "probability variable gaming state," the determination flag is set to "1."

[0289] In this embodiment, as shown in Fig. 16, when the first starting hole 44 is entered, if the probability variable flag is "0" and the random number value for jackpot determination is any one of "777" to "943", a "jackpot" is won and "jackpot determination value data" is determined. That is, the winning probability of the "jackpot" in this case ("selection rate" in Fig. 16) is 167 / 65536.

[0290] Also, when the first starting hole 44 is entered, if the probability variable flag is "0" and the random number value for determining the big win is any of "1" to "300", the "small win" is won and the "small win determination value data" is determined. That is, the winning probability of the "small win" in this case is 300 / 65536.

[0291] Furthermore, when the first starting port 44 is won, if the probability flag is "0" and the random number value for determining a jackpot is neither "1" to "300" nor "777" to "943", a "miss" is won and the "miss determination value data" is determined.

[0292] On the other hand, when the first starting slot 44 is entered, if the probability variable flag is "1" and the random number value for jackpot determination is any one of "777" to "1277", a "jackpot" is won and the "jackpot determination value data" is determined, as shown in Fig. 16. That is, the winning probability of the "jackpot" in this case ("selection rate" in Fig. 16) is 500 / 65536, which is higher than when the probability variable flag is "0".

[0293] Also, when the first starting hole 44 is entered, if the probability variable flag is "1" and the random number value for determining the big win is any one of "1" to "300", the "small win" is won and the "small win determination value data" is determined. In other words, the winning probability of the "small win" in this case is 300 / 65536, which is the same as when the probability variable flag is "0".

[0294] Furthermore, when the first starting port 44 is won, if the probability flag is "1" and the random number value for determining a jackpot is neither "1" to "300" nor "777" to "1277", a "miss" is won and the "miss determination value data" is determined.

[0295] As described above, in this embodiment, when a gaming ball enters the first starting hole 44, the selection rate (jackpot probability) varies depending on whether the gaming state at the time of the winning is a "probability variable gaming state." Specifically, the jackpot probability when a gaming ball enters the first starting hole 44 when the gaming state is a "probability variable gaming state" is about three times higher than when the gaming state is not a "probability variable gaming state."

[0296] [Jackpot Random Number Judgment Table (When Winning at the Second Starting Port)] Next, the jackpot random number determination table (when the ball enters the second starting hole) will be described with reference to Fig. 17. The jackpot random number determination table (when the ball enters the second starting hole) is This is a table that is referenced when a lottery is conducted to determine whether or not a "jackpot" has been won based on the random number value for jackpot determination obtained when a prize is won.

[0297] In this embodiment, when a gaming ball enters the second starting port 45, either a "jackpot" or a "miss" is determined by lottery. Note that when a gaming ball enters the second starting port 45, a "small jackpot" is not won. Therefore, as shown in FIG. 17, the jackpot random number determination table (when a gaming ball enters the second starting port) specifies the relationship between the range of jackpot determination random numbers that determine whether a "jackpot" or a "miss" has been won, and the corresponding determination value data (either "jackpot determination value data" or "miss determination value data") for each value of the probability variable flag ("0 (= off)" or "1 (= on)").

[0298] In this embodiment, as shown in Fig. 17, when the second starting hole 45 is entered, if the probability variable flag is "0" and the random number value for jackpot determination is any one of "777" to "943", the "jackpot" is won and the "jackpot determination value data" is determined. That is, the winning probability of the "jackpot" in this case ("selection rate" in Fig. 17) is 167 / 65536.

[0299] Also, when the second starting port 45 is won, if the probability flag is "0" and the random number value for determining a jackpot is not between "777" and "943", a "miss" is won and the "miss determination value data" is determined.

[0300] On the other hand, when the second starting port 45 is entered, if the probability variable flag is "1" and the random number value for jackpot determination is any of "777" to "1277", a "jackpot" is won and the "jackpot determination value data" is determined, as shown in Figure 17. In other words, the winning probability of the "jackpot" in this case (jackpot probability) is 500 / 65536, which is higher than when the probability variable flag is "0".

[0301] Also, when the second starting port 45 is won, if the probability flag is "1" and the random number value for determining a jackpot is not between "777" and "1277", it is considered a "miss" and the "miss determination value data" is determined.

[0302] As described above, in this embodiment, even when a game ball enters the second starting hole 45, the selection rate (jackpot probability) also varies depending on whether the game state at the time of entry is a "probability variable game state." Specifically, similar to when a game ball enters the first starting hole 44, when a game ball enters the second starting hole 45, the jackpot probability when the game state is a "probability variable game state" is about three times higher than when the game state is not a "probability variable game state."

[0303] [Pattern determination table (when winning the first starting gate)] Next, the symbol determination table (when winning at the first starting slot) will be described with reference to FIG.

[0304] In this embodiment, a special symbol is selected based on the winning type ("big hit," "small hit," or "miss") of a lottery based on a random number value for determining a big hit that is held when a gaming ball enters the first starting hole 44, and the symbol random number value (random number value for determining a symbol) obtained when the ball enters the first starting hole. The symbol determination table (when the ball enters the first starting hole) is a table that is referenced when selecting the special symbol. The symbol random number value is a random number value for determining the special symbol, and is selected from 0 to 99 (100 types), regardless of the winning type of the lottery based on the random number value for determining a big hit.

[0305] As shown in Figure 18, the pattern determination table (when the first starting port is won) specifies the relationship between the pattern designation command ("zA1" to "zA3") for designating a special pattern and the pattern random number value from which the pattern designation command is selected, for each determination value data indicating the type of winning in the lottery based on the random number value for determining a jackpot.

[0306] Furthermore, when the winning type of the lottery based on the random number value for determining a jackpot is a "small win" (small win determination value data), there is only one type of symbol designation command (zA2) to be selected, and that symbol designation command (zA2) is always determined. Also, when the winning type of the lottery based on the random number value for determining a jackpot is a "loss" (loss determination value data), there is only one type of symbol designation command (zA3) to be selected, and that symbol designation command (zA3) is always determined.

[0307] On the other hand, when the winning type of the lottery based on the random number value for determining a jackpot is a "jackpot" (jackpot determination value data), as shown in FIG. 18, there are multiple types of special symbols to select, and multiple types ("z0" to "z4") of symbol designation commands for a "jackpot" (jackpot selection symbol command in FIG. 18) are also prepared. Then, when a "jackpot" occurs, the jackpot selection symbol command to be determined changes depending on the symbol random number value obtained. For example, when the symbol random number value obtained at the time of a "jackpot" is one of "40" to "59," the jackpot selection symbol command "z2" is selected, and its selection rate is 20 / 100.

[0308] [Pattern determination table (when winning the second starting gate)] Next, the symbol determination table (when winning at the second starting port) will be described with reference to FIG.

[0309] In this embodiment, the special symbol is selected based on the winning type ("jackpot" or "loss") of the lottery based on the random number value for jackpot determination that is performed when the gaming ball enters the second starting hole 45, and the symbol random number value (random number value for symbol determination) obtained when the ball enters the second starting hole. The symbol determination table (when the ball enters the second starting hole) is a table that is referenced when selecting the special symbol.

[0310] As shown in Figure 19, the pattern determination table (when the ball enters the second starting port) specifies the relationship between the pattern designation commands ("zA1" and "zA3") for designating special patterns and the pattern random number value from which the pattern designation command is selected, for each determination value data indicating the type of winning in the lottery based on the random number value for determining a jackpot.

[0311] Furthermore, even if the winning type of the lottery based on the random number value for determining a jackpot is "miss" (miss determination value data), only one type of pattern designation command (zA3) is selected, and that pattern designation command (zA3) is always determined.

[0312] On the other hand, when the winning type of the lottery based on the random number value for determining a jackpot is a "jackpot" (jackpot determination value data), as shown in FIG. 19, there are multiple types of special symbols to select, and multiple types ("z0" and "z4") of symbol designation commands for a "jackpot" (jackpot selection symbol command in FIG. 19) are also prepared. Then, when a "jackpot" occurs, the jackpot selection symbol command to be determined changes depending on the symbol random number value obtained. For example, when the symbol random number value obtained at the time of a "jackpot" is between "29" and "99," the jackpot selection symbol command "z4" is selected, and its selection rate is 80 / 100.

[0313] [Jackpot type determination table] Next, the jackpot type determination table will be described with reference to Figures 20 to 23. In this embodiment, when a jackpot selection symbol command (any of "z0" to "z4") is determined with reference to the symbol determination table (see Figures 18 and 19), the type of "jackpot" (contents of the jackpot game) is determined based on the determined jackpot selection symbol command. The jackpot type determination table is a table that is referenced when determining the type of "jackpot" (contents of the jackpot game) based on the jackpot selection symbol command.

[0314] In this embodiment, a jackpot type determination table is provided for each game state when a "jackpot" is won. Fig. 20 is a jackpot type determination table (part 1) that is referenced when a "jackpot" is won when the game state is "without low-probability time reduction," and Fig. 21 is a jackpot type determination table (part 2) that is referenced when a "jackpot" is won when the game state is "with low-probability time reduction." Also, Fig. 22 is a jackpot type determination table (part 3) that is referenced when a "jackpot" is won when the game state is "without high-probability time reduction," and Fig. 23 is a jackpot type determination table (part 4) that is referenced when a "jackpot" is won when the game state is "with high-probability time reduction."

[0315] Each jackpot type determination table defines the relationship between the jackpot selection command ("z0" to "z4") and various parameters that determine the type of "jackpot." The various parameters that determine (the content of the jackpot game) include the value of the time-saving flag, the number of time-saving times, the value of the probability change flag, and the number of rounds in the jackpot game.

[0316] For example, if a "jackpot" is won in a "high probability time-saving" state and "z1" is determined as the pattern command to be selected at the time of the jackpot, the various parameters that determine the type of "jackpot" (the content of the jackpot game) are set to the time-saving flag "1", the number of time-saving times "100", the probability flag "0", and the number of rounds "10", as shown in Figure 23.

[0317] The "number of rounds" specified in each jackpot type determination table is the number of rounds in which the opening time of the jackpot slot becomes relatively long during the jackpot game. The "time-saving flag" is one of the management flags stored in the main RAM 73, and is a flag for managing whether the game state is in the "time-saving game state." When the game state is in the "time-saving game state," the time-saving flag becomes "1 (ON)." The "number of time-saving times" is the number of times the variable display of the special symbol given in the "time-saving game state."

[0318] [Winning performance information determination table] Next, the winning effect information determination table will be described with reference to FIG.

[0319] In this embodiment, the main control circuit 70 (main CPU 71) determines information that the sub-control circuit 200 uses to determine the content of the presentation, based on the type of win ("big win," "small win," or "miss") determined at the time of winning (when the ball enters the starting hole) and the symbol designation command or the symbol selection command at the time of winning. For example, the sub-control circuit 200 determines information that will be used when determining the content related to the color change presentation of reserved symbols that indicate reserved balls with special symbols, the content related to the pre-reading presentation, etc. The presentation information determination table at the time of winning is a table that is referenced when determining the outline of the presentation content to be executed by the sub-control circuit 200, based on the information acquired by the main control circuit 70 at the time of winning (when the ball enters the starting hole).

[0320] The winning performance information determination table defines the relationship between the combination of various information determined at the time of winning (at the time of winning the starting hole) and "winning performance information 1" and "winning performance information 2" that show an outline of the performance content executed by the sub-control circuit 200. In this embodiment, the winning performance information determination table defines the type of starting hole, the type of judgment value data, the type of symbol selection command at the time of big win, and the type of symbol designation command as various information determined at the time of winning (at the time of winning the starting hole).

[0321] The winning effect information 1 ("1A" to "1D") defined in the winning effect information determination table is effect information that is mainly used by the sub-control circuit 200 when determining the content related to the color change effect of reserved symbols that indicate reserved balls with special symbols. When the sub-control circuit 200 receives the winning effect information 1 determined based on the winning effect information determination table, the sub-control circuit 200 selects one effect pattern from a plurality of effect patterns related to the color change effect of reserved symbols included in the classification of the winning effect information 1.

[0322] Furthermore, the winning effect information 2 ("2A" to "2D") defined in the winning effect information determination table is effect information that is used by the sub-control circuit 200 when determining the content of the look-ahead effect (look-ahead continuous effect) based on reserved balls with special symbols. When the sub-control circuit 200 receives the winning effect information 2 determined based on the winning effect information determination table, the sub-control circuit 200 selects one effect pattern from the multiple look-ahead effect patterns included in the classification of the winning effect information 2.

[0323] When referring to the winning performance information determination table of this embodiment, for example, when a "jackpot" is won when the first starting slot is won, "1A" is determined as winning performance information 1, and "2A" is determined as winning performance information 2, regardless of the type of jackpot selection symbol command.

[0324] [Variation effect pattern determination table] Next, the variable effect pattern determination table will be described with reference to FIG.

[0325] In this embodiment, when the variable display of the special symbol starts, the main control circuit 70 (main CPU 71) determines the variable presentation pattern of the special symbol based on information such as the type of win ("big win", "small win", or "miss"), the symbol designation command, the symbol selection command at the time of big win, the variable presentation time, etc. The variable presentation pattern determination table is a table that is referenced when determining the variable presentation pattern of this special symbol.

[0326] The variable effect pattern determined based on the variable effect pattern determination table (information included in the special symbol effect start command described later) is transmitted from the main control circuit 70 to the sub-control circuit 200 (host control circuit 210). Then, when the sub-control circuit 200 receives the information on the variable effect pattern, it determines the type of effect based on the received information on the variable effect pattern, the game status, etc.

[0327] As shown in Figure 25, the variable presentation pattern determination table specifies the relationship between the combination of the pattern designation command, jackpot selection pattern command, and special pattern variation time that is determined at the time of winning (when the ball enters the starting hole), and the type of presentation (variable presentation pattern) that is executed by the sub-control circuit 200 while the special pattern is being displayed.

[0328] In this embodiment, the variable presentation pattern is represented by a two-digit number, and is expressed as a combination of a "higher" (first digit) parameter and a "lower" (second digit) parameter described in the variable presentation pattern column in Fig. 25. For example, if the symbol designation command determined at the time of winning (at the time of winning at the starting port) is "zA1", the jackpot selection symbol command is "z0", and the variable time of the special symbol is "15000 msec", the variable presentation parameter will be "C1" (a combination of the higher "C" and the lower "1").

[0329] In this embodiment, the information on the variable performance parameters is included in the special symbol performance start command described later. At this time, the "higher" parameters and the "lower" parameters specified in the variable performance pattern column are stored in different parameter areas. Therefore, in the variable performance pattern determination table, the "higher" parameters and the "lower" parameters of the variable performance pattern are separately specified.

[0330] <Data table configuration stored in the sub-main ROM> Next, the configuration of various data tables stored in the sub-main ROM 205 of the sub-control circuit 200 will be described with reference to FIG.

[0331] [Variable performance table] First, the variable effect table will be described with reference to FIG.

[0332] In the pachinko gaming machine 1 of this embodiment, as described above, various effects are executed during the variable display of the special symbols under the control of the sub-control circuit 200 (host control circuit 210). The content of the effect (effect pattern) executed at this time is determined based on information on the variable effect pattern of the special symbols included in the special symbol effect start command (described later) sent from the main control circuit 70 to the sub-control circuit 200 when the variable display of the special symbols starts. The variable effect table stores the content of this effect. This is referenced when determining the (presentation pattern) based on information such as the variable presentation pattern and game status.

[0333] As shown in Fig. 26, the variable effect table defines a correspondence relationship between a combination of various information (including information on variable effect patterns) determined at the time of winning (at the time of winning in the starting port), the effect patterns ("EN00" to "EN44") and effect contents determined by lottery, and the random number values ​​and selection rates (probabilities of winning) for selecting (determining) each effect pattern. In this embodiment, the variable effect table defines, as various information determined at the time of winning (at the time of winning in the starting port), the types of variable effect patterns of special symbols ("A0" to "A4", "B1" to "B3", and "C1" to "CF"), the variation time of special symbols, the type of winning ("jackpot", "small hit", or "miss"), the symbol designation command, and the symbol selection command at the time of jackpot.

[0334] In this embodiment, the variation time of the special symbol specified in the variation effect table is approximately the same as the variation time of the corresponding effect pattern. Also, the random number value specified in the variation effect table is a random number value obtained by the sub-lottery process and is one of "0" to "999" (1000 types).

[0335] When the effect pattern is determined by referring to the variable effect table of this embodiment, for example, if the variable special symbol pattern determined at the start of the variable special symbol display is "C1" and the random number value acquired when selecting the effect pattern is any value between "0" and "499", then "EN15" is selected as the effect pattern. In this case, during the variable special symbol display period (15000 msec), an effect called "normal reach effect A" is performed. Then, upon completion of the "normal reach effect A", a "jackpot" mode is displayed in the display area 13a of the display device 13, and the special symbol stops varying.

[0336] <Outline of drawing control method> Next, an outline of the drawing process executed by the display control circuit 230 when a drawing request is output from the host control circuit 210 to the display control circuit 230 will be described with reference to Fig. 27. Fig. 27 is a diagram showing the flow of image data (moving image data and still image data) during the drawing process.

[0337] In this embodiment, data (compressed data) of images (moving images and / or still images) to be displayed on the liquid crystal screen of the display device 13 is stored in a CGROM 206 in a CGROM board 204. When a drawing request is input to the display control circuit 230, the display control circuit 230 first reads and decodes (expands) the compressed image data from the CGROM 206. At this time, if compressed moving image data is read, the compressed moving image data is decoded by a moving image decoder 234 in the display control circuit 230, and if compressed still image data is read, the compressed still image data is decoded by a still image decoder 235 in the display control circuit 230.

[0338] Next, the display control circuit 230 writes the decoded result of the image data (decompressed image data) to a predetermined buffer designated as a texture source. In this embodiment, a movie buffer or texture buffer provided in the SDRAM 250 (external RAM) or a sprite buffer in the built-in VRAM 237 is designated as the texture source. For example, when displaying one video, the decompressed video data (decoded result) is written to the movie buffer in the SDRAM 250. Also, when displaying one still image, the decompressed still image data is written to the sprite buffer in the built-in VRAM 237.

[0339] Next, the display control circuit 230 specifies a rendering target to which the rendering (drawing) results of the image data are written. Note that the rendering target may be, for example, a frame buffer provided in the SDRAM 250 (external RAM) or a frame buffer provided in the built-in VRAM 237.

[0340] Next, the display control circuit 230 activates the rendering engine 241 to perform rendering processing on the decoded result of the image data written to the texture source, and writes the rendering result to the rendering target. Note that this rendering processing is performed in accordance with specification information (various information input from the 3D geometry engine 240) such as the scaling and rotation of the video.

[0341] Next, the display control circuit 230 displays the rendering result (display output data) written to the rendering target on the display screen of the display device 13.

[0342] In this embodiment, two frame buffers are prepared as rendering targets. When the rendering engine 241 writes rendering results to the frame buffers, the frame buffer to which the rendering results are written is switched for each frame. For example, if the rendering results are written to one frame buffer in a given frame, the rendering results are written to the other frame buffer in the next frame, and the rendering results are written to one frame buffer in the frame after that. In other words, in this embodiment, the process of writing the rendering results to one frame buffer and the process of writing the rendering results to the other frame buffer are alternately switched for each frame.

[0343] Furthermore, in the flow of the above-described rendering result writing process and display process, the rendering result written to one frame buffer in a given frame is displayed on the display screen of the display device 13 in the next frame (the function of one frame buffer is switched from the drawing function to the display function). Also, the rendering result written to the other frame buffer in the next frame is displayed on the display screen of the display device 13 in the frame after that (the function of the other frame buffer is switched from the drawing function to the display function). That is, in this embodiment, the display process of the rendering result in one frame buffer and the display process of the rendering result in the other frame buffer are alternately switched and executed for each frame.

[0344] <Outline of audio playback control method> Next, referring back to FIG. 8, an outline of the sound reproduction process executed by the audio / LED control circuit 220 when a sound request is output from the host control circuit 210 to the audio / LED control circuit 220 will be described.

[0345] In this embodiment, the audio data to be output to the speaker 11 is stored in the CGROM 206. The audio data stored in the CGROM 206 is compressed phrase data identified by a 13-bit phrase number NUM (000H to 1FFFH), and up to 8192 types (=213) of a series of background music (BGM) or a collection of sound effects (preview sounds) are stored, each corresponding to a phrase number NUM. The phrase number NUM is identified by a setting value (operation parameter) of an audio command transmitted from the host control circuit 210 to the command register 225 of the audio / LED control circuit 220.

[0346] The voice command is used for either an Individual Write purpose, which transmits a one-byte setting value to one of the many voice control registers built into the voice / LED control circuit 220, or a Block Write purpose, which transmits a group of N setting values ​​to a series of N consecutive voice control registers.

[0347] In either case, the audio control register to be accessed is specified by a 1-byte register address, and each audio control register has a storage capacity of 1 byte. In this embodiment, a large number of audio control registers are allocated by dividing the register banks into seven. In other words, since the register banks are divided into seven, the total number of audio control registers can theoretically be up to 7 x 256.

[0348] In this embodiment, in all register banks, a specific register address is the voice control register for register bank setting. Therefore, to specify one of the 7 x 256 voice control registers, the register bank is written to the voice control register for bank setting by the preceding voice command, and then the voice control register belonging to that register bank is specified by a 1-byte register address.

[0349] Incidentally, the operation of setting values ​​to audio control registers does not necessarily require directly specifying the register address of the audio control register to be set, but a series of setting operations for a group of audio control registers can also be completed by specifying SAC data (Simple Access Code Data) or sequence code (Sequence Code) stored in CGROM 206. To achieve this operation, the audio / LED control circuit 220 has four simple access controllers 226a and 16 sequencers 226b (Sequencers) built in, as shown in Fig. 8.

[0350] To explain the SAC (Simple Access Code) data for making the simple access controller 226a function, the SAC data is a set of up to 512 pairs of register addresses (1 byte) of audio control registers corresponding to the set values ​​(1 byte) for the audio control registers. It is a data group of 1024 bytes (=1024 bytes) and refers to a collection terminated with the SAC end code (FFFFH) (see Figure 8).

[0351] In this embodiment, a maximum of 8192 (=213) types of such SAC data can be provided, and the host control circuit 210 can activate the simple access controller 226a by writing a 13-bit SAC number to an audio control register (see FIG. 8) for SAC control. Once the simple access controller 226a has started functioning, it sequentially reads out a group of SAC data specified by the SAC number from the CGROM 206, and sets the setting value indicated by the SAC data in the audio control register indicated by the SAC data.

[0352] Therefore, the host control circuit 210 only needs to write (register) the SAC number in the audio control register for SAC control, and can instruct a series of setting operations without individually specifying the register addresses of the audio control registers. Note that a waiting time (waiting information as ancillary data) that specifies the start timing of the series of setting operations can also be set in the audio control register for SAC control, and the timing at which the simple access controller 226a starts setting the audio control register can be delayed from the timing at which the SAC number is written to the audio control register for SAC control.

[0353] Next, we will explain the sequence code (Sequence Code) that causes the sequencer 226b to function. Like the SAC data, the sequence code is a set of data that associates the register address (1 byte) of an audio control register with the setting value (1 byte) for that audio control register (see FIG. 8). However, unlike the SAC data, the sequence code can specify a number of operation steps (a number of sequence steps) that can be executed intermittently after a predetermined waiting time has elapsed.

[0354] The audio control register for controlling the sequencer can contain information about the waiting time (waiting information) that determines the start timing of the set operation for each sequencer SQ0 to SQ15, whether or not the operation is repeated, and the number of times it is repeated (loop information). Therefore, the sequence code specifies a series of audio effects that take a predetermined time to be executed.

[0355] 8, a plurality of operation steps are separated by a step end code (FFFEH), and the end of a plurality of operation steps is terminated by a sequence end code (FFFFH). In this embodiment, a maximum of 8192 (=213) types of sequence codes can be provided, and the host control circuit 210 can instruct the sequencer 226b to perform a series of setting operations by writing a 13-bit sequence code number and additional data that specifies the operation of the sequencer to an audio control register for controlling the sequencer.

[0356] In this embodiment, only the necessary sets of such SAC data and sequence codes are stored in advance in the CGROM 206, and a group of SAC data or a group of sequence codes is identified by a SAC number or a sequence code number. Therefore, in this embodiment, voice commands for write use include not only cases in which direct setting operations to voice control registers are specified, but also cases in which indirect setting operations via the simple access controller 226a or the sequencer 226b are specified.

[0357] To achieve the above operation, the host control circuit 210 and the audio / LED control circuit 220 are connected by a parallel signal line (data bus) capable of sending and receiving 1 byte of data, a 2-bit operation management data line (address bus) capable of sending operation management data, a 2-bit control signal line capable of controlling read / write operations, and a chip select signal line that selects the audio / LED control circuit 220.

[0358] The parallel signal lines are realized by the data bus of the host control circuit 210, and the operation management data lines are realized by the address bus of the host control circuit 210. The sound / LED control circuit 220 is assigned three port numbers PORT, with the upper six bits being common and the lower two bits being 00, 01, and 10, and the circuit is configured so that when the host control circuit 210 executes an I / OREAD command or an I / OWRITE command for these port numbers PORT, the chip select signal CS becomes active in either case.

[0359] When the I / OREAD or I / OWRITE command is executed, the data output to the lowest two bits A0-A1 of the address bus becomes operation control data A0-A1 for the sound / LED control circuit 220, and based on these two bits A0-A1, it is possible to determine whether the 1 byte of data on the data bus at that time is a register address or write data or read data.

[0360] That is, if the address data is

[00] , the data on the data bus at that timing is evaluated as a register address, while if the address data is

[01] , the data on the data bus at that timing is either write data or read data. Note that when an I / OREAD instruction is executed, the data is read, and when an I / OWRITE instruction is executed, the data is written.

[0361] Therefore, the operation of transmitting a voice command that writes a predetermined setting value to a predetermined voice control register is realized by successively executing the I / OWRITE command while transitioning the two lowest bits A0 and A1 of the port number PORT of the voice / LED control circuit 220. Specifically, the operation of transmitting a predetermined voice command is realized by transitioning the two lowest bits A0-A1 of the address data from

[00] to

[01] while transitioning one byte of data on the data bus from [register address of voice control register] to [write data to voice control register].

[0362] When the write data is multiple bytes long and the register addresses of the control register are consecutive, such as when transmitting the SAC number (13 bits), sequence code number (13 bits), and associated control data (wait information, loop information, etc.), the operation management data A0 to A1 of

[01] is transmitted in the order

[00] →

[01] →

[01] →

[01] , and multiple bytes of write data are transmitted.

[0363] The voice command transmitted in this manner is then executed within the voice / LED control circuit 220 unless there is a communication error. However, if a communication error is detected, such as when multiple bytes of data do not match, the voice command will not be executed. An error flag in the voice control register is then set, but this error flag (status information STS) can be received by executing an I / OREAD command that transitions the operation management data A0-A1 of the address bus from

[01] to

[10] .

[0364] In this embodiment, in the final cycle in which the operation management data A0 to A1 are changed from

[00] to

[01] to

[01] to

[10] , the error information of a multi-bit length is (FFH in the case of an abnormality) can be acquired. Then, by retransmitting the voice command that could not be properly parallel transmitted, the voice performance can be properly progressed. Therefore, according to the configuration of this embodiment, it is possible to eliminate the unnaturalness of the voice performance suddenly being interrupted.

[0365] On the other hand, data reading operation by I / OREAD operation is realized by successively executing the I / OWRITE command and the I / OREAD command while changing the two lowest bits A0 and A1 of the port number PORT of the sound / LED control circuit 220. If the read data is multiple bytes long, the I / OREAD command is executed successively for the required number of bytes.

[0366] Specifically, first, as an I / O Write operation, the [register address (1 byte length) of the audio control register that stores the operation status, etc.] is output to the port number PORT where the lowest 2 bits A0-A1 of the address data are

[00] . Next, by executing an I / O READ command to the port number PORT where the lowest 2 bits A0-A1 of the address data are

[01] , necessary data such as the operation status can be obtained from the specified audio control register.

[0367] The sound reproduced by the sound / LED control circuit 220 configured as described above is transmitted as a digital sound signal of the sound / LED control circuit 220 to the digital audio power amplifier 262 in the form of a 5-bit signal (SCLK, LRO, SD0, SD1, SD2), where it is amplified by the digital audio power amplifier 262 to a class D level and supplied to each speaker as an analog sound signal. Specifically, the amplified output (analog sound signal) of the digital audio power amplifier 262 is supplied to a lower bass speaker, and the amplified output (analog sound signal) of the digital audio power amplifier 262 is supplied to four normal speakers (e.g., see FIG. 9 (L0, R0, L1, R1)) and two deep bass (vibration) speakers (e.g., see FIG. 9 (SUB0, SUB1)) that are aligned approximately above, below, left, and right of the player.

[0368] <Main control circuit operation explanation> Next, the contents of various processes executed by the main CPU 71 of the main control circuit 70 will be described with reference to FIGS.

[0369] [Main control main processing] First, the main control main process under the control of the main CPU 71 will be described with reference to Fig. 28. Fig. 28 is a flowchart showing the procedure of the main control main process in this embodiment.

[0370] When the power is turned on to the pachinko gaming machine 1, the main CPU 71 first performs an initial setting process (S1). In this process, the main CPU 71 performs processes such as permission to access the main RAM 73, restoring backup data, and initializing the work area. Next, the main CPU 71 performs an initial random number update process (S2). In this process, the main CPU 71 updates the initial random number counter value.

[0371] Next, the main CPU 71 performs a special symbol control process (S3). In this process, the main CPU 71 performs a predetermined control process regarding the progress of the special symbol game and the special symbols (first special symbol and second special symbol) displayed on the special symbol display device 61. Details of the special symbol control process will be described later with reference to FIG. 29.

[0372] Next, the main CPU 71 performs a normal symbol control process (S4). In this process, the main CPU 71 performs predetermined control processes regarding the progress of the normal symbol game and the normal symbols displayed on the normal symbol display device 62.

[0373] Next, the main CPU 71 performs a control process for the symbol display device (S5). In this process, the main CPU 71 controls the display of the special symbols (first special symbol and second special symbol) and the variable display of the normal symbol based on the execution results of the special symbol control process (S3) and the normal symbol control process (S4).

[0374] Next, the main CPU 71 performs a game information data generation process (S6). In this process, the main CPU 71 generates game information data to be transmitted to the payout / launch control circuit 123, the sub-control circuit 200, the hall computer of the gaming parlor, etc., and stores the game information data in the main RAM 73.

[0375] Next, the main CPU 71 performs a memory / game status data generation process (S7). In this process, the main CPU 71 generates memory / game status data to be transmitted to the sub-control circuit 200 based on the value of the probability variable flag and the value of the time-shortening flag, and stores the memory / game status data in the main RAM 73.

[0376] After the process of S7, the main CPU 71 returns the process to the process of S2 and repeats the processes from S2 onwards.

[0377] [Special pattern control processing] Next, with reference to Fig. 29, the special symbol control process performed in S3 in the main control process (see Fig. 28) will be described. Fig. 29 is a flowchart showing the procedure of the special symbol control process in this embodiment. Note that the numbers in parentheses ("00" to "08") next to the symbols of each processing step shown in Fig. 29 indicate the value of a control status flag, and this control status flag is stored in a predetermined storage area in the main RAM 73. The main CPU 71 progresses the special symbol game by executing each processing step corresponding to the value of the control status flag.

[0378] First, the main CPU 71 loads the control status flag (S11). In this process, the main CPU 71 reads the value of the control status flag stored in the main RAM 73.

[0379] The main CPU 71 determines whether to execute various processes in S12 to S20, which will be described later, based on the value of the control status flag loaded in S11. This control status flag indicates the status of the special symbol game, and enables execution of any of the processes in S12 to S20.

[0380] The main CPU 71 also executes the processing of each step at a predetermined timing determined according to the waiting time set for each process of S12 to S20. Note that, before reaching this predetermined timing, the main CPU 71 executes other subroutine processing without executing the processing of each step. In addition, the main CPU 71 also executes a system timer interrupt process (see FIG. 33) described later at a predetermined cycle.

[0381] Then, when the process of S11 is completed, the main CPU 71 performs a special symbol memory check process (S12).

[0382] In this process, when the control status flag is a value ("00") indicating a special symbol memory check process, the main CPU 71 checks the number of reserved special symbol variable displays, and when the reserved number is not "0" (there are reserved balls), it performs processes such as winning judgment, determination of special symbols, and determination of special symbol variation patterns. Also, in this process, the main CPU 71 sets the control status flag to a value ("01") indicating a special symbol variation time management process (S13) described later, and sets the variation time of the special symbol corresponding to the variation pattern determined in this process in the waiting time timer. In other words, this process sets the special symbol variation time management process described later to be executed after the variation time of the special symbol corresponding to the variation pattern determined in the process of S12 has elapsed.

[0383] On the other hand, if the number of reserved balls is "0" (there are no reserved balls), the main CPU 71 performs a demo display process to display a demo screen. Details of the special symbol memory check process will be described later with reference to FIG. 30.

[0384] Next, the main CPU 71 performs a special symbol variation time management process (S13). In this process, when the control status flag is a value ("01") indicating a special symbol variation time management process and the variation time of the special symbol has elapsed, the main CPU 71 sets the control status flag to a value ("02") indicating a special symbol display time management process (S14) to be described later, and sets the post-determination waiting time in the waiting time timer. That is, by this process, after the post-determination waiting time set in the process of S13 has elapsed, the special symbol display time management process to be described later is set to be executed.

[0385] Next, the main CPU 71 performs a special symbol display time management process (S14). In this process, when the control status flag is a value ("02") indicating the special symbol display time management process and the post-confirmation waiting time set in the process of S13 has elapsed, the main CPU 71 determines whether the result of the hit determination is a "big hit" or a "small hit." If the result of the hit determination is a "big hit" or a "small hit," the main CPU 71 sets the control status flag to a value ("03") indicating the jackpot start interval management process (S15) described later, and sets the waiting time timer to a time corresponding to the jackpot start interval. That is, this process sets the jackpot start interval management process described later to be executed after the time corresponding to the jackpot start interval set in the process of S14 has elapsed.

[0386] On the other hand, if the result of the hit determination is not a "big hit" or a "small hit," the main CPU 71 sets the control status flag to a value ("08") indicating a special symbol game end process (S20) to be described later. That is, in this case, it is set so that a special symbol game end process to be described later is executed. Details of the special symbol display time management process will be described later with reference to FIG. 31.

[0387] Next, when the result of the hit determination in S14 is determined to be a "big hit" or a "small hit," the main CPU 71 performs a big hit start interval management process (S15). In this process, the main CPU 71 updates the variables located in the main RAM 73 based on the data read from the main ROM 72 in order to open the first big win opening 53 or the second big win opening 54 when the control status flag is a value ("03") indicating the big hit start interval management process and the time corresponding to the big hit start interval set in the process of S14 has elapsed.

[0388] In addition, in this process, the main CPU 71 sets the control status flag to a value ("04") indicating the large prize opening process (S16) described later, and sets the large prize opening opening time upper limit (for example, 30 seconds) in the large prize opening time timer. In other words, this process sets the large prize opening opening process described later to be executed.

[0389] Next, the main CPU 71 performs the special prize opening process (S16). In this process, first, when the control status flag is a value ("04") indicating the special prize opening process, the main CPU 71 determines whether one of the following conditions is satisfied: the special prize opening counter is equal to or greater than a predetermined number; and the opening upper limit time has elapsed (the special prize opening opening time timer is "0"). It is determined whether the predetermined closing condition is met.

[0390] In S16, if one of the conditions is satisfied, the main CPU 71 updates the variables stored in the main RAM 73 to close the specified special prize opening (the first special prize opening or the second special prize opening). The main CPU 71 then sets the control status flag to a value ("05") indicating the special prize opening remaining ball monitoring process (S17), which will be described later, and sets the waiting time timer to the special prize opening remaining ball monitoring time. In other words, this process sets the special prize opening remaining ball monitoring process, which will be described later, to be executed after the special prize opening remaining ball monitoring time set in S17 has elapsed.

[0391] In addition, in S16, the main CPU 71 transmits an inter-round display command to the sub-control circuit 200 immediately before the end of the process during the opening of the special prize opening.

[0392] Next, the main CPU 71 performs a process of monitoring balls remaining in the special prize opening (S17). In this process, the main CPU 71 determines whether or not the condition that the value of the special prize opening opening number counter is equal to or greater than the maximum value of the special prize opening opening number (it is the final round) is satisfied when the control status flag is a value ("05") indicating the process of monitoring balls remaining in the special prize opening and the special prize opening remaining ball monitoring time has elapsed.

[0393] In S17, if the main CPU 71 determines that the above condition is not satisfied, the main CPU 71 sets a value ("06") indicating the special prize opening reopening waiting time management process to the control status flag. The main CPU 71 also sets a time corresponding to the interval between rounds to the waiting time timer. That is, this process sets the special prize opening reopening waiting time management process, which will be described later, to be executed after the time corresponding to the interval between rounds has elapsed.

[0394] On the other hand, in S17, when the main CPU 71 determines that the above condition is satisfied, the main CPU 71 sets a value ("07") indicating the jackpot end interval processing to the control status flag, and sets a time corresponding to the jackpot end interval (jackpot end interval time) to the waiting time timer. That is, by this processing, after the time corresponding to the jackpot end interval set in S17 has elapsed, the jackpot end interval processing described later is set to be executed.

[0395] Next, in S17, if the main CPU 71 determines that the value of the special prize opening count counter is not equal to or greater than the maximum value of the special prize opening count, the main CPU 71 performs a special prize opening reopening waiting time management process (S18). In this process, when the control status flag is a value ("06") indicating a special prize opening reopening waiting time management process and a time corresponding to the inter-round interval has elapsed, the main CPU 71 stores and updates the value of the special prize opening count counter so that it increases by "1." The main CPU 71 also sets the control status flag to a value ("04") indicating a special prize opening in-progress process. The main CPU 71 then sets the special prize opening opening time timer to an upper limit opening time (e.g., 30 seconds). In other words, this process sets the special prize opening in-progress process (S16) to be executed again after the process of S18.

[0396] Furthermore, in S18, the main CPU 71 transmits a command to display that the special prize opening is open to the sub-control circuit 200 immediately before the end of the waiting time management process before the special prize opening is reopened.

[0397] Furthermore, in S17, when the main CPU 71 determines that the value of the special prize opening count counter is equal to or greater than the maximum value of the special prize opening count, it performs a jackpot end interval process (S19). In this process, when the control status flag is a value ("07") indicating a jackpot end interval process and a time corresponding to the jackpot end interval has elapsed, the main CPU 71 sets the control status flag to a value ("08") indicating a special symbol game end process. That is, this process sets the special symbol game end process, which will be described later, to be executed after the process of S19. Details of the jackpot end interval process will be described later with reference to FIG. 32.

[0398] The main CPU 71 controls the game state to transition to a variable probability game state when the jackpot symbol is a variable probability game state, and controls the game state to transition to a normal game state when the jackpot symbol is a non-variable probability game state. Note that when the jackpot symbol is a symbol corresponding to a "small win", the main CPU 71 controls the game state after the "small win" game ends so that it does not transition to a game state that is more advantageous than the game state that was controlled when the "small win" was won.

[0399] Next, when the big win game state or the small win game state is ended, or when a "miss" is won, the main CPU 71 performs a special symbol game ending process (S20).

[0400] In this process, when the control status flag is a value ("08") indicating special symbol game end processing, the main CPU 71 updates and stores data indicating the number of reserved symbols (start memory information) so as to decrease it by "1." In addition, the main CPU 71 updates the special symbol memory area in order to perform the next variable display of special symbols. Furthermore, the main CPU 71 sets the control status flag to a value ("00") indicating special symbol memory check processing. That is, this process sets the above-mentioned special symbol memory check processing (S12) to be executed after the processing of S20.

[0401] After the process of S20, the main CPU 71 ends the special symbol control process and moves the process to S4 of the main control main process (see FIG. 28).

[0402] As described above, in the pachinko gaming machine 1 of this embodiment, the special symbol game progresses by sequentially setting various values ​​to the control status flag. Specifically, when the gaming status is neither a big hit gaming status nor a small hit gaming status and the result of the hit determination is "miss," the main CPU 71 sets the control status flags to "00," "01," "02," and "08" in that order. As a result, the main CPU 71 executes the above-mentioned special symbol memory check process (S12), special symbol variation time management process (S13), special symbol display time management process (S14), and special symbol game end process (S20) in this order at predetermined timings.

[0403] Furthermore, when the gaming state is neither a big win gaming state nor a small win gaming state and the result of the hit determination is a "big win" or a "small win," the main CPU 71 sets the control state flags in the order of "00," "01," "02," and "03." As a result, the main CPU 71 executes the above-mentioned special symbol memory check processing (S12), special symbol variation time management processing (S13), special symbol display time management processing (S14), and big win start interval management processing (S15) in this order at predetermined timings, and executes transition control to a big win gaming state or a small win gaming state.

[0404] Furthermore, when transition control to a big win gaming state or a small win gaming state is executed, the main CPU 71 sets the control state flags in the order of "04," "05," and "06." As a result, the main CPU 71 executes the above-mentioned large prize opening opening processing (S16), large prize opening remaining ball monitoring processing (S17), and large prize opening re-opening waiting time management processing (S18) in this order at predetermined timings, and executes a big win gaming state or a small win gaming state.

[0405] If the conditions for ending the jackpot gaming state are met during a jackpot game, the main CPU 71 sets the control state flags in the order of "04," "05," "07," and "08." As a result, the main CPU 71 executes the above-mentioned large prize opening process (S16), large prize opening remaining ball monitoring process (S17), jackpot end interval process (S19), and special symbol game end process (S20) at predetermined timings in this order, and ends the jackpot gaming state.

[0406] As described above, in the special symbol control process, the process flow is branched depending on the status. Also, in the normal symbol control process of S4 in the main control main process shown in Figure 28, the process flow is also branched depending on the status, as will be described later, just like the special symbol control process.

[0407] The processing program of this embodiment is programmed so that when processing is branched depending on the status, a call instruction enables simple return processing from a small module to a parent module. As a result, the size of the program can be reduced in this embodiment compared to when a jump table is placed to execute the above processing.

[0408] [Special pattern memory check process] Next, the special symbol memory check process performed in S12 in the special symbol control process (see Fig. 29) will be described with reference to Fig. 30. Fig. 30 is a flowchart showing the procedure of the special symbol memory check process in this embodiment.

[0409] First, the main CPU 71 loads the control status flag (S31). In this process, the main CPU 71 reads the value of the control status flag stored in the main RAM 73.

[0410] Next, the main CPU 71 determines whether the control status flag is a value ("00") indicating the special symbol memory check process (S32). In S32, when the main CPU 71 determines that the control status flag is not "00" (when S32 is determined as NO), the main CPU 71 ends the special symbol memory check process and returns the process to the special symbol control process (see FIG. 29).

[0411] On the other hand, in S32, if the main CPU 71 determines that the control status flag is "00" (if S32 is judged as YES), the main CPU 71 determines whether the number of reserved second start port winnings (variable display of second special pattern) (second start memory number) is "0" (S33).

[0412] In S33, if the main CPU 71 determines that the number of reserved winning balls for the second start port is not "0" (if S33 is judged as NO), the main CPU 71 subtracts "1" from the value of the second start memory number corresponding to the number of reserved winning balls for the second start port (S34).

[0413] In this embodiment, the main CPU 71 determines whether data is stored in the second special symbol start memory area (0) to the second special symbol start memory area (4) provided in the main RAM 73, and determines whether there is a start memory of a special symbol game corresponding to the variable display of a changing or reserved second special symbol. The second special symbol start memory area (0) stores data (information) of the special symbol game corresponding to the variable display of the changing second special symbol as the start memory. The second special symbol start memory area (1) to the second special symbol start memory area (4) store data (information) of the special symbol game corresponding to the reserved variable display (reserved ball) of four second special symbols as the start memory. The data included in the start memory stored in each second special symbol start memory area is, for example, data such as a random number value for determining a jackpot and a random number value of a jackpot symbol obtained when a prize is won in the second start slot 45.

[0414] After the process of S34, the main CPU 71 performs a special symbol storage transfer process based on the winning of the second start port (S35). In this process, the main CPU 71 transfers (stores) the data of the second special symbol start storage areas (1) to (4) to the second special symbol start storage areas (0) to (3), respectively. Then, after the process of S35, the main CPU 71 performs the process of S40 described later.

[0415] Here, returning to the processing of S33 again, if the main CPU 71 determines in S33 that the number of reserved winnings for the second start port is "0" (if S33 judges YES), the main CPU 71 determines whether the number of reserved winnings for the first start port (variable display of the first special pattern) (first start memory number) is "0" (S36).

[0416] In S36, when the main CPU 71 determines that the number of reserved winnings in the first starting slot is "0" (when S36 is judged as YES), the main CPU 71 performs demo display processing (S37). After processing S37, the main CPU 71 ends the special symbol memory check processing and returns the processing to the special symbol control processing (see FIG. 29).

[0417] In the demo display process of S37, the main CPU 71 sets a demo display permission value in the main RAM 73. That is, when the state in which the number of reserved symbols for the first start port winning and the second start port winning becomes "0" (the state in which the start memory of the special symbol game becomes "0") is maintained for a predetermined time (e.g., 30 seconds), the main CPU 71 sets a predetermined value as the demo display permission value. Also, when the demo display permission value is the predetermined value in the demo display process of S37, the main CPU 71 sets demo display command data in the main RAM 73. Then, the demo display command data is transmitted from the main CPU 71 of the main control circuit 70 to the host control circuit 210 in the sub-control circuit 200. When the sub-control circuit 200 receives the demo display command data, it displays a demo screen in the display area 13a of the display device 13.

[0418] On the other hand, in S36, if the main CPU 71 determines that the number of reserved winning balls for the first start port is not "0" (if S36 judges NO), the main CPU 71 subtracts "1" from the value of the first start memory number corresponding to the number of reserved winning balls for the first start port (S38).

[0419] In this embodiment, the main CPU 71 determines whether data is stored in the first special symbol start memory area (0) to the first special symbol start memory area (4) provided in the main RAM 73, and determines whether there is a start memory of a special symbol game corresponding to the variable display of the first special symbol that is currently changing or on hold. The first special symbol start memory area (0) stores data (information) of the special symbol game corresponding to the variable display of the first special symbol that is currently changing as the start memory. The first special symbol start memory area (1) to the first special symbol start memory area (4) store data (information) of the special symbol game corresponding to the variable display (reserved ball) of the first special symbol for four times that are on hold as the start memory. The data included in the start memory stored in each first special symbol start memory area is, for example, data such as a random number value for determining a jackpot and a random number value of a jackpot symbol obtained when the first start hole 44 wins.

[0420] After the process of S38, the main CPU 71 performs a special symbol storage transfer process based on the winning of the first start port (S39). In this process, the main CPU 71 transfers (stores) the data of the first special symbol start storage areas (1) to (4) to the first special symbol start storage areas (0) to (3), respectively. Then, after the process of S39, the main CPU 71 performs a process of S40, which will be described later.

[0421] Next, after the process of S35 or S39, the main CPU 71 determines whether the value of the time-shortening state variation counter is "0" or not (S40).

[0422] In S40, when the main CPU 71 determines that the value of the time-saving state variation counter is "0" (when S40 is judged as YES), the main CPU 71 performs the process of S44 described below. On the other hand, in S40, when the main CPU 71 determines that the value of the time-saving state variation counter is not "0" (when S40 is judged as NO), the main CPU 71 subtracts "1" from the value of the time-saving state variation counter (S41).

[0423] After the process of S41, the main CPU 71 determines whether the value of the time-saving state variation counter is "0" or not (S42).

[0424] In S42, when the main CPU 71 determines that the value of the time-saving state variation counter is not "0" (when S42 is judged as NO), the main CPU 71 performs the process of S44 described below. On the other hand, in S42, when the main CPU 71 determines that the value of the time-saving state variation counter is "0" (when S42 is judged as YES), the main CPU 71 sets the time-saving flag to "0" (S43).

[0425] After the process of S43, if S40 is judged as YES, or if S42 is judged as NO, the main CPU 71 sets the control status flag to a value ("01") indicating the special symbol variation time management process (S44). In addition, in this process, the main CPU 71 transmits a reserved subtraction command and a special symbol effect start command to the sub-control circuit 200.

[0426] Next, the main CPU 71 performs a jackpot determination process (S45). In this process, the main CPU 71 determines (determines) whether the winning result is a "jackpot," a "small jackpot," or a "miss" by lottery based on the random number value for jackpot determination obtained when the ball enters the starting slot.

[0427] Next, the main CPU 71 clears the information (data) in the memory area used for the previous variable display (S46). Next, the main CPU 71 sets the variable time corresponding to the determined variable pattern of the special symbol in the waiting time timer (S47). Then, after processing S47, the main CPU 71 ends the special symbol memory check process and returns the process to the special symbol control process (see FIG. 29).

[0428] [Special pattern display time management processing] Next, the special symbol display time management process performed in S14 in the special symbol control process (see Fig. 29) will be described with reference to Fig. 31. Fig. 31 is a flowchart showing the procedure of the special symbol display time management process in this embodiment.

[0429] First, the main CPU 71 determines whether the control status flag is a value ("02") indicating the special symbol display time management process (S51). In S51, when the main CPU 71 determines that the control status flag is not a value ("02") indicating the special symbol display time management process (when S51 is judged as NO), the main CPU 71 ends the special symbol display time management process and returns the process to the special symbol control process (see FIG. 29).

[0430] On the other hand, in S51, when the main CPU 71 determines that the control status flag is a value ("02") indicating the special symbol display time management process (when S51 is judged as YES), the main CPU 71 determines whether the value (waiting time) of the waiting time timer is "0" (S52). In this process, the main CPU 71 determines whether the waiting time (waiting time to start fluctuation) set in the waiting time timer after the fluctuation is determined has expired.

[0431] In S52, when the main CPU 71 determines that the value of the waiting time timer is not "0" (when S52 is determined as NO), the main CPU 71 ends the special symbol display time management process and returns the process to the special symbol control process (see FIG. 29). On the other hand, in S52, when the main CPU 71 determines that the value of the waiting time timer is "0" (when S52 is determined as YES), the main CPU 71 determines whether the special symbol game is a "jackpot" (S53). In addition, in this process, the main CPU 71 simultaneously transmits a special effect stop command to the sub-control circuit 200.

[0432] In S53, when the main CPU 71 determines that the special symbol game is not a "jackpot" (when S53 is determined as NO), the main CPU 71 sets the control status flag to a value ("08") indicating special symbol game termination processing (S54). Then, after processing S54, the main CPU 71 ends the special symbol display time management processing and returns the processing to the special symbol control processing (see FIG. 29).

[0433] On the other hand, in S53, when the main CPU 71 determines that the special symbol game is a "jackpot" (when S53 is judged as YES), the main CPU 71 sets the jackpot flag to an ON state (S55). The jackpot flag is a flag indicating whether or not a jackpot game is to be played.

[0434] Next, the main CPU 71 clears the value of the time-saving state variation counter, the value of the time-saving flag, and the value of the probability variable flag (S56). Next, the main CPU 71 sets the control state flag to a value ("03") indicating the jackpot start interval management process (S57).

[0435] Next, the main CPU 71 sets a jackpot start interval time (for example, 5000 msec) corresponding to the special symbol (first special symbol or second special symbol) in the waiting time timer (S58). Next, the main CPU 71 sets a jackpot start command (special symbol win start display command) corresponding to the special symbol in the main RAM 73 (S59). In addition, in this process, the main CPU 71 simultaneously transmits the special symbol win start display command to the sub-control circuit 200.

[0436] Next, the main CPU 71 sets the round number display LED pattern flag to the ON state (S60). The round number display LED pattern flag is a flag indicating whether or not the remaining round number is to be displayed in a predetermined pattern. After processing S60, the main CPU 71 ends the special symbol display time management process and returns the process to the special symbol control process (see FIG. 29).

[0437] [Jackpot End Interval Processing] Next, the jackpot end interval process performed in S19 in the special symbol control process (see FIG. 29) will be described with reference to Fig. 32. Fig. 32 is a flowchart showing the procedure of the jackpot end interval process in this embodiment.

[0438] First, the main CPU 71 determines whether or not the control status flag is a value ("07") indicating the big win end interval process (S71).

[0439] In S71, when the main CPU 71 determines that the control status flag is not the value ("07") indicating the jackpot end interval processing (when S71 is determined to be NO), the main CPU 71 ends the jackpot end interval processing and returns the processing to the special symbol control processing (see FIG. 29). On the other hand, in S71, when the main CPU 71 determines that the control status flag is the value ("07") indicating the jackpot end interval processing (when S71 is determined to be YES), the main CPU 71 determines whether the value of the waiting time timer is "0" or not (S72). In this processing, the main CPU 71 determines whether the jackpot end interval time set in the waiting time timer has expired or not.

[0440] In S72, when the main CPU 71 determines that the value of the waiting time timer is not "0" (when S72 is determined as NO), the main CPU 71 ends the big win end interval process and returns the process to the special symbol control process (see FIG. 29). On the other hand, in S72, when the main CPU 71 determines that the value of the waiting time timer is "0" (when S72 is determined as YES), the main CPU 71 clears the big prize opening count display LED pattern flag (S73).

[0441] Next, the main CPU 71 clears the round number allocation flag (sets it to "0") (S74).

[0442] Next, the main CPU 71 sets the control status flag to a value ("08") indicating the special symbol game end process (S75). In addition, in this process, the main CPU 71 simultaneously transmits a special symbol win end display command to the sub-control circuit 200. Next, the main CPU 71 clears the big win flag (S76).

[0443] Next, the main CPU 71 refers to the jackpot type determination table (see Figures 20 to 23), and sets the value of the probability variable flag based on the game state at the time of the jackpot win and the type of the jackpot selection symbol command (S77). (See FIGS. 20 to 23), and based on the game state at the time of winning the jackpot and the type of the symbol selection command at the time of winning the jackpot, the value of the time-shortening flag is set (S78).

[0444] Next, the main CPU 71 determines whether the value of the time-shortening flag is "1" (whether the time-shortening flag is in an on state) (S79). In S79, when the main CPU 71 determines that the value of the time-shortening flag is not "1" (when S79 is determined as NO), the main CPU 71 ends the big win end interval process and returns the process to the special symbol control process (see FIG. 29).

[0445] On the other hand, in S79, when the main CPU 71 determines that the value of the time-saving flag is "1" (when S79 is judged as YES), the main CPU 71 refers to the jackpot type determination table (see Figs. 20 to 23), and sets the corresponding value of the number of time-saving times in the time-saving state variation counter based on the game state at the time of winning the jackpot and the type of the jackpot selection symbol command (S80). Then, after processing S80, the main CPU 71 ends the jackpot end interval processing, and returns the processing to the special symbol control processing (see Fig. 29).

[0446] [System timer interrupt processing] In the pachinko gaming machine 1 of this embodiment, the main CPU 71 interrupts the main processing at predetermined intervals even during execution of the main processing, and executes system timer interrupt processing. Specifically, the main CPU 71 executes the system timer interrupt processing in response to clock pulses generated at predetermined intervals (e.g., 2 msec) from the clock generating circuit 74. Here, the system timer interrupt processing executed by the main CPU 71 will be described with reference to Fig. 33. Note that Fig. 33 is a flowchart showing the procedure of the system timer interrupt processing in this embodiment.

[0447] First, the main CPU 71 saves the data (information) in each register (S121). Next, the main CPU 71 performs random number update processing (S122). In this processing, the main CPU 71 updates various random number values ​​extracted from the jackpot determination counter, the symbol determination counter, the hit determination counter, the fall determination counter, the variation pattern determination counter, the effect pattern determination counter, and the like. Note that the jackpot determination counter and the symbol determination counter lack fairness if the update timing of the counter values ​​is indefinite. Therefore, the jackpot determination counter and the symbol determination counter are updated at fixed timing in 2 msec cycles to ensure fairness.

[0448] Next, the main CPU 71 performs a switch input detection process (S123). In this process, the main CPU 71 detects winning or passing through various starting holes, various winning holes, and the ball passing detector 43. Details of the switch input detection process will be described later with reference to FIG. 34.

[0449] Next, the main CPU 71 performs a timer update process (S124). Specifically, the main CPU 71 performs an update process for various timers, such as a waiting time timer for synchronizing the main control circuit 70 and the sub-control circuit 200, and a special prize opening time timer for measuring the opening time of the special prize opening.

[0450] Next, the main CPU 71 performs a command output process (S125). In this process, the main CPU 71 outputs various commands, such as a winning command, a variable command, etc., to the host control circuit 210 of the sub-control circuit 200.

[0451] Next, the main CPU 71 performs a game information output process (S126). In this process, the main CPU 71 outputs various pieces of game-related information processed by the main control circuit 70, the sub-control circuit 200, the payout / launch control circuit 123, etc. to the hall computer of the gaming parlor.

[0452] Next, the main CPU 71 restores the data of each register that was saved in S121. (S127) After the process of S127, the main CPU 71 ends the system timer interrupt process.

[0453] [Switch input detection process] Next, the switch input detection process performed in S123 in the system timer interrupt process (see Fig. 33) will be described with reference to Fig. 34. Fig. 34 is a flowchart showing the procedure of the switch input detection process in this embodiment.

[0454] First, the main CPU 71 performs a start port winning detection process (S131). In this process, the main CPU 71 determines whether or not a gaming ball has entered (passed through) the first start port 44 or the second start port 45. That is, the main CPU 71 detects whether or not the first start port winning ball sensor 44a or the second start port winning ball sensor 45a has detected the winning of a gaming ball. Details of the start port winning detection process will be described later with reference to FIG. 35.

[0455] Next, the main CPU 71 performs a general winning opening passage detection process (S132). In this process, the main CPU 71 determines whether or not a gaming ball has entered the general winning opening 51 or 52. That is, the main CPU 71 detects whether or not the general winning ball sensor 51a or 52a has detected the entry of a gaming ball. Then, when the entry of a gaming ball into the general winning opening 51 or 52 is detected, the main CPU 71 performs various predetermined processes corresponding to the entry.

[0456] Next, the main CPU 71 performs a special prize opening passage detection process (S133). In this process, the main CPU 71 determines whether or not a gaming ball has entered the first special prize opening 53 or the second special prize opening 54. That is, the main CPU 71 detects whether or not the entry of a gaming ball has been detected by the first special prize opening solenoid 53b or the second special prize opening solenoid 54b. Then, when the entry of a gaming ball into the first special prize opening 53 or the second special prize opening 54 is detected, the main CPU 71 performs various predetermined processes corresponding to the entry.

[0457] Next, the main CPU 71 performs gate passage detection processing (S134). In this processing, the main CPU 71 determines whether or not the gaming ball has passed through the ball passage detector 43. That is, the main CPU 71 detects whether or not the passage of the gaming ball has been detected by the passing ball sensor 43a. Next, when it is detected that the gaming ball has passed through the ball passage detector 43, the main CPU 71 performs various predetermined processes corresponding to the passage. Then, after processing S134, the main CPU 71 ends the switch input detection processing and returns to the system timer interrupt processing. (See FIG. 33)

[0458] [Starting gate winning detection process] Next, the start gate winning detection process performed in S131 of the switch input detection process (see Fig. 34) will be described with reference to Fig. 35. Fig. 34 is a flowchart showing the procedure of the start gate winning detection process in this embodiment.

[0459] First, the main CPU 71 determines whether or not the entry of a gaming ball into the first start hole 44 has been detected based on the output signal of the first start hole entry ball sensor 44a (S141).

[0460] In S141, when the main CPU 71 determines that the entry of a gaming ball into the first start port 44 has not been detected (when S141 is a NO judgment), the main CPU 71 performs the processing of S149, which will be described later. On the other hand, in S141, when the main CPU 71 determines that the entry of a gaming ball into the first start port 44 has been detected (when S141 is a YES judgment), the main CPU 71 sets payout information corresponding to the entry into the first start port in the main RAM 73 (S142). In this embodiment, when a gaming ball enters the first start port 44, a predetermined number of gaming balls are paid out. Therefore, in the processing of S142, payout information for the predetermined number of gaming balls is set.

[0461] After the process of S142, the main CPU 71 determines whether or not the number of reserved balls (number of reserved balls) of the first start port winning (variable display of the first special symbol) is less than "4" (S143).

[0462] In S143, if the main CPU 71 determines that the number of reserved first start port winning prizes is not less than "4" (if S143 is a NO judgment), the main CPU 71 performs the process of S149 described below. On the other hand, in S143, if the main CPU 71 determines that the number of reserved first start port winning prizes is less than "4" (if S143 is a YES judgment), the main CPU 71 performs the process of adding "1" to the number of reserved first start port winning prizes (S144).

[0463] After the process of S144, the main CPU 71 acquires various random number values ​​to be used in the lottery and stores the acquired various random number values ​​in a predetermined area of ​​the main RAM 73 (S145). Specifically, the main CPU 71 acquires various random number values ​​such as a random number value for determining a jackpot, a random number value for a symbol, a random number value for determining a fall, etc.

[0464] Next, the main CPU 71 performs a first special stop symbol determination process (S146). In this process, the main CPU 71 refers to the jackpot random number determination table (first start port) (see FIG. 16) and the symbol determination table (first start port) (see FIG. 18), and determines whether or not a "jackpot" has occurred based on the jackpot determination random number value and the symbol random number value acquired in S145, and if a "jackpot" has occurred, selects (determines) a jackpot symbol (an identification symbol for performance) to be displayed on the display screen of the display device 13.

[0465] Next, the main CPU 71 performs a process of determining whether or not a fall has occurred (S147). In this process, the main CPU 71 performs a fall lottery based on the fall determination random number value acquired in S145, and determines whether or not a fall has occurred. As a result, the main CPU 71 acquires fall lottery information ("0": no fall, or "1": fall has occurred).

[0466] Next, the main CPU 71 sets the pending addition command data at the time of winning the first starting port in the main RAM 73 (S148).

[0467] In this process, the main CPU 71 determines the information (transmission content) to be included in the pending addition command based on information such as the game status ("normal", "probable change", "time-saving"), winning type ("jackpot", "small win", "miss"), start memory number (number of reserved first special patterns), pattern designation command, jackpot selection pattern command, winning performance information, jackpot determination result information, and fall-down lottery information, which are obtained by referring to the jackpot random number determination table (first start port) (see Figure 16), pattern determination table (first start port) (see Figure 18), jackpot type determination table (see Figures 20 to 23), and winning performance information determination table (see Figure 24).

[0468] At this time, the game status is acquired by referring to the values ​​of the probability variable flag and the time-saving flag, the winning type is acquired by referring to the jackpot random number determination table (first start port) (see FIG. 16), the symbol designation command and the jackpot selection symbol command are acquired by referring to the symbol determination table (first start port) (see FIG. 18), and the winning performance information is acquired by referring to the winning performance information determination table (see FIG. 24). In addition, the jackpot determination result information is acquired in the process of S146, and the fall lottery information is acquired in the process of S147.

[0469] In this embodiment, in the process of S148, a reserve addition command at the time of winning the first start port is sent from the main CPU 71 to the sub-control circuit 200 (host control circuit 210). Then, based on this reserve addition command at the time of winning the first start port, the sub-control circuit 200 selects a performance pattern for the reserve performance and the pre-reading performance.

[0470] After processing S148, or if S141 or S143 is judged as NO, the main CPU 71 determines whether or not a game ball has entered the second start port 45 based on the output signal of the second start port entry ball sensor 45a (S149).

[0471] In S149, if the main CPU 71 determines that the entry of a gaming ball into the second start port 45 has not been detected (if S149 is a NO judgment), the main CPU 71 ends the start port entry detection process and moves the process to S132 of the switch input detection process (see FIG. 34). On the other hand, in S149, if the main CPU 71 determines that the entry of a gaming ball into the second start port 45 has been detected (if S149 is a YES judgment), the main CPU 71 sets payout information corresponding to the second start port entry in the main RAM 73 (S150). In this embodiment, when a gaming ball enters the second start port 45, a predetermined number of gaming balls are paid out. Therefore, in the process of S150, payout information for the predetermined number of gaming balls is set.

[0472] After the process of S150, the main CPU 71 determines whether or not the number of reserved balls (number of reserved balls) for the second start port winning (variable display of the second special symbol) is less than "4" (S151).

[0473] In S151, if the main CPU 71 determines that the number of reserved balls for the second start port winning is not less than "4" (if S151 is a NO judgment), the main CPU 71 ends the start port winning detection process and moves the process to S132 of the switch input detection process (see FIG. 34). On the other hand, in S151, if the main CPU 71 determines that the number of reserved balls for the second start port winning is less than "4" (if S151 is a YES judgment), the main CPU 71 performs a process to increment the number of reserved balls for the second start port winning by "1" (S152). After processing S152, the main CPU 71 acquires various random number values ​​to be used in the lottery and stores the acquired various random number values ​​in a predetermined area of ​​the main RAM 73 (S153). Specifically, the main CPU 71 acquires various random number values ​​such as a random number value for determining a jackpot, a random number value for a pattern, a random number value for determining a fall, etc.

[0474] Next, the main CPU 71 performs a second special stop symbol determination process (S154). In this process, the main CPU 71 refers to the jackpot random number determination table (second start port) (see FIG. 17) and the symbol determination table (second start port) (see FIG. 19), and determines whether or not a "jackpot" has occurred based on the jackpot determination random number value and the symbol random number value obtained in S153, and in the case of a jackpot, selects (determines) a jackpot symbol (an identification symbol for performance) to be displayed on the display screen of the display device 13.

[0475] Next, the main CPU 71 performs a process of determining whether or not a fall has occurred (S155). In this process, the main CPU 71 performs a fall lottery based on the fall determination random number value acquired in S153, and determines whether or not a fall has occurred. As a result, the main CPU 71 acquires fall lottery information ("0": no fall, or "1": fall has occurred).

[0476] Next, the main CPU 71 sets the reserved addition command data at the time of winning the second start port in the main RAM 73 (S156).

[0477] In this process, the main CPU 71 determines the information (transmission content) to be included in the pending addition command based on information such as the game status ("normal", "probable change", "time-saving"), winning type ("jackpot", "miss"), start memory number (number of reserved second special patterns), pattern designation command, jackpot selection pattern command, winning performance information, jackpot determination result information, and fall-down lottery information, which are obtained by referring to the jackpot random number determination table (second start port) (see Figure 17), pattern determination table (second start port) (see Figure 19), jackpot type determination table (see Figures 20 to 23), and winning performance information determination table (see Figure 24).

[0478] At this time, the game status is acquired by referring to the values ​​of the probability variable flag and the time-saving flag, the winning type is acquired by referring to the jackpot random number determination table (second start port) (see Fig. 17), the symbol designation command and the jackpot selection symbol command are acquired by referring to the symbol determination table (second start port) (see Fig. 19), and the winning performance information is acquired by referring to the winning performance information determination table (see Fig. 24). In addition, the jackpot determination result information is acquired in the process of S154, and the fall lottery information is acquired in the process of S155.

[0479] In this embodiment, in the processing of S156, a reserve addition command for when the second start port is won is sent from the main CPU 71 to the sub-control circuit 200 (host control circuit 210). The sub-control circuit 200 selects a presentation pattern for the reserve presentation and the pre-read presentation based on this reserve addition command for when the second start port is won. Then, after processing of S156, the main CPU 71 ends the start port winning detection processing and moves the processing to S132 of the switch input detection processing (see FIG. 34).

[0480] <Operational explanation of the sub-control circuit> 36 to 74, the contents of various processes executed by various control circuits in the sub-board 202 of the sub-control circuit 200 (see, for example, FIG. 6 for all of them) will be described. The sub-control circuit 200 receives various commands transmitted from the main control circuit 70 (see, for example, FIG. 6), and performs various processes based on these various commands.

[0481] [Secondary control main processing] First, with reference to FIG. 36, the sub-control main processing executed by the host control circuit 210 (see, for example, FIG. 6, the same below) will be described. FIG. 36 is a flowchart showing an example of the sub-control main processing in this embodiment. The sub-control main processing is processing that starts when the power is turned on. In the sub-control main processing described with reference to FIG. 36 and the sub-control main processing described later (see FIGS. 47, 48, and 49), the same processing is assigned different reference numerals for ease of explanation. For example, taking various initialization processing as an example, the various initialization processing (step S201) in FIG. 36, the various initialization processing (step S381) in FIG. 47, the various initialization processing (step S391) in FIG. 48, and the various initialization processing (step S401) in FIG. 48 are essentially the same processing but are assigned different reference numerals.

[0482] First, the host control circuit 210 performs various initialization processes (step S201). In this process, the host control circuit 210 performs various initialization processes, such as hardware initialization process, device initialization process, various application initialization process, backup data restoration initialization process, and RTC acquisition process. When game data has been erased by clearing the RAM, the host control circuit 210 also performs random number initialization process. The host control circuit 210 also clears the watchdog timer counter each time each initialization process ends. At startup, the watchdog timer reset time is set, and if no service pulse is written thereafter (timeout occurs), power cutoff process is performed. The watchdog timer is cleared at the start of each process in the main loop within the sub-control main process, the start of each initialization process, and the transition to power cutoff process.

[0483] Next, the host control circuit 210 enters the main loop and performs RTC acquisition processing based on the RTC time, that is, processing to acquire the current time (step S202).

[0484] In step S203, the host control circuit 210 performs random number initialization processing, which will be described later.

[0485] The host control circuit 210 acquires the control code of the reel in step S204 and performs synchronization processing between the reel and the solenoid (step S205). These processing steps will be explained later in "Reel Solenoid Control Processing."

[0486] The host control circuit 210 performs sub-device input processing in step S206. In this processing, the host control circuit 210 performs processing such as acquiring information on the operation content based on the input state of the operation means, etc. (processing to determine whether or not the player has operated the operation means, such as a button). This sub-device input processing (step S206) includes adjusting the brightness of LEDs, etc., through operations by the player, etc.

[0487] In step S207, the host control circuit 210 performs various request control processes. In this process, the host control circuit 210 performs various request control processes, such as sound request control process, LED request control process, and prop request control process. The sound request, LED request, prop request, etc. are saved in a buffer and output to each device after a bank flip in step S213, which will be described later. This allows synchronization with drawing. A bank flip is a process in which the function of one frame buffer is switched from a drawing function to a display function, and the function of the other frame buffer is switched from a display function to a drawing function.

[0488] Next, the host control circuit 210 enters a packet reception loop within the main loop and performs main-sub command control processing (step S208). In this processing, the host control circuit 210 reads command data when command data is received from the main CPU 71 (command reception processing) and stores the command data in the sub work RAM 210a (received data storage processing).

[0489] In step S209, the host control circuit 210 performs a game data backup process. In the pachinko gaming machine 1 of this embodiment, first data (a magic code, a program version, and a SUM value) and second data (a magic code and a SUM value, both of which are information set in the hall menu) are prepared as game data used to determine whether RAM is cleared. In the game data backup process, the first data is saved in the game data and then backed up to the SRAM 210b (see FIG. 6). The game data is also backed up (mirrored) in another area of ​​the SRAM 210b. After power is turned on, the game data is restored from the data backed up in the SRAM 210b. At this time, the first data is used to check whether the backed up data is corrupted. If the backed up data is corrupted, the second data is checked whether it is corrupted. At this time, all data saved in the SRAM 210b, such as hall menu information, is also initialized.

[0490] Next, the host control circuit 210 performs an animation request construction process (step S210). In this process, the host control circuit 210 performs command analysis, status setting, and lottery processing, and in response to these, generates an animation request required for controlling the performance using the display device 13, and generates various requests (sound request, lamp request, and accessory request) for operating various performance devices in response to the performance control (display) on the display device 13 executed based on this animation request.

[0491] The host control circuit 210 executes the above steps S202 to S05 until it has executed the number of received commands, and once it has executed the number of received commands, it exits the loop for the number of received packets. Thereafter, the host control circuit 210 goes through animation update processing (step S211), drawing processing (step S212), and bank flip / bank flip end wait (step S213), and repeats each process in the main loop.

[0492] The host control circuit 210 performs an example of the process of steps S202 to S213 described above. (Main loop processing) is repeatedly executed at a predetermined FPS cycle. The FPS cycle is set to, for example, approximately 16.7 msec (60 FPS), approximately 33.3 msec (30 FPS), etc. The predetermined FPS cycle is adjusted in step S213.

[0493] The following will explain the timer interrupt processing, sub-device input processing, backlight control processing, backlight and various LED brightness adjustment, RTC acquisition processing, composition playback control, sound amplifier control processing, sound request control processing (when there are multiple sound requests for the same channel), sound request control processing (when volume adjustment has been made), LED brightness adjustment processing, role-play solenoid control processing, data load processing, and sub-random number processing in this order. Note that the order in which the above processes are explained is different from the actual processing order for the sake of convenience.

[0494] [Timer interrupt processing] In the pachinko gaming machine 1 of this embodiment, the host control circuit 210 performs interrupt processing at 1 msec intervals. The interrupt processing will be described in detail in the respective processes described later, but here, a representative example of the interrupt processing will be briefly described with reference to FIG. 37. FIG. 37 is a flowchart showing an example of timer interrupt processing executed by the host control circuit (sub-control circuit). For convenience of explanation, the timer interrupt processing briefly described with reference to FIG. 37 and the timer interrupt processing described later (see FIGS. 44 and 46) are denoted by different reference numerals even if they are the same processes. For example, taking the role motor control as an example, the role motor control (step S251) in FIG. 37, the role motor control (step S352) in FIG. 44, and the role motor control (step S371) in FIG. 46 are essentially the same processes but are denoted by different reference numerals.

[0495] 37, in the timer interrupt process, the host control circuit 210 first controls the accessory motor (step S251). Next, the host control circuit 210 performs input state determination processing based on the input information of the sub-device (step S252). Next, the host control circuit 210 performs control processing for, for example, the backlight of a liquid crystal display device used as the display device 13 based on the brightness value (step S253). Next, the host control circuit 210 performs sound amplifier check processing (step S254).

[0496] [Sub-device input processing] In this embodiment, the host control circuit 210 creates sub-device input discrimination information in the main processing every 33.3 msec based on the input status of the sub-device detected by a timer interrupt every 1 msec, and controls the sub-device based on this created sub-device input discrimination information.

[0497] When the host control circuit 210 detects the input state of the sub-device by a timer interrupt every 1 msec, it creates the sub-device input information, sub-device input ON edge information, sub-device input ON edge information (with repeat function), and sub-device input OFF edge information as the above-mentioned sub-device input discrimination information created in the main processing based on this detection result.

[0498] The sub-device input processing shown in FIG. 36 will be described below with reference to FIGS. 38 to 41. A sub-device, such as a push button, is controlled by the host control circuit 210 based on input (e.g., operation) information. FIG. 38 shows an example of the sub-device input discrimination information to be created, including (a) a diagram showing the input state of the sub-device detected by a timer interrupt, (b) a diagram showing sub-device input information created in the main processing, (c) a diagram showing sub-device input ON edge information created in the main processing, (d) a diagram showing sub-device input ON edge information (with repeat function) created in the main processing, and (e.g., sub-device OFF edge information created in the main processing. FIG. 39 is a flowchart showing an example of the sub-device input processing. FIG. 40 is a flowchart showing an example of the sub-device input ON edge information (with repeat function) processing. FIG. 41 is a flowchart continuing from FIG. 40, showing an example of the sub-device input ON edge information (with repeat function) processing.

[0499] The sub-device input information created in the main processing is created according to the sub-device input state detected by the timer interrupt (see FIG. 38(a)), as shown in FIG. 38(b). That is, if the sub-device input state detected by the timer interrupt is ON, 1 is set. Also, if the sub-device input state detected by the timer interrupt is OFF, 0 is set.

[0500] As shown in Figure 38(c), when it is detected that the sub-device input state detected by the timer interrupt has changed from OFF to ON, the sub-device input ON edge information is set to 1 for only one frame in the main processing.

[0501] The sub-device input ON edge information (with repeat function) is information used for control when, for example, debugging or when an operation button is pressed and held down, and as shown in FIG. 38(d), when it is detected that the sub-device input state detected by a timer interrupt has changed from OFF to ON, 1 is set for one frame in the main processing. If the sub-device input state continues to be ON thereafter, 1 is set for one frame after, for example, 10 frames have elapsed in the main processing as a fixed time until key repeat begins, and thereafter 1 is set for, for example, every four frames in the main processing. In this way, the reason only the first frame is made 10 frames long is to make it possible to determine whether the sub-device has been pressed and held down, and if the first frame is short, it can be determined that it was not pressed and held down.

[0502] As shown in Figure 38(e), when it is detected that the sub-device input state detected by the timer interrupt has changed from ON to OFF, the sub-device input OFF edge information is set to 1 for only one frame in the main processing.

[0503] In this embodiment, assuming there are multiple sub-devices, the host control circuit 210 manages the sub-device input discrimination information in bit units. For example, bit 0 is the main button, bit 1 is the left button, bit 2 is the right button, and so on, so that the host control circuit 210 can manage the sub-device input discrimination information for up to 32 devices.

[0504] Next, the sub-device input process (see, for example, step S206 in FIG. 36) will be described with reference to Fig. 39. This sub-device input process is a process for creating, for example, four types of information as input discrimination information for a sub-device: sub-device input information, sub-device input ON edge information, sub-device input ON edge information (with repeat function), and sub-device input OFF edge information.

[0505] First, the host control circuit 210 creates input information for the current sub-device based on the current input state of the sub-device (step S301). Specifically, if the sub-device is in the ON state, it sets 1, and if the sub-device is in the OFF state, it sets 0.

[0506] Next, the host control circuit 210 updates the input information of the sub-device to match the current sub-device input information, i.e., the input information of the sub-device created in step S301. (Step S302).

[0507] Next, the host control circuit 210 determines whether the previous sub-device input information is 0 and the current sub-device input information is 1 (step S303). If the previous sub-device input information is 0 and the current sub-device input information is 1 (YES in step S303), the host control circuit 210 sets the sub-device input ON edge information to 1 (step S304) and proceeds to step S306. On the other hand, if the previous sub-device input information is 0 and the current sub-device input information is not 1 (i.e., if the previous sub-device input information is 1 and / or the current sub-device input information is 0), the host control circuit 210 sets the sub-device input ON edge information to 0 (step S305) and proceeds to step S306.

[0508] In step S306, the host control circuit 210 determines whether the previous sub-device input information is 1 and the current sub-device input information is 0. If the previous sub-device input information is 1 and the current sub-device input information is 0 (YES in step S306), the host control circuit 210 sets the sub-device input OFF edge information to 1 (step S307) and proceeds to step S309. On the other hand, if the previous sub-device input information is 1 and the current sub-device input information is not 0 (i.e., if the previous sub-device input information is 0 and / or the current sub-device input information is 1), the host control circuit 210 sets the sub-device input OFF edge information to 0 (step S308) and proceeds to step S309.

[0509] In step S309, the host control circuit 210 performs sub-device input ON edge information (with repeat function) processing. Details of this sub-device input ON edge information (with repeat function) processing will be described later.

[0510] When the sub-device input ON edge information (with repeat function) processing in step S309 is completed, the host control circuit 210 sets the current sub-device input information to the previous sub-device input information (step S310), and ends the sub-device input processing.

[0511] Next, sub-device input ON edge information (with repeat function) processing will be described with reference to FIGS.

[0512] 40, in the sub-device input ON edge information (with repeat function) processing, the host control circuit 210 first determines whether the previous sub-device input information is 0 (step S321). If the previous sub-device input information is 0 (YES in step S321), the process proceeds to step S322.

[0513] In step S322, the host control circuit 210 determines whether the current sub-device input information is 1. If the current sub-device input information is 1 (YES in step S322), that is, if the previous sub-device input information was 0 and the current sub-device input information is 1, the process proceeds to step S323. On the other hand, if the current sub-device input information is not 1 (NO in step S322), that is, if the previous sub-device input information was 0 and the current sub-device input information is 0, the sub-device input ON edge information (with repeat function) process ends.

[0514] Next, the host control circuit 210 sets the sub-device input ON edge information (with repeat function) to 1 (step S323), sets 10 frames as the elapsed frames (step S324), and ends the sub-device input ON edge information (with repeat function) processing.

[0515] In step S321, if the previous sub-device input information is 1 (NO in step S321), the host control circuit 210 proceeds to step S325 in FIG.

[0516] 41, in step S325, the host control circuit 210 determines whether the current sub-device input information is 1. If the current sub-device input information is 1, (YES in step S325), that is, if the previous sub-device input information was 1 and the current sub-device input information is 1, 1 is subtracted from the elapsed frames (step S326), and the process proceeds to step S327.

[0517] In step S327, the host control circuit 210 determines whether the number of elapsed frames is 0. If the number of elapsed frames is 0 (YES in step S327), the host control circuit 210 sets the sub-device input ON edge information (with repeat function) to 1 (step S328), sets the number of elapsed frames to 4 (step S329), and ends the sub-device input ON edge information (with repeat function) processing.

[0518] In step S325, if the current sub-device input information is not 1 (NO in step S325), that is, if the previous sub-device input information was 1 and the current sub-device input information is 0, the host control circuit 210 sets the elapsed frames to 0 (step S330) and proceeds to step S331.

[0519] In step S331, the host control circuit 210 sets the sub-device input ON edge information (with repeat function) to 0, and then ends the sub-device input ON edge information (with repeat function) processing.

[0520] In this way, the host control circuit 210 creates the above-mentioned four types of sub-device input discrimination information in the main processing every 33.3 msec based on the input status of the sub-device detected by the timer interrupt every 1 msec, and by controlling the sub-device based on these four types of sub-device input discrimination information, it becomes possible to easily control the sub-device's rapid tap effects, long press effects, time setting effects, and other operations.

[0521] [Backlight control processing] Next, backlight control processing (for example, backlight control processing for controlling the backlight of a liquid crystal display or the like) will be described with reference to Fig. 42 and Fig. 43. Fig. 42 is a diagram illustrating an example of the backlight control processing conceptually. Fig. 43 is a flowchart showing an example of the backlight control processing.

[0522] The backlight control process of this embodiment uses the SPI asynchronous data write (SPI+DMA) function to continuously and continuously output a signal equivalent to pulse width modulation (PWM) from the serial output terminal of the Serial Peripheral Interface (SPI), enabling the duty (brightness) to be changed. This makes it possible to control the backlight without using a backlight control driver.

[0523] In this embodiment, for example, the SPI clock frequency is 100 kHz, the SPI1 clock is 0.01 msec, the time required to transmit 16 bits of data (1 luminance data item is 16 bits) via SPI is 0.16 msec, the scheduled interrupt of the host control circuit 210 is 1 msec, and the number of luminance data items transmitted from the SPI between scheduled interrupts of the host control circuit 210 is 100 bits. Therefore, the number of luminance data items transmitted between scheduled interrupts of the host control circuit 210 is 6.25 (100 / 16) (see FIG. 42). Therefore, it is considered that the number of scheduled interrupts executed until 32 pieces of luminance data are replenished in a data area of ​​a FIFO (First In First Out) that can set (store) 64 pieces of 16-bit luminance data is 5 to 6 times. Note that this number varies depending on the time of the scheduled interrupt of the host control circuit 210.

[0524] For example, the FIFO (First In First Out) data area, which can set (store) 64 pieces of 16-bit brightness data, will callback function when the number of brightness data sets (stored) in the area falls below 32, so the FIFO data area is not always full. Therefore, if other processes in the main process, which is executed every 33.3 msec, take time to set (store) brightness data in the FIFO data area, there is a possibility that the FIFO data area will become empty (the backlight will go dark).

[0525] Therefore, in this embodiment, after power is turned on, 64 pieces of 16-bit brightness data are first set to fill the FIFO data area, and then when the number of pieces of brightness data set in the FIFO data area falls below 32, a callback function is called and 32 pieces of data are set within the callback function to prevent the FIFO data area from becoming empty.

[0526] 43, in the backlight control process, host control circuit 210 first determines whether or not the process is for initial setup (step S341). If host control circuit 210 determines that the process is for initial setup (i.e., one of the processes in step 201 in FIG. 36) (YES in step S341), it sets 64 pieces of brightness data with brightness 0 in the data area of ​​FIFO (step S342) and proceeds to step S343. On the other hand, if host control circuit 210 determines that the process is not for initial setup (i.e., the process in step S253 in FIG. 37) (NO in step S341), it skips the process in step S342 and proceeds to step S343.

[0527] In step S343, host control circuit 210 determines whether the brightness value has been changed. If host control circuit 210 determines that the brightness value has been changed (YES in step S343), it changes the brightness data to be set in the FIFO data area (step S344) and proceeds to step S345. On the other hand, if it determines that the brightness value has not been changed (NO in step S343), it skips the processing of step S344 and proceeds to step S345.

[0528] In step S345, host control circuit 210 determines whether the number of brightness data sets in the FIFO data area is less than 32, and if the number of brightness data sets in the FIFO data area is less than 32 (YES in step S345), it sets 32 brightness data sets in the FIFO data area, i.e., replenishes the data area (step S346), and terminates the backlight control process. On the other hand, if the number of brightness data sets in the FIFO data area is more than 32 (NO in step S345), host control circuit 210 terminates the backlight process.

[0529] In this way, by processing the brightness data set in the FIFO data area so that it does not become empty, a PWM-equivalent signal can be output continuously and uninterrupted from the SPI serial data output terminal, making it possible to control the backlight without going through a backlight control driver.

[0530] Note that the processing of steps S343 to S346 in the backlight control processing of this embodiment can also be changed as follows. That is, after setting 64 pieces of data with brightness 0 (see step S342), a process is performed to determine whether the number of brightness data sets set in the FIFO data area is less than 32. Thereafter, it is determined whether the brightness value has been changed, and if it is determined that the brightness value has been changed, 32 pieces of brightness data according to the setting are set in the FIFO data area. If it is determined that the brightness value has not been changed, 32 pieces of brightness data that are the same as the previous time are set in the FIFO data area. The brightness data may be set in the FIFO data area in this way, and the backlight control processing may be terminated.

[0531] In this embodiment, 32 pieces of luminance data are set in the data area of ​​the FIFO. In the present embodiment, 32 pieces of luminance data are replenished when the number of pieces of luminance data set in the FIFO data area falls below half (half the number of pieces of data that can be set in the FIFO). However, the timing for replenishing the luminance data and the number of pieces of luminance data to be replenished are not limited to this. It is sufficient that the predetermined number of pieces of luminance data be replenished when the number of pieces of luminance data set in the FIFO data area falls below a predetermined number. Furthermore, the number of pieces of luminance data replenished in the FIFO data area does not have to be the predetermined number. For example, when the number of pieces of luminance data set in the FIFO data area falls below a first number, a second number of pieces of luminance data may be replenished. However, from the viewpoint of preventing the frequency of setting luminance data in the FIFO data area from becoming too frequent and preventing the FIFO data area from becoming empty, it is preferable that the predetermined number or the first number be about half the number of pieces of luminance data that can be set in the FIFO data area, but as mentioned above, it is not limited to this. Note that the above "about half" may be within a range in which the frequency of setting luminance data in the FIFO data area is not too frequent and the FIFO data area does not become empty. Various methods for determining this, such as less than half, can be used depending on the consumption speed of the luminance data set in the FIFO data area, etc. For example, since the FIFO data area in this embodiment can store up to 64 pieces of 16-bit luminance data, one or more new pieces of luminance data may be set when the luminance data stored in the FIFO data area is between 1 and 64. However, from the viewpoint of preventing the backlight from becoming dim (the luminance data stored in the FIFO data area becoming 0), it is preferable to set one or more new pieces of luminance data when two or more pieces of luminance data are stored in the FIFO data area. Furthermore, the number of pieces of luminance data that can be stored in the FIFO data area is not limited to 64, as long as at least two or more pieces of luminance data can be stored. In this way, when the luminance data that can be stored in the FIFO data area is, for example, two or more pieces, if the number of pieces of luminance data stored in the FIFO data area falls below a first number (e.g., two), a second number (e.g., one piece) of luminance data may be added.

[0532] [Modification of backlight control process] Next, a modified example of the backlight control process will be described with reference to Fig. 44 and Fig. 45. Fig. 44 is a flowchart showing an example of timer interrupt processing associated with the modified example of the backlight control process. Fig. 45 is a flowchart showing the modified example of the backlight control process.

[0533] In a modified example of the backlight control process, when there is a possibility that the 1 msec timer interrupt process will take time to process, the backlight control process determines whether or not a predetermined time has passed since data was set in the FIFO data area, and if the predetermined time has passed, the data is set in the FIFO data area.

[0534] 44, the host control circuit 210 first performs backlight control processing (step S351). For convenience of explanation, the backlight control processing of step S351 will be described below with reference to FIG. 45 before describing the processing of step S352 and subsequent steps.

[0535] As shown in Fig. 45, in the backlight control process, the host control circuit 210 first determines whether or not the process is for initial setup (step S361). If the host control circuit 210 determines that the process is for initial setup (i.e., one of the processes in step 201 in Fig. 36) (YES in step S361), it sets 64 pieces of brightness data with brightness 0 in the data area of ​​the FIFO (step S362), and then proceeds to step S366. On the other hand, if the host control circuit 210 determines that the process is not for initial setup (i.e., the process in step S351), (NO in step S361), proceed to step S363.

[0536] In step S363, host control circuit 210 determines whether the number of luminance data sets set in the FIFO data area is less than 32. If the number of luminance data sets set in the FIFO data area is less than 32 (YES in step S363), it sets, i.e., supplements, 32 pieces of luminance data in the FIFO data area (step S364) and proceeds to step S365. On the other hand, if the number of luminance data sets set in the FIFO data area is more than 32 (NO in step S363), it proceeds to step S366. As described above, 32 is half the number of pieces of data that can be set in FIFO.

[0537] In step S365, the host control circuit 210 resets the elapsed time (step S365) and starts measuring the elapsed time (step S366). After starting to measure the elapsed time in step S366, the host control circuit 210 ends the backlight control process.

[0538] Returning to FIG. 44, after completing the backlight control process in step S351, the host control circuit 210 performs accessory motor control (step S352).

[0539] In this modification, after performing processing that may take time, such as controlling a role-playing motor, the host control circuit 210 determines whether or not the elapsed time since timing began in step S366 has exceeded a predetermined time (step S353). If the predetermined time has passed (YES in step S353), 32 pieces of luminance data are set in the FIFO data area (step S354). On the other hand, if the predetermined time has not passed (NO in step S353), there is no need to add luminance data to the FIFO data area, and the process proceeds to step S357.

[0540] As mentioned above, since the time required to transmit 16 bits of data (1 luminance data is 16 bits) via SPI is 0.16 msec, it is considered that it takes 5.12 msec to transmit 32 pieces of luminance data. Therefore, in this modified example, in step S353, it is determined whether or not a predetermined time of 5.12 msec or more has elapsed.

[0541] After performing the process of step S354, host control circuit 210 resets the elapsed time (step S355) and starts counting the elapsed time again (step S356). Then, after starting to count the elapsed time in step S356, host control circuit 210 performs input state determination processing (step S357) and ends the timer interrupt processing.

[0542] In this way, timing starts when brightness data is set in the data area of ​​the FIFO, and after processing that may take time, if the timing time has passed for more than a predetermined time, brightness data is replenished, thereby making it possible to prevent the brightness data in the data area of ​​the FIFO from becoming empty.

[0543] In this modified example, the processing of steps S353 to S357 is performed after the accessory motor control (step S352), but this is merely an example. In other words, from the viewpoint of preventing the brightness data set in the FIFO data area from becoming empty, the processing of steps S353 to S357 may be performed after processing that may take time, and such processing is not limited to a specific processing.

[0544] [Backlight and LED brightness adjustment] Next, variations in brightness adjustment of the backlight and various LEDs will be described. The various LEDs correspond to board-side LEDs (e.g., LEDs arranged on the gaming board 12) and frame-side LEDs, and in this specification, this corresponds to a lamp group 18 including LEDs (see, for example, FIG. 5). Furthermore, in this specification, three variations of brightness adjustment of the backlight and various LEDs, namely, a first embodiment to a third embodiment, will be described with reference to FIGS. 46 to 49, respectively. FIG. 46 is a flowchart showing an example of timer interrupt processing showing backlight control processing. FIG. 47 is a sub-control main processing (overall flow) executed by the host control circuit 210 to explain a first embodiment of processing for brightness adjustment of the backlight and various LEDs. FIG. 48 is a sub-control main processing executed by the host control circuit 210 to explain a second embodiment of processing for brightness adjustment of the backlight and various LEDs. FIG. 49 shows the sub-control main process (overall flow) executed by the host control circuit 210 to explain a third embodiment of the process for adjusting the brightness of the backlight and various LEDs. However, FIGS. 47 to 49 only show the processes necessary for the explanation, and other processes are omitted. Note that, as described above, in the first to third embodiments described below, the host control circuit 210 also replenishes brightness data in the data area of ​​the FIFO when the brightness data set in the data area of ​​the FIFO becomes about half.

[0545] The timing for replenishing the FIFO data area with luminance data is not limited to when the luminance data set in the FIFO data area becomes approximately half full. In this embodiment, the FIFO data area can store up to 64 pieces of 16-bit luminance data, for example. Therefore, when the luminance data set in the FIFO data area is between 1 and 64, one or more new pieces of luminance data may be set. However, from the perspective of preventing the backlight from becoming dim (the luminance data set in the FIFO data area becoming 0), it is preferable to set one or more new pieces of luminance data when two or more pieces of luminance data are set in the FIFO data area. Furthermore, the number of pieces of luminance data that can be set in the FIFO data area is not limited to 64, as long as at least two or more pieces of luminance data can be set. In this way, when the luminance data that can be set in the FIFO data area is, for example, two or more pieces of luminance data, if the luminance data set in the FIFO data area falls below a first number (for example, two), a second number (for example, one) of luminance data may be replenishing.

[0546] (First Example) For example, when a player or other user adjusts the brightness of a backlight (e.g., the backlight of a liquid crystal display, etc.), the brightness of the backlight is changed, which may affect the control of the board-side LEDs and the frame-side LEDs. In this embodiment, in such a case, the brightness setting of the backlight and the brightness settings of the board-side LEDs and the frame-side LEDs are set as a common setting, and the backlight, board-side LEDs, and frame-side LEDs are controlled according to this setting. This makes it possible to simplify processing even if the update timing of the backlight control differs from the update timing of the board-side LEDs and the frame-side LEDs.

[0547] In the timer interrupt process of FIG. 46, the host control circuit 210 performs accessory motor control (step S371), input state determination process (step S372), and backlight control process (step S373) in this order.

[0548] 47, the host control circuit 210 performs an initialization process (step S381), then moves to the main loop and performs an LED request control process (step S382). The LED request performed in step S382 was created in the animation creation process of the previous frame (step S386, described later).

[0549] After performing the process of step S382, the host control circuit 210 performs the process of generating the sub-device (button) input determination information described above (step S383) based on the input state of the sub-device, and then proceeds to step S384.

[0550] In step S384, the host control circuit 210 sets the brightness of the backlight based on the input state of the sub-device (for example, a player or the like operating a brightness setting screen displayed on a liquid crystal display device used as the display device 13). The brightness of the backlight is set to, for example, three levels: strong, medium, and weak.

[0551] After the process of step S384 is completed, the host control circuit 210 moves to a packet reception loop, and first sets the brightness values ​​of the board-side LEDs and frame-side LEDs according to the performance mode to be executed and the brightness value setting (step S385). The brightness of the board-side LEDs and frame-side LEDs is set to three levels, for example, strong, medium, and weak, just like the backlight.

[0552] Here, by setting the brightness of the board-side LEDs and frame-side LEDs and the brightness of the backlight to a common setting, both the brightness of the board-side LEDs and frame-side LEDs and the brightness of the backlight can be changed by a player or other user while suppressing an increase in the control load. For example, based on a player's operation of the brightness setting screen displayed on the liquid crystal display device used as the display device 13, the host control circuit 210 changes the brightness value ...

Claims

[Claim 1] A gaming machine capable of switching between a drawing output buffer in which a drawing result is stored and a frame buffer used for displaying the result, comprising: A registration means for registering image information relating to a performance image to be displayed on a predetermined display means in the drawing output destination buffer; a performance image display control means for controlling the predetermined display means to display a performance image based on the image information registered by the registration means after switching from the drawing output buffer to the frame buffer; Equipped with When the image information stored in the frame buffer switched from the drawing output destination buffer is pause image information for temporarily stopping an image, pause image information can be registered in the drawing output destination buffer switched from the frame buffer, The image information can be controlled by display control according to a priority; When the image information is not registered in the drawing output destination buffer by the registration means, a determination regarding a playback mode can be made, When the image information is not registered in the drawing output destination buffer by the registration means, loop playback can be controlled to be performed from the beginning. A gaming machine characterized by:

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