Semiconductor storage device

Abstract

To provide a memory replaceable with a redundant cell even upon generation of a plurality of defective cells.SOLUTION: A memory includes a cell array. A first wire is connected to memory cells arrayed in a first direction. A second wire is connected to memory cells arrayed in a second direction. Multiple third wires are provided correspondingly to respective multiple second wires arrayed in a third direction. A first sense circuit is connected to a first pair of the third wires. A second sense circuit is connected to a second pair of the third wires. A switching circuit is connected to the first and second sense circuits and selectively outputs signals of the first and second sense circuits. A switch control circuit stores addresses of the second and third wires connected to defective cells, and outputs a control signal for controlling the switching circuit based on the addresses of the second and third wires connected to a selected cell to be read out.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] Semiconductor memory devices such as DRAMs (Dynamic Random Access Memories) in which memory cells are arranged three-dimensionally have been developed. The three-dimensional memory cell array has a hierarchical bit line structure in which the bit lines are hierarchically arranged into global bit lines and local bit lines in order to reduce the bit line capacitance and ensure a sense margin. In such a memory cell array, when a defective cell occurs, it is necessary to replace (relieve) the defective cell with a redundant cell. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-9767 A [Patent Document 2] International Patent Application Publication No. 2002 / 061839 [Patent Document 3] JP 2013-65638 A Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a semiconductor memory device capable of replacing a defective cell with a redundant cell with high reliability even if the defective cell occurs. [Means for solving the problem]

[0005] The semiconductor memory device according to the present embodiment includes a cell array including a plurality of memory cells. The plurality of first wirings are commonly connected to a plurality of memory cells arranged in a first direction in the cell array. The plurality of second wirings are commonly connected to a plurality of memory cells arranged in a second direction intersecting the first direction in the cell array. The plurality of third wirings are provided corresponding to each of the plurality of second wirings arranged in a third direction intersecting the first and second directions. The first sense circuit is connected to a first pair of two third wirings. The second sense circuit is connected to a second pair of the other two third wirings. The switching circuit is connected to the first and second sense circuits and selectively outputs an output signal of either the first or second sense circuit. The switch control circuit stores the addresses of the second and third wirings connected to the defective cell, and outputs a control signal for controlling the switching circuit based on the addresses of the second and third wirings connected to the selected cell to be read. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic perspective view showing a configuration example of a semiconductor memory device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic perspective view showing one bit line and its surrounding configuration. [Diagram 3] 1 is a block diagram showing an example of the configuration of a semiconductor memory device according to a first embodiment. [Figure 4] 1A and 1B are conceptual diagrams showing a configuration example and an operation example of a switching circuit. [Diagram 5] 1A and 1B are conceptual diagrams showing a configuration example and an operation example of a switching circuit. [Figure 6] 1A and 1B are conceptual diagrams showing a configuration example and an operation example of a switching circuit. [Figure 7] FIG. 4 is a circuit diagram showing a configuration example of a switch element. [Figure 8] 1A and 1B are conceptual diagrams showing a configuration example and an operation example of a switching control circuit. [Figure 9] FIG. 2 is a block diagram showing a configuration example of a gate circuit. [Figure 10] FIG. 2 is a block diagram showing a configuration example of a shift circuit. [Figure 11] 7 is a conceptual diagram showing a configuration example and an operation example of a switching control circuit according to a second embodiment. [Figure 12] FIG. 2 is a schematic plan view showing an example of the arrangement of bit lines; [Figure 13] FIG. 13 is a schematic plan view showing another example of the arrangement of bit lines. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual. In the specification and the drawings, the same elements are given the same reference numerals.

[0008] (First embodiment) 1 is a schematic perspective view showing a configuration example of a semiconductor memory device 1 according to a first embodiment. The semiconductor memory device 1 of this embodiment is, for example, a DRAM including a three-dimensional memory cell array MCA in which memory cells MC are arranged three-dimensionally (stereoscopically). The memory cells MC are used as memory cells for storing one-bit data or multi-bit data.

[0009] The memory cells MC are arranged in a matrix in the XY plane to form one memory cell layer LYR. The memory cell layers LYR are stacked in the Z direction to form a memory cell array MCA. In the memory cell array MCA, the memory cell layers LYR are stacked substantially parallel to each other. This allows the memory cells MC to be arranged three-dimensionally.

[0010] The semiconductor memory device 1 according to this embodiment includes a memory cell array MCA, a plurality of word lines WL, a plurality of bit lines VBL, a plurality of global bit lines GBL, a plurality of bit line selection transistors Tbls, and a plurality of memory cell layer selection transistors Tlys, bTlys.

[0011] The word lines WL extend in the X direction within the plane of the memory cell layer LYR and are connected to the memory cells MC arranged in the X direction. In the memory cell layer LYR, the word lines WL are arranged in the Y direction. One end of the word lines WL is connected to a word line driver (not shown) via a memory cell layer selection transistor Tlys. The other end of the word lines WL is connected to a non-selection voltage source of the word lines WL via a memory cell layer selection transistor bTlys. The word lines WL are configured in the same way in each memory cell layer LYR.

[0012] The layer selection word line MWL is connected to the gate of the memory cell layer selection transistor Tlys, and makes the memory cell layer selection transistor Tlys conductive when the memory cell layer LYR is selected. The layer selection word line bMWL is connected to the gate of the memory cell layer selection transistor bTlys, and makes the memory cell layer selection transistor bTlys non-conductive when the memory cell layer LYR is selected. Conversely, the layer selection word line MWL makes the memory cell layer selection transistor Tlys non-conductive when the memory cell layer LYR is not selected. The layer selection word line bMWL makes the memory cell layer selection transistor bTlys conductive when the memory cell layer LYR is not selected. The layer selection word line bMWL transmits a signal of opposite phase (opposite logic) to the layer selection word line MWL. Therefore, when one of the memory cell layer selection transistors Tlys, bTlys is conductive, the other is non-conductive.

[0013] The multiple bit lines (local bit lines) VBL extend in the stacking direction (Z direction) of the multiple memory cell layers LYR and are connected to the multiple memory cells MC arranged in the Z direction. The multiple memory cells MC arranged in the Z direction are connected to a common bit line VBL. In a plan view seen from the Z direction, the multiple bit lines VBL are two-dimensionally arranged in a matrix in the XY directions corresponding to the memory cells MC in the memory cell layer LYR. One end of the multiple bit lines VBL is connected to a global bit line GBL via a bit line selection transistor Tbls.

[0014] The multiple global bit lines GBL extend in the Y direction in the XY plane, and are connected to one ends of the multiple bit lines VBL arranged in the Y direction via bit line selection transistors Tbls. The multiple bit lines VBL arranged in the Y direction are connected to a common global bit line GBL. The multiple global bit lines GBL are arranged in the X direction. One ends of the multiple global bit lines GBL are connected to a sense circuit SAC. The global bit line GBL is provided in common to the multiple memory cell layers LYR in the memory cell array MCA.

[0015] The sense circuit SAC is connected to a plurality of global bit lines GBL. As shown in FIG. 3, the sense circuit SAC includes a plurality of sense amplifiers SA connected to two global bit lines GBL. The sense circuit SAC receives a read voltage corresponding to the data stored in the selected memory cell MC via one of the pair of selected global bit lines GBL, and receives a reference voltage corresponding to a reference signal from the other global bit line GBL. Furthermore, the sense circuit SAC detects the logic of the data by comparing the read voltage with the reference voltage and amplifying the voltage difference between them.

[0016] 2 is a schematic perspective view showing one bit line VBL and its surrounding configuration. Each memory cell MC includes a cell transistor Tmc and a cell capacitor Cmc. The gate of the cell transistor Tmc is connected to one of the word lines WL. One of the source and drain of the cell transistor Tmc is connected to the bit line VBL, and the other of the source and drain is connected to one end of the cell capacitor Cmc. The cell capacitor Cmc is connected between the other of the source and drain of the cell transistor Tmc and a reference voltage source (for example, ground or an intermediate voltage VDD / 2).

[0017] The memory cell MC can store logical data by storing charge in the cell capacitor Cmc via the cell transistor Tmc, or by discharging charge from the cell capacitor Cmc.

[0018] 3 is a block diagram showing a configuration example of a semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 includes a memory cell array MCA, a sense amplifier SA, a switching circuit SWC, a switch control circuit SSC, and a controller CNT. For convenience, the word lines WL are not shown in FIG. 3.

[0019] A plurality of memory cells MC arranged in the Z direction are commonly connected to one bit line (local bit line) VBL extending in the Z direction. A plurality of bit lines VBL arranged in the Y direction are provided corresponding to one global bit line GBL extending in the Y direction for every n lines (n is an integer of 2 or more), and are commonly connected to the corresponding global bit line GBL. A plurality of global bit lines GBL are connected to the sense amplifier SA in pairs of two lines. In this way, the semiconductor memory device 1 has a hierarchical bit line configuration consisting of the bit lines VBL and the global bit lines GBL. In this embodiment, the memory cell array MCA is a three-dimensional memory cell array as an example. However, the memory cell array MCA may be a planar memory cell array in which a plurality of memory cells MC are arranged two-dimensionally in a plane, as long as it has a hierarchical bit line configuration.

[0020] As shown in FIG. 3, a pair of global bit lines GBL is connected to one sense amplifier SA. n bit lines VBL corresponding to each pair of global bit lines GBL connected to each sense amplifier SA are connected to a plurality of memory cells MC for storing data. When reading data from a memory cell MC of a bit line VBL connected to one global bit line GBL, each sense amplifier SA transmits a reference signal of, for example, an intermediate voltage between "1" and "0" to the other global bit line GBL. Note that, although n is 4 in FIG. 3, n may be 3 or less or 5 or more.

[0021] The bit line selection transistors Tbls are provided between the bit lines VBL and the global bit lines GBL. The bit line selection transistors Tbls selectively connect one bit line VBL to one global bit line GBL at a time in each memory unit MU. That is, in a data read operation or a data write operation, the bit line selection transistors Tbls selectively connect the bit line VBL to one global bit line GBL in each memory unit MU. The bit line selection transistors Tbls do not connect any bit line VBL to the other global bit line GBL.

[0022] Furthermore, among the memory cells MC connected to one bit line VBL connected to one of the pair of global bit lines GBL, one memory cell MC connected to a word line WL selected by a row address RADD outputs data as a selected memory cell MC. Alternatively, data is written to the selected memory cell MC. The other of the pair of global bit lines GBL is not connected to the bit line VBL, and a reference signal is transmitted from the sense amplifier SA.

[0023] Each of the sense amplifiers SA is connected to a pair of global bit lines GBL. Each sense amplifier SA compares data obtained from one global bit line GBL with a reference signal obtained from the other global bit line GBL, and detects the logic of the data based on the reference signal. The reference signal is, for example, data of an intermediate voltage between "1" and "0".

[0024] Conversely, when a memory cell MC connected to one bit line VBL connected to the other of the pair of global bit lines GBL is selected, the bit line VBL is not connected to one of the pair of global bit lines GBL, and a reference signal is transmitted from the sense amplifier SA.

[0025] The plurality of bit lines VBL and the plurality of memory cells MC corresponding to the global bit line GBL are also called columns CL. Furthermore, two data columns CL corresponding to one sense amplifier SA constitute one memory unit MU.

[0026] One redundant unit RDD is provided for one or more memory units MU. The redundant unit RDD has the same configuration as the memory unit MU. Therefore, one of the multiple memory units MU may be set as the redundant unit RDD. In order to distinguish the redundant unit RDD from the memory units MU, the reference symbol for the configuration of the redundant unit RDD is given the suffix "_RDD". For example, the sense amplifier SA_RDD is connected to a pair of global bit lines GBL_RDD of the redundant unit RDD.

[0027] When a bit line VBL of a memory unit MU has a defective cell, the bit line VBL_RDD of the redundant unit RDD is used to store data in place of the bit line VBL with the defective cell. At this time, the entire bit line VBL with the defective cell is replaced with one bit line VBL_RDD of the redundant unit RDD. Therefore, in a data read operation, data is read from the bit line VBL_RDD of the redundant unit RDD in place of the bit line VBL with the defective cell.

[0028] For example, the bit line VBLf1 with the defective cell MCf1 in FIG. 3 is replaced with the bit line VBLf1_RDD with the memory cell MCf1_RDD of the redundant unit RDD. In this case, since the entire bit line VBL is replaced, other memory cells connected to the bit line VBLf1 are also replaced with memory cells connected to the bit line VBLf1_RDD. The memory cells of the bit line VBLf1 share the word line WL with the memory cells of the bit line VBLf1_RDD of the redundant unit RDD. The defective cell MCf1 is replaced with MCf1_RDD of the bit line VBLf1_RDD of the redundant unit RDD connected to the same word line WL. That is, the row address RADD of the defective cell MCf1 and MCf1_RDD of the bit line VBLf1_RDD are the same.

[0029] Also, the bit line VBLf2 on which the defective cell MCf2 is located is replaced with the bit line VBLf2_RDD on which the memory cell MCf2_RDD of the redundant unit RDD is located. In this case, the entire bit line VBL is replaced, so that other memory cells connected to the bit line VBLf2 are also replaced with memory cells connected to the bit line VBLf2_RDD. The memory cells of the bit line VBLf2 share the word line WL with the memory cells of the bit line VBLf2_RDD of the redundant unit RDD. The defective cell MCf2 is replaced with MCf2_RDD of the bit line VBLf2_RDD of the redundant unit RDD, which is connected to the same word line WL. That is, the row address RADD of the defective cell MCf2 and MCf2_RDD of the bit line VBLf2_RDD are the same.

[0030] In a data read operation, as described above, the switching circuit SWC selectively outputs an output signal from the sense amplifier SA_RDD in order to read data from the bit line VBL_RDD of the redundant unit RDD instead of the bit line VBL having a defective cell.

[0031] When there is no defective cell in the bit line VBL to be read in each memory unit MU, the switching circuit SWC selects only the output signal from the sense amplifier SA of the memory unit MU and does not select the output signal from the sense amplifier SA_RDD of the redundant unit RDD.

[0032] In this way, the switching circuit SWC according to the present embodiment switches the output signals of the sense amplifiers SA and SA_RDD for each bit line (local bit line) VBL. For example, in a read operation, when the addresses of the bit lines VBLf1 and VBLf2 having the defective cells MCf1 and MCf2 are specified, the switching circuit SWC selectively outputs the output signal of the sense amplifier SA_RDD of the redundant unit RDD instead of the bit lines VBLf1 and VBLf2. As a result, data of the bit line VBLf1_RDD is output instead of the bit line VBLf1, and data of the bit line VBLf2_RDD is output instead of the bit line VBLf2. When the address of the bit line VBL other than the bit lines VBLf1 and VBLf2 is specified, the switching circuit SWC does not select the sense amplifier SA_RDD of the redundant unit RDD, but selects only the sense amplifier SA of the memory unit MU. A more detailed configuration of the switching circuit SWC will be described later.

[0033] The switch control circuit SSC stores the address of the defective cell in advance, and controls the switching circuit SWC based on the address specified in the read operation. That is, the switch control circuit SSC stores the address of the global bit line GBL and the address of the bit line (local bit line) VBL of the defective cell in advance, and outputs a control signal CNT_SW based on the address of the global bit line GBL and the address of the bit line VBL of the selected cell to be read. A more detailed configuration of the switch control circuit SSC will be described later.

[0034] The controller CNT transmits a row address RADD of a selected word line WL designated in a read operation to the switch control circuit SSC. For example, a CPU (Central Processing Unit) and software, or a logic circuit such as a PLC (Programmable Logic Controller) can be used as the controller CNT.

[0035] 4 to 6 are conceptual diagrams showing configuration and operation examples of the switching circuit SWC. It is assumed that n (n is an integer of 2 or more) memory units MU1 to MUn are provided corresponding to one redundant unit RDD. In this case, the switching circuit SWC is provided with the same number of switch elements SW1 to SWn as the memory units MU1 to MUn or the corresponding sense amplifiers SA1 to SAn. The switching circuit SWC is provided corresponding to the memory units MU1 to MUn or the sense amplifiers SA1 to SAn. The switch element SWk (k=any integer from 1 to n-1) can be connected to two adjacent memory units MUk and MUk+1. The switch element SWn can be connected to the memory unit MUn and the redundant unit RDD. That is, the switch element SWn can perform switching between the sense amplifier SA_RDD of the redundant unit RDD and the sense amplifier SAn adjacent to the sense amplifier SA_RDD.

[0036] 4 shows the state of the switching circuit SWC when there is no defective cell in the bit line VBL to be read in each memory unit MU. In this case, the switch elements SW1 to SWn are connected to the sense amplifiers SA of the memory units MU1 to MUn, respectively. That is, the switch elements SW1 to SWn are in the initial state, and the switch elements SW1 to SWn are not switched. Therefore, the switching circuit SWC selectively outputs the output signals from the sense amplifiers SA of all memory units MU1 to MUn. It does not select the output signal of the sense amplifier SA_RDD of the redundant unit RDD.

[0037] FIG. 5 shows the state of the switching circuit SWC when the bit line VBLf1 with the defective cell MCf1 is the read target. In this case, in order to deselect the memory unit MU1 with the bit line VBLf1, the switch elements SW1 to SWn are switched to the memory units MU2 to MUn and the sense amplifier SA of the redundant unit RDD, respectively. That is, the switching circuit SWC switches all the switch elements SW1 to SWn from the switch element SW1 corresponding to the memory unit MU1 with the bit line VBLf1 and the sense amplifier SA1 to the switch element SWn corresponding to the sense amplifier SAn adjacent to the sense amplifier SA_RDD. As a result, the switch elements SW1 to SWn are switched to connect to the sense amplifiers SA and SA_RDD of the memory units MU2 to MUn and the redundant unit RDD, respectively. Therefore, the switching circuit SWC selectively outputs the output signals from the sense amplifier SA of the memory units MU2 to MUn and the SA_RDD of the redundant unit RDD. The signal from the sense amplifier SA1 of the memory unit MU1 is not output.

[0038] The switch element SWn outputs data from the bit line VBLf1_RDD of the redundant unit RDD. The memory cell MCf1_RDD of the bit line VBLf1_RDD stores data in place of the defective cell MCf1. Therefore, the switch element SWn can output the data that should be stored in the defective cell MCf1.

[0039] FIG. 6 shows the state of the switching circuit SWC when the bit line VBLf2 with the defective cell MCf2 is the read target. In this case, in order to deselect the memory unit MU2 with the bit line VBLf2, the switch elements SW2-SWn are switched to the memory units MU3-MUn and the sense amplifier SA of the redundant unit RDD, respectively. That is, the switching circuit SWC switches all the switch elements SW2-SWn from the switch element SW2 corresponding to the memory unit MU2 with the bit line VBLf2 and the sense amplifier SA2 to the switch element SWn corresponding to the sense amplifier SAn adjacent to the sense amplifier SA_RDD. Meanwhile, the switch element SW1 remains connected to the sense amplifier SA of the memory unit MU1, similar to the switch element SW1 in FIG. 4. Therefore, the switching circuit SWC selectively outputs the output signals from the sense amplifier SA of the memory units MU1, MU3-MUn, and the sense amplifier SA_RDD of the redundant unit RDD.

[0040] The switch element SWn outputs data from the bit line VBLf2_RDD of the redundant unit RDD. The memory cell MCf2_RDD of the bit line VBLf2_RDD stores data in place of the defective cell MCf2. Therefore, the switch element SWn can output the data that should be stored in the defective cell MCf2.

[0041] Similarly, when there is a memory unit MUj (j=any integer from 1 to n) including a bit line VBL with a defective cell among the bit lines VBL to be read from each of the memory units MU1 to MUn, in order to deselect the bit line VBL of the memory unit MUj, the switch elements SWj to SWn are switched to the sense amplifier SA of the memory units MUj+1 to MUn and the redundant unit RDD, respectively. That is, the switch elements SWj to SWn switch all the switch elements SWj to SWn from the switch element SWj corresponding to the memory unit MUj and the sense amplifier SAj with the bit line VBLj to the switch element SWn corresponding to the sense amplifier SAn adjacent to the sense amplifier SA_RDD. Meanwhile, the switch elements SW1 to SWj-1 remain connected to the sense amplifiers SA1 to SAj-1 of the memory units MU1 to MUj-1, similar to the switch element SW1 in FIG. 4. As a result, the switching circuit SWC selectively outputs the output signals from the sense amplifiers SA of the memory units MU1 to MUj-1, MUJ+1 to MUn, and SA_RDD of the redundant unit RDD. No signal is output from the sense amplifier SAj of the memory unit MUj.

[0042] The switch element SWn outputs data from the redundant unit RDD. The selected memory cell of the redundant unit RDD stores data in place of the defective cell. Therefore, the switch element SWn can output the data that should be stored in the defective cell.

[0043] FIG. 7 is a circuit diagram showing a configuration example of a switch element SWj. The switch element SWj includes transistors TrL and TrR. One end of the transistor TrL is connected to the output of the sense amplifier SA of the memory unit MUj, and the other end is connected to the transistor TrR. The gate of the transistor TrL is connected to the switch control circuit SSC via the inverter INV and receives an inverted signal of the control signal CNT_SW. One end of the transistor TrR is connected to the output of the sense amplifier SA of the memory unit MUj+1, and the other end is connected to the transistor TrL. The gate of the transistor TrR is connected to the switch control circuit SSC and receives the control signal CNT_SW. Therefore, the transistor TrR is in a non-conductive state (off state) when the transistor TrL is in a conductive state (on state), and is in an on state when the transistor TrL is in an off state. That is, the transistors TrR and TrL perform on / off operations complementary to each other.

[0044] The transistors TrL and TrR are connected in series between the outputs of two adjacent sense amplifiers SAj and SAj+1. Alternatively, the transistors TrL and TrR are connected in series between the outputs of two adjacent sense amplifiers SAn and SA_RDD. The node between the series-connected transistors TrL and TrR becomes the output SWout. Therefore, when the transistor TrL is in an on state, the switch element SWj outputs data from the memory unit MUj. When the transistor TrR is in an on state, the switch element SWj outputs data from the memory unit MUj+1 or the redundant unit RDD. In this way, the switch element SWj outputs data from either the sense amplifier SAj of the memory unit MUj or the sense amplifier SAj+1 of the memory unit MUj+1. However, the switch element SWn between the memory unit MUn and the redundant unit RDD is connected to the sense amplifier SAn of the memory unit MUn and the sense amplifier SA_RDD of the redundant unit RDD, and outputs data from either the sense amplifier SAn or SA_RDD.

[0045] The transistors TrL and TrR may be n-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). By using MOSFETs of the same conductivity type for the transistors TrL and TrR, the design becomes easier. The transistor TrL may be configured as a p-type MOSFET. This allows the switch element SW to be configured as a Complementary Metal Oxide Semiconductor (CMOS). In this case, the inverter INV connected to the gate of the transistor TrL is omitted.

[0046] 8 is a conceptual diagram showing a configuration example and an operation example of the switch control circuit SSC. The switch control circuit SSC includes a memory NVM, a multiplexer MUX, a decoder DC, a latch circuit LAT, a gate circuit GT, and a shift circuit SHC. For example, a CPU and software, or a logic circuit such as a PLC may be used for the switch control circuit SSC.

[0047] The memory NVM stores address information of the defective cell. The address information of the defective cell is, for example, the address ADD_GBLf of the global bit line GBL connected to the bit line VBL having the defective cell. The address information ADD_GBLf of the defective cell can be stored one by one for each address ADD_VBL (VBL0, VBL1, VBL2, . . .) of the bit line VBL. The address ADD_VBL of the bit line VBL to be read is specified by the row address RADD. Therefore, a plurality of bit lines VLB arranged in the extending direction of the word line WL (X direction in FIG. 3) are specified by the address ADD_VBL. For example, when the address ADD_VBL of the bit line VBL to be read is VBL0, one of the bit lines VBL0 at the beginning of each memory unit MU in FIG. 3 and one of VBL_RDD0 at the beginning of the redundant unit RDD are selected. Data from the multiple selected bit lines VBL0 and / or VBL_RDD0 selected in each of the multiple memory units MU is output at once from the global bit line GBL of the corresponding column. The address information ADD_GBLf of the defective cell is the address of the global bit line GBL connected to the bit line VBL having the defective cell among the multiple selected bit lines VBL0 specified by the address ADD_VBL of the bit line VBL.

[0048] When there is no defective cell in a bit line VBLk (k is an integer) connected to the same word line WL (that is, specified by the same row address RADD), the address information ADD_GBLf may be arbitrary.

[0049] Meanwhile, the memory NVM stores validity information Valid indicating the presence or absence of a defective cell for each address ADD_VBL. In an address ADD_VBL with a defective cell, the validity information Valid is set to "1", and in an address ADD_VBL without a defective cell, the validity information Valid is set to "0". For example, when the address ADD_VBL is VBLk, there is no defective cell, so the validity information Valid is "0". In this case, as described above, the address information ADD_GBLf corresponding to the bit line VBLk may be any value.

[0050] The memory NVM is, for example, a non-volatile memory such as a fuse, a flash memory, etc. The memory NVM may be provided in common to a plurality of memory units MU and a redundancy unit RDD.

[0051] The multiplexer MUX receives a row address RADD of the selected word line WL to be read from the controller CNT. The multiplexer MUX selectively transmits an address ADD_GBLf of the global bit line GBL corresponding to the address ADD_VBL of the bit line VBL to be read to the decoder DC based on the row address RADD of the selected word line WL. The multiplexer MUX also selectively transmits valid information Valid corresponding to the address ADD_VBL of the bit line VBL to be read to the gate circuit GT.

[0052] For convenience, the switching circuit SWC is assumed to be composed of 16 switch elements SW. In this case, as shown in FIG. 8, the address ADD_GBLf can be expressed by 4-bit data. The transmitted address ADD_GBLf (4-bit data) indicates the position of the global bit line GBL connected to the bit line VBL0 including the defective cell among the multiple bit lines VBL0 specified by the row address RADD. For example, when the address of the selected bit line VBL is VBL0, the multiplexer MUX transmits the address ADD_GBLf "0010" to the decoder DC. The address ADD_GBLf "0010" indicates, for example, that there is a defective cell in the bit line VBL0 connected to the global bit line GBL in the third column from the right among the global bit lines GBL.

[0053] The decoder DC decodes the address ADD_GBLf from the multiplexer MUX and transmits it to the latch circuit LAT. For example, the decoder DC converts the 4-bit data “0010” of the address ADD_GBLf into 16-bit data. This 16-bit data is conversion data that indicates the position of the switch element SWj corresponding to the global bit line GBL including the defective cell.

[0054] The latch circuit LAT latches the conversion data decoded by the decoder DC. For example, the latch circuit LAT latches 16-bit data based on the 4-bit data "0010" of the address ADD_GBLf as the conversion data. In the 16-bit data in FIG. 8, the third bit from the right is inverted to "1" and the other bits are "0". This indicates that there is a defective cell in the bit line VBL0 connected to the global bit line GBL in the third column from the right among the global bit lines GBL. The latch circuit LAT is, for example, a volatile memory such as an SRAM or a flip-flop.

[0055] Based on the validity information Valid, the gate circuit GT either validly transmits the converted data (16-bit data) latched in the latch circuit LAT to the shift circuit SHC, or invalidates the converted data latched in the latch circuit LAT and does not transmit it to the shift circuit SHC. For example, when the validity information Valid is "1", the gate circuit GT validly transmits the converted data latched in the latch circuit LAT to the shift circuit SHC. On the other hand, when the validity information Valid is "0", the gate circuit GT invalidates the converted data latched in the latch circuit LAT and does not transmit it to the shift circuit SHC. The case where the validity information Valid is "0" will be described later.

[0056] 9 is a block diagram showing a configuration example of a gate circuit. The gate circuit GT includes AND circuits Ga corresponding to each bit of the conversion data. For example, when the conversion data is 16-bit data, the gate circuit GT includes 16 AND circuits Ga. One input terminal of the AND circuits Ga inputs a corresponding bit of the conversion data. The other input terminal of the AND circuits Ga commonly inputs validity information Valid. As a result, when the validity information Valid is "1", the AND circuits Ga validly output the conversion data (16-bit data). On the other hand, when the validity information Valid is "0", the AND circuits Ga invalidate the conversion data and do not output it. Note that the configuration of the gate circuit GT is not limited to this.

[0057] The shift circuit SHC converts the conversion data sent from the gate circuit GT into a control signal CNT_SW for the transistors TrL and TrR of the switch element SW. For example, only the third bit from the right of the 16-bit data of the conversion data in FIG. 8 is inverted to "1". In this case, the shift circuit SHC generates a control signal CNT_SW for the transistor TrR, which is the same 16-bit data as the conversion data, with the third bit from the right end being "1" and the other bits being "0". In this case, in the switch element SWj, a signal that is an inverted signal of the control signal CNT_SW input to the gate of the transistor TrR is input to the gate of the transistor TrL. That is, the control signal input to the gate of the transistor TrL has the third bit from the right end being "0" and the other bits being "1". The shift circuit SHC transmits the control signal CNT_SW to the switching circuit SWC.

[0058] FIG. 10 is a block diagram showing an example of the configuration of a shift circuit. The shift circuit SHC includes an OR circuit Gor corresponding to each bit of the conversion data. For example, when the conversion data is 16-bit data, the shift circuit SHC includes 16 OR circuits Gor. One input terminal of the OR circuit Gor inputs a corresponding bit of the conversion data. The other input terminal of the OR circuit Gor inputs 0 or the output of the OR circuit Gor of the adjacent previous column. As a result, all OR circuits Gor from the OR circuit Gor of the first column that inputs 0 from the other input terminal to the OR circuit Gor that inputs "0" of the conversion data output "0". All OR circuits Gor of columns after the OR circuit Gor that inputs "1" of the conversion data output "1". As a result, the shift circuit SHC converts the conversion data from the gate circuit GT into the control signal CNT_SW of the transistor TrR. The control signal CNT_SW of the transistor TrL can be obtained by inverting the logic of the control signal CNT_SW of the transistor TrR using an inverter or the like. In FIG. 10, the output signal from the OR circuit Gor is output to the switching circuit SWC side via a buffer, but this buffer can be omitted.

[0059] When all bits of the conversion data are "0" (ie, when there are no defective cells), all control signals CNT_SW of the transistor TrR are "0", and all signals input to the gate of the transistor TrL are "1".

[0060] Also, for example, when the control signal CNT_SW for the transistor TrR has the third bit from the right end as "1" and the other bits as "0", the switching circuit SWC turns on the third transistor TrR from the right end and turns off the other transistors TrR. On the other hand, the control signal input to the gate of the transistor TrL has the third bit from the right end as "0" and the other bits as "1", so the switching circuit SWC turns off the third transistor TrL from the right end and turns on the other transistors TrL. As a result, the switching circuit SWC does not output data from the sense amplifier SA of the third column from the right. That is, the switching circuit SWC does not output data from the bit line VBL0 and the global bit line GBL in which the defective cell is located, but instead outputs data from the sense amplifier SA_RDD of the redundant unit RDD.

[0061] Similarly, when the address ADD_VBL of the selected bit line VBL specified by the row address RADD is VBL1, the multiplexer MUX transmits the address ADD_GBLf “1010” to the decoder DC. The address ADD_GBLf “1010” indicates, for example, that there is a defective cell in the bit line VBL1 connected to the global bit line GBL in the 11th column from the right among the global bit lines GBL.

[0062] When the decoder DC decodes the address ADD_GBLf "1010", the 16-bit data becomes "0000010000000000".

[0063] When the address ADD_VBL is VBL1, the validity information Valid is "1", so that the gate circuit GT validly transmits the converted data latched in the latch circuit LAT to the shift circuit SHC.

[0064] When the shift circuit SHC changes this 16-bit data, the control signal CNT_SW of the transistor TrR becomes "0000011111111111." The control signal input to the gate of the transistor TrL becomes "1111100000000000."

[0065] As a result, the switching circuit SWC turns on the first eleventh transistor TrR from the right end and turns off the other transistors TrR. On the other hand, the switching circuit SWC turns off the first eleventh transistor TrL from the right end and turns on the other transistors TrL. As a result, the switching circuit SWC does not output data from the sense amplifier SA in the eleventh column from the right. In other words, the switching circuit SWC does not output data from the bit line VBL1 and global bit line GBL in which the defective cell is located, but instead outputs data from the sense amplifier SA_RDD of the redundant unit RDD.

[0066] Similarly, when the address of the selected bit line VBL specified by the row address RADD is VBL2, the switch control circuit SSC transmits an address ADD_GBLf “1000” to the multiplexer MUX. The address ADD_GBLf “1000” indicates, for example, that there is a defective cell in the bit line VBL2 connected to the global bit line GBL in the ninth column from the right among the global bit lines GBL.

[0067] When the latch circuit LAT decodes the address ADD_GBLf "1000", the 16-bit data becomes "0000000100000000".

[0068] When the address ADD_VBL is VBL2, the validity information Valid is "1", so that the gate circuit GT validly transmits the converted data latched in the latch circuit LAT to the shift circuit SHC.

[0069] When the shift circuit SHC changes this 16-bit data, the control signal CNT_SW of the transistor TrR becomes "0000000111111111." The control signal input to the gate of the transistor TrL becomes "1111111000000000."

[0070] As a result, the switching circuit SWC turns on the first ninth transistor TrR from the right end and turns off the other transistors TrR. On the other hand, the switching circuit SWC turns off the first ninth transistor TrL from the right end and turns on the other transistors TrL. As a result, the switching circuit SWC does not output data from the sense amplifier SA in the ninth column from the right. In other words, the switching circuit SWC does not output data from the bit line VBL2 and global bit line GBL that have a defective cell, but instead outputs data from the sense amplifier SA_RDD of the redundant unit RDD.

[0071] When the address ADD_VBL of the selected bit line VBL specified by the row address RADD is VBLk, the switch control circuit SSC transmits an arbitrary address ADD_GBLf "****" to the multiplexer MUX. The arbitrary address ADD_GBLf "****" is decoded in the decoder DC via the multiplexer MUX and latched in the latch circuit LAT. However, since the valid information Valid is "0", the gate circuit GT sets all bits of the conversion data to 0 regardless of the address ADD_GBLf. In this case, the shift circuit SHC sets all bits of the control signal CNT_SW of the transistor TrR to "0". In this case, in the switch element SWj, the control signal input to the gate of the transistor TrL is set to an inverted signal of the control signal CNT_SW to the transistor TrR. That is, all bits of the control signal CNT_SW of the transistor TrL are "1".

[0072] As a result, the switching circuit SWC turns on the transistors TrL of all columns, causing the switching circuit SWC to output data from the sense amplifiers SA of all columns and not output data from the sense amplifiers SA_RDD of the redundant unit RDD.

[0073] The configuration of the shift circuit SHC is not limited to this.

[0074] In this manner, in the read operation of the memory cell array MCA having a hierarchical bit line structure, the semiconductor memory device 1 according to the present embodiment specifies the global bit line GBL connected to the local bit line VBL having the defective cell based on the row address RADD specifying the local bit line VBL. The switching circuit SWC selects the redundant unit RDD instead of the global bit line GBL connected to the local bit line VBL having the defective cell. This allows the switching circuit SWC to be switched for each local bit line VBL specified by the row address RADD in the read operation, and the global bit line GBL_RDD of the redundant unit RDD to be selected instead of the global bit line GBL connected to the local bit line VBL having the defective cell. As a result, even if multiple defective cells exist across multiple local bit lines VBL, they can be relieved by the redundant unit RDD as long as the row addresses RADD are different.

[0075] When the switching circuit SWC is fixed by a fuse or the like, the redundancy unit RDD can repair a defective cell on one global bit line GBL, but cannot repair a defective cell on another global bit line GBL. In addition, the normal local bit line VBL that shares the global bit line GBL with the local bit line VBL with the defective cell is wasted because it is not used.

[0076] In contrast, the switching circuit SWC according to the present embodiment switches the switch element SW according to the local bit line VBL designated by the row address RADD. Therefore, in this embodiment, even if multiple defective cells exist across multiple global bit lines GBL or multiple local bit lines VBL, they can be relieved by the redundant unit RDD as long as the row addresses RADD are different. In addition, the local bit line VBL with the defective cell and the normal local bit line VBL that shares the global bit line GBL can be used without waste.

[0077] However, if there are multiple defective cells in multiple bit lines VBL0 at the same row address that share a word line, they cannot be relieved by the redundant array RDD. In this case, a redundant array, redundant word lines, and redundant bit lines VBL (none of which are shown) can be added in the Y direction of Figure 3, Figure 12, or Figure 13, and a row address that selects the redundant word line can be specified instead of the row address that specifies the bit line VBL0. This makes it possible to relieve multiple defective cells even if there are multiple defective cells in multiple bit lines VBL0 at the same row address.

[0078] The gate circuit GT may be provided between the decoder DC and the latch circuit LAT. When the gate circuit GT is between the decoder DC and the latch circuit LAT, the gate circuit GT transfers data from the decoder DC to the latch circuit LAT as is when the valid information Valid is "1". When the valid information Valid is "0", the gate circuit GT does not transfer data from the decoder DC to the latch circuit LAT. Even with such a configuration, the effect of this embodiment is not lost. Second embodiment 11 is a conceptual diagram showing a configuration example and an operation example of the switch control circuit SSC according to the second embodiment. In the second embodiment, the switch control circuit SSC pre-decodes the address ADD_GBLf of the global bit line GBL having a defective cell and the address ADD_VBL of the bit line VBL in a read operation and holds them in the latch circuit LAT. In addition, the validity information Valid is also held in another latch circuit (not shown).

[0079] The multiplexer MUX transmits the address ADD_GBLf of the global bit line GBL connected to the bit line VBL to be read from the latch circuit LAT to the gate circuit GT based on the row address RADD. The gate circuit GT transmits the conversion data latched in the latch circuit LAT to the shift circuit SHC as valid based on the validity information Valid of the corresponding row address RADD, or does not transmit the conversion data latched in the latch circuit LAT to the shift circuit SHC as invalid.

[0080] In this manner, the multiplexer MUX may selectively output the address ADD_GBLf of the global bit line GBL connected to the local bit line VBL having a defective cell from the latch circuit LAT.

[0081] In this case, the multiplexer MUX is provided between the latch circuit LAT and the gate circuit GT. The gate circuit GT is provided between the multiplexer MUX and the shift circuit SHC.

[0082] Other configurations and operations of the second embodiment may be the same as the corresponding configurations and operations of the first embodiment, so that the second embodiment can obtain the same effects as the first embodiment.

[0083] (Bit line VBL arrangement) Fig. 12 is a schematic plan view showing an example of the arrangement of the bit lines VBL. Fig. 12 shows a plan view seen from the Z direction. In this example, the bit lines VBL are intermittently arranged at the intersections of the word lines WL and the global bit lines GBL. For example, the bit lines VBL are arranged at every other intersection position arranged in the X direction along the word lines WL, and at every other intersection position arranged in the Y direction along the global bit lines GBL.

[0084] In this case, the two input terminals of the sense amplifier SA are respectively connected to a pair of two adjacent global bit lines GBL electrically connected to one memory cell array. A bit line VBL connected to one word line WL selected by a row address is connected to only one of the pair of adjacent global bit lines GBL. The other of the pair of global bit lines GBL is not connected to the bit line VBL and transmits a reference signal. The sense amplifier SA_RDD also has a similar connection configuration.

[0085] In this way, the sense amplifiers SA and SA_RDD may be connected to a pair of global bit lines GBL electrically connected to one memory cell array. Such a bit line configuration is also called a folded bit line configuration.

[0086] Fig. 13 is a schematic plan view showing another arrangement example of the bit lines VBL. Fig. 13 shows a plan view seen from the Z direction. In this example, the bit lines VBL are arranged at each of the intersection positions of the word lines WL and the global bit lines GBL. For example, the bit lines VBL are arranged at each of the intersection positions arranged in the X direction along the word lines WL, and are also arranged at each of the intersection positions arranged in the Y direction along the global bit lines GBL.

[0087] In this case, the two input terminals of the sense amplifier SA are connected to a pair of two global bit lines GBL electrically connected to two memory cell arrays on both sides of the sense amplifier SA. A bit line VBL connected to one word line WL selected by a row address is connected to one of the pair of global bit lines GBL. The other of the pair of global bit lines GBL is not connected to the bit line VBL and transmits a reference signal. The sense amplifier SA_RDD also has a similar connection configuration.

[0088] In this way, the sense amplifiers SA and SA_RDD may be connected to a pair of global bit lines GBL electrically connected to the two memory cell arrays. Such a bit line configuration is also called an open-type bit line configuration.

[0089] The bit line configuration in the above embodiments may be either a folded bit line configuration or an open bit line configuration.

[0090] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0091] 1. Semiconductor memory device MCA Memory Cell Array WL Word Line VBL bit line GBL Global Bit Line SA Sense Amplifier MU Memory Unit RDD Redundancy Unit SWC Switching circuit SSC Switch control circuit CNT Controller SW Switch element TrL, TrR transistors NVM Memory DC Decoder MUX Multiplexer GT Gate Circuit LAT Latch circuit SHC Shift Circuit

Claims

1. a cell array including a plurality of memory cells; a plurality of first wirings connected in common to the plurality of memory cells arranged in a first direction in the cell array; a plurality of second wirings connected in common to the plurality of memory cells arranged in a second direction intersecting the first direction in the cell array; a plurality of third wirings provided corresponding to the plurality of second wirings arranged in a third direction intersecting the first and second directions; a first sense circuit connected to a first pair of the two third wirings; a second sense circuit connected to a second pair of the other two third wirings; a switching circuit connected to the first and second sense circuits and configured to selectively output an output signal of either the first or second sense circuit; a switch control circuit that stores the addresses of the second wiring and the third wiring connected to a defective cell, and outputs a control signal that controls the switching circuit based on the addresses of the second wiring and the third wiring connected to a selected cell to be read.

2. A plurality of the first sense circuits are provided, the switching circuit includes a plurality of switch elements provided corresponding to a plurality of the first sense circuits, and the switch element corresponding to the first sense circuit adjacent to the second sense circuit is switchable between the first sense circuit and the second sense circuit, 2. The semiconductor memory device according to claim 1, wherein the switch control circuit generates conversion data indicating the switch element corresponding to the first sense circuit connected to the third wiring connected to the defective cell from an address of the second wiring and the third wiring connected to the defective cell, and switches the switch elements from the switch element indicated by the conversion data to the switch element corresponding to the first sense circuit adjacent to the second sense circuit.

3. 3. The semiconductor memory device according to claim 2, wherein the control signal is generated based on the conversion data, includes bits corresponding to the plurality of switch elements, and a bit corresponding to a switch element to be switched among the plurality of switch elements is inverted relative to other bits.

4. 4. The semiconductor memory device according to claim 2, wherein said switch control circuit does not switch said plurality of switch elements of said switching circuit when an address corresponding to said second wiring connected to said selected cell is an address without said defective cell.

5. The switch control circuit includes: a memory for storing addresses of the second wiring and the third wiring connected to the defective cell; a multiplexer that selectively outputs, from the memory, an address of the third wiring corresponding to the second wiring connected to the selected cell, based on an address of the first wiring connected to the selected cell; a decoder for converting the address of the third line from the multiplexer into the conversion data; a latch circuit for latching the converted data; 3. The semiconductor memory device according to claim 2, further comprising: a shift circuit that generates the control signal indicating switching of the switch element from the switch element indicated by the conversion data to the switch element corresponding to the first sense circuit adjacent to the second sense circuit.

6. The switch control circuit includes: a memory for storing addresses of the second wiring and the third wiring connected to the defective cell; a decoder for converting an address of the third wiring of the memory into the conversion data; a latch circuit for latching the converted data; a multiplexer that selectively outputs the conversion data corresponding to the second wiring connected to the selected cell from the latch circuit based on an address of the first wiring connected to the selected cell; 3. The semiconductor memory device according to claim 2, further comprising: a shift circuit that generates the control signal indicating switching of the switch element from the switch element indicated by the conversion data from the multiplexer to the switch element corresponding to the first sense circuit adjacent to the second sense circuit.

7. the memory further stores validity information indicating the presence or absence of the defective cell for each address of the second wiring; 7. The semiconductor memory device according to claim 5, further comprising a gate circuit which transmits or does not transmit said converted data to said shift circuit based on said validity information.

8. 3. The semiconductor memory device according to claim 2, wherein said switch element outputs data from either one of two adjacent first sense circuits, or data from either one of said first sense circuit and said second sense circuit which are adjacent to each other.

9. 9. The semiconductor memory device according to claim 8, wherein the switch element includes two transistors connected in series between two adjacent first sense circuits or between the first sense circuit and the second sense circuit, the two transistors operating in a complementary manner to each other, and outputs data from a node between the two transistors.

10. 3. The semiconductor memory device according to claim 1, wherein said cell array includes said plurality of memory cells arranged three-dimensionally along said first, second and third wirings.

11. 3. The semiconductor memory device according to claim 1, wherein the memory cell includes a first transistor having a gate connected to the first wiring and one of a source and a drain connected to the second wiring (VBL), and a first capacitor connected to the other of the source and drain of the first transistor.

12. 3. The semiconductor memory device according to claim 1, wherein one of the pairs of third wirings connected to the first and second sense circuits transmits data in a read operation, and the other transmits a reference signal used to detect the logic of the data.

13. the two third wirings of the first pair are electrically connected to the same cell array; 3. The semiconductor memory device according to claim 1, wherein the two third wirings of the second pair are electrically connected to the same cell array.

14. the two third wirings of the first pair are electrically connected to the two cell arrays, respectively; 3. The semiconductor memory device according to claim 1, wherein the two third wirings of the second pair are electrically connected to two of the cell arrays, respectively.

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