Imaging device

Abstract

To distribute charging of sample and hold capacitances of a plurality of columns of an imaging device.SOLUTION: An imaging device includes a vertical signal line connected to a pixel, a load transistor capable of constituting a source follower with the pixel via the vertical signal line, a load transistor for setting a current flowing through the vertical signal line, a sample and hold capacitance for setting a gate bias for the load transistor, a charge transistor for setting a charge path to the sample and hold capacitance via the vertical signal line, a sample and hold transistor connected in series to the sample and hold capacitance, a mirror source transistor that performs a current mirror operation with the sample and hold transistor as a mirror destination, and a bias transistor that is connected in series to the mirror source transistor and sets a bias for the charge transistor.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present technology relates to an imaging device, and more particularly to an imaging device capable of sampling and holding a bias of a load transistor that can configure a source follower between itself and a pixel. [Background technology]

[0002] In order to reduce horizontal stripe noise, there is a method of AD converting the potential of a vertical signal line by sampling and holding the bias of a load transistor that constitutes a source follower between the pixel and the vertical signal line. For example, an imaging device has been proposed in which a sample-and-hold circuit is inserted between the gate of a transistor that supplies a bias current to an amplifier transistor in a selected row and the gate of a mirror transistor of a current source (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-109888 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above-mentioned conventional technology, mirror transistors are used centrally to charge the sample and hold capacitances of multiple columns, so if the sampling period is short, the charging of the sample and hold capacitances may not be completed in time, which may cause instability of the load current of the source follower.

[0005] The present technology was developed in view of these circumstances, and aims to distribute the charging of sample-and-hold capacitances of multiple columns of an imaging device. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect of the present technology is an imaging device including a vertical signal line connected to a pixel, a load transistor capable of forming a source follower between the pixel and the vertical signal line, a sample and hold capacitance for setting a gate bias of the load transistor, a charge transistor for setting a charge path to the sample and hold capacitance via the vertical signal line, a sample and hold transistor connected in series to the sample and hold capacitance, a mirror source transistor for performing a current mirror operation with the sample and hold transistor as a mirror destination, and a bias transistor connected in series to the mirror source transistor and setting a bias of the charge transistor. This brings about an effect that the charge path to the sample and hold capacitance is distributed for each vertical signal line.

[0007] In addition, in the first aspect, during an AD conversion period, the sample and hold transistor may be turned off, and the load transistor and the sample and hold capacitance may operate as a current source, thereby providing an effect that a current flowing through a vertical signal line is set based on a voltage of the sample and hold capacitance.

[0008] In the first aspect, during the AD conversion period, the pixel and the load transistor may form a source follower via the vertical signal line, thereby providing an effect that a potential of the vertical signal line is set based on a charge accumulated in the pixel.

[0009] In the first aspect, the sample and hold capacitance may be charged so that a gate voltage of the load transistor and a gate voltage of the mirror source transistor become equal to each other. This brings about an effect that the voltage of the sample and hold capacitance is set based on a current mirror operation.

[0010] In the first aspect, the bias transistor may set the bias so that the gate voltage of the mirror source transistor and the gate voltage of the load transistor are equal when the sample and hold transistor is on. This brings about an effect that a charging path to the sample and hold capacitance is set while the gate voltage of the load transistor and the gate voltage of the mirror source transistor are made equal to each other.

[0011] In the first aspect, the semiconductor device may further include a bypass transistor connected in parallel to the charging transistor for bypassing a current flowing through the charging transistor, thereby bringing about an effect that the gate voltage of the charging transistor and the gate voltage of the bias transistor are made to match each other, and the restriction on the voltage amplitude of the vertical signal line caused by the charging transistor is alleviated.

[0012] In the first aspect, the pixel circuit may further include a switching transistor connected in series to the charging transistor for switching a connection between the charging transistor and the vertical signal line, and a sub-bias transistor connected in parallel to the series circuit of the charging transistor and the switching transistor for setting a gate bias to a value lower than that of the charging transistor. This brings about an effect that the gate voltage of the charging transistor and the gate voltage of the bias transistor are made to match each other, while mitigating the constraint on the voltage amplitude of the vertical signal line caused by the charging transistor.

[0013] In the first aspect, a charging current to the sample and hold capacitor may be supplied from the pixel, thereby providing an effect that a charging path to the sample and hold capacitor via a vertical signal line is set.

[0014] In the first aspect, the pixel circuit may further include a current supply source connected to the vertical signal line and supplying a charging current to the sample and hold capacitor, thereby providing an effect that a charging path to the sample and hold capacitor via the vertical signal line is set without an intervening pixel.

[0015] In addition, in the first aspect, the pixel array section may include pixels arranged in a matrix in the row and column directions, the vertical signal line may be provided for each column, and the mirror source transistor and the bias transistor may be shared by a plurality of columns, thereby providing one mirror source transistor and one bias transistor to charge the sample hold capacitances of a plurality of columns. [Brief description of the drawings]

[0016] [Figure 1] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment. [Diagram 2] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment. [Diagram 3] 2 is a diagram illustrating an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. [Figure 4] 2 is a diagram illustrating an example of the configuration of a column readout circuit provided in the solid-state imaging device according to the first embodiment; FIG. [Diagram 5] 4 is a timing chart showing waveforms of sample and hold voltages according to the first embodiment. [Figure 6] 4 is a timing chart showing waveforms of various parts during operation of the solid-state imaging device according to the first embodiment. [Figure 7] FIG. 11 illustrates an example of the configuration of an imaging device according to a second embodiment. [Figure 8] FIG. 13 is a diagram illustrating an example of the configuration of an imaging device according to a third embodiment. [Figure 9] FIG. 13 is a diagram illustrating an example of the configuration of an imaging device according to a fourth embodiment. [Figure 10] FIG. 13 is a perspective view showing an example of a stack of a pixel array unit according to a fifth embodiment. [Figure 11] 1 is a block diagram showing a schematic configuration example of a vehicle control system; [Figure 12] FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (an example in which a charging transistor that sets a charging path to a sample hold capacitance via a vertical signal line and a bias transistor that sets a bias for the charging transistor are provided) 2. Second embodiment (example in which a bypass transistor is provided to bypass the current flowing through the charging transistor) 3. Third embodiment (an example in which a switching transistor that switches the connection between the charging transistor and the vertical signal line and a sub-bias transistor whose gate bias is set to a value lower than the gate bias of the charging transistor are provided) 4. Fourth embodiment (example in which charging current is supplied from pixels to sample hold capacitors via vertical signal lines) 5. Fifth embodiment (example in which semiconductor chips forming a solid-state imaging device are stacked) 6. Mobile application examples

[0018] <1. First embodiment> FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to the first embodiment.

[0019] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, or a vehicle or a drone.

[0020] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0021] The solid-state imaging device 102 converts an optical image formed on a light receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor.

[0022] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on a command from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, and the like of the solid-state imaging device 102.

[0023] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0024] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program for operating the imaging device 100 based on software. The storage unit 105 may include a read only memory (ROM), a random access memory (RAM), and a memory card.

[0025] The display unit 106 displays captured images and various information supporting the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0026] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit .

[0027] Depending on the configuration of the imaging device 100, some of the above-mentioned functions may not be present, and conversely, the imaging device 100 may further include functions that are not disclosed.

[0028] FIG. 2 is a block diagram illustrating an example of the configuration of the solid-state imaging device according to the first embodiment. As shown in FIG.

[0029] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0030] The pixel array unit 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along a row direction (also referred to as a horizontal direction) and a column direction (also referred to as a vertical direction). Each pixel 120 can form a source follower for each column between the pixel 120 and the column readout circuit 113 when reading out a signal. Each pixel 120 is connected to a horizontal drive line HSL for each row, and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel 120 for each row when reading out a signal from each pixel 120. The vertical signal line VSL transmits a potential based on a current flowing when reading out a signal from the pixel 120 to the column signal processing unit 114 for each column.

[0031] The vertical scanning circuit 112 scans the pixels 120 to be read in the column direction. The vertical scanning circuit 112 may be configured using a vertical register.

[0032] The column readout circuit 113 can configure a source follower for each column between each pixel 120 and the pixel 120 via the vertical signal line VSL when reading out a signal from the pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL based on the charge held in the pixel 120.

[0033] Here, the column readout circuit 113 can sample the gate bias of the load transistor used as a current source for setting the current of the vertical signal line VSL in a sample-and-hold capacitor and hold it during the AD conversion period. This makes it possible to make the noise caused by the mirror source transistor a fixed DC value, and to prevent random noise generated in the mirror source transistor from propagating uniformly to all columns and causing horizontal stripes.

[0034] At this time, the column readout circuit 113 charges the sample and hold capacitance via the vertical signal line VSL, and the charging path to the sample and hold capacitance can be distributed for each column. This makes it unnecessary to centrally charge the sample and hold capacitances of all columns using the mirror source transistors. This makes it possible to speed up the convergence of the sample and hold voltage used for the gate bias of the load transistor, and to reduce the variation of the sample and hold voltage for each column.

[0035] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel 120. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 120. Here, by generating a gate bias of the load transistor based on the sample hold voltage, it is possible to prevent random noise caused by the mirror source transistor from affecting the gate bias of the load transistor during the AD conversion period. At this time, noise caused by the mirror source transistor superimposed during the sampling period becomes a direct current offset, and can be removed by CDS. In addition, the column signal processing unit 114 can perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 120, and output an imaging signal Gout.

[0036] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on a comparison result between a pixel signal read from the pixel 120 and a reference signal.

[0037] The horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0038] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. The control circuit 116 can also control the sampling timing of a sample and hold capacitance that holds the gate bias of a load transistor.

[0039] FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0040] In the figure, a pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. The transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 can be MOS (Metal Oxide Semiconductor) transistors.

[0041] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode 121 is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to a power supply VDD via a reset transistor 123. The power supply VDD is connected to a vertical signal line VSL via a series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0042] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, the reset signal RST, and the selection signal SEL can be transmitted to each pixel 120 via the horizontal drive line HSL in FIG.

[0043] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode 121 is transferred to the floating diffusion FD. When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is applied to the vertical signal line VSL via the selection transistor 125 and transmitted via the vertical signal line VSL. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0044] 4 is a diagram showing a configuration example of a column readout circuit provided in the solid-state imaging device according to the first embodiment. In the diagram, an example in which three columns COL1 to COL3 are provided is shown, but three or more columns may be provided.

[0045] In the figure, the pixel array unit 111 is provided with vertical signal lines VSL1 to VSL3 for each of the columns COL1 to COL3. The vertical signal lines VSL1 to VSL3 are drawn into the column readout circuit 113 for each of the columns COL1 to COL3. The column readout circuit 113 is provided with mirror source circuits MRA, charging transistors 211 to 213, load transistors 221 to 223, sample hold transistors 231 to 233, and sample hold capacitors 241 to 243. The column readout circuit 113 may be provided with power supply transistors 311 to 313 for each of the columns COL1 to COL3. The column ADC unit 114A is provided with comparators 261 to 263 for each of the columns COL1 to COL3.

[0046] Load transistors 221 to 223 are connected to the vertical signal lines VSL1 to VSL3, respectively. The load transistors 221 to 223 can configure source followers for each of columns COL1 to COL3 between the pixel 120 and the vertical signal lines VSL1 to VSL3, respectively. Here, the load transistors 221 to 223 can set a current flowing through each of the vertical signal lines VSL1 to VSL3 based on the source followers configured for each of columns COL1 to COL3 between the pixel 120 and the vertical signal lines VSL1 to VSL3. At this time, the potential of each of the vertical signal lines VSL1 to VSL3 changes according to the current flowing based on the source followers configured for each of columns COL1 to COL3 between the pixel 120 and the vertical signal lines VSL1 to VSL3. For example, a MOS transistor can be used for each of the load transistors 221 to 223.

[0047] Further, each of the vertical signal lines VSL1 to VSL3 is connected to the inverting input of each of the comparators 261 to 263. At this time, the potential of each of the vertical signal lines VSL1 to VSL3 is applied to the inverting input of each of the comparators 261 to 263. A reference signal RAP is input to the non-inverting input of each of the comparators 261 to 263. The reference signal RAP may include, for example, a ramp signal.

[0048] Each of the power supply transistors 331 to 333 supplies a current to each of the vertical signal lines VSL1 to VSL3. Each of the power supply transistors 331 to 333 is connected between each of the vertical signal lines VSL1 to VSL3 and a power supply. Each of the power supply transistors 331 to 333 may be, for example, a MOS transistor. A sample and hold signal SH is applied to the gate of each of the power supply transistors 331 to 333. The power supply transistors 331 to 333 are an example of a current supply source as defined in the claims.

[0049] Each of the sample and hold transistors 231 to 233 samples and holds charges that generate the gate bias of each of the load transistors 221 to 223 in the sample and hold capacitors 241 to 243, respectively. Each of the sample and hold transistors 231 to 233 may be a MOS transistor. A sample and hold signal SH is applied to the gate of each of the sample and hold transistors 231 to 233.

[0050] Each of the sample and hold transistors 231 to 233 and each of the power supply transistors 331 to 333 are turned on during the sampling period. At this time, electric charges can be accumulated in the sample and hold capacitors 241 to 243 while currents are supplied to the vertical signal lines VSL1 to VSL3 via the power supply transistors 331 to 333. Furthermore, when each of the sample and hold transistors 231 to 233 is turned on, discharge paths K1 to K3 for the electric charges accumulated in each of the sample and hold capacitors 241 to 243 are set. At this time, the electric charges accumulated in each of the sample and hold capacitors 241 to 243 are discharged via the load transistors 221 to 223, respectively.

[0051] Each of the sample and hold transistors 231 to 233 and each of the power supply transistors 331 to 333 are turned off during the AD conversion period. At this time, each of the load transistors 221 to 223 and each of the sample and hold capacitors 241 to 243 can be operated as a current source. Here, current paths P1 to P3 of a current flowing based on the source follower between this current source and the pixel 120 are set. At this time, the gate bias of each of the load transistors 221 to 223 is set based on the charge accumulated in each of the sample and hold capacitors 241 to 243.

[0052] Each of the sample and hold capacitances 241 to 243 generates a sample and hold voltage for each of the columns COL1 to COL3. At this time, each of the sample and hold capacitances 241 to 243 sets a gate bias for each of the load transistors 221 to 223 based on the sample and hold voltage, and applies the gate bias to each of the load transistors 221 to 223. Each of the sample and hold transistors 231 to 233 is connected in series to the gate of each of the load transistors 221 to 223. Each of the sample and hold capacitances 241 to 243 is connected in parallel to the gate of each of the load transistors 221 to 223. Here, by having each of the sample and hold capacitances 241 to 243 sample and hold the charge that generates the gate bias for each of the load transistors 221 to 223, and then applying the gate bias to each of the load transistors 221 to 223, it is possible to prevent cross-draw noise during AD conversion.

[0053] Each of the charging transistors 211 to 213 sets a charging path R1 to R3 to each of the sample and hold capacitors 241 to 243 via the vertical signal lines VSL1 to VSL3, respectively. Each of the charging transistors 211 to 213 is connected in series to each of the load transistors 221 to 223. At this time, each of the load transistors 221 to 223 can be connected to each of the vertical signal lines VSL1 to VSL3 via each of the charging transistors 211 to 213. Also, each of the sample and hold transistors 231 to 233 can be connected between each of the charging transistors 211 to 213 and each of the sample and hold capacitors 241 to 243. Each of the charging transistors 211 to 213 may be a MOS transistor.

[0054] The mirror source circuit MRA operates as a mirror source for each of the sample and hold transistors 231 to 233. The mirror source circuit MRA includes a current source 201, a bias transistor 202, and a mirror source transistor 203.

[0055] The mirror source transistor 203 performs a current mirror operation with each of the sample and hold transistors 231 to 233 as a mirror destination. The gate of the mirror source transistor 203 is connected to the drain of the mirror source transistor 203. The mirror source transistor 203 may be a MOS transistor.

[0056] The bias transistor 202 sets the bias of each of the charging transistors 211 to 213. The bias transistor 202 is connected in series to the mirror source transistor 203. The gate of the bias transistor 202 is connected to the drain of the bias transistor 202 and the gate of each of the charging transistors 211 to 213. Here, the bias transistor 202 can set the bias so that the voltages of the nodes B, B1 to B3 are equal to each other based on the current mirror operation when the sample and hold transistors 231 to 233 are on. At this time, the gate voltage of the mirror source transistor 203 and the gate voltages of the load transistors 221 to 223 are equal to each other. Also, each of the sample and hold capacitors 241 to 243 is charged so that the gate voltage of the mirror source transistor 203 and the gate voltage of the load transistors 221 to 223 are equal to each other. The bias transistor 202 may be a MOS transistor. At this time, the aspect ratios of the bias transistor 202 and each of the charging transistors 211 to 213 may be the same. The aspect ratio of the mirror source transistor 203 and each of the load transistors 221 to 223 may be the same. Parasitic resistances 251 to 254 may be added to the wiring connected to the gate of the bias transistor 202 and the gates of each of the charging transistors 211 to 213, respectively.

[0057] The current source 201 sets the current flowing through the mirror source transistor 203 and the bias transistor 202. The current source 201 is connected to the bias transistor 202 in series.

[0058] FIG. 5 is a timing chart showing waveforms of the sample and hold voltage according to the first embodiment.

[0059] In the figure, a sampling period H1 and an AD conversion period H2 are repeated for each horizontal period. When the sample-and-hold signal SH rises, the period moves to the sampling period H1, and when the sample-and-hold signal SH falls, the period moves to the AD conversion period H2.

[0060] Here, it is assumed that the charging current to each of the sample and hold capacitances 241 to 243 is supplied centrally from the mirror source transistor 203. In this case, the output resistance of the mirror source transistor 203 is limited by 1 / gm, where gm is the mutual conductance. For this reason, the convergence speed of the sample and hold voltage VH' that sets the gate bias of each of the load transistors 221 to 223 becomes slow, and if the sampling period H1 is short, it does not converge within the sampling period H1. In addition, since the voltage drop caused by the parasitic resistances 251 to 254 differs for each of the columns COL1 to COL3, the convergence level of the sample and hold voltage VH' during the AD conversion period H2 varies.

[0061] On the other hand, it is assumed that the charging paths R1 to R3 to the sample and hold capacitances 241 to 243 are distributed and set for each of the columns COL1 to COL3. In this case, the convergence speed of the sample and hold voltage VH that sets the gate bias of each of the load transistors 221 to 223 becomes faster, and the sampling period H1 can be shortened while being converged within the sampling period H1. Also, in each of the columns COL1 to COL3, the effect of the voltage drop caused by the parasitic resistances 251 to 254 is eliminated, and the variation in the convergence level of the sample and hold voltage VH during the AD conversion period H2 is suppressed.

[0062] FIG. 6 is a timing chart showing waveforms at various parts during operation of the solid-state imaging device according to the first embodiment.

[0063] In the figure, when the sample and hold signal SH rises, a transition to the sampling period H1 occurs (time t1). At this time, the sample and hold transistors 231 to 233 and the power supply transistors 331 to 333 are turned on, and the sample and hold capacitors 241 to 243 are charged via the vertical signal lines VSL1 to VSL3, respectively.

[0064] Next, when the sample and hold signal SH falls, the AD conversion period H2 begins (time t2). At this time, the sample and hold transistors 231 to 233 and the power supply transistors 331 to 333 are turned off, and the gate bias of the load transistors 221 to 223 is set based on the sample and hold voltages of the sample and hold capacitors 241 to 243. At this time, the load transistors 221 to 223 operate as current sources. In addition, the selection signal SEL rises, and the selection transistor 125 is turned on.

[0065] Next, when the reset signal RST rises (t3), the reset transistor 123 turns on and the floating diffusion FD is reset.

[0066] Next, the reset signal RST falls (t4), turning off the reset transistor 123. At this time, the potentials of the vertical signal lines VSL1 to VSL3 are set based on the source follower operation when the P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124.

[0067] Then, in each of the comparators 261 to 263, the potential of each of the vertical signal lines VSL1 to VSL3 corresponding to the P-phase level is compared with the reference signal RAP for each of the columns COL1 to COL3. Then, the timing when the level of the reference signal RAP matches the potential of each of the vertical signal lines VSL1 to VSL3 is output as each of the comparison results VO1 to VO3. At this time, the P-phase level read out from the pixel 120 is AD converted for each of the columns COL1 to COL3 based on the counting operation until the level of the reference signal RAP matches the potential of each of the vertical signal lines VSL1 to VSL3.

[0068] Next, the transfer signal TGL rises (t5), turning on the transfer transistor 122. At this time, the charge accumulated in the photodiode 121 is transferred to the floating diffusion FD.

[0069] Next, the transfer signal TGL falls (t6), turning off the transfer transistor 122. At this time, the potentials of the vertical signal lines VSL1 to VSL3 are set based on the source follower operation when the D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124.

[0070] Then, in each of the comparators 261 to 263, the potential of each of the vertical signal lines VSL1 to VSL3 corresponding to the D-phase level is compared with the reference signal RAP for each of the columns COL1 to COL3. Then, the timing when the level of the reference signal RAP matches the potential of each of the vertical signal lines VSL1 to VSL3 is output as each of the comparison results VO1 to VO3. At this time, the D-phase level read out from the pixel 120 is AD converted for each of the columns COL1 to COL3 based on the counting operation until the level of the reference signal RAP matches the potential of each of the vertical signal lines VSL1 to VSL3.

[0071] In this manner, in the first embodiment described above, charging paths R1 to R3 are set from the vertical signal lines VSL1 to VSL3 to the sample hold capacitances 241 to 243 via the charging transistors 211 to 213 that operate as a current mirror with the bias transistor 202. This allows the charging paths R1 to R3 to the sample hold capacitances 241 to 243 to be set in a distributed manner for each column COL1 to COL3, making it unnecessary to centrally supply charging currents from the mirror source transistor 203 to the sample hold capacitances 241 to 243. This makes it possible to speed up the convergence of the sample hold voltages used for the gate bias of each load transistor 221 to 223, and to reduce pixel output errors while suppressing a decrease in frame rate. In addition, it is possible to suppress variations in the sample hold voltages for each column COL1 to COL3 caused by the parasitic resistances 251 to 254, and it is possible to suppress shading while dealing with an increase in the number of columns.

[0072] <2. Second embodiment> In the above-described first embodiment, charging paths R1 to R3 are set from the vertical signal lines VSL1 to VSL3 to the sample and hold capacitors 241 to 243 via the charging transistors 211 to 213 that operate as current mirrors with the bias transistor 202. In this second embodiment, bypass transistors are provided to bypass the currents that flow through the charging transistors 211 to 213, respectively.

[0073] FIG. 7 is a diagram illustrating an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the second embodiment.

[0074] In the figure, this imaging device is the same as the imaging device of the first embodiment described above, except that bypass transistors 271 to 273 are added. Other configurations of the imaging device of the second embodiment are similar to those of the imaging device of the first embodiment described above.

[0075] Each of the bypass transistors 271 to 273 bypasses the current flowing through each of the charging transistors 211 to 213 during the AD conversion period. Each of the bypass transistors 271 to 273 is connected in parallel to each of the charging transistors 211 to 213. Each of the bypass transistors 271 to 273 may be a MOS transistor. A sample and hold inversion signal SHX is applied to the gate of each of the bypass transistors 271 to 273. The sample and hold inversion signal SHX is an inverted signal of the sample and hold signal SH.

[0076] During the sampling period, the bypass transistors 271 to 273 are turned off. At this time, charging paths R1 to R3 are set from the vertical signal lines VSL1 to VSL3 via the charging transistors 211 to 213 to the sample and hold capacitors 241 to 243.

[0077] During the AD conversion period, each of the bypass transistors 271 to 273 is turned on. At this time, the source and drain of each of the charging transistors 211 to 213 are shorted, and current paths P1' to P3' are set from each of the vertical signal lines VSL1 to VSL3 to each of the load transistors 221 to 223 via each of the bypass transistors 271 to 273. Here, since the source and drain of each of the charging transistors 211 to 213 are shorted, it is possible to relax the constraints on the voltage amplitude of the vertical signal lines VSL1 to VSL3 accompanying the operation of each of the charging transistors 211 to 213.

[0078] For example, the gate voltage Vg1 of each of the charging transistors 211 to 213 is the sum of the gate-source voltage Vgs2 of the mirror source transistor 203 and the gate-source voltage Vgs2 of the bias transistor 202, as shown below. Vg1=Vgs2+Vgs3

[0079] Therefore, the range of drain voltage Vd1 in which each of the charging transistors 211 to 213 can operate in the saturation region can be given by the following formula, where the threshold voltage of each of the charging transistors 211 to 213 is Vth1. Vd1>Vg1-Vth1=Vgs2+Vgs3-Vth1

[0080] Assuming that Vgs2=Vgs3=0.5 V and Vth1=0.3 V as typical values, the left side of the above equation is about 0.7 V. Since the drains of the charging transistors 211 to 213 are connected to the vertical signal lines VSL1 to VSL3, respectively, the constraints of the above equation limit the voltage amplitude of each of the vertical signal lines VSL1 to VSL3.

[0081] At this time, during the AD conversion period, each of the bypass transistors 271 to 273 is turned on, and the drain and source of each of the charge transistors 211 to 213 are shorted. As a result, during the AD conversion period, the drain of each of the load transistors 221 to 223 is directly connected to each of the vertical signal lines VSL1 to VSL3, and the lower limit of each of the vertical signal lines VSL1 to VSL3 is expanded. For example, if the gate-source voltage Vgs4 of each of the load transistors 221 to 223 is set to 0.5 V and the threshold voltage Vth4 is set to 0.3 V, the range of the drain voltage Vd4> in which each of the load transistors 221 to 223 can operate in the saturation region can be given by the following formula: Vd4>Vgs4-Vth4=0.2V

[0082] Therefore, in the configuration in which the bypass transistors 271 to 273 are provided, the voltage amplitude of the vertical signal lines VSL1 to VSL3 can be increased compared to a configuration in which the bypass transistors 271 to 273 are not provided.

[0083] In this way, in the above-described second embodiment, bypass transistors 271 to 273 are provided to respectively bypass the current flowing through each of the charging transistors 211 to 213. This enables each of the charging transistors 211 to 213 to operate in the saturation region during the sampling period, while alleviating the constraints on the voltage amplitude of the vertical signal lines VSL1 to VSL3 caused by each of the charging transistors 211 to 213 during the AD conversion period.

[0084] <3. Third embodiment> In the above-described second embodiment, bypass transistors 271 to 273 are provided to bypass the currents flowing through the charging transistors 211 to 213. In this third embodiment, during the AD conversion period, the load transistors 221 to 223 are connected to the vertical signal lines VSL1 to VSL3 via sub-bias transistors whose gate biases are set to values ​​lower than the gate biases of the charging transistors 211 to 213.

[0085] FIG. 8 is a diagram illustrating an example of a configuration of an imaging device according to the third embodiment.

[0086] In the figure, this imaging device is obtained by adding switching transistors 281 to 283 and sub-bias transistors 291 to 293 to the imaging device of the above-mentioned first embodiment. Other configurations of the imaging device of the third embodiment are similar to those of the imaging device of the above-mentioned first embodiment.

[0087] Each of the switching transistors 281 to 283 switches the connection between each of the charging transistors 211 to 213 and each of the vertical signal lines VSL1 to VSL3. Each of the switching transistors 281 to 283 is connected in series to each of the charging transistors 211 to 213. At this time, each of the charging transistors 211 to 213 is connected to each of the vertical signal lines VSL1 to VSL3 via each of the switching transistors 281 to 283. Each of the switching transistors 281 to 283 may be a MOS transistor. A sample and hold signal SH is applied to the gate of each of the switching transistors 281 to 283.

[0088] A gate bias Vb of each of the sub-bias transistors 291 to 293 is set to a value lower than the gate bias of each of the charging transistors 211 to 213. At this time, the gate bias Vb is applied to the gate of each of the sub-bias transistors 291 to 293. Each of the sub-bias transistors 291 to 293 is connected in parallel to a series circuit of each of the charging transistors 211 to 213 and each of the switching transistors 281 to 283. Each of the sub-bias transistors 291 to 293 may be a MOS transistor.

[0089] During the sampling period, each of the switching transistors 281 to 283 is turned on. At this time, charging paths R1 to R3 are set from each of the vertical signal lines VSL1 to VSL3 to each of the sample and hold capacitors 241 to 243 via each of the switching transistors 281 to 283 and each of the charging transistors 211 to 213. Here, each of the charging transistors 211 to 213 and each of the sub-bias transistors 291 to 293 have a common source voltage. However, since Vg1>Vg2, if Vg1-Vg2>Vth, a current flows through each of the charging transistors 211 to 213, but no current flows through each of the sub-bias transistors 291 to 293. Vg2 is the gate voltage of each of the sub-bias transistors 291 to 293, and Vth is the threshold voltage of each of the sub-bias transistors 291 to 293.

[0090] During the AD conversion period, each of the switching transistors 281 to 283 is turned off. At this time, each of the charging transistors 211 to 213 and each of the vertical signal lines VSL1 to VSL3 are separated from each other. Then, current paths P1' to P3' are set from each of the vertical signal lines VSL1 to VSL3 to each of the load transistors 221 to 223 via each of the sub-bias transistors 291 to 293. Here, the gate voltages of each of the sub-bias transistors 291 to 293 are lowered. Therefore, each of the sub-bias transistors 291 to 293 can operate as a low-voltage cascode while relaxing the constraints on the voltage amplitude of the vertical signal lines VSL1 to VSL3 that are caused by the operation of each of the charging transistors 211 to 213.

[0091] In this manner, in the above-described third embodiment, during the AD conversion period, the load transistors 221 to 223 are connected to the vertical signal lines VSL1 to VSL3 via the sub-bias transistors. This enables the charging transistors 211 to 213 to operate in the saturation region during the sampling period, while relaxing the constraints on the voltage amplitude of the vertical signal lines VSL1 to VSL3 caused by the charging transistors 211 to 213 during the AD conversion period.

[0092] <4. Fourth embodiment> In the above-described first embodiment, each of the power supply transistors 331 to 333 serves as a current supply source to supply a charging current to each of the sample and hold capacitors 241 to 243 via the vertical signal lines VSL1 to VSL3, respectively. In this fourth embodiment, a charging current is supplied to each of the sample and hold capacitors 241 to 243 from the pixel 120 via the vertical signal lines VSL1 to VSL3.

[0093] FIG. 9 is a diagram illustrating an example of a configuration of an imaging device according to the fourth embodiment.

[0094] In the figure, this imaging device is obtained by removing power supply transistors 331 to 333 from the imaging device of the above-mentioned first embodiment. Other configurations of the imaging device of the fourth embodiment are similar to those of the imaging device of the above-mentioned first embodiment.

[0095] At this time, the charging transistors 211 to 213 set charging paths R1' to R3' from the pixel 120 to the sample and hold capacitors 241 to 243 via the vertical signal lines VSL1 to VSL3.

[0096] In this manner, in the above-described fourth embodiment, a charging current is supplied from the pixel 120 to each of the sample and hold capacitors 241 to 243 via the vertical signal lines VSL1 to VSL3. This makes it possible to disperse the charging paths R1' to R3' to each of the sample and hold capacitors 241 to 243 for each of the columns COL1 to COL3 while eliminating the need for the power supply transistors 331 to 333. This makes it possible to reduce pixel output errors while suppressing a decrease in frame rate, and also to suppress an increase in circuit size.

[0097] <5. Fifth embodiment> In the above-described first embodiment, charging paths R1 to R3 are set from the vertical signal lines VSL1 to VSL3 to the sample and hold capacitors 241 to 243 via the charging transistors 211 to 213. In this fifth embodiment, semiconductor chips each having a pixel array portion in which pixels are arranged in a matrix are stacked.

[0098] FIG. 10 is a perspective view showing an example of lamination of a pixel array unit according to the fifth embodiment.

[0099] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0100] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0101] A peripheral circuit 924 is formed in the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides in the column direction of the pixel array unit 923. The column readout circuit 925 can be provided with any of the column readout circuits according to the first to fourth embodiments described above.

[0102] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding may be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected to each other based on a Cu-Cu connection. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0103] In this manner, in the above-described fifth embodiment, the semiconductor chip 922 in which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 in which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip in which the solid-state imaging device is formed.

[0104] <7. Application examples for mobile devices> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0105] FIG. 11 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0106] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 11, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0107] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0108] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0109] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0110] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0111] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0112] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0113] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0114] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0115] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 11, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0116] FIG. 12 is a diagram showing an example of the installation position of the imaging unit 12031.

[0117] In FIG. 12, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0118] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0119] 12 shows an example of the imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0120] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0121] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0122] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0123] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0124] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 in the configuration described above. Specifically, for example, the imaging device of the above-mentioned embodiment can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to accommodate higher resolution and higher frame rates while suppressing deterioration in image quality.

[0125] The above-mentioned embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specified in the claims correspond to each other. Similarly, the matters specified in the claims and the matters in the embodiment of the present technology with the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist of the technology. In addition, the effects described in this specification are merely examples and are not limited, and other effects may be present.

[0126] The present technology can also be configured as follows. (1) a vertical signal line connected to a pixel; a load transistor capable of forming a source follower between the pixel and the vertical signal line; a sample and hold capacitor for setting a gate bias of the load transistor; a charging transistor that sets a charging path to the sample and hold capacitor via the vertical signal line; a sample and hold transistor connected in series to the sample and hold capacitor; a mirror source transistor that performs a current mirror operation with the sample-and-hold transistor as a mirror destination; a bias transistor connected in series with the mirror source transistor and setting a bias for the charging transistor; An imaging device comprising: (2) During an AD conversion period, the sample-and-hold transistor is turned off, and the load transistor and the sample-and-hold capacitor operate as a current source. The imaging device according to (1) above. (3) The imaging device according to (2), wherein during the AD conversion period, the pixel and the load transistor form a source follower via the vertical signal line. (4) The sample and hold capacitance is charged so that the gate voltage of the load transistor and the gate voltage of the mirror source transistor become equal to each other. The imaging device according to any one of (1) to (3). (5) The bias transistor sets the bias so that the gate voltage of the mirror source transistor and the gate voltage of the load transistor become equal to each other when the sample-and-hold transistor is on. The imaging device according to any one of (1) to (4). (6) a bypass transistor connected in parallel to the charging transistor for bypassing a current flowing through the charging transistor; The imaging device according to any one of (1) to (5), further comprising: (7) a switching transistor connected in series to the charging transistor and switching a connection between the charging transistor and the vertical signal line; a sub-bias transistor connected in parallel to the series circuit of the charging transistor and the switching transistor, the gate bias of which is set to a value lower than the gate bias of the charging transistor; The imaging device according to any one of (1) to (6), further comprising: (8) A charging current to the sample and hold capacitance is supplied from the pixel. The imaging device according to any one of (1) to (7). (9) a current supply source connected to the vertical signal line and supplying a charging current to the sample-and-hold capacitor; The imaging device according to any one of (1) to (7), further comprising: (10) A pixel array section in which the pixels are arranged in a matrix in row and column directions, the vertical signal line is provided for each of the columns, The mirror source transistor and the bias transistor are shared by a plurality of columns. The imaging device according to any one of (1) to (9). [Explanation of symbols]

[0127] 201 Current source 202 Bias transistor 203 Mirror source transistor 211 to 213 Charging transistor 221 to 223 Load transistors 231 to 233 Sample and hold transistors 241 to 243 sample hold capacity 251 to 254 Parasitic resistance 261 to 263 Comparator

Claims

1. A vertical signal line connected to the pixel; a load transistor capable of forming a source follower between the pixel and the vertical signal line; a sample and hold capacitor for setting a gate bias of the load transistor; a charging transistor that sets a charging path to the sample and hold capacitor via the vertical signal line; a sample and hold transistor connected in series to the sample and hold capacitor; a mirror source transistor that performs a current mirror operation with the sample-and-hold transistor as a mirror destination; a bias transistor connected in series with the mirror source transistor and setting a bias for the charging transistor; An imaging device comprising:

2. During the AD conversion period, the sample-and-hold transistor is turned off, and the load transistor and the sample-and-hold capacitance operate as a current source. The imaging device according to claim 1 .

3. The imaging device according to claim 2 , wherein during the AD conversion period, the pixel and the load transistor form a source follower via the vertical signal line.

4. The sample and hold capacitance is charged so that the gate voltage of the load transistor and the gate voltage of the mirror source transistor become equal to each other. The imaging device according to claim 1 .

5. The bias transistor sets the bias so that the gate voltage of the mirror source transistor and the gate voltage of the load transistor are equal to each other when the sample-and-hold transistor is on. The imaging device according to claim 1 .

6. A bypass transistor connected in parallel to the charging transistor for bypassing a current flowing through the charging transistor. The imaging device according to claim 1 , further comprising:

7. a switching transistor connected in series to the charging transistor and switching a connection between the charging transistor and the vertical signal line; a sub-bias transistor connected in parallel to the series circuit of the charging transistor and the switching transistor, the gate bias of which is set to a value lower than the gate bias of the charging transistor; The imaging device according to claim 1 , further comprising:

8. The charging current to the sample and hold capacitance is supplied from the pixel. The imaging device according to claim 1 .

9. a current supply source connected to the vertical signal line and supplying a charging current to the sample and hold capacitor; The imaging device according to claim 1 , further comprising:

10. a pixel array section in which the pixels are arranged in a matrix in a row direction and a column direction; the vertical signal line is provided for each of the columns, The mirror source transistor and the bias transistor are shared by a plurality of columns. The imaging device according to claim 1 .

Images