Printed wiring board, printed circuit board, electronic apparatus, and head-mounted display

Abstract

To provide a printed wiring board that can reduce skew in a differential signal, as well as a printed circuit board and a head-mounted display using the same.SOLUTION: A printed wiring board has: a substrate that has a first conductor layer and a second conductor layer which are laminated, and a third conductor layer laminated on the outside of any one of the first conductor layer and the second conductor layer; first differential signal wiring that is provided on the first conductor layer, and has first wiring and second wiring; second differential signal wiring that is provided on the second conductor layer, and has third wiring and fourth wiring; a first via that is provided between the first conductor layer and the second conductor layer, and connects the first wiring and the third wiring to each other; and a second via that is provided between the first conductor layer and the second conductor layer, and connects the second wiring and the fourth wiring to each other. The third conductor layer is provided with a first clearance to include the first via and the second via in plan view seen perpendicularly to the substrate.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present invention relates to a printed wiring board, a printed circuit board, an electronic device, and a head mounted display. [Background technology]

[0002] Conventionally, with the digitalization and high-speed of electronic devices, differential transmission methods have been widely used for high-frequency digital signals. Differential transmission methods are characterized by their resistance to external noise and their ease of high-speed transmission. However, if there is a difference in the length of the two signal lines that transmit the differential signals, a phase shift called skew occurs between the differential signals, which can deteriorate the transmission characteristics.

[0003] For this reason, in the differential transmission method, it is necessary to devise a way to physically make the lengths of the two signal wires as close to equal as possible. However, on the same printed wiring board, the positions of the output terminals for the P (Positive / positive logic) and N (Negative / negative logic) signals of a device such as an IC (Integrated Circuit) do not necessarily match the positions of the P and N signals of the connector. This means that there are places where the signal wires must be swapped, and there are likely to be places where there is a difference in the wiring length between the signal wires transmitting the P signals and the signal wires transmitting the N signals on each layer, which results in large skew.

[0004] In Patent Document 1, it is proposed to prevent the occurrence of skew by devising an arrangement of vias and wiring for switching wiring between P and N signals, and by switching the wiring while maintaining the equal length of the wiring for each layer and the symmetry of the vias, making the wiring equal in length. In addition, meander wiring may be used to maintain the equal length for each layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-287750 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, the technology disclosed in Patent Document 1 requires a large number of vias and therefore a long wiring length. Therefore, the technology disclosed in Patent Document 1 has problems such as an increase in wiring area and a deterioration in transmission characteristics (transmission characteristics). In addition, when meander wiring is used to maintain the general equal length of each layer, similar problems occur due to the increase in wiring length.

[0007] An object of the present invention is to provide a printed wiring board capable of reducing skew in differential signals, and a printed circuit board, electronic device, and head mounted display using the same. [Means for solving the problem]

[0008] According to one aspect of the present invention, there is provided a printed wiring board having a substrate having a first conductor layer and a second conductor layer stacked together, and a third conductor layer stacked on the outside of either the first conductor layer or the second conductor layer, a first differential signal wiring provided on the first conductor layer and having a first wiring and a second wiring, a second differential signal wiring provided on the second conductor layer and having a third wiring and a fourth wiring, a first via provided between the first conductor layer and the second conductor layer and connecting the first wiring and the third wiring, and a second via provided between the first conductor layer and the second conductor layer and connecting the second wiring and the fourth wiring, wherein a first clearance is provided in the third conductor layer so as to include the first via and the second via in a plan view perpendicular to the substrate. Effect of the Invention

[0009] According to the present invention, it is possible to reduce skew in differential signals. [Brief description of the drawings]

[0010] [Figure 1A] 1 is a transparent top view showing a printed wiring board according to a first embodiment. [Figure 1B] 1 is a cross-sectional view showing a cross section of a printed wiring board according to a first embodiment. [Figure 1C] 4 is a cross-sectional view showing another example of a cross section of the printed wiring board according to the first embodiment. FIG. [Figure 2A] 1 is a plan view showing a conductor layer of a printed wiring board according to a first embodiment. [Figure 2B] 1 is a plan view showing a conductor layer of a printed wiring board according to a first embodiment. [Figure 2C] 1 is a plan view showing a conductor layer of a printed wiring board according to a first embodiment. [Figure 2D] 1 is a plan view showing a conductor layer of a printed wiring board according to a first embodiment. [Figure 2E] 1 is a plan view showing a conductor layer of a printed wiring board according to a first embodiment. [Figure 3A] FIG. 11 is a transparent top view showing a printed wiring board according to a second embodiment. [Figure 3B] FIG. 11 is a plan view showing a conductor layer of a printed wiring board according to a second embodiment. [Figure 3C] FIG. 11 is a plan view showing a conductor layer of a printed wiring board according to a second embodiment. [Figure 3D] FIG. 11 is a plan view showing a conductor layer of a printed wiring board according to a second embodiment. [Figure 3E] FIG. 11 is a plan view showing a conductor layer of a printed wiring board according to a second embodiment. [Figure 3F] FIG. 11 is a plan view showing a conductor layer of a printed wiring board according to a second embodiment. [Figure 4] FIG. 11 is a plan view illustrating a clearance in a printed wiring board according to a second embodiment. [Figure 5A] FIG. 11 is a transparent top view showing a printed wiring board according to a third embodiment. [Figure 5B] FIG. 11 is a plan view showing a conductor layer of a printed wiring board according to a third embodiment. [Figure 5C]FIG. 11 is a plan view showing a conductor layer of a printed wiring board according to a third embodiment. [Figure 5D] FIG. 11 is a plan view showing a conductor layer of a printed wiring board according to a third embodiment. [Figure 5E] FIG. 11 is a plan view showing a conductor layer of a printed wiring board according to a third embodiment. [Figure 5F] FIG. 11 is a plan view showing a conductor layer of a printed wiring board according to a third embodiment. [Figure 6] 13 is a plan view illustrating a clearance in a printed wiring board according to a third embodiment. FIG. [Figure 7A] FIG. 11 is a transparent top view showing a printed wiring board according to a fourth embodiment. [Figure 7B] FIG. 13 is a plan view showing a conductor layer of a printed wiring board according to a fourth embodiment. [Figure 7C] FIG. 13 is a plan view showing a conductor layer of a printed wiring board according to a fourth embodiment. [Figure 7D] FIG. 13 is a plan view showing a conductor layer of a printed wiring board according to a fourth embodiment. [Figure 7E] FIG. 13 is a plan view showing a conductor layer of a printed wiring board according to a fourth embodiment. [Figure 7F] FIG. 13 is a plan view showing a conductor layer of a printed wiring board according to a fourth embodiment. [Figure 8A] FIG. 13 is a transparent top view showing a printed wiring board according to a fifth embodiment. [Figure 8B] FIG. 13 is a plan view showing a conductor layer of a printed wiring board according to a fifth embodiment. [Figure 8C] FIG. 13 is a plan view showing a conductor layer of a printed wiring board according to a fifth embodiment. [Figure 8D] FIG. 13 is a plan view showing a conductor layer of a printed wiring board according to a fifth embodiment. [Figure 8E] FIG. 13 is a plan view showing a conductor layer of a printed wiring board according to a fifth embodiment. [Figure 8F] FIG. 13 is a plan view showing a conductor layer of a printed wiring board according to a fifth embodiment. [Figure 9]FIG. 13 is a plan view illustrating a clearance in a printed wiring board according to a fifth embodiment. [Figure 10A] FIG. 13 is a transparent top view showing a printed wiring board according to a sixth embodiment. [Figure 10B] FIG. 13 is a cross-sectional view showing a cross section of a printed wiring board according to a sixth embodiment. [Figure 11A] FIG. 13 is a side view showing a head mounted display as an example of an electronic device according to a seventh embodiment. [Figure 11B] FIG. 13 is a front view showing a head mounted display as an example of an electronic device according to a seventh embodiment. [Figure 12A] 1 is a transparent top view showing a printed wiring board according to an embodiment of the present invention; [Figure 12B] FIG. 11 is a transparent top view showing a printed wiring board according to a comparative example. [Figure 12C] 4 is a diagram showing waveforms of a P signal and an N signal in the first embodiment. FIG. [Figure 12D] FIG. 13 is a diagram showing waveforms of a P signal and an N signal in a comparative example. [Figure 13] 1 is a graph showing the transmission characteristics of Example 1 and a comparative example. [Figure 14A] 1 is a schematic diagram showing equal length wiring and non-equal length wiring of differential signal wiring in a multilayer printed wiring board. [Figure 14B] 1 is a schematic diagram showing equal length wiring and non-equal length wiring of differential signal wiring in a multilayer printed wiring board. [Figure 14C] 1 is a schematic diagram showing equal length wiring and non-equal length wiring of differential signal wiring in a multilayer printed wiring board. [Figure 14D] 1 is a schematic diagram showing equal length wiring and non-equal length wiring of differential signal wiring in a multilayer printed wiring board. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] [Background technology] Prior to describing the embodiments of the present invention, the wiring of differential signal wiring in a multilayer printed wiring board will be described with reference to Figures 14A to 14D. Figures 14A to 14D are schematic diagrams illustrating non-equal length wiring and equal length wiring of differential signal wiring in a multilayer printed wiring board.

[0012] 14A is a top perspective view of a multilayer printed wiring board showing differential signal wiring in which the P-side wiring and the N-side wiring are interchanged. The P-side wiring is a wiring that transmits a P (Positive / positive logic) signal in the differential signal. The N-side wiring is a wiring that transmits an N (Negative / negative logic) signal in the differential signal.

[0013] As shown in FIG. 14A, multilayer printed wiring board 300 is provided with wirings 311 and 312 that are provided in the same layer and that constitute differential signal wiring, and wirings 313 and 314 that are provided in the same layer and that constitute differential signal wiring. Wirings 311 and 312 and wirings 313 and 314 are provided in different layers. Wiring 311 is a P-side wiring and is connected to wiring 313 that is a P-side wiring provided in a layer different from wiring 311 through via 321. Wiring 312 is an N-side wiring and is connected to wiring 314 that is an N-side wiring provided in a layer different from wiring 312 through via 322. Note that in FIG. 14A, wirings 311 and 312 are shown by thick dashed lines, and wirings 313 and 314 are shown by thick solid lines, thereby distinguishing wirings 311 and 312 and wirings 313 and 314 that are provided in different layers.

[0014] In Fig. 14A, on the left side of the paper, P-side wiring 311 and N-side wiring 312 are arranged in order from top to bottom of the paper, while on the right side of the paper, P-side wiring 313 and N-side wiring 314 are arranged in order from bottom to top of the paper. Therefore, the differential signal wiring shown in Fig. 14A is wiring in which the P-side wiring and the N-side wiring are swapped in different layers. Since the P-side wiring and the N-side wiring are swapped in this way, in the differential signal wiring shown in Fig. 14A, the symmetry of the wiring for each layer is lost and the wiring lengths of the P-side wiring and the N-side wiring are different, resulting in a state in which skew occurs.

[0015] As a countermeasure against skew, a method of making the wiring lengths of each layer equal is generally used. Fig. 14B is a top perspective view of a multilayer printed wiring board in which equal-length wiring has been performed on the wiring shown in Fig. 14A. As shown in Fig. 14B, wiring 311 and wiring 312 provided on the same layer are made to have the same length by adding redundant wiring. Also, wiring 313 and wiring 314 provided on the same layer are made to have the same length by adding redundant wiring. In the case shown in Fig. 14B, the skew is improved, but the wiring area increases and the wiring length also increases, resulting in a deterioration in the transmission characteristics of the differential signal.

[0016] FIG. 14C is a top perspective view of a multilayer printed wiring board showing differential signal wiring with an exchange of P-side wiring and N-side wiring, different from that in FIG. 14A. In FIG. 14A, the differential signal wiring composed of wirings 311 and 312 and the differential signal wiring composed of wirings 313 and 314 are arranged on the left and right sides of the paper. In contrast, in FIG. 14C, the differential signal wiring composed of wirings 313 and 314 is arranged so as to be bent 90 degrees to the right side with respect to the differential signal wiring composed of wirings 311 and 312 on the lower side of the paper. In the case shown in FIG. 14C as well, the P-side and N-side are exchanged in the relative positions of the P-side wiring 313 and N-side wiring 314 with respect to the relative positions of the P-side wiring 311 and N-side wiring 312. Therefore, the differential signal wiring shown in FIG. 14C is also exchanged between the P-side wiring and the N-side wiring in different layers. FIG. 14D is a transparent top view of a multilayer printed wiring board in which equal-length wiring has been performed on the wiring shown in FIG. 14C.

[0017] The printed wiring board according to the embodiment of the present invention described below reduces the skew in the differential signal without increasing the wiring length or area of ​​the differential signal wiring, thereby minimizing deterioration of the transmission characteristics, such as the transmittance characteristics, of the differential signal.

[0018] [First embodiment] A printed wiring board according to a first embodiment of the present invention will be described with reference to Figs. 1A to 2E. Fig. 1A is a top perspective view showing a printed wiring board according to this embodiment. Fig. 1B is a cross-sectional view showing a cross section of the printed wiring board according to this embodiment. Fig. 1C is a cross-sectional view showing another example of a cross section of the printed wiring board according to this embodiment. Figs. 2A to 2E are plan views showing each conductor layer of the printed wiring board according to this embodiment. Fig. 1A and Figs. 3A to 3F are views seen perpendicular to the printed wiring board. Figs. 1B and 1C show a vertical cross section along line AA' in Fig. 1A.

[0019] 1A and 1B, the printed wiring board 10 according to the present embodiment is a multilayer printed wiring board having five laminated conductor layers 41, 42, 43, 44, and 45, and has wirings 11, 12, wirings 13, 14, and vias 21, 22. The number of conductor layers in the printed wiring board 10 is not limited to five. The number of conductor layers in the printed wiring board 10 may be three or more layers including the conductor layer 42 on which the wirings 11 and 12 are provided, the conductor layer 44 on which the wirings 13 and 14 are provided, and at least one of the conductor layers 41 and 45.

[0020] The conductor layers 41, 42, 43, 44, and 45 are laminated in this order from the upper surface, which is the first surface of the printed wiring board 10, to the lower surface, which is the second surface, via insulating layers 51, 52, 53, 54, and 55. That is, the conductor layer 41 and the conductor layer 42 are laminated via the insulating layer 51. The conductor layer 42 and the conductor layer 43 are laminated via the insulating layer 52. The conductor layer 43 and the conductor layer 44 are laminated via the insulating layer 53. The conductor layer 44 and the conductor layer 45 are laminated via the insulating layer 54. The conductor material constituting the conductor layers 41, 42, 43, 44, and 45 is not particularly limited, but is copper or the like. The laminate of the conductor layers 41, 42, 43, 44, and 45 via the insulating layers 51, 52, 53, 54, and 55 is a plate-shaped substrate that becomes the main body of the printed wiring board 10. This substrate may be a rigid substrate or a flexible substrate.

[0021] The vias 21 and 22 are provided adjacent to each other in the insulating layers 51, 52, and 53 between the conductor layers 42 and 44. The vias 21 and 22 have pad portions in the same layers as the conductor layers 42, 43, and 44, respectively. The via 21 electrically connects the wiring 11 and the wiring 13. The via 22 electrically connects the wiring 12 and the wiring 14.

[0022] The wirings 11 and 12 are a pair of wirings constituting a differential signal wiring for transmitting a differential signal, and are provided in the same layer as each other on the conductor layer 42. The conductor layer 42 on which the wirings 11 and 12 are provided is a layer corresponding to the ends of the vias 21 and 22 on the upper surface side of the printed wiring board 10, and is the uppermost layer among the layers in which the vias 21 and 22 exist.

[0023] The wirings 13 and 14 are a pair of wirings constituting a differential signal wiring for transmitting a differential signal, and are provided in the same layer as each other on the conductor layer 44. The conductor layer 44 on which the wirings 13 and 14 are provided is a layer corresponding to the ends of the vias 21 and 22 on the lower surface side of the printed wiring board 10, and is the lowest layer among the layers on which the vias 21 and 22 exist. The wirings 13 and 14 are arranged so as to be bent, for example, by 90° with respect to the wirings 11 and 12.

[0024] In this way, the differential signal wiring having the wires 11 and 12 and the differential signal wiring having the wires 13 and 14 are provided in different layers. In Fig. 1A and subsequent figures, the wires 11 and 12 are shown by thick dashed lines and the wires 13 and 14 are shown by thick solid lines to distinguish between the wires 11 and 12 and the wires 13 and 14, which are provided in different layers.

[0025] The wiring 11 is connected to the wiring 13 through the via 21. The wiring 12 is connected to the wiring 14 through the via 22. For example, the wirings 11 and 13 are P-side wirings, and the wirings 12 and 14 are N-side wirings. The relative positions of the wirings 11 and 12 and the wirings 13 and 14 are interchanged. Due to such interchange of the relative positions of the wirings, the wiring 12, which is one of the wirings 11 and 12, and the wiring 13, which is one of the wirings 13 and 14, have an intersecting region 61 in a plan view perpendicular to the printed wiring board 10. Since the wirings 12 and 14 are arranged to intersect in this way, the wiring lengths of the wirings 11 and 13 and the wiring lengths of the wirings 12 and 14 are equal to each other. The wiring lengths of the wirings 11 and 13 and the wiring lengths of the wirings 12 and 14 may be different from each other.

[0026] In this embodiment, the wiring 12 and the wiring 14 intersect in a plan view, but this is not necessarily limited to this. The wirings 11, 12, 13, and 14 may be arranged such that one of the wirings 11 and 12 intersects one of the wirings 13 and 14 in a plan view. The wirings 11, 12, 13, and 14 may be arranged such that the wiring 11 does not intersect with either of the wirings 13 and 14, and the wiring 12 does not intersect with either of the wirings 13 and 14, in a plan view, as in the fourth and fifth embodiments described later.

[0027] Conductive layers 42, 43, and 44, which are layers in which vias 21 and 22 exist, each have a clearance 1 of size S around the vias 21 and 22. Conductive layer 41, which is stacked adjacently to conductor layer 42, which is the top layer in which vias 21 and 22 exist, via insulating layer 51, also has a clearance 1 of size S. Conductive layer 45, which is stacked adjacently to conductor layer 44, which is the bottom layer in which vias 21 and 22 exist, via insulating layer 54, also has a clearance 1 of size S around the vias 21 and 22 to include the vias 21 and 22. The clearances 1 in conductor layers 41, 42, 43, 44, and 45 are regions in which no conductors are provided in conductor layers 41, 42, 43, 44, and 45, respectively.

[0028] 1C, the conductor layer 41 may not be provided adjacent to the outer side of the conductor layer 42, which is the uppermost layer in which the vias 21 and 22 are present. Although not shown, the conductor layer 45 may not be provided adjacent to the outer side of the conductor layer 44, which is the lowermost layer in which the vias 21 and 22 are present. That is, it is sufficient that at least one of the conductor layers 41 and 45 having the clearance 1 is provided, and both the conductor layers 41 and 45 may be provided, or only one of the conductor layers 41 and 45 may be provided, or only the other of the conductor layers 41 and 45 may be provided.

[0029] 2A to 2E are plan views of the layers of printed wiring board 10 according to the present embodiment, viewed perpendicularly to printed wiring board 10. FIG.

[0030] 2A shows a conductor layer 41 that is stacked adjacently to the outer side of a conductor layer 42, which is the uppermost layer in which vias 21 and 22 exist, with an insulating layer 51 interposed therebetween. As shown in Fig. 2A, a clearance 1 is provided in the conductor layer 41 so as to correspond to the periphery of the vias 21 and 22 and to include the vias 21 and 22. The conductor layer 41 around the clearance 1 serves as a ground plane (GND plane) 31.

[0031] 2B shows the conductor layer 42, which is the uppermost layer in which the vias 21 and 22 exist. As shown in FIG. 2B, the conductor layer 42 has a clearance 1 around the vias 21 and 22. The conductor layer 42 also has an opening 2 around and between the wirings 11 and 12 connected to the vias 21 and 22, respectively, so as to connect to the clearance 1. The conductor layer 41 around the clearance 1 and the opening 2 forms a GND plane 31.

[0032] 2C shows a conductor layer 43, which is an intermediate layer in which the vias 21 and 22 exist. As shown in Fig. 2C, the conductor layer 43 has a clearance 1 around the vias 21 and 22. The conductor layer 43 around the clearance 1 serves as a GND plane 31.

[0033] 2D shows the conductor layer 44, which is the lowest layer in which the vias 21 and 22 exist. As shown in FIG. 2D, the conductor layer 44 has a clearance 1 around the vias 21 and 22. The conductor layer 44 also has an opening 3 around and between the wirings 13 and 14 connected to the vias 21 and 22, respectively, so as to connect to the clearance 1. The conductor layer 44 around the clearance 1 and the opening 3 forms a GND plane 31.

[0034] 2E shows a conductor layer 45 that is stacked adjacent to the outer side of the conductor layer 44, which is the lowest layer in which the vias 21 and 22 are present, with an insulating layer 54 interposed therebetween. As shown in FIG. 2E, the conductor layer 45 has a clearance 1 that corresponds to the periphery of the vias 21 and 22 and includes the vias 21 and 22. The conductor layer 45 around the clearance 1 serves as a GND plane 31.

[0035] The clearances 1 of the conductor layers 41, 42, 43, 44, and 45 have the same planar shape in a plan view perpendicular to the printed wiring board 10, and are arranged to overlap each other so as to match and include a region 61. In the plan view, the clearances 1 are provided in the conductor layers 41, 42, 43, 44, and 45 so as to include the vias 21 and 22 and the region 61 where the wiring 12 and the wiring 13 intersect. In addition, in the plan view, the clearances 1 have a planar shape of an outer shape in which two arcs at an equal distance from the outer periphery of the vias 21 and 22 having a circular planar shape are connected by two parallel line segments. The planar shape of the clearances 1 is not particularly limited, and may be various shapes such as a polygon such as a rectangle, an ellipse, or a combination thereof, depending on the layout of the wirings 11, 12, 13, and 14, the vias 21 and 22, etc.

[0036] In this embodiment, the clearance 1 is provided up to the conductor layers 41, 45 adjacent to the outer side of the uppermost and lowermost conductor layers 42, 44 in which the vias 21, 22 exist, for the wirings 11, 12 and wirings 13, 14 in which the relative positions of the P-side wiring and the N-side wiring are interchanged. The clearance 1 is provided in the conductor layers 41, 45 so as to include the vias 21, 22 in a plan view perpendicular to the printed wiring board 10, and to include the region 61 in which the wirings 12 and 13 intersect. Such clearance 1 can enhance the coupling between the vias 21, 22, the coupling between the wirings 11, 12, the coupling between the wirings 13, 14, the coupling between the vias 21, 22 and the wirings 11, 12, and the coupling between the vias 21, 22 and the wirings 13, 14. As a result, a crosstalk-like return current occurs between the P-side wiring and the N-side wiring, and this effect can reduce the skew between the P signal and the N signal in the differential signal.

[0037] In this manner, according to the present embodiment, it is possible to reduce the skew in the differential signals, thereby minimizing the deterioration of the transmission characteristics, such as the transmittance characteristics, of the differential signals. Since the present embodiment does not require equal-length wiring, the wiring length and area of ​​the wiring on the printed wiring board 10 are not increased.

[0038] [Second embodiment] A printed wiring board according to a second embodiment of the present invention will be described with reference to Figs. 3A to 4. Fig. 3A is a top perspective view showing the printed wiring board according to this embodiment. Figs. 3B to 3F are plan views showing each conductor layer of the printed wiring board according to this embodiment. Fig. 4 is a plan view explaining clearances in the printed wiring board according to this embodiment. Figs. 3A to 4 are views seen perpendicularly to the printed wiring board. Note that the same reference numerals are used for components similar to those in the first embodiment, and descriptions thereof will be omitted or simplified.

[0039] 3A, the basic configuration of the printed wiring board 10 according to the present embodiment is similar to that of the first embodiment. In the present embodiment, like the first embodiment, the wirings 11 and 12 are connected to the wirings 13 and 14 through the vias 21 and 22. Also, in the present embodiment, like the first embodiment, there is an intersecting region 61 between the wiring 12, which is one of the wirings 11 and 12, and the wiring 13, which is one of the wirings 13 and 14, in a plan view perpendicular to the printed wiring board 10.

[0040] Printed wiring board 10 according to the present embodiment differs from the first embodiment in terms of the range of clearance 1. Figures 3B to 3F show clearance 1 provided in conductor layers 41, 42, 43, 44, and 45 in printed wiring board 10 according to the present embodiment.

[0041] 3B shows a conductor layer 41 that is stacked adjacently to the outer side of conductor layer 42, which is the uppermost layer in which vias 21 and 22 are present, with an insulating layer 51 interposed therebetween. As shown in FIG. 3B, the conductor layer 41 is provided with clearance 1 including clearance 1a in a manner that corresponds to the periphery of vias 21 and 22 and includes vias 21 and 22. The conductor layer 41 around clearances 1 and 1a forms a GND plane 31.

[0042] 3C shows the conductor layer 42, which is the uppermost layer in which the vias 21 and 22 exist. As shown in FIG. 3C, the conductor layer 42 has clearances 1 including a clearance 1a around the vias 21 and 22. The conductor layer 42 also has openings 2 around and between the wirings 11 and 12 connected to the vias 21 and 22, respectively, so as to connect to the clearance 1. The conductor layer 42 around the clearances 1 and 1a and the openings 2 forms a GND plane 31.

[0043] 3D shows a conductor layer 43, which is an intermediate layer in which the vias 21 and 22 exist. As shown in FIG. 3D, the conductor layer 43 has clearances 1 including clearances 1a around the vias 21 and 22. The conductor layer 43 around the clearances 1 and 1a forms a GND plane 31.

[0044] 3E shows the conductor layer 44, which is the lowest layer in which the vias 21 and 22 are present. As shown in FIG. 3E, the conductor layer 44 has clearances 1 including a clearance 1a around the vias 21 and 22. The conductor layer 44 also has openings 3 around and between the wirings 13 and 14 connected to the vias 21 and 22, respectively, so as to connect to the clearance 1. The conductor layer 44 around the clearances 1 and 1a and the openings 3 forms a GND plane 31.

[0045] 3F shows a conductor layer 45 that is stacked adjacently to the outer side of the conductor layer 44, which is the lowest layer in which the vias 21 and 22 are present, with an insulating layer 54 interposed therebetween. As shown in FIG. 3F, the conductor layer 45 is provided with a clearance 1 including a clearance 1a in a manner that corresponds to the periphery of the vias 21 and 22 and includes the vias 21 and 22. The conductor layer 45 around the clearances 1 and 1a forms a GND plane 31.

[0046] The clearances 1 including the clearances 1a of the conductor layers 41, 42, 43, 44, and 45 have the same planar shape and are arranged to match each other in a plan view perpendicular to the printed wiring board 10. The clearances 1 are provided in each of the conductor layers 41, 42, 43, 44, and 45 so as to include the vias 21 and 22 in the plan view and to include a region 61 where the wiring 12 and the wiring 13 intersect.

[0047] Here, the details of the clearance 1 including the clearance 1a according to this embodiment will be described with reference to FIG. 4. As shown in FIG. 4, in a plan view perpendicular to the printed wiring board 10, the clearance 1 includes the vias 21 and 22, and also includes a region 61 where the wiring 12 and the wiring 13 intersect. The clearance 1 is set so that the vias 21 and 22 are spaced apart from the GND plane 31 of each layer by a distance D111. Furthermore, the clearance 1a included in the clearance 1 is set with respect to the wirings 11, 12, 13, and 14 based on the distance D101 between the vias 21 and 22, as described below. Here, the distance D101 between the vias 21 and 22 is the distance between the pad portion of the via 21 and the pad portion of the via 22 in a plan view perpendicular to the printed wiring board 10.

[0048] In each of the pair of wires 11, 12 and the pair of wires 13, 14, the wire width and the spacing between the wires are different between the extension parts for the vias 21, 22 and the main parts away from the vias 21, 22. In the main parts away from the vias 21, 22, the wire width and the spacing between the wires are set to a constant width and a constant spacing determined for each layer as differential signal wiring. That is, the wires 11, 12 have extension parts for the vias 21, 22 where the widths of the wires and the spacing between the wires vary, and a main part where the widths of the wires and the spacing between the wires are constant. Also, the wires 13, 14 have extension parts for the vias 21, 22 where the widths of the wires and the spacing between the wires vary, and a main part where the widths of the wires and the spacing between the wires are constant.

[0049] The clearance 1a is set as follows based on the distance D101 between the vias 21 and 22 in a plan view perpendicular to the printed wiring board 10. That is, the clearance 1a is set to a range in which the distance D114 of the overlapping with the wirings 11 and 12, which are set to a constant wiring width and a constant spacing between the wirings, is preferably larger than the distance D101, as viewed from the drawn-out portion of the vias 21 and 22. The clearance 1a is also set to a range in which the distance D114 of the overlapping with the wirings 13 and 14, which are set to a constant wiring width and a constant spacing between the wirings, is preferably larger than the distance D101, as viewed from the drawn-out portion of the vias 21 and 22. Furthermore, the clearance 1a is set so that at least the distance D112 is provided between the wirings 11, 12 and the wirings 13 and 14 and the GND plane 31 of each layer. It is sufficient that clearance 1a is set to an extent that, in a plan view viewed perpendicularly to printed wiring board 10, it overlaps with wirings 11, 12, 13, and 14 that are set to a constant wiring width and constant spacing between wirings.

[0050] As in this embodiment, the clearance 1 can be set to include the clearance 1a. As a result, according to this embodiment, the skew between the P signal and the N signal in the differential signal can be further reduced.

[0051] [Third embodiment] A printed wiring board according to a third embodiment of the present invention will be described with reference to Figs. 5A to 6. Fig. 5A is a top perspective view showing the printed wiring board according to this embodiment. Figs. 5B to 5F are plan views showing each conductor layer of the printed wiring board according to this embodiment. Fig. 6 is a plan view explaining clearances in the printed wiring board according to this embodiment. Figs. 5A to 6 are views seen perpendicularly to the printed wiring board. Note that the same reference numerals are used for components similar to those in the first and second embodiments, and descriptions thereof will be omitted or simplified.

[0052] 5A, the basic configuration of the printed wiring board 10 according to this embodiment is similar to that of the second embodiment. In this embodiment, like the second embodiment, the wirings 11 and 12 are connected to the wirings 13 and 14 through the vias 21 and 22. Also in this embodiment, like the second embodiment, there is an intersecting region 61 between the wiring 12, which is one of the wirings 11 and 12, and the wiring 13, which is one of the wirings 13 and 14, in a plan view perpendicular to the printed wiring board 10.

[0053] The printed wiring board 10 according to this embodiment differs from the first embodiment in terms of the positional relationship between the vias 21 and 22 and the positional relationship between the wires 11 and 12 and the wires 13 and 14. In this embodiment, the wires 13 and 14 are arranged so as to bend at an obtuse angle with respect to the wires 11 and 12. The angle at which the wires 13 and 14 are bent with respect to the wires 11 and 12 is not limited to an obtuse angle, and may be 90° as in the first embodiment, or may be an acute angle. The vias 21 and 22 are arranged in a positional relationship according to the angle at which the wires 13 and 14 are bent with respect to the wires 11 and 12.

[0054] 5B to 5F show clearances 1 provided in conductor layers 41, 42, 43, 44, and 45 in printed wiring board 10 according to this embodiment. In this embodiment, clearances 1 including clearance 1a are provided, similarly to the second embodiment.

[0055] 5B shows a conductor layer 41 adjacent to the outer side of the conductor layer 42, which is the uppermost layer in which the vias 21 and 22 are present. As shown in Fig. 5B, the conductor layer 41 is provided with a clearance 1 including a clearance 1a in a manner to include the vias 21 and 22 in correspondence with the periphery of the vias 21 and 22. The conductor layer 41 around the clearances 1 and 1a forms a GND plane 31.

[0056] 5C shows the conductor layer 42, which is the uppermost layer in which the vias 21 and 22 exist. As shown in FIG. 5C, the conductor layer 42 has clearances 1 including a clearance 1a around the vias 21 and 22. The conductor layer 42 also has openings 2 around and between the wirings 11 and 12 connected to the vias 21 and 22, respectively, so as to connect to the clearance 1. The conductor layer 42 around the clearances 1 and 1a and the openings 2 forms a GND plane 31.

[0057] 5D shows a conductor layer 43, which is an intermediate layer in which vias 21 and 22 exist. As shown in Fig. 5D, the conductor layer 43 has clearances 1 including clearances 1a around the vias 21 and 22. The conductor layer 43 around the clearances 1 and 1a forms a GND plane 31.

[0058] 5E shows the conductor layer 44, which is the lowest layer in which the vias 21 and 22 are present. As shown in FIG. 5E, the conductor layer 44 has clearances 1 including a clearance 1a around the vias 21 and 22. The conductor layer 44 also has openings 3 around and between the wirings 13 and 14 connected to the vias 21 and 22, respectively, so as to connect to the clearance 1. The conductor layer 44 around the clearances 1 and 1a and the openings 3 forms a GND plane 31.

[0059] 5F shows a conductor layer 45 adjacent to the outer side of the conductor layer 44, which is the lowest layer in which the vias 21 and 22 are present. As shown in Fig. 5F, the conductor layer 45 is provided with a clearance 1 including a clearance 1a in a manner to include the vias 21 and 22 in correspondence with the periphery of the vias 21 and 22. The conductor layer 45 around the clearances 1 and 1a forms a GND plane 31.

[0060] The clearances 1 including the clearance 1a of the conductor layers 41, 42, 43, 44, and 45 have the same planar shape and are arranged to match each other in a plan view perpendicular to the printed wiring board 10. In this plan view, the clearance 1 including the clearance 1a is provided in each of the conductor layers 41, 42, 43, 44, and 45 so as to include the vias 21 and 22 and the region 61 where the wiring 12 and the wiring 13 intersect.

[0061] Fig. 6 shows details of the clearance 1 including the clearance 1a according to this embodiment. Fig. 6 differs from Fig. 4 in the positional relationship between the vias 21 and 22 and the positional relationship between the wirings 11 and 12 and the wirings 13 and 14.

[0062] In this embodiment, similarly to the second embodiment, the clearance 1a is set as follows based on the distance D101 between the vias 21 and 22 in a plan view perpendicular to the printed wiring board 10. That is, the clearance 1a is set to a range where the distance D114 of the overlap with the wirings 11 and 12 set to a constant wiring width and a constant wiring interval is larger than the distance D101 when viewed from the lead-out portion of the vias 21 and 22. Also, the clearance 1a is set to a range where the distance D114 of the overlap with the wirings 13 and 14 set to a constant wiring width and a constant wiring interval is larger than the distance D101 when viewed from the lead-out portion of the vias 21 and 22. Note that the clearance 1a may be set to a range where the overlap with the wirings 11, 12, 13, and 14 set to a constant wiring width and a constant wiring interval is larger than the distance D101 when viewed from the lead-out portion of the vias 21 and 22.

[0063] As in this embodiment, the positional relationship between the vias 21, 22 and the wirings 11, 12 and the wirings 13, 14 can be appropriately set according to the wiring layout and the like.

[0064] [Fourth embodiment] A printed wiring board according to a fourth embodiment of the present invention will be described with reference to Figs. 7A to 7F. Fig. 7A is a top perspective view showing the printed wiring board according to this embodiment. Figs. 7B to 7F are plan views showing each conductor layer of the printed wiring board according to this embodiment. Figs. 7A to 7F are views seen perpendicularly to the printed wiring board. Note that components similar to those in the first to third embodiments are given the same reference numerals and descriptions thereof will be omitted or simplified.

[0065] As shown in FIG. 7A, the printed wiring board 10 according to this embodiment is different from the first embodiment in that the relative positions of the P-side wiring and the N-side wiring are not swapped between the wirings 11, 12 and the wirings 13, 14. The printed wiring board 10 according to this embodiment is also different from the first embodiment in the drawing direction of the wirings 11, 12, 13, 14 and the positional relationship of the vias 21, 22. The configuration of the printed wiring board 10 according to this embodiment is the same as that of the first embodiment except for these points. In this embodiment, since the wirings are not swapped, the wiring 11 does not cross any of the wirings 13, 14, and the wiring 12 does not cross any of the wirings 13, 14 in a plan view perpendicular to the printed wiring board 10. However, in this embodiment, although the wirings are not swapped, the wiring lengths of the wirings 11, 13 and the wirings 12, 14 are different from each other due to the drawing direction of the wirings 11, 12, 13, 14 and the positional relationship of the vias 21, 22, and a difference occurs between the wiring lengths of the two wirings.

[0066] 7B to 7F show clearances 1 provided in conductor layers 41, 42, 43, 44, and 45 in printed wiring board 10 according to this embodiment. In this embodiment, clearances 1 are provided according to the lead-out directions of wirings 11, 12, 13, and 14 and the positional relationship of vias 21 and 22, as in the first embodiment.

[0067] 7B shows a conductor layer 41 adjacent to the outer side of the conductor layer 42, which is the uppermost layer in which the vias 21 and 22 exist. As shown in Fig. 7B, the conductor layer 41 is provided with a clearance 1 in a manner that corresponds to the periphery of the vias 21 and 22 and includes the vias 21 and 22. The conductor layer 41 around the clearance 1 serves as a GND plane 31.

[0068] 7C shows the conductor layer 42, which is the uppermost layer in which the vias 21 and 22 exist. As shown in Fig. 7C, the conductor layer 42 has a clearance 1 around the vias 21 and 22. The conductor layer 42 also has an opening 2 around and between the wirings 11 and 12 connected to the vias 21 and 22, respectively, so as to connect to the clearance 1. The conductor layer 42 around the clearance 1 and the opening 2 forms a GND plane 31.

[0069] 7D shows a conductor layer 43, which is an intermediate layer in which the vias 21 and 22 exist. As shown in Fig. 7D, the conductor layer 43 has a clearance 1 around the vias 21 and 22. The conductor layer 43 around the clearance 1 serves as a GND plane 31.

[0070] 7E shows the conductor layer 44, which is the lowest layer in which the vias 21 and 22 exist. As shown in Fig. 7E, the conductor layer 44 has a clearance 1 around the vias 21 and 22. The conductor layer 44 also has an opening 3 around and between the wirings 13 and 14 connected to the vias 21 and 22, respectively, so as to connect to the clearance 1. The conductor layer 44 around the clearance 1 and the opening 3 forms a GND plane 31.

[0071] 7F shows a conductor layer 45 adjacent to the outer side of the conductor layer 44, which is the lowest layer in which the vias 21 and 22 are present. As shown in Fig. 7F, the conductor layer 45 has a clearance 1 provided in correspondence with the periphery of the vias 21 and 22 so as to include the vias 21 and 22. The conductor layer 45 around the clearance 1 serves as a GND plane 31.

[0072] The clearances 1 of the conductor layers 41, 42, 43, 44, and 45 have the same planar shape and are arranged to overlap each other so as to match each other in a plan view perpendicular to the printed wiring board 10. In this plan view, the clearances 1 are provided in each of the conductor layers 41, 42, 43, 44, and 45 so as to include the vias 21 and 22.

[0073] In this embodiment, when the relative positions of the P-side wiring and the N-side wiring are not swapped between the wirings 11, 12 and the wirings 13, 14, the clearance 1 is provided up to the conductor layers 41, 45 adjacent to the outer sides of the uppermost and lowermost conductor layers 42, 44 in which the vias 21, 22 are present. As a result, in this embodiment, even when the relative positions of the P-side wiring and the N-side wiring are not swapped, the skew in the differential signal can be reduced, and thus deterioration of the transmission characteristics such as the transmission characteristics of the differential signal can be reduced.

[0074] [Fifth embodiment] A printed wiring board according to a fifth embodiment of the present invention will be described with reference to Figs. 8A to 9. Fig. 8A is a top perspective view showing the printed wiring board according to this embodiment. Figs. 8B to 8F are plan views showing each conductor layer of the printed wiring board according to this embodiment. Fig. 9 is a plan view explaining clearances in the printed wiring board according to this embodiment. Figs. 8A to 9 are views seen perpendicularly to the printed wiring board. Note that the same reference numerals are used for components similar to those of the first to fourth embodiments, and descriptions thereof will be omitted or simplified.

[0075] 8A, the basic configuration of the printed wiring board 10 according to this embodiment is similar to that of the fourth embodiment. In this embodiment, the relative positions of the P-side wiring and the N-side wiring are not swapped between the wirings 11 and 12 and the wirings 13 and 14, as in the fourth embodiment.

[0076] Printed wiring board 10 according to the present embodiment differs from the fourth embodiment in terms of the range of clearance 1. Figures 8B to 8F show clearance 1 provided in conductor layers 41, 42, 43, 44, and 45 in printed wiring board 10 according to the present embodiment.

[0077] 8B shows a conductor layer 41 adjacent to the outer side of the conductor layer 42, which is the uppermost layer in which the vias 21 and 22 are present. As shown in Fig. 8B, the conductor layer 41 is provided with a clearance 1 including a clearance 1a in a manner to include the vias 21 and 22 in correspondence with the periphery of the vias 21 and 22. The conductor layer 41 around the clearances 1 and 1a forms a GND plane 31.

[0078] 8C shows the conductor layer 42, which is the uppermost layer in which the vias 21 and 22 exist. As shown in FIG. 8C, the conductor layer 42 has clearances 1 including a clearance 1a around the vias 21 and 22. The conductor layer 42 also has openings 2 around and between the wirings 11 and 12 connected to the vias 21 and 22, respectively, so as to connect to the clearance 1. The conductor layer 42 around the clearances 1 and 1a and the openings 2 forms a GND plane 31.

[0079] 8D shows a conductor layer 43, which is an intermediate layer in which vias 21 and 22 exist. As shown in Fig. 8D, the conductor layer 43 has clearances 1 including clearance 1a around the vias 21 and 22. The conductor layer 43 around the clearances 1 and 1a forms a GND plane 31.

[0080] 8E shows the conductor layer 44, which is the lowest layer in which the vias 21 and 22 are present. As shown in FIG. 8E, the conductor layer 44 has clearances 1 including a clearance 1a around the vias 21 and 22. The conductor layer 44 also has openings 3 around and between the wirings 13 and 14 connected to the vias 21 and 22, respectively, so as to connect to the clearance 1. The conductor layer 44 around the clearances 1 and 1a and the openings 3 forms a GND plane 31.

[0081] 8F shows a conductor layer 45 adjacent to the lower side of the conductor layer 44, which is the lowest layer in which the vias 21 and 22 are present. As shown in Fig. 8F, the conductor layer 45 is provided with a clearance 1 including a clearance 1a in a manner to include the vias 21 and 22 in correspondence with the periphery of the vias 21 and 22. The conductor layer 45 around the clearances 1 and 1a forms a GND plane 31.

[0082] The clearances 1 including the clearances 1a of the conductor layers 41, 42, 43, 44, and 45 have the same planar shape and are arranged to overlap each other so as to match each other in a plan view perpendicular to the printed wiring board 10. In this plan view, the clearances 1 including the clearances 1a are provided in each of the conductor layers 41, 42, 43, 44, and 45 so as to include the vias 21 and 22.

[0083] 9 shows details of the clearance 1 including the clearance 1a according to this embodiment. In this embodiment, as in the second and third embodiments, the clearance 1a is set as follows based on the distance D101 between the vias 21 and 22 in a plan view perpendicular to the printed wiring board 10. That is, the clearance 1a is set to a range where the distance D114 of the overlap with the wirings 11 and 12, which are set to a constant wiring width and a constant spacing between the wirings, is larger than the distance D101, when viewed from the lead-out portion of the vias 21 and 22. Also, the clearance 1a is set to a range where the distance D114 of the overlap with the wirings 13 and 14, which are set to a constant wiring width and a constant spacing between the wirings, is larger than the distance D101, when viewed from the lead-out portion of the vias 21 and 22, when viewed from the lead-out portion of the vias 21 and 22. It is sufficient that clearance 1a is set to an extent that, in a plan view viewed perpendicularly to printed wiring board 10, it overlaps with wirings 11, 12, 13, and 14 that are set to a constant wiring width and constant spacing between wirings.

[0084] Even when the relative positions of the P-side wiring and the N-side wiring are not swapped between the wirings 11 and 12 and the wirings 13 and 14 as in this embodiment, the clearance 1 can be set to include the clearance 1a. This makes it possible to further reduce the skew between the P signal and the N signal in the differential signal according to this embodiment.

[0085] [Sixth embodiment] A printed wiring board according to a sixth embodiment of the present invention will be described with reference to Figs. 10A and 10B. Fig. 10A is a top perspective view showing the printed wiring board according to this embodiment. Fig. 10B is a cross-sectional view showing a cross section of the printed wiring board according to this embodiment. Fig. 10A is a view seen perpendicular to the printed wiring board. Fig. 10B shows a vertical cross section taken along line AA' in Fig. 10A. Note that components similar to those in the first to fifth embodiments are given the same reference numerals and descriptions thereof will be omitted or simplified. The basic configuration of the printed wiring board 10 according to this embodiment is the same as that of the first embodiment. As shown in Figures 10A and 10B, the printed wiring board 10 according to this embodiment is a multilayer printed wiring board having conductor layers 40 and 46 in addition to the five conductor layers 41, 42, 43, 44, and 45 similar to those of the first embodiment.

[0086] The conductor layer 40 is a conductor layer stacked adjacent to the outer side of the conductor layer 41 with an insulating layer 50 interposed therebetween. The conductor layer 40 is provided with a clearance 1, similar to the conductor layer 41. The conductor layer 40 around the clearance 1 serves as a GND plane 31. A distance D200 between the conductor layer 40 and the conductor layer 42, which is the uppermost layer in which the vias 21 and 22 exist, is preferably set to be smaller than a distance D101 between the vias 21 and 22.

[0087] The conductor layer 46 is a conductor layer stacked adjacent to the outer side of the conductor layer 45 with an insulating layer 55 interposed therebetween. The conductor layer 46 is provided with a clearance 1, similar to the conductor layer 45. The conductor layer 46 around the clearance 1 serves as a GND plane 31. A distance D201 between the conductor layer 46 and the conductor layer 44, which is the lowest layer in which the vias 21 and 22 exist, is preferably set to be smaller than a distance D101 between the vias 21 and 22.

[0088] As in the present embodiment, the conductor layers 40 and 46 having the clearance 1 may be provided adjacent to the outside of the conductor layers 41 and 45, respectively. By further providing the conductor layers 40 and 46 having the clearance 1, the skew between the P signal and the N signal in the differential signal can be further reduced.

[0089] It is not necessary that both the conductor layers 40 and 46 are provided, and it is sufficient that either the conductor layer 40 or the conductor layer 46 is provided. Also, a conductor layer similar to the conductor layers 40 and 46 may be provided adjacent to the outside of the conductor layers 40 and 46 via an insulating layer. Also, in the second to fifth embodiments, the conductor layers 40 and 46 provided with the clearance 1 similar to the conductor layers 41 and 45 in the same manner as in this embodiment may be provided.

[0090] [Seventh embodiment] An electronic device according to a seventh embodiment of the present invention will be described with reference to Figs. 11A and 11B. Figs. 11A and 11B are schematic diagrams showing a head mounted display (HMD) as an example of an electronic device according to this embodiment. Fig. 11A is a side view of the HMD, and Fig. 11B is a front view of the HMD. Note that components similar to those in the first to sixth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. In this embodiment, an HMD, which is a display device, will be described as an example of an electronic device using a printed wiring board 10 according to any one of the first to sixth embodiments.

[0091] 11A and 11B, the HMD 200 has a housing 201, a wearing device 202, display units 203 for the left and right eyes, and a control unit 204. The display units 203 and the control unit 204 are housed and arranged inside the housing 201. The display units 203 for the left and right eyes are display units that display images for the left and right eyes, respectively. The control unit 204 is a control unit that controls the operation of the HMD 200 including the display units 203, etc.

[0092] The control unit 204 is a printed circuit board having the printed wiring board 10 according to any one of the first to sixth embodiments and a semiconductor device 205 as a component mounted on the printed wiring board 10. The semiconductor device 205 controls each part of the HMD 200 such as the display unit 203, and transmits and receives signals such as video signals and control signals using differential signal wiring formed by wirings 11, 12, 13, and 14 on the printed wiring board 10.

[0093] As in this embodiment, the printed wiring board 10 according to any of the first to sixth embodiments can be used in the HMD 200. The printed wiring board 10 according to any of the first to sixth embodiments can also be used in electronic devices such as computers, displays, and video equipment, in addition to the HMD 200. In electronic devices, the printed wiring board 10 is used as a printed circuit board on which various components such as semiconductor devices are mounted.

[0094] (Example) The effect of improving skew according to the above embodiment and its mechanism will be described with reference to FIGS. 12A to 13. FIG.

[0095] FIG. 12A is a top view of the printed wiring board 10 of the embodiment. FIG. 12B is a top view of the printed wiring board 10' of the comparative example. The embodiment shown in FIG. 12A has a configuration corresponding to the printed wiring board 10 of the second embodiment. In the embodiment, in order to enhance the coupling effect between the wiring and the via, the clearance 1 is increased, and the clearance 1 is provided from the conductor layer 41 above the top conductor layer 42 in which the vias 21 and 22 exist, to the conductor layer 45 below the bottom conductor layer 44 in which the vias 21 and 22 exist. Furthermore, in the embodiment, a clearance 1a is provided that overlaps the wiring portion. On the other hand, the comparative example has a configuration in which the clearance 1 is not provided in the conductor layers 41 and 45 in the printed wiring board 10 of the first embodiment.

[0096] A simulation was performed for the embodiment and the comparative example to compare the skew. As a result of the simulation, the skew of the embodiment was 10.7ps, while the skew of the comparative example was 10.2ps. This shows that the embodiment has an improved skew compared to the comparative example, and is effective in improving the skew.

[0097] In the embodiment, it is considered that the coupling between vias 21 and 22 shown by dashed line 301, the coupling between wires 11 and 12 shown by dashed line 302, the coupling between wires 13 and 14 also shown by dashed line 302, and the coupling between vias and wires (not shown) are enhanced. As a result, in the embodiment, as shown by arrow 303, return currents due to coupling with the signal current are generated in wires 11, 12, 13, and 14, and it is considered that the skew is improved by this return current.

[0098] Fig. 12D shows the waveforms of the P signal and the N signal in the comparative example shown in Fig. 12B. As shown in Fig. 12D, in the comparative example, skew occurs due to the difference in wiring length.

[0099] Fig. 12C shows the waveforms of the P signal and the N signal in the example shown in Fig. 12A. As shown in Fig. 12C, in the example, although skew occurs due to the difference in wiring length, the skew is reduced compared to the comparative example.

[0100] FIG. 13 is a graph showing the transmission characteristics of the embodiment and the comparative example. In FIG. 13, the vertical axis shows the transmission characteristics, and the higher it is, the better the transmission characteristics are. The horizontal axis shows the frequency, and the transmission characteristics were confirmed from 0 Hz to 7 GHz. From the graph shown in FIG. 13, it can be seen that the transmission characteristics of the embodiment are improved compared to the comparative example. For example, assuming a 10 Gbps signal, the frequency is confirmed at half the frequency, 5 GHz. In this case, the transmission characteristics of the comparative example were -0.8 dB, whereas the transmission characteristics of the embodiment were improved to -0.6 dB.

[0101] The present invention is not limited to the above-described embodiments, and many modifications are possible within the technical concept of the present invention. Furthermore, the effects described in the embodiments are merely a list of the most preferable effects resulting from the present invention, and the effects of the present invention are not limited to those described in the embodiments.

[0102] The disclosure of this embodiment includes the following configuration. (Configuration 1) A substrate having a first conductor layer and a second conductor layer stacked together, and a third conductor layer stacked on the outside of either the first conductor layer or the second conductor layer; a first differential signal wiring provided in the first conductor layer and having a first wiring and a second wiring; a second differential signal wiring provided in the second conductor layer and having a third wiring and a fourth wiring; a first via provided between the first conductor layer and the second conductor layer and connecting the first wiring and the third wiring; a second via provided between the first conductor layer and the second conductor layer and connecting the second wiring and the fourth wiring; The third conductor layer has a first clearance so as to include the first via and the second via in a plan view perpendicular to the substrate. A printed wiring board comprising: (Configuration 2) The first wiring, the second wiring, the third wiring, and the fourth wiring are arranged such that, in the plan view, one of the first wiring and the second wiring intersects with one of the third wiring and the fourth wiring. 2. The printed wiring board according to configuration 1. (Configuration 3) The first clearance is provided so as to include a region where one of the first wiring and the second wiring intersects with one of the third wiring and the fourth wiring in the plan view. 3. The printed wiring board according to configuration 2. (Configuration 4) The first wiring, the second wiring, the third wiring, and the fourth wiring are arranged such that, in the plan view, the first wiring does not intersect with either the third wiring or the fourth wiring, and the second wiring does not intersect with either the third wiring or the fourth wiring. 2. The printed wiring board according to configuration 1. (Configuration 5) The wiring length of the first wiring and the third wiring is different from the wiring length of the second wiring and the fourth wiring. 5. The printed wiring board according to claim 1, wherein the printed wiring board is a printed wiring board having a first insulating layer and a second insulating layer. (Configuration 6) the first wiring and the second wiring have a first portion having a constant wiring width and a constant interval; The first clearance is provided so as to cover the first portion in the plan view. 6. The printed wiring board according to any one of configurations 1 to 5. (Configuration 7) the third wiring and the fourth wiring have second portions having constant wiring widths and intervals; The first clearance is provided so as to cover the second portion in the plan view. 7. The printed wiring board according to configuration 6. (Configuration 8) A distance over which the first clearance covers the first portion in the plan view is greater than a distance between the first via and the second via. 8. The printed wiring board according to configuration 6 or 7. (Configuration 9) A distance over which the first clearance covers the second portion in the plan view is greater than a distance between the first via and the second via. 8. The printed wiring board according to configuration 7. (Configuration 10) a fourth conductor layer laminated on the outside of the other of the first conductor layer and the second conductor layer; The fourth conductor layer has a second clearance so as to include the first via and the second via in the plan view. 10. The printed wiring board according to any one of configurations 1 to 9. (Configuration 11) a fourth conductor layer laminated on the outside of the third conductor layer; The fourth conductor layer is provided with a third clearance so as to include the first via and the second via in the plan view. 11. The printed wiring board according to any one of configurations 1 to 10. (Configuration 12) A distance between the first conductor layer or the second conductor layer adjacent to the third conductor layer on the outside and the fourth conductor layer is greater than a distance between the first via and the second via. 12. The printed wiring board according to claim 11, (Configuration 13) A printed wiring board according to any one of configurations 1 to 12, A component mounted on the printed wiring board; A printed circuit board comprising: (Configuration 14) A housing and 14. The printed circuit board of configuration 13 disposed inside the housing; 1. An electronic device comprising: (Configuration 15) A housing and A display unit that is disposed inside the housing and displays an image; The printed wiring board according to any one of configurations 1 to 12, which is disposed inside the housing; and a semiconductor device mounted on the printed wiring board and controlling the display unit; A head mounted display comprising: [Explanation of symbols]

[0103] 1 Clearance 2, 3 Opening 10 Printed wiring board 11, 12, 13, 14 Wiring 21, 22 Via 31 Ground Plane 40, 41, 42, 43, 44, 45 Conductor layers 50, 51, 52, 53, 54, 55 Insulating layer 103 Display unit 200 HMD 201 Case 202 Wearing equipment 203 Display unit 204 Control Unit 205 Semiconductor Devices

Claims

1. A substrate having a first conductor layer and a second conductor layer stacked on one of the first conductor layer and the second conductor layer, and a third conductor layer stacked on the outside of either the first conductor layer or the second conductor layer; a first differential signal wiring provided in the first conductor layer and having a first wiring and a second wiring; a second differential signal wiring provided in the second conductor layer and having a third wiring and a fourth wiring; a first via provided between the first conductor layer and the second conductor layer and connecting the first wiring and the third wiring; a second via provided between the first conductor layer and the second conductor layer and connecting the second wiring and the fourth wiring; The third conductor layer is provided with a first clearance so as to include the first via and the second via in a plan view perpendicular to the substrate. A printed wiring board comprising:

2. The first wiring, the second wiring, the third wiring, and the fourth wiring are arranged such that, in the plan view, one of the first wiring and the second wiring intersects with one of the third wiring and the fourth wiring.

2. The printed wiring board according to claim 1.

3. The first clearance is provided so as to include a region where one of the first wiring and the second wiring intersects with one of the third wiring and the fourth wiring in the plan view.

3. The printed wiring board according to claim 2.

4. The first wiring, the second wiring, the third wiring, and the fourth wiring are arranged such that, in the plan view, the first wiring does not intersect with either the third wiring or the fourth wiring, and the second wiring does not intersect with either the third wiring or the fourth wiring.

2. The printed wiring board according to claim 1.

5. The wiring lengths of the first wiring and the third wiring are different from the wiring lengths of the second wiring and the fourth wiring.

5. The printed wiring board according to claim 1, wherein the first insulating layer is a conductive layer.

6. the first wiring and the second wiring have a first portion having a constant wiring width and a constant interval; The first clearance is provided so as to cover the first portion in the plan view.

5. The printed wiring board according to claim 1, wherein the first insulating layer is a conductive layer.

7. the third wiring and the fourth wiring have second portions having constant wiring widths and intervals; The first clearance is provided so as to cover the second portion in the plan view.

7. The printed wiring board according to claim 6.

8. A distance over which the first clearance covers the first portion in the plan view is greater than a distance between the first via and the second via.

7. The printed wiring board according to claim 6.

9. A distance over which the first clearance covers the second portion in the plan view is greater than a distance between the first via and the second via.

8. The printed wiring board according to claim 7.

10. a fourth conductor layer laminated on the outside of the other of the first conductor layer and the second conductor layer; The fourth conductor layer is provided with a second clearance so as to include the first via and the second via in the plan view.

5. The printed wiring board according to claim 1, wherein the first insulating layer is a conductive layer.

11. a fourth conductor layer laminated on the outside of the third conductor layer; The fourth conductor layer is provided with a third clearance so as to include the first via and the second via in the plan view.

5. The printed wiring board according to claim 1, wherein the first insulating layer is a conductive layer.

12. A distance between the first conductor layer or the second conductor layer adjacent to the third conductor layer on the outside and the fourth conductor layer is greater than a distance between the first via and the second via. The printed wiring board according to claim 11 .

13. The printed wiring board according to any one of claims 1 to 4, A component mounted on the printed wiring board; A printed circuit board comprising:

14. A housing and The printed circuit board according to claim 13 disposed inside the housing; 1. An electronic device comprising:

15. A housing and A display unit that is disposed inside the housing and displays an image; The printed wiring board according to claim 1 , which is disposed inside the housing; a semiconductor device mounted on the printed wiring board and controlling the display unit; A head mounted display comprising:

Images