Memory system and memory system control method

Abstract

To implement a memory system which can prevent erroneous data from being transmitted to a host due to erroneous reading.SOLUTION: A controller manages a plurality of flags corresponding to a plurality of physical addresses. In response to receiving a read command from a host, the controller acquires a physical address mapped in a logical address designated by the read command, from a first management table and reads data from a nonvolatile memory on the basis of the acquired physical address. The controller determines whether or not the read data should be transmitted to the host based on whether a current state of a flag corresponding to the acquired physical address is set to a first value indicating valid data or a second value indicating invalid data.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a memory system and a method for controlling a memory system. [Background technology]

[0002] 2. Description of the Related Art As a memory system that has become widespread in recent years, for example, a solid state drive (SSD) that includes a nonvolatile memory and a controller that controls the nonvolatile memory is known.

[0003] A memory system is usually connected to an external host and is capable of transmitting and receiving data to and from the external host. For example, in an SSD, a controller receives a specific command from the external host, and executes a process of writing data received from the host to a non-volatile memory, reading data written in the non-volatile memory and transmitting the data to the host.

[0004] In data transmission and reception in memory systems such as SSDs, when data written in non-volatile memory is read and transmitted to the host, there is a need for technology that can prevent incorrect data from being transmitted to the host due to a read error. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2020 / 0201785 [Patent Document 2] US Patent Application Publication No. 2020 / 0278883 [Patent Document 3] US Patent Application Publication No. 2020 / 0371861 [Patent Document 4] Patent No. 5221699 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a memory system and a method for controlling the memory system that can prevent erroneous data from being transmitted to a host due to erroneous reading. [Means for solving the problem]

[0007] According to an embodiment, a memory system is connectable to a host. The memory system includes a non-volatile memory and a controller configured to control the non-volatile memory. The controller uses a first management table to manage mapping information indicating a mapping between a plurality of logical addresses for the host to access the memory system and a plurality of physical addresses of the non-volatile memory. The controller uses a second management table to manage a plurality of flags associated with the plurality of physical addresses. The plurality of flags are set to either a first value indicating that data stored in a memory location of the non-volatile memory corresponding to the physical address is valid data or a second value indicating that data is invalid data. In response to receiving a write command specifying a first logical address from the host, the controller assigns a first physical address to the first logical address. The controller writes first data associated with the write command to a first memory location of the non-volatile memory corresponding to the first physical address. The controller sets a first flag corresponding to the first physical address to the first value. In response to the first data being made invalid by updating or deleting the first data, the controller sets the first flag to the second value. In response to receiving a read command specifying the first logical address from the host, the controller acquires from the first management table a physical address that is mapped to the first logical address at the time of executing the read command. The controller reads data from the non-volatile memory based on the acquired physical address. The controller determines whether or not to transmit the read data to the host based on whether a current state of a flag corresponding to the acquired physical address is set to the first value or the second value. [Brief description of the drawings]

[0008] [Figure 1]1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Diagram 2] FIG. 1 is a block diagram showing an example of a configuration showing the relationship between multiple channels and multiple flash dies used in a memory system according to an embodiment. [Diagram 3] FIG. 2 is a diagram showing an example of the configuration of a superblock used in the memory system according to the embodiment. [Figure 4] 1 is a diagram showing an example of the configuration of a valid flag table used in a memory system according to an embodiment; [Diagram 5] 1 is a diagram showing an example of a configuration relating to control of write data and read data in a memory system according to an embodiment; [Figure 6] FIG. 4 is a diagram showing the flow of a write process in the memory system according to the embodiment. [Figure 7] 1 is a diagram showing a flow of an invalidation process of a memory system according to an embodiment; [Figure 8] FIG. 4 is a diagram showing the flow of a read process in the memory system according to the embodiment. [Figure 9] FIG. 4 is a diagram showing the flow of garbage collection processing in the memory system according to the embodiment. [Figure 10] FIG. 4 is a diagram showing a first example of write data in the memory system according to the embodiment. [Figure 11] FIG. 4 is a diagram showing a first example of read data of the memory system according to the embodiment. [Figure 12] 1 is a flowchart showing a first example of a procedure of a write process in the memory system according to the embodiment. [Figure 13] 11 is a flowchart showing a first example of a procedure of a read process of the memory system according to the embodiment. [Figure 14] FIG. 11 is a diagram showing a second example of write data in the memory system according to the embodiment. [Figure 15] FIG. 11 is a diagram showing a second example of read data of the memory system according to the embodiment. [Figure 16] FIG. 11 is a diagram showing a second example of the procedure of a write process in the memory system according to the embodiment. [Figure 17] FIG. 11 is a diagram showing a second example of the procedure of a read process of the memory system according to the embodiment. [Figure 18] FIG. 11 is a diagram showing a third example of write data in the memory system according to the embodiment. [Figure 19] FIG. 11 is a diagram showing a third example of read data of the memory system according to the embodiment. [Figure 20] FIG. 11 is a diagram showing a third example of a procedure of a write process in the memory system according to the embodiment. [Figure 21] FIG. 11 is a diagram showing a third example of a procedure of a read process of the memory system according to the embodiment. [Figure 22] FIG. 11 is a diagram showing a fourth example of write data in the memory system according to the embodiment. [Diagram 23] FIG. 11 is a diagram showing a fourth example of read data of the memory system according to the embodiment. [Figure 24] FIG. 11 is a diagram showing a fourth example of a procedure of a write process in the memory system according to the embodiment. [Diagram 25] FIG. 11 is a diagram showing a fourth example of a procedure of a read process of the memory system according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings.

[0010] 1 is a block diagram showing an example of the configuration of an information processing system 1 including a memory system according to an embodiment. The information processing system 1 includes a host (host device) 2 and an SSD (Solid State Drive) 3 as a memory system.

[0011] The host 2 is, for example, an information processing device such as a personal computer, a server computer, or a mobile device. The host 2 is connected to the SSD 3 and can access the SSD 3. Specifically, the host 2 issues a write command to the SSD 3 to write data. The host 2 also issues a read command to the SSD 3 to read data.

[0012] The SSD3 is also called a storage device, and is capable of writing data to an internal non-volatile memory and reading data from the internal non-volatile memory.

[0013] The communication between the SSD 3 and the host 2 is performed via a bus 7. The bus 7 is a transmission path that connects the host 2 and the SSD 3. The bus 7 is, for example, a PCI express TM (PCIe TM ) bus. The PCIe bus is a full duplex transmission path. The full duplex transmission path includes both a transmission path for transmitting data and input / output (I / O) commands from the host 2 to the SSD 3, and a transmission path for transmitting data and responses from the SSD 3 to the host 2. I / O commands are issued from the host 2 to the SSD 3, and include a write command for writing data to the nonvolatile memory, or a read command for reading data from the nonvolatile memory.

[0014] The logical interface connecting host 2 and SSD 3 is, for example, NVM express TM (NVMe TM ) standard may be used. In an interface conforming to the NVMe standard, communication between the host 2 and the SSD 3 is performed using a pair of queues including at least one submission queue (SQ) and a completion queue (CQ) associated with the submission queue (SQ). For example, the pair of queues is referred to as a submission queue / completion queue pair (SQ / CQ pair).

[0015] Next, the configuration of the host 2 will be described.

[0016] The host 2 includes a processor 21 and a memory 22 , and the processor 21 and the memory 22 are interconnected via an internal bus 20 .

[0017] The processor 21 is, for example, a CPU (Central Processing Unit). The processor 21 executes software (host software) loaded into the memory 22 from the SSD 3 or another storage device connected to the host 2. The host software includes, for example, an operating system, a file system, and an application program.

[0018] The memory 22 is, for example, a volatile memory. The memory 22 is also referred to as a main memory, a system memory, or a host memory. The memory 22 is, for example, a dynamic random access memory (DRAM). A part of the storage area of ​​the memory 22 is used as a host write buffer. The host write buffer is a storage area that temporarily stores data to be written to the non-volatile memory of the SSD 3. Another part of the storage area of ​​the memory 22 is used as a host read buffer. The host read buffer is a storage area that temporarily stores data that is read from the non-volatile memory of the SSD 3 and is to be transmitted (transferred) to the host.

[0019] Next, we will explain the internal configuration of the SSD 3. Here, it is assumed that the nonvolatile memory included in the SSD 3 is a NAND type flash memory, but it may be other flash memory, or other nonvolatile memory such as MRAM, ReRAM, FeRAM, or phase change memory.

[0020] The SSD 3 includes a controller 4 and a NAND flash memory 5. The NAND flash memory 5 may be a two-dimensional flash memory or a three-dimensional flash memory. The SSD 3 may further include a random access memory, for example, a dynamic random access memory (DRAM) 6 which is a volatile memory.

[0021] The controller 4 is a memory controller. The controller 4 is a control circuit such as a System-on-a-Chip (SoC). The controller 4 is electrically connected to each of the NAND flash memory 5 and the DRAM 6. The controller 4 processes various commands received from the host 2. When the controller 4 receives a write command, it executes a process of writing data to the NAND flash memory 5. When the controller 4 receives a read command, it executes a process of reading data from the NAND flash memory 5. Furthermore, when the controller 4 receives a trim command, it executes a process of invalidating data stored in the NAND flash memory 5. The trim command is also called a deallocate command or an unmap command, and is a command that requests the SSD 3 to invalidate data. The invalidated data is called invalid data that will not be accessed by the host 2. On the other hand, data that may be accessed by the host 2 before being invalidated is called valid data.

[0022] For example, a Toggle interface or an Open NAND Flash Interface (ONFI) is used as a physical interface connecting the controller 4 and the NAND flash memory 5. The functions of each part of the controller 4 can be realized by dedicated hardware, a processor that executes a program, or a combination of the dedicated hardware and the processor.

[0023] The NAND flash memory 5 may include multiple dies. The dies are also called flash dies, memory dies, memory chips, flash chips, etc. In the following description, the dies are called flash dies. In Fig. 1, an example is shown in which the NAND flash memory 5 includes 32 flash dies #0 to #31.

[0024] Each of the multiple flash dies included in the NAND flash memory 5 is composed of multiple blocks. Each of the multiple blocks is the smallest unit of a data erase operation. Each of the multiple blocks is also referred to as a memory block or a physical block. Each of the multiple blocks includes multiple pages. Each of the multiple pages is a unit of a data write operation and a data read operation. A page includes a set of memory cells connected to the same word line. A page is also referred to as a physical page.

[0025] The DRAM 6 is a volatile memory. A part of the storage area of ​​the DRAM 6 is used by the controller 4, for example, to temporarily store data to be written to the NAND flash memory 5 or to temporarily store data read from the NAND flash memory 5.

[0026] Next, a description will be given of the internal configuration of the controller 4. The controller 4 includes components such as a host interface (host I / F) 41, a static RAM (SRAM) 42, a CPU 43, a check circuit 44, an error correction circuit 45, a NAND interface (NAND I / F) 46, and a DRAM interface (DRAM I / F) 47. These components are connected to each other via an internal bus 40.

[0027] The host interface 41 is a communication interface circuit that executes communication with the host 2. The host interface 41 is realized by, for example, a PCIe controller.

[0028] The SRAM 42 is a volatile memory. A storage area of ​​the SRAM 42 is used, for example, as a working area of ​​the CPU 43. In addition, another storage area of ​​the SRAM 42 can be used as a storage area for temporarily storing data to be written to the NAND flash memory 5.

[0029] The CPU 43 is a processor. The CPU 43 loads a control program (firmware) stored in the NAND flash memory 5 or a ROM (not shown) into the SRAM 42. The CPU 43 then executes the firmware to perform various processes. The firmware may be one that has been loaded into the DRAM 6.

[0030] The CPU 43, for example, as a flash translation layer (FTL), manages data stored in the NAND flash memory 5 and manages blocks included in the NAND flash memory 5. The management of data stored in the NAND flash memory 5 includes, for example, management of mapping information using a logical-physical address conversion table (L2P table) 61. The L2P table 61 is a table that holds mapping information indicating mapping between each of a plurality of logical addresses and each of a plurality of physical addresses. Details of the mapping information will be described later.

[0031] Of the data stored in the NAND flash memory 5, data stored in a memory location indicated by a physical address mapped to a logical address is valid data. On the other hand, data stored in a memory location indicated by a physical address not mapped to any logical address is invalid data. In other words, even if data is stored in a memory location corresponding to a physical address, if the physical address is not mapped to a logical address, the data becomes invalid. The CPU 43 manages a block that holds at least one valid data as an active block. On the other hand, the CPU 43 manages a block that does not hold valid data as a free block.

[0032] Management of each block in the NAND flash memory 5 includes management of defective blocks (bad blocks), wear leveling (WL), garbage collection (GC), and the like.

[0033] The check circuit 44 is a circuit that checks whether data (read data) read from the NAND flash memory 5 is correct or not. In the check circuit 44, for example, a check code may be used to check whether the read data is correct or not, that is, to check the integrity of the read data. The check circuit 44 includes, for example, a check code generation circuit 441, a check code check circuit 442, a flag check circuit 443, a PBA check circuit 444, and an LBA check circuit 445. Some or all of the check code check circuit 442, the flag check circuit 443, the PBA check circuit 444, and the LBA check circuit 445 can operate as a data check circuit 44a.

[0034] The check code generation circuit 441 generates a check code by using, for example, data to be written to the NAND flash memory 5. The check code is a code for checking whether or not this data is correct, that is, for checking the consistency of the data. The check code is, for example, a cyclic redundancy code (CRC) or a hash value. The check code generation circuit 441 generates a check code by using at least user data. The user data is data associated with a write command received from the host 2. For example, two check codes generated from two identical data have values ​​that match each other. Also, two check codes generated from two different data have values ​​that are different from each other. Therefore, two data used to generate two check codes with matching values ​​are determined to be the same data. Also, two data used to generate two check codes with different values ​​are determined to be data that are different from each other.

[0035] In this way, the check code generation circuit 441 generates a check code to check the consistency of user data. For example, when writing data, the user data and the check code generated from the user data are written as one data set to a write destination storage location in the NAND flash memory 5. Also, for example, when reading data, the check code generation circuit 441 generates a check code to be compared with the check code read together with the user data from the read target storage location in the NAND flash memory 5.

[0036] The check code generation circuit 441 may generate a check code by using not only user data but also a logical address (e.g., a logical block address (LBA)), a physical address (e.g., a physical block address (PBA)), or a flag. That is, the check code generation circuit 441 may generate a check code for checking the consistency of information including all of the LBA, PBA, and flags and user data by using the LBA, PBA, and flags and user data. Alternatively, the check code generation circuit 441 may generate a check code for checking the consistency of information including any combination of the LBA, PBA, and flags and user data by using this any combination of the LBA, PBA, and flags and user data. Here, the flag is 1-bit information indicating whether data stored in one storage location in the NAND flash memory 5 indicated by a certain physical address is valid data or invalid data. When the data is valid data, a first value is set to the value of the flag, and when the data is invalid data, a second value is set to the value of the flag.

[0037] The data check circuit 44a judges whether the data read from the NAND flash memory 5 matches the data of the check code generated by the check code generation circuit 441. Note that the data here refers to the data of the check code generated by the check code generation circuit 441 from (1) user data and / or (2) any combination of the LBA, PBA, and flag. If the two match, it is judged to be the same data. If the two do not match, it is judged to be not the same data.

[0038] The data check circuit 44a may include, for example, all or some of the check code check circuit 442, the flag check circuit 443, the PBA check circuit 444, and the LBA check circuit 445.

[0039] The operation of each of the check code check circuit 442 and check devices 443, 444, and 445 that may be included in the data check circuit 44a will be described below.

[0040] The check code inspection circuit 442 is a circuit that checks whether or not two check codes match. The check code inspection circuit 442 compares the check code of the data read from the NAND flash memory 5 with the check code generated by the check code generation circuit 441. If these two check codes match, the check code inspection circuit 442 determines that the data read from the NAND flash memory 5 is the same data, that is, correct data. If the two check codes do not match, the check code inspection circuit 442 determines that the data read from the NAND flash memory 5 is not the same data, that is, incorrect data.

[0041] The flag check circuit 443 is a circuit that judges whether or not the current state of a flag corresponding to a physical address that is mapped to a logical address to be read at the time of execution of a read is set to a first value. That is, the flag check circuit 443 refers to the value of a flag corresponding to a physical address that is mapped to a logical address designated by a read command received from the host 2 at the time of execution of a read, and judges whether or not the value of this flag is kept at the first value. If the value of the flag is the first value, the flag check circuit 443 judges that the user data read from the NAND flash memory 5 is correct data. On the other hand, if the value of the flag does not hold the first value, the flag check circuit 443 judges that the user data read from the NAND flash memory 5 is incorrect data.

[0042] The PBA check circuit 444 is a circuit that checks whether two physical addresses (PBAs) match. For example, the PBA check circuit 444 checks whether the PBA read from the NAND flash memory 5 matches the latest PBA mapped to the LBA specified by the read command at the time of execution of the read. If these two PBAs match each other, the PBA check circuit 444 determines that the data read from the NAND flash memory 5 is correct data. If these two PBAs do not match each other, the PBA check circuit 444 determines that the data read from the NAND flash memory 5 is incorrect data.

[0043] The LBA check circuit 445 is a circuit that checks whether two logical addresses (LBAs) match. For example, the LBA check circuit 445 checks whether the latest LBA specified by a read command matches the LBA read from the NAND flash memory 5 together with the read data. If these two LBAs match, the LBA check circuit 445 determines that the data read from the NAND flash memory 5 is correct. If these two LBAs do not match, the LBA check circuit 445 determines that the data read from the NAND flash memory 5 is incorrect.

[0044] In the read process executed in this embodiment, if the read data is previous data (i.e., old data) corresponding to the logical address specified by the read command received from the host 2, the read data is detected as incorrect data by the inspection circuit 44. That is, even if the read data is data corresponding to the same logical address as the logical address specified by the read command, if the read data is not the latest data (new data) corresponding to this logical address but previous data (old data), the read data is detected as incorrect data.

[0045] In the NAND flash memory 5, when data corresponding to a certain logical address is updated, the updated data (new data) is written to a different storage location, not to the storage location where the previous data (old data) is stored. As a result, multiple generations of data corresponding to the same logical address may exist in the NAND flash memory 5. Therefore, if an error occurs in part of the mapping information due to data corruption or the like in the L2P table 61, there is a possibility that the previous data (old data) corresponding to a certain logical address may be erroneously read from the NAND flash memory 5.

[0046] However, according to the present embodiment, when the previous data (old data) corresponding to a certain logical address is invalidated by writing update data (new data) corresponding to this logical address, the flag corresponding to the physical address indicating the storage location where the previous data (old data) is stored is set to a second value indicating invalid data. The controller 4 acquires from the L2P table 61 the latest physical address that is mapped to the logical address (logical address to be read) designated by the read command received from the host 2 at the time of executing the read command, and reads data from the NAND flash memory 5 based on the acquired physical address. When reading data, it is determined whether the current state of the flag corresponding to the acquired latest physical address is maintained in a state set to the first value. This makes it possible to determine whether the data read from the NAND flash memory 5 is correct data or incorrect data. Based on the result of this determination, the controller 4 decides whether to transmit the data read from the NAND flash memory 5 to the host 2. As a result, it is possible to prevent incorrect data due to erroneous reading, such as the previous data (old data) corresponding to the logical address to be read or data already invalidated by a trim command, from being transmitted to the host 2.

[0047] There are two methods for determining whether the current state of a flag corresponding to a physical address that is mapped to the logical address to be read at the time of execution of the read is maintained at a first value, as described below.

[0048] The first method is to refer to the flag itself corresponding to the physical address that is mapped to the logical address to be read at the time of execution of the read, and determine whether the value of this flag is being maintained at the first value using the flag inspection circuit 443 (logical-physical map flag value determination method ("1 / 0"). Hereinafter, this may also be simply referred to as the flag value determination method).

[0049] The second method is to use a check code written together with user data when writing to the NAND flash memory 5 to check the consistency of information including the user data and a flag having a first value (check code determination method (“match / mismatch”)).

[0050] According to the second method, when user data is read from a storage location indicated by a physical address mapped to a logical address to be read at the time of execution of a read command, a check code is also read together with the user data. Then, a new check code for checking the consistency of information including a flag corresponding to a physical address mapped to a logical address to be read at the time of execution of a read and the read user data is generated using the flag and the read user data. If the value of the flag is set to a second value, the new check code does not match the read check code. Therefore, by determining whether the new check code matches the read check code, it is possible to determine whether the current state of the flag corresponding to a physical address mapped to a logical address to be read at the time of execution of a read is maintained at the first value. Therefore, it is not necessary for the flag check circuit 443 to refer to the flag itself and determine the value. That is, in the case of the second method, the check circuit 44 does not need to include the flag check circuit 443.

[0051] As described above, the physical address of the memory location where previous data (old data) corresponding to a certain logical address is stored is different from the physical address of the memory location where the latest data (new data) corresponding to this logical address is stored. However, even if the contents of the mapping information in the L2P table 61 are correct, if a malfunction occurs in the address decoder or the like in the NAND flash memory 5, data may be erroneously read from the memory location where the previous data (old data) corresponding to this logical address is stored. Even in this case, there is a possibility that erroneous data may be transmitted to the host 2 due to erroneous reading.

[0052] In this way, even in the case of a read error caused by a malfunction occurring in the NAND flash memory 5, it is necessary to prevent erroneous data from being sent to the host 2. For this purpose, the controller 4 may write the user data to the NAND flash memory 5 together with additional information determined directly or indirectly from the physical address to which the user data is to be written. As the additional information determined directly or indirectly from the physical address to which the user data is to be written, the physical address itself to which the user data is to be written may be used. Alternatively, a check code generated from information including the user data and the physical address may be used as this additional information.

[0053] When reading data corresponding to a read target logical address designated by a read command from the NAND flash memory 5, the controller 4 acquires from the L2P table 61 the latest physical address (read target physical address) that is mapped to the read target logical address at the time of executing the read command. The controller 4 reads both user data and additional information from the NAND flash memory 5 based on the acquired read target physical address. The controller 4 judges whether the read additional information matches additional information determined directly or indirectly from the read target logical address. In a case where the physical address itself is used as the additional information, the controller 4 judges whether the read additional information matches the read target physical address. On the other hand, in a case where a check code of information including the user data and the physical address is used as the additional information, the controller 4 first generates a check code using the read user data and the read target physical address. Then, the controller 4 judges whether the read additional information matches the generated check code.

[0054] In this way, by determining whether the read additional information matches the additional information determined directly or indirectly from the read target physical address, it is possible to determine whether the user data read from the NAND flash memory 5 is correct data read from the read target physical address or incorrect data read from another physical address different from the read target physical address. In this way, the controller 4 determines whether to transmit the user data read from the NAND flash memory 5 to the host 2 based on whether the additional information read from the NAND flash memory 5 matches the additional information determined directly or indirectly from the read target physical address. As a result, it is possible to prevent incorrect data such as previous data corresponding to the read target logical address from being transmitted to the host 2.

[0055] As described above, the direct or indirect additional information may be, for example, a physical address (PBA) itself. In this case, the controller 4 writes the user data to the NAND flash memory 5 together with the PBA to which the user data should be written (also called the write destination PBA).

[0056] Alternatively, as described above, the direct or indirect additional information may be, for example, a check code. In this case, the controller 4 first generates a check code for checking the consistency of information including the user data and the write destination PBA, and then writes the user data together with the generated check code into the NAND flash memory 5.

[0057] When the additional information is the PBA itself (PBA additional information), the PBA inspection circuit 444 compares two PBAs to determine whether the user data read from the NAND flash memory 5 is correct. On the other hand, when the additional information is a check code (check code additional information), the check code inspection circuit 442 compares two check codes to determine whether the data read from the NAND flash memory 5 is correct. Therefore, in this case, since it is not necessary for the PBA inspection circuit 444 to compare the PBA itself, the inspection circuit 44 does not need to include the PBA inspection circuit 444.

[0058] The error correction circuit 45 executes an encoding process when data is written to the NAND flash memory 5. In the encoding process, the error correction circuit 45 adds an error correction code (ECC) as a redundant code to the data to be written to the NAND flash memory 5. In the decoding process, the error correction circuit 45 executes a decoding process when data is read from the NAND flash memory 5. In the decoding process, the error correction circuit 45 executes error correction of the data read from the NAND flash memory 5 by using the ECC added to the data.

[0059] The NAND interface 46 is a circuit that controls the NAND flash memory 5. The NAND interface 46 is electrically connected to a plurality of flash dies included in the NAND flash memory 5.

[0060] Each flash die can operate independently. Therefore, the flash die functions as a unit capable of operating in parallel. The NAND interface 46 includes, for example, NAND controllers 461-0, 461-1, ..., 461-7. The NAND controllers 461-0, 461-1, ..., 461-7 are connected to channels ch0, ch1, ..., ch7, respectively. Each of the NAND controllers 461-0, 461-1, ..., 461-7 is connected to one or more flash dies via a corresponding channel. FIG. 1 illustrates a case in which four flash dies are connected to each of channels ch0, ch1, ..., ch7. In this case, the NAND controller 461-0 is connected to flash dies #0, #8, #16, and #24 via channel ch0. The NAND controller 461-1 is connected to flash dies #1, #9, #17, and #25 via channel ch1. The NAND controller 461-7 is connected to the flash dies #7, #15, #23, and #31 via the channel ch7. The flash dies #0, #1, ..., #7 are treated as a bank BNK0 by the controller 4. The flash dies #8, #9, ..., #15 are treated as a bank BNK1 by the controller 4. The flash dies #16, #17, ..., #23 are treated as a bank BNK2 by the controller 4. The flash dies #24, #25, ..., #31 are treated as a bank BNK3 by the controller 4. The bank is a unit that operates multiple flash dies in parallel by interleaving operation. Also, each of the flash dies #0 to #31 includes multiple blocks BLK1 to BLKx-1 as shown in FIG. 2.

[0061] 1 and 2, the controller 4 can access the flash dies #0 to #31 in parallel using eight channels and bank interleaving operations. Therefore, the controller 4 can write or read data in parallel to a maximum of 32 flash dies.

[0062] Each of the flash dies #0 to #31 may have a multi-plane configuration having multiple planes. For example, if each of the flash dies #0 to #31 includes four planes, the controller 4 can write or read data to a maximum of 128 planes in parallel.

[0063] Each of the multiple write destination blocks may be a single block (physical block), or may be a superblock including a set of multiple physical blocks capable of operating in parallel.

[0064] Although not limited thereto, one superblock may include a total of 32 physical blocks selected one by one from the NAND flash memory dies #0 to #31. Each of the NAND flash memory dies #0 to #31 may have a multi-plane configuration. For example, when each of the NAND flash memory dies #0 to #31 has a multi-plane configuration including four planes, one superblock may include a total of 128 physical blocks selected one by one from the 128 planes corresponding to the NAND flash memory dies #0 to #31.

[0065] FIG. 3 illustrates one superblock (SB) including 32 physical blocks (here, physical block BLK2 of NAND flash memory die #0, physical block BLK3 of NAND flash memory die #1, physical block BLK7 of NAND flash memory die #2, ..., physical block BLK4 in NAND flash memory die #24, physical block BLK6 in NAND flash memory die #25, ..., physical block BLK3 in NAND flash memory die #31).

[0066] The superblock (SB) includes the same number of superpages as the number of pages included in each of the 32 physical blocks. For example, Page 0 of physical block BLK2 of NAND flash memory die #0, Page 0 of physical block BLK3 of NAND flash memory die #1, Page 0 of physical block BLK7 of NAND flash memory die #2, ..., Page 0 of physical block BLK4 in NAND flash memory die #24, Page 0 of physical block BLK6 in NAND flash memory die #25, ..., Page 0 of physical block BLK3 in NAND flash memory die #31 may be treated by the controller 4 as one superpage of the 32 superpages in the superblock (SB).

[0067] It should be noted that a configuration in which one superblock includes only one physical block may be used, in which case one superblock is equivalent to one physical block.

[0068] Returning to the explanation of Fig. 1, the DRAM interface 47 is a circuit that controls the DRAM 6. The DRAM interface 47 stores data in the DRAM 6. In addition, the DRAM interface 47 reads the data stored in the DRAM 6.

[0069] Next, the configuration of the DRAM 6 will be described.

[0070] The DRAM 6 includes a storage area for storing a logical-to-physical address translation table (L2P table) 61. The DRAM 6 further includes a storage area for storing a valid flag table 62, a storage area for storing an active block list 63, and a storage area for storing a free block list 64.

[0071] The L2P table 61 is a table that stores mapping information. The mapping information is information that indicates the mapping between each logical address and each physical address of the NAND flash memory 5 in a unit of a predetermined management size. The logical address is an address used by the host 2 to access the SSD 3. As the logical address, for example, a logical block address (LBA) is used. The physical address is an address that indicates a storage location in the NAND flash memory 5. The physical address can be expressed by, for example, a flash die address, a block address, a page address, an offset address within a page, or any combination of all or part of these.

[0072] The valid flag table 62 is a table for managing a plurality of flags. Each of the plurality of flags corresponds to each of the plurality of physical addresses in the SSD 3 in a one-to-one relationship. Each of the plurality of flags indicates whether the data stored in the storage location indicated by the corresponding physical address is valid data or invalid data. For example, a first flag corresponding to a first physical address is set to a first value indicating valid data in response to data associated with a write command received from the host 2 being written to the first storage location indicated by the first physical address. Then, in response to the data stored in the first storage location becoming invalid data due to an update or deletion of the data stored in the first storage location, the first flag is set to a second value corresponding to invalid data. Here, the update of the data stored in the first storage location means that the updated data (new data) corresponding to the logical address of this data has been written to the NAND flash memory 5. Also, the deletion of the data stored in the first storage location means that this data has been invalidated by a trim command.

[0073] The active block list 63 is a table that manages a list of active blocks, which are blocks that hold at least valid data.

[0074] The free block list 64 is a table that manages a list of free blocks, which are blocks that do not hold valid data.

[0075] Next, a description will be given of the functional configuration of the CPU 43. The CPU 43 includes a read processing unit 431 and a write processing unit 432 in addition to the components that function as an FTL.

[0076] A part or the whole of each of the read processing unit 431 and the write processing unit 432 may be realized by dedicated hardware of the controller 4.

[0077] The read processing unit 431 executes a read process by processing each read command received from the host 2. The read process includes a process of converting a logical address specified by the read command into a physical address by referring to the L2P table 61, a process of reading data from a storage location in the NAND flash memory 5 indicated by the physical address, and a process of transferring the read data to the memory 22 of the host 2.

[0078] The write processing unit 432 executes write processing by processing each write command received from the host 2. The write processing includes a process of loading (transferring) write data from the memory 22 of the host 2 to the SRAM 42 or the DRAM 6, a process of writing the write data loaded to the SRAM 42 or the DRAM 6 to a storage location in the NAND flash memory 5, and a process of updating the L2P table 61 to map a physical address indicating the storage location where the write data has been written to a logical address specified by the write command.

[0079] The write processing unit 432 includes a flash PBA allocation unit 433 .

[0080] The flash PBA allocation unit 433 allocates, to the LBA specified by the write command, a PBA indicating a storage location in the NAND flash memory 5 where data associated with this write command should be written. The PBA allocated to the LBA is a PBA indicating a storage location available for writing update data (new data).

[0081] Next, a description will be given of the valid flag table 62. Fig. 4 is a diagram showing an example of the configuration of the valid flag table 62 used in the memory system according to the embodiment.

[0082] The valid flag table 62 includes a plurality of valid flag table areas 62-0, ..., 62-n. Each of the plurality of valid flag table areas 62-1, ..., 62-n corresponds to one block BLK among the plurality of blocks BLK1, ..., BLKn.

[0083] For example, the valid flag table area 62-1 corresponds to the block BLK1. The valid flag table area 62-1 includes a number of flags. The flags are also referred to as bitmap data. The bitmap data stored in the valid flag table area 62-1 includes the same number of bits (i.e., flags) as the number of physical addresses (PBAs) indicating the storage locations included in the block BLK1. Each of the flags indicates whether the data stored in the storage location indicated by the physical address corresponding to the flag is valid or not. The flag corresponding to the physical address indicating the storage location where valid data is stored is set to a first value (e.g., “1”). Also, the flag corresponding to the physical address indicating the storage location where invalid data is stored is set to a second value (e.g., “0”). In the following, a case where the first value is “1” and the second value is “0” will be described as an example.

[0084] For example, page P0 of block BLK1 includes four storage locations respectively indicated by four PBAs (PBAx, PBA(x+1), PBA(x+2), PBA(x+3)). Data D0, data D1, data D2, and data D3 are stored in these four storage locations. When each of data D0, data D2, and data D3 is valid data and data D1 is invalid data, the four flags corresponding to the four PBAs (PBAx, PBA(x+1), PBA(x+2), PBA(x+3)), i.e., the four-bit bitmap data, indicate "1011".

[0085] Page P1 of block BLK1 includes four storage locations respectively indicated by four PBAs (PBA(x+4), PBA(x+5), PBA(x+6), PBA(x+7)). Data D4, data D5, data D6, and data D7 are stored in these four storage locations. When each of data D4, data D5, data D6, and data D7 is valid data, the four flags corresponding to the four PBAs (PBA(x+4), PBA(x+5), PBA(x+6), PBA(x+7)), i.e., the 4-bit bitmap data, indicate "1111".

[0086] Page P2 of block BLK1 includes four storage locations respectively indicated by four PBAs (PBA(x+8), PBA(x+9), PBA(x+10), PBA(x+11)). Data D8, data D9, data D10, and data D11 are stored in these four storage locations. If each of data D8 and data D9 is valid data and each of data D10 and data D11 is invalid data, the four flags corresponding to the four PBAs (PBA(x+8), PBA(x+9), PBA(x+10), PBA(x+11)), i.e., the 4-bit bitmap data, indicate "1100".

[0087] FIG. 5 is a diagram showing a configuration example relating to control of write data and read data in the memory system according to the embodiment.

[0088] In a data write operation to the NAND flash memory 5, the memory system 3 writes data to a storage location indicated by the write destination PBA output from the flash PBA allocation unit 433. This data is data output by the error correction circuit 45, that is, a codeword (ECC frame) including data to be written to the NAND flash memory 5 and ECC. The data to be written to the NAND flash memory 5 includes, for example, user data, an LBA, and a check code. The data to be written to the NAND flash memory 5 may further include a PBA. The user data is data associated with a write command received from the host 2. The LBA is a write destination LBA to which the user data is to be written, that is, an LBA (request LBA) specified by the write command. The PBA is a write destination PBA output from the flash PBA allocation unit 433 according to the request LBA specified by the write command.

[0089] In a data read operation from the NAND flash memory 5, the memory system 3 reads data (e.g., user data, LBA, check code, ECC) stored in a memory location indicated by a read target PBA recorded in the L2P table 61. The read data is sent to the error correction circuit 45.

[0090] When the SSD 3 receives a write command from the host 2, the check circuit 44 generates a check code (e.g., a CRC) using, for example, the data associated with the write command, the request LBA specified by the write command, the write destination PBA, and a flag having a value indicating valid data. Then, the check circuit 44 outputs the data associated with the write command, the request LBA, and the generated CRC to the error correction circuit 45.

[0091] When the SSD 3 receives a read command from the host 2, the check circuit 41 generates a check code in the check code generation circuit 441 using, for example, the data read from the NAND flash memory 5, the requested LBA (read target LBA) designated by the read command, the read target PBA acquired from the L2P table 61, and a flag corresponding to the read target PBA. Here, the read target PBA is a PBA that is mapped to the read target LBA when the read command is executed. Then, the check circuit 44 compares the check code generated in the check code generation circuit 441 with the check code read from the NAND flash memory 5. When the comparison results of the two check codes match each other, the check circuit 44 determines that the read data (user data) is correct data. The read data is transmitted to the host 2 via the host I / F 41. On the other hand, when the comparison results of the two check codes do not match each other, the check circuit 44 determines that the read data is incorrect data. In this case, an error is notified to the host 2 via the host I / F 41.

[0092] The error correction circuit 45 encodes data to be written to the NAND flash memory 5 or decodes read data. The error correction circuit 45 receives the data, LBA, and check code from the check circuit 44 and generates an ECC using the data, LBA, and check code. The error correction circuit 45 then outputs the data, LBA, check code, and ECC to the NAND flash memory 5.

[0093] The error correction circuit 45 receives the data, LBA, check code, and ECC read from the NAND flash memory 5 and performs error correction using the ECC. When the error correction is completed, the error correction circuit 45 outputs the data, LBA, and check code to the check circuit 44.

[0094] The L2P table 61 manages the mapping between each LBA and each PBA corresponding to each LBA. When the SSD 3 receives a write command or a trim command from the host 2, the controller 4 acquires from the L2P table 61 a PBA (also called a final PBA) corresponding to the requested LBA specified by the received command. The final PBA is a PBA that is mapped to the LBA specified by the write command or trim command at the time of receiving the write command or trim command. The acquired final PBA is output to the valid flag table 62. When the SSD 3 receives a read command from the host 2, the controller 4 acquires from the L2P table 61 a PBA (read target PBA) corresponding to the requested LBA specified by the received read command. The read target PBA is output to the NAND flash memory 5 and the valid flag table 62. In addition, in a write process or a GC process, the L2P table 61 is updated so that the write destination PBA output from the flash PBA allocation unit 433 is mapped to the LBA specified by the write command.

[0095] The valid flag table 62 manages a plurality of flags corresponding to different PBAs. When the SSD3 receives a write command from the host 2, the flag in the valid flag table 62 corresponding to the last PBA recorded in the L2P table 61 is set to a second value. Then, the flag corresponding to the write destination PBA output from the flash PBA allocation unit 433 is set to a first value. When the SSD3 receives a read command from the host 2, the controller 4 acquires a flag corresponding to the read target PBA recorded in the L2P table 61 from the valid flag table 62, and outputs the acquired flag to the inspection circuit 44. Furthermore, when the SSD3 executes GC processing, the controller 4 selects PBAs corresponding to the flags set to the first value from the plurality of PBAs of the GC copy source block, and outputs each of the selected PBAs to the flash PBA allocation unit 433 as a GC copy source PBA. The flash PBA allocation unit 433 determines the GC copy destination PBA as a write destination PBA for each GC copy source PBA. When valid data stored in a memory location indicated by the GC copy source PBA is copied to a memory location indicated by the GC copy destination PBA, a flag corresponding to the GC copy source PBA is set to a second value, and a flag corresponding to the GC copy destination PBA is set to a first value.

[0096] Next, various processes in the configuration example of the memory system shown in Fig. 5 will be described below. More specifically, the write process, invalidation process, read process, and garbage collection process of the memory system will be described in order with reference to Figs. 6, 7, 8, and 9, respectively. 6 is a diagram for explaining the flow of a write process in the memory system. In response to receiving a write command from the host 2, the controller 4 of the SSD 3 starts the write process. Here, as an example, a case will be described below in which the check is performed by the second method (check code determination method) and the additional information is a check code (check code additional information).

[0097] (1) The write destination LBA designated by the write command received from the host 2 is output to the L2P table 61, the flash PBA allocation unit 433, and the check circuit .

[0098] (2) The controller 4 obtains, as the final PBA, the PBA that is mapped to the write destination LBA when the write command is executed, from the L2P table 61. The controller 4 sets the flag in the valid flag table 62 that corresponds to the final PBA to a second value.

[0099] (3) The flash PBA allocation unit 433 of the controller 4 determines a memory location where the data associated with the received write command should be written, and allocates the write destination PBA indicating this memory location to the write destination LBA. The flash PBA allocation unit 433 outputs the write destination PBA to the NAND flash memory 5, the L2P table 61, and the valid flag table 62.

[0100] (4) Furthermore, the flash PBA allocation unit 433 outputs the write destination PBA to the check circuit 44.

[0101] (5) The check circuit 44 generates a check code using the data associated with the received write command, a flag having a first value, the destination LBA, and the destination PBA. This flag does not need to be a flag corresponding to a specific memory location, but is simply a bit having a first value. The generated check code is, for example, a CRC. The check circuit 44 outputs the data and the generated check code to the error correction circuit 45.

[0102] (6) The error correction circuit 45 generates an error correction code (ECC) using the data and the check code. Then, the error correction circuit 45 outputs the data, the check code, and the ECC to the NAND flash memory 5 as data (ECC frame) to be written to the NAND flash memory 5. The NAND flash memory 5 writes the ECC frame to the memory location indicated by the write destination PBA.

[0103] (7) Then, the controller 4 updates the mapping information in the L2P table 61 so that the write destination PBA is mapped to the write destination LBA. Also, the controller 4 sets the flag in the valid flag table 62 corresponding to the write destination PBA to a first value.

[0104] 7 is a diagram for explaining the flow of the invalidation process, focusing on a configuration example portion related to the invalidation process of the memory system. In response to receiving a trim command from the host 2, the controller 4 of the SSD 3 starts the invalidation process.

[0105] (1) The LBA corresponding to the data to be invalidated, which is specified by a TRIM command received from the host 2, is output to the L2P table 61.

[0106] (2) The controller 4 obtains, as the final PBA, the PBA that is mapped to the LBA corresponding to the data to be invalidated at the time of execution of the TRIM command from the L2P table 61. The controller 4 sets the flag in the valid flag table 62 that corresponds to the final PBA to a second value. 8 is a diagram for explaining the flow of the read process, focusing on the configuration example portion related to the read process of the memory system. In response to receiving a read command from the host 2, the controller 4 of the SSD 3 executes the read process.

[0107] (1) The read target LBA designated by the read command is output to the L2P table 61 and the check circuit 44.

[0108] (2) The controller 4 obtains, as the read target PBA, the PBA that is mapped to the read target LBA at the time of executing the read command, from the L2P table 61. The controller 4 outputs the obtained read target PBA to the check circuit 44 and the valid flag table 62.

[0109] (3) The controller 4 acquires a flag corresponding to the PBA to be read from the valid flag table 62. The controller 4 outputs the acquired flag to the check circuit .

[0110] (4) The controller 4 outputs the read target PBA to the NAND flash memory 5, and instructs the NAND flash memory 5 to read data.

[0111] (5) The NAND flash memory 5 reads the data (ECC frame) stored in the memory location indicated by the read target PBA, and outputs it to the error correction circuit 45.

[0112] (6) The error correction circuit 45 decodes the ECC frame to generate error-corrected data (user data and check code). The error correction circuit 45 outputs the generated data and check code to the check circuit .

[0113] (7) The check circuit 44 generates a check code in the check code generation circuit 441 using the user data output from the error correction circuit 45, the flag acquired from the valid flag table 62, the LBA to be read, and the PBA to be read. The check circuit 44 compares the check code output from the error correction circuit 45 with the generated check code. If the two check codes match each other, the check circuit 44 determines that correct user data has been read, and transmits the read user data to the host 2. If the two check codes do not match each other, the check circuit 44 determines that incorrect data has been read, and executes error processing. In the error processing, the controller 4 does not transmit the read user data to the host 2, and notifies the host 2 of an error, for example.

[0114] 9 is a diagram for explaining the flow of garbage collection processing of the memory system. The controller 4 of the SSD 3 starts GC processing in response to the number of free blocks in the SSD 3 falling below a threshold. When the GC processing starts, an arbitrary block is selected as a copy source block from a set of blocks managed by the active block list 63. The selected block is, for example, a block in which the ratio of valid data to the stored data is low.

[0115] (1) The valid flag table 62 selects, as a GC copy source PBA, a PBA whose corresponding flag indicates a first value from among multiple PBAs corresponding to multiple storage locations included in the copy source block. The valid flag table 62 outputs the selected PBA to the flash PBA allocation unit 433 as the GC copy source PBA.

[0116] (2) The controller 4 outputs the GC copy source PBA as the read target PBA to the NAND flash memory 5, and instructs the NAND flash memory 5 to read data.

[0117] (3) The NAND flash memory 5 reads the data (ECC frame) from the read target PBA and outputs it to the error correction circuit 45.

[0118] (4) The error correction circuit 45 decodes the ECC frame to generate error-corrected data (user data and check code). The error correction circuit 45 outputs the generated data and check code to the check circuit .

[0119] (5) The flash PBA allocating unit 433 allocates, as a GC copy destination PBA, a physical address indicating a storage location where the data read from the GC copy source PBA should be written. The flash PBA allocating unit 433 outputs the allocated GC copy destination PBA to the NAND flash memory 5.

[0120] (6) The flash PBA allocation unit 433 outputs the allocated GC copy destination PBA to the inspection circuit 44.

[0121] (7) The check circuit 44 generates a check code in the check code generation circuit 441 using the data (GC copy target data) read from the GC copy source PBA of the NAND flash memory 5, the flag having the first value, the GC copy target LBA, and the GC copy destination PBA. The check circuit 44 outputs the GC copy target data and the generated check code to the error correction circuit 45.

[0122] (8) The error correction circuit 45 generates an error correction code (ECC) using the data to be GC copied and the check code. Then, the error correction circuit 45 outputs the data to be GC copied, the check code, and the ECC as write data (ECC frame) to the NAND flash memory 5. The NAND flash memory 5 writes the write data (ECC frame) to a storage location indicated by the GC copy destination PBA output by the flash PBA allocation unit 433.

[0123] (9) Then, the controller 4 obtains, as the final PBA, the PBA that is mapped to the LBA corresponding to the GC copy target data at the time of execution of the copy operation from the L2P table 61. The controller 4 updates the mapping information in the L2P table 61 so that the GC copy destination PBA is mapped to the LBA corresponding to the GC copy target data. Then, the controller 4 sets the flag in the valid flag table 62 that corresponds to the GC copy destination PBA to a first value.

[0124] (10) The controller 4 sets the flag in the valid flag table 62 corresponding to the obtained final PBA to a second value.

[0125] In this manner, write processing, invalidation processing, read processing, and garbage collection processing are performed in the memory system.

[0126] Next, various inspection methods for the memory system of this embodiment will be described below using specific examples. (First method (logical / physical map flag determination method (data PBA and / or LBA flag)) and inspection using PBA additional information) First, a description will be given of a case where read data is inspected using a physical address stored in the NAND flash memory 5 together with the data and a value of a valid flag managed in the valid flag table 62. That is, a description will be given of a case where the flag is inspected using the first method (logical-physical map flag determination method) and the additional information is the PBA itself (PBA additional information).

[0127] First, the write data will be described. Fig. 10 is a diagram showing a first example of write data in the memory system according to the embodiment.

[0128] The write-related data is data related to data to be written to the NAND flash memory 5 and used in the write process. The write-related data includes, for example, user data, an LBA, and a PBA. The user data is data associated with a write command received from the host 2. The LBA is a requested LBA (destination LBA) specified by this write command. The PBA is a destination PBA assigned to the destination LBA by the flash PBA allocation unit 433. It is sufficient for the write-related data to include the user data and the PBA, and it does not necessarily have to include the LBA.

[0129] The check code generation circuit 441 generates a check code by using at least user data. Note that the check code generation circuit 441 may generate a check code by using either the LBA or the PBA, or both the LBA and the PBA, in addition to the user data.

[0130] The error correction circuit 45 encodes a data set including the user data, the LBA, the PBA, and the check code to generate an ECC frame. Then, the ECC frame including the user data, the LBA, the PBA, the check code, and the ECC is written to the same page of the NAND flash memory 5.

[0131] Next, a case will be described where the write data explained in Fig. 10 is read from the NAND flash memory 5. Fig. 11 is a diagram showing a first example of read data in the memory system according to the embodiment.

[0132] The data read from the NAND flash memory 5 includes user data, an LBA, a PBA, a check code, and an ECC. The error correction circuit 45 executes a decoding process to perform error correction on the read data.

[0133] When the error correction is completed, the error correction circuit 45 outputs the user data, the LBA, the PBA, and the check code.

[0134] The flag check circuit 443 checks whether the value of the flag corresponding to the PBA mapped to the LBA specified by the read command at the time of reading is maintained at a first value. If the flag is the first value, the flag check circuit 443 determines that correct data has been read. If the flag is the second value, the flag check circuit 443 determines that incorrect data has been read due to a corruption of part of the mapping information of the L2P table 61.

[0135] The PBA check circuit 444 checks whether the PBA mapped to the LBA specified by the read command at the time of reading matches the PBA output by the error correction circuit 45. If the two PBAs match, the PBA check circuit 444 determines that correct data has been read. If the two PBAs do not match, the PBA check circuit 444 determines that incorrect user data has been read due to a malfunction of the address decoder of the NAND flash memory 5.

[0136] The LBA check circuit 445 checks whether the LBA specified by the read command received from the host 2 matches the LBA output by the error correction circuit 45. If the two LBAs match, the LBA check circuit 445 determines that correct data has been read. If the two LBAs do not match, the LBA check circuit 445 determines that incorrect data has been read due to corruption of part of the mapping information in the L2P table 61.

[0137] The check code generation circuit 441 generates a check code by using at least the user data output by the error correction circuit 45. For example, assume that when writing this data, a check code is generated by using either or both of the LBA and the PBA in addition to the user data. In this case, the check code generation circuit 441 generates a check code by using, in addition to the user data output by the error correction circuit 45, either or both of the LBA specified by the read command and the PBA mapped to this LBA at the time of reading.

[0138] The check code inspection circuit 442 checks whether the check code generated by the check code generation circuit 441 matches the check code output by the error correction circuit 45. If the two check codes do not match, the check code inspection circuit 442 determines that incorrect data has been read. If the two check codes match, the check code inspection circuit 442 determines that correct data has been read.

[0139] If the check code check circuit 442 , the flag check circuit 443 , the PBA check circuit 444 , and the LBA check circuit 445 all determine that correct data has been read, the controller 4 transmits the read data to the host 2 .

[0140] If any of the check code inspection circuit 442, the flag inspection circuit 443, the PBA inspection circuit 444, and the LBA inspection circuit 445 determines that incorrect data has been read, the controller 4 executes error processing. For example, as the error processing, the controller 4 notifies the host 2 of the error. In this case, the controller 4 may send a response indicating that the processing of the read command has failed to the host 2 as a completion response indicating the completion of the read command.

[0141] Furthermore, when only the PBA inspection circuit 444 determines that incorrect user data has been read, the controller 4 may execute again, as error processing, a process of reading data from the storage location in the NAND flash memory 5 indicated by the read target PBA. This is because it is assumed that the cause of only the PBA inspection circuit 444 detecting an error is a malfunction of the address decoder in the NAND flash memory 5, causing data to be read from a storage location different from the storage location indicated by the read target PBA.

[0142] Next, a procedure of the write process will be described with reference to a flowchart of FIG 12. The procedure of the write process of the memory system according to the embodiment is shown in FIG. In response to the SSD 3 receiving a write command from the host 2 (step S1001), the controller 4 starts the write process.

[0143] The controller 4 judges whether old data is associated with the write destination LBA specified by the write command received in S1001 (step S1002). When the PBA is mapped to the write destination LBA from the L2P table 61, the controller 4 judges that old data is associated with the write destination LBA.

[0144] If old data is associated with the write destination LBA (Yes in S1002), the controller 4 obtains the last PBA mapped to the write destination LBA from the L2P table 61 (step S1003).

[0145] The controller 4 resets the flag in the valid flag table 62 corresponding to the final PBA (step S1004). In step S1004, the flag in the valid flag table 62 corresponding to the final PBA is set to the second value.

[0146] If no old data is associated with the write destination LBA (No in S1002), the controller 4 skips the processes of S1003 and S1004.

[0147] The controller 4 assigns a new PBA to the write destination LBA (step S1005). The assigned PBA is a write destination PBA that indicates the storage location where the data associated with the write command should be written.

[0148] The controller 4 generates a check code in the check code generation circuit 441 using the data associated with the write command received in S1001 and the write destination LBA (step S1006). This check code is a code for checking the consistency of information including the data and the write destination LBA.

[0149] The controller 4 encodes the data, the write destination LBA, the write destination PBA, and the check code to generate a codeword (ECC frame) (step S1007).

[0150] The controller 4 writes the data, the write destination LBA, the write destination PBA, the check code, and the ECC to a storage location in the NAND flash memory 5 that is indicated by the write destination PBA (step S1008).

[0151] The controller 4 sets a flag corresponding to the write destination PBA in the valid flag table 62 (step S1009), and ends the write process. In step S1009, the controller 4 sets the flag corresponding to the write destination PBA to the first value.

[0152] 12, a case has been described in which data, a write destination LBA, a write destination PBA, and a check code are written to the NAND flash memory 5. However, the controller 4 may write only the data, the write destination PBA, and the check code to the NAND flash memory 5 without writing the write destination LBA to the NAND flash memory 5. This is because the check code is generated using the data and the write destination LBA.

[0153] Next, a procedure of a read process will be described with reference to a flowchart of FIG 13. The procedure of a read process of the memory system according to the embodiment is shown in FIG.

[0154] In response to the SSD 3 receiving a read command from the host 2 (step S1101), the controller 4 starts the read process.

[0155] The controller 4 acquires the PBA corresponding to the LBA designated by the read command received in S1101 from the L2P table 61 (step S1102).

[0156] The controller 4 acquires a flag corresponding to the PBA acquired in S1102 from the valid flag table 62 (step S1103).

[0157] The controller 4 reads the data to be read (here, the user data, LBA, PBA, and check code) stored in the storage location indicated by the PBA acquired in S1102 from the NAND flash memory 5 (step S1104).

[0158] The controller 4 generates a check code in the check code generation circuit 441 using the user data included in the read target data read in S1104 and the LBA specified by the read command received in S1101 (step S1105).

[0159] The controller 4 determines whether or not the check code generated in S1105 matches the check code included in the data to be read out in S1104 (step S1106).

[0160] The controller 4 determines whether or not the PBA acquired from the L2P table 61 in S1102 matches the PBA included in the data to be read out in S1104 (step S1107).

[0161] The controller 4 determines whether or not the flag acquired in S1103 is set to a value indicating validity (step S1108).

[0162] The determinations of S1106, S1107, and S1108 may be performed in any order.

[0163] If the check code generated in S1105 matches the check code included in the data to be read read in S1104 (Yes in S1106), if the PBA obtained from L2P table 61 in S1102 matches the PBA included in the data to be read read in S1104 (Yes in S1107), and if the flag obtained in S1103 is set to a value indicating valid (Yes in S1108), the controller 4 sends the data (user data) included in the data to be read read in S1104 to the host 2 (step S1109), and terminates the read process.

[0164] If the check code generated in S1105 does not match the check code contained in the data to be read out in S1104 (No in S1106), if the PBA obtained from L2P table 61 in S1102 does not match the PBA contained in the data to be read out in S1104 (No in S1107), or if the flag obtained in S1103 is set to a value indicating invalid (No in S1108), the controller 4 executes error processing (step S1110) and terminates the read processing.

[0165] In the above description, the case where all of the flag, PBA, and check code are checked has been described, but in the check using the first method (logical-physical map flag determination method) and the PBA (PBA additional information), the check using the check code (S1106) may be omitted. That is, in the check using the first method (logical-physical map flag determination method) and the PBA (PBA additional information), the controller 4 determines whether or not to transmit the data read from the NAND flash memory 5 to the host 2 based on whether or not the following conditions are satisfied: the flag acquired in S1103 is set to a value indicating validity, and the PBA read from the NAND flash memory 5 matches the latest PBA acquired from the L2P table 61.

[0166] (Second method (check code judgment method (data flag PBA)) and check code additional information inspection) Next, a case where a check code is generated using at least the data, the flag, and the physical address, and the read data is checked using the check code will be described. That is, a case where the flag is checked using the second method (check code determination method) and the additional information is the check code (check code additional information) will be described.

[0167] First, the write data will be described. Fig. 14 is a diagram showing a second example of the write data in the memory system according to the embodiment.

[0168] The write-related data includes user data, an LBA, a PBA, and a flag. The user data is data associated with a write command received from the host 2. The LBA is a requested LBA (destination LBA) specified by this write command. The PBA is a destination PBA assigned to the destination LBA by the flash PBA allocation unit 433. The flag is a flag having a first value indicating valid data, that is, 1-bit information indicating, for example, "1".

[0169] Here, the check code generation circuit 441 generates the check code using at least the user data, the PBA, and the flag. Also, the check code generation circuit 441 may generate the check code using the LBA in addition to the user data, the PBA, and the flag.

[0170] Then, the error correction circuit 45 encodes the data set including the user data, the LBA, and the check code to generate an ECC frame. Then, the ECC frame including the user data, the LBA, the check code, and the ECC is written to the same page of the NAND flash memory 5.

[0171] Next, a case will be described where the write data explained in Fig. 14 is read from the NAND flash memory 5. Fig. 15 is a diagram showing a second example of read data in the memory system according to the embodiment.

[0172] The data read from the NAND flash memory 5 includes user data, an LBA, a check code, and an ECC. The error correction circuit 45 executes a decoding process to perform error correction on the read data.

[0173] When the error correction is completed, the error correction circuit 45 outputs the user data, the LBA, and the check code.

[0174] The check code generation circuit 441 generates a check code by using the user data output by the error correction circuit 45, the PBA associated with the read target LBA in the L2P table 61, and the flag associated with this PBA in the valid flag table 62. If a check code was generated using an LBA in addition to the user data, PBA, and flag when writing this data, the check code generation circuit 441 further generates a check code by using the read target LBA specified by the read command received from the host 2.

[0175] The check code inspection circuit 442 checks whether the check code generated by the check code generation circuit 441 matches the check code output by the error correction circuit 45. If the two check codes do not match, the check code inspection circuit 442 determines that incorrect user data has been read. If the two check codes match, the check code inspection circuit 442 determines that correct user data has been read.

[0176] If the check code inspection circuit 442 determines that correct user data has been read, the controller 4 transmits the read user data to the host 2.

[0177] If the check code inspection circuit 442 determines that incorrect user data has been read, the controller 4 executes error processing. For example, as the error processing, the controller 4 notifies the host 2 of the error.

[0178] Next, a procedure of the write process will be described with reference to a flowchart shown in FIG 16. The procedure of the write process of the memory system according to the embodiment is shown in FIG.

[0179] In response to the SSD 3 receiving a write command from the host 2 (step S1201), the controller 4 starts the write process.

[0180] The controller 4 determines whether old data is associated with the write destination LBA specified by the write command received in S1201 (step S1202). If a PBA is mapped to the write destination LBA in the L2P table 61, the controller 4 determines that old data is associated with the write destination LBA.

[0181] If old data is associated with the write destination LBA (Yes in S1202), the controller 4 obtains the last PBA mapped to the write destination LBA from the L2P table 61 (step S1203).

[0182] The controller 4 resets the flag in the valid flag table 62 corresponding to the final PBA (step S1204). In step S1204, the flag in the valid flag table 62 corresponding to the final PBA is set to the second value.

[0183] If no old data is associated with the write destination LBA (No in S1202), the controller 4 skips the processes of S1003 and S1004.

[0184] The controller 4 assigns a new PBA to the write destination LBA (step S1205). The assigned PBA is a write destination PBA that indicates the storage location where the data associated with the write command should be written.

[0185] The controller 4 uses the data associated with the write command received in S1201, the write destination LBA, the PBA assigned in S1205, and the flag set to a value indicating validity to generate a check code in the check code generation circuit 441 (step S1206). This check code is a code for checking the consistency of information including the data, the write destination LBA, the PBA, and the flag.

[0186] The controller 4 encodes the data, the write destination LBA, and the check code to generate a codeword (ECC frame) (step S1207).

[0187] The controller 4 writes the data, the write destination LBA, the check code, and the ECC to a storage location in the NAND flash memory 5 that is indicated by the write destination PBA (step S1208).

[0188] The controller 4 sets a flag corresponding to the write destination PBA in the valid flag table 62 (step S1209), and ends the write process. In step S1209, the controller 4 sets the flag corresponding to the write destination PBA to the first value.

[0189] In the write process shown in FIG. 16, the case where data, destination LBA, and check code are written to the NAND flash memory 5 has been described. However, it is also possible to write only the data and check code to the NAND flash memory 5 without writing the destination LBA to the NAND flash memory 5.

[0190] Next, the procedure of the read process will be described with reference to Fig. 17. Fig. 17 is a flowchart showing a second example of the procedure of the read process of the memory system according to the embodiment.

[0191] In response to the SSD 3 receiving a read command from the host 2 (step S1301), the controller 4 starts the read process.

[0192] The controller 4 acquires the PBA corresponding to the LBA designated by the read command received in S1301 from the L2P table 61 (step S1302).

[0193] The controller 4 acquires a flag corresponding to the PBA acquired in S1302 from the valid flag table 62 (step S1303).

[0194] The controller 4 reads the data to be read (here, data, LBA, and check code) stored in the storage location indicated by the PBA acquired in S1302 from the NAND flash memory 5 (step S1304).

[0195] The controller 4 generates a check code in the check code generation circuit 441 using the data contained in the read target data read in S1304, the LBA specified by the read command received in S1301, the PBA obtained in S1302, and the flag obtained in S1303 (step S1305).

[0196] The controller 4 determines whether or not the check code generated in S1305 matches the check code included in the data to be read out in S1304 (step S1306).

[0197] If the check code generated in S1305 matches the check code contained in the read target data read in S1304 (Yes in S1306), the controller 4 sends the data (user data) contained in the read target data read in S1304 to the host 2 (step S1307), and terminates the read process.

[0198] If the check code generated in S1305 does not match the check code included in the data to be read out in S1304 (No in S1306), the controller 4 executes error processing (step S1308) and ends the read processing. (First method (logical-physical map flag determination method) and inspection using check code additional information) Next, a description will be given of a case where read data is checked using a check code generated using data and a physical address, and a flag value managed in the valid flag table 62. That is, a description will be given of a case where the flag is checked using the first method (logical-physical map flag determination method) and the additional information is a check code.

[0199] First, the write data will be described. Fig. 18 is a diagram showing a third example of the write data in the memory system according to the embodiment.

[0200] The write-related data includes user data, an LBA, and a PBA. The user data is data associated with a write command received from the host 2. The LBA is a request LBA (write destination LBA) specified by this write command. The PBA is a write destination PBA assigned to the write destination LBA by the flash PBA allocation unit 433.

[0201] The check code generation circuit 441 generates a check code using at least the user data and the write destination PBA. The check code generation circuit 441 may generate a check code using the LBA in addition to the user data and the write destination PBA.

[0202] The error correction circuit 45 encodes a data set including the user data, the LBA, and the check code to generate an ECC frame. Then, the ECC frame including the user data, the LBA, the check code, and the ECC is written to the same page of the NAND flash memory 5.

[0203] Next, a case will be described where the write data explained in Fig. 18 is read from the NAND flash memory 5. Fig. 19 is a diagram showing a third example of read data in the memory system according to the embodiment.

[0204] The data read from the NAND flash memory 5 includes user data, an LBA, a check code, and an ECC. The error correction circuit 45 executes a decoding process to perform error correction on the read data.

[0205] When the error correction is completed, the error correction circuit 45 outputs the user data, the LBA, and the check code.

[0206] The check code generation circuit 441 generates a check code by using the user data output by the error correction circuit 45 and the PBA associated with the read target LBA specified by the read command received from the host 2. If an LBA was used in addition to the user data and PBA when writing this data, the check code generation circuit 441 generates a check code by using the user data output by the error correction circuit 45, the PBA associated with the LBA specified by the read command received from the host 2, and the LBA specified by the read command received from the host 2.

[0207] The check code inspection circuit 442 checks whether the check code generated by the check code generation circuit 441 matches the check code output by the error correction circuit 45. If the two check codes do not match, the check code inspection circuit 442 determines that incorrect user data has been read. If the two check codes match, the check code inspection circuit 442 determines that correct user data has been read.

[0208] The flag check circuit 443 checks whether the value of the flag corresponding to the PBA associated with the read target LBA specified by the read command in the L2P table 61 is a first value. If the flag is the first value, the flag check circuit 443 determines that correct user data has been read. If the flag is the second value, the flag check circuit 443 determines that incorrect user data has been read.

[0209] If the check code inspection circuit 442 and the flag inspection circuit 443 determine that correct user data has been read, the controller 4 transmits the read user data to the host 2 .

[0210] If the check code inspection circuit 442 or the flag inspection circuit 443 determines that incorrect user data has been read, the controller 4 executes error processing. For example, as the error processing, the controller 4 notifies the host 2 of the error.

[0211] Furthermore, when only the check code inspection circuit 442 determines that incorrect user data has been read, the controller 4 may execute again, as error processing, a process of reading data from the storage location in the NAND flash memory 5 indicated by the read target PBA. This is because it is assumed that the cause of only the check code inspection circuit 442 detecting an error is a malfunction of the address decoder in the NAND flash memory 5 causing data to be read from a storage location different from the storage location indicated by the read target PBA.

[0212] Next, a procedure of the write process will be described with reference to Fig. 20. Fig. 20 is a flowchart showing a third example of the procedure of the write process of the memory system according to the embodiment.

[0213] In response to the SSD 3 receiving a write command from the host 2 (step S1401), the controller 4 starts the write process.

[0214] The controller 4 judges whether old data is associated with the write destination LBA specified by the write command received in S1401 (step S1402). If a PBA is mapped to the write destination LBA in the L2P table 61, the controller 4 judges that old data is associated with the write destination LBA.

[0215] If old data is associated with the write destination LBA (Yes in S1402), the controller 4 obtains the last PBA mapped to the write destination LBA from the L2P table 61 (step S1403).

[0216] The controller 4 resets the flag in the valid flag table 62 corresponding to the final PBA (step S1404). In step S1404, the flag in the valid flag table 62 corresponding to the final PBA is set to the second value.

[0217] If no old data is associated with the write destination LBA (No in S1402), the controller 4 skips the processes of S1403 and S1404.

[0218] The controller 4 assigns a new PBA to the write destination LBA (step S1405). The assigned PBA is a write destination PBA that indicates the storage location where the data associated with the write command should be written.

[0219] The controller 4 uses the data associated with the write command received in S1401, the write destination LBA, and the write destination PBA assigned in S1405 to generate a check code in the check code generation circuit 441 (step S1406). This check code is a code for checking the consistency of information including the data, the write destination LBA, and the write destination PBA.

[0220] The controller 4 encodes the data, the write destination LBA, and the check code to generate a codeword (ECC frame) (step S1407).

[0221] The controller 4 writes the data, the write destination LBA, the check code, and the ECC to a storage location in the NAND flash memory 5 that is indicated by the write destination PBA (step S1408).

[0222] The controller 4 sets a flag corresponding to the write destination PBA in the valid flag table 62 (step S1409), and ends the write process. In step S1409, the controller 4 sets the flag corresponding to the write destination PBA to the first value.

[0223] 20, the case where the data, the write destination LBA, and the check code are written to the NAND flash memory 5 has been described, but it is also possible to write only the data and the check code to the NAND flash memory 5 without writing the write destination LBA to the NAND flash memory 5. This is because the check code is generated using the data, the write destination LBA, and the write destination PBA.

[0224] Next, the procedure of the read process will be described with reference to Fig. 21. Fig. 21 is a flowchart showing a third example of the procedure of the read process of the memory system according to the embodiment.

[0225] In response to the SSD 3 receiving a read command from the host 2 (step S1501), the controller 4 starts the read process.

[0226] The controller 4 acquires from the L2P table 61 the PBA corresponding to the LBA specified by the read command received in S1501 (step S1502).

[0227] The controller 4 acquires a flag corresponding to the PBA acquired in S1502 from the valid flag table 62 (step S1503).

[0228] The controller 4 reads the data to be read (here, data, LBA, and check code) stored in the storage location indicated by the PBA acquired in S1502 from the NAND flash memory 5 (step S1504).

[0229] The controller 4 generates a check code in the check code generation circuit 441 using the user data included in the read target data read in S1504, the LBA specified by the read command received in S1501, and the PBA obtained in S1502 (step S1505).

[0230] The controller 4 determines whether or not the check code generated in S1505 matches the check code included in the data to be read out in S1504 (step S1506).

[0231] The controller 4 determines whether the flag acquired in S1503 is set to a value indicating validity (step S1507).

[0232] The determinations of S1506 and S1507 may be performed in any order.

[0233] If the check code generated in S1505 matches the check code contained in the read target data read in S1504 (Yes in S1506) and the flag obtained in S1503 is set to a value indicating valid (Yes in S1507), the controller 4 sends the data (user data) contained in the read target data read in S1504 to the host 2 (step S1508), and terminates the read process.

[0234] Furthermore, if the check code generated in S1505 does not match the check code contained in the data to be read out in S1504 (No in S1506), or if the flag obtained in S1507 is set to a value indicating invalidity (No in S1507), the controller 4 executes error processing (step S1509) and terminates the read process. (Second method (check code determination method) and check using PBA additional information) Next, a description will be given of a case where read data is checked using a physical address stored in the NAND flash memory 5 together with the data, and a check code generated using user data and a flag managed in the valid flag table 62. That is, a description will be given of a case where the flag is checked using the second method (check code determination method) and the additional information is the PBA itself.

[0235] First, the write data will be described. Fig. 22 is a diagram showing a fourth example of write data in the memory system according to the embodiment.

[0236] The write-related data includes user data, an LBA, a PBA, and a flag. The user data is data associated with a write command received from the host 2. The LBA is a requested LBA (destination LBA) specified by this write command. The PBA is a destination PBA allocated to the destination LBA by the flash PBA allocation unit 433. The flag is a flag having a first value indicating valid data, that is, 1-bit information indicating, for example, "1". It is sufficient for the write-related data to include user data, a PBA, and a flag, and it does not necessarily have to include an LBA.

[0237] The check code generation circuit 441 generates a check code using at least the user data and the flag. Note that the check code generation circuit 441 may generate a check code using an LBA in addition to the user data and the flag.

[0238] The error correction circuit 45 encodes a data set including the user data, the LBA, the PBA, and the check code to generate an ECC frame. Then, the ECC frame including the user data, the LBA, the PBA, the check code, and the ECC is written to the same page of the NAND flash memory 5.

[0239] Next, a case will be described where the write data explained in Fig. 22 is read from the NAND flash memory 5. Fig. 23 is a diagram showing a fourth example of read data in the memory system according to the embodiment.

[0240] The data read from the NAND flash memory 5 includes user data, an LBA, a PBA, a check code, and an ECC. The error correction circuit 45 executes a decoding process to perform error correction on the read data.

[0241] When the error correction is completed, the error correction circuit 45 outputs the user data, the LBA, the PBA, and the check code.

[0242] The check code generation circuit 441 generates a check code by using at least the user data output by the error correction circuit 45 and the flag associated with the read target PBA in the valid flag table 62. If an LBA is used in addition to the user data and the flag when writing this data, the check code generation circuit 441 generates a check code by further using the read target LBA specified by the read command received from the host 2 in addition to the user data and the flag.

[0243] The check code inspection circuit 442 checks whether the check code generated by the check code generation circuit 441 matches the check code output by the error correction circuit 45. If the two check codes do not match, the check code inspection circuit 442 determines that incorrect user data has been read. If the two check codes match, the check code inspection circuit 442 determines that correct user data has been read.

[0244] The PBA check circuit 444 checks whether the PBA mapped to the LBA specified by the read command at the time of reading matches the PBA output by the error correction circuit 45. If the two PBAs match, the PBA check circuit 444 determines that correct user data has been read. If the two PBAs do not match, the PBA check circuit 444 determines that incorrect user data has been read due to a malfunction of the address decoder of the NAND flash memory 5.

[0245] If the check code check circuit 442 and the PBA check circuit 444 determine that correct user data has been read, the controller 4 transmits the read user data to the host 2.

[0246] If the check code inspection circuit 442 or the PBA inspection circuit 444 determines that incorrect user data has been read, the controller 4 executes error processing. For example, as the error processing, the controller 4 notifies the host 2 of the error. In this case, the controller 4 may send a response indicating that the processing of the read command has failed to the host 2 as a completion response indicating the completion of the read command.

[0247] Furthermore, when only the PBA inspection circuit 444 determines that incorrect user data has been read, the controller 4 may execute again, as error processing, a process of reading data from the storage location in the NAND flash memory 5 indicated by the read target PBA. This is because it is assumed that the cause of only the PBA inspection circuit 444 detecting an error is a malfunction of the address decoder in the NAND flash memory 5, causing data to be read from a storage location different from the storage location indicated by the read target PBA.

[0248] Next, a procedure of the write process will be described with reference to a flowchart of FIG 24. The procedure of the write process of the memory system according to the embodiment is shown in FIG.

[0249] In response to the SSD 3 receiving a write command from the host 2 (step S1601), the controller 4 starts the write process.

[0250] The controller 4 judges whether old data is associated with the write destination LBA specified by the write command received in S1601 (step S1602). When the PBA is mapped to the write destination LBA from the L2P table 61, the controller 4 judges that old data is associated with the write destination LBA.

[0251] If old data is associated with the write destination LBA (Yes in S1602), the controller 4 obtains the last PBA mapped to the write destination LBA from the L2P table 61 (step S1603).

[0252] The controller 4 resets the flag in the valid flag table 62 corresponding to the final PBA (step S1604). In step S1604, the flag in the valid flag table 62 corresponding to the final PBA is set to the second value.

[0253] If no old data is associated with the write destination LBA (No in S1602), the controller 4 skips the processes of S1603 and S1604.

[0254] The controller 4 assigns a new PBA to the write destination LBA (step S1605). The assigned PBA is a write destination PBA that indicates the storage location where the data associated with the write command should be written.

[0255] The controller 4 uses the data associated with the write command received in S1601, the write destination LBA, and the flag indicating validity to generate a check code in the check code generation circuit 441 (step S1606). This check code is a code for checking the consistency of information including the data, the write destination LBA, and the flag.

[0256] The controller 4 encodes the data, the write destination LBA, the write destination PBA, and the check code to generate a codeword (ECC frame) (step S1607).

[0257] The controller 4 writes the data, the write destination LBA, the write destination PBA, the check code, and the ECC to a storage location in the NAND flash memory 5 that is indicated by the write destination PBA (step S1608).

[0258] The controller 4 sets a flag corresponding to the write destination PBA in the valid flag table 62 (step S1609), and ends the write process. In step S1609, the controller 4 sets the flag corresponding to the write destination PBA to the first value.

[0259] 24, the case where the data, the write destination LBA, the write destination PBA, and the check code are written to the NAND flash memory 5 has been described, but it is also possible to write only the data, the write destination PBA, and the check code to the NAND flash memory 5 without writing the write destination LBA to the NAND flash memory 5. This is because the check code is generated using the data, the write destination LBA, and the flag.

[0260] Next, a procedure of the read process will be described with reference to Fig. 25. Fig. 25 is a flowchart showing a fourth example of the procedure of the read process of the memory system according to the embodiment.

[0261] In response to the SSD 3 receiving a read command from the host 2 (step S1701), the controller 4 starts the read process.

[0262] The controller 4 acquires the PBA corresponding to the LBA designated by the read command received in S1701 from the L2P table 61 (step S1702).

[0263] The controller 4 obtains the flag corresponding to the PBA obtained in S1702 from the valid flag table 62 (step S1703).

[0264] The controller 4 reads the data to be read (here, data, LBA, PBA, and check code) stored in the storage location indicated by the PBA acquired in S1702 from the NAND flash memory 5 (step S1704).

[0265] The controller 4 generates a check code in the check code generation circuit 441 using the user data included in the read target data read in S1704, the LBA specified by the read command received in S1701, and the flag acquired in S1703 (step S1705).

[0266] The controller 4 determines whether or not the check code generated in S1705 matches the check code included in the data to be read out in S1704 (step S1706).

[0267] The controller 4 determines whether or not the PBA acquired from the L2P table 61 in S1702 matches the PBA included in the data to be read out in S1704 (step S1707).

[0268] The controller 4 determines whether or not the flag acquired in S1703 is set to a value indicating validity (step S1708).

[0269] The determinations of S1706 and S1707 may be performed in any order.

[0270] If the check code generated in S1705 matches the check code included in the read target data read in S1704 (Yes in S1706), and if the PBA obtained from L2P table 61 in S1702 matches the PBA included in the read target data read in S1704 (Yes in S1707), the controller 4 sends the data (user data) included in the read target data read in S1704 to the host 2 (step S1708), and terminates the read process.

[0271] If the check code generated in S1705 does not match the check code contained in the read target data read in S1704 (No in S1706), or if the PBA obtained from L2P table 61 in S1702 does not match the PBA contained in the read target data read in S1704 (No in S1707), the controller 4 executes error processing (step S1709) and terminates the read processing.

[0272] As described above, according to this embodiment, in response to receiving a read command from the host 2, the controller 4 acquires from the L2P table 61 a physical address (PBA) that is mapped to the logical address (read target LBA) designated by the read command at the time of executing the read command, and reads data (user data) from the NAND flash memory 5 based on the acquired PBA. Then, the controller 4 determines whether or not to transmit the read data (user data) to the host 2 based on whether or not the current state of the flag corresponding to the acquired PBA is maintained in a state in which it is set to the first value. That is, the controller 4 can use the flag to check whether the data read from the NAND flash memory 5 is correct data that is the latest data corresponding to the read target LBA, or incorrect data that is data other than the latest data corresponding to the read target LBA. This makes it possible to prevent the incorrect data from being transmitted to the host 2 even if the incorrect data is read from the NAND flash memory 5 due to a part of the mapping information of the L2P table 61 being corrupted.

[0273] Specifically, when the current state of the flag corresponding to the acquired PBA is set to the second value, the controller 4 notifies the host 2 of an error. This allows the controller 4 to notify the host 2 of an error when past data of the same LBA is read due to an error in the L2P table 61.

[0274] Furthermore, the controller 4 can use additional information determined directly or indirectly from the physical address to check whether the data read from the NAND flash memory 5 is correct.

[0275] If the additional information acquired based on the LBA specified by the read command received from the host 2 does not match the additional information included in the data read from the NAND flash memory 5, the controller 4 executes error processing. In this case, it is detected that the PBA specified based on the read command does not match the PBA determined based on the data read from the NAND flash memory 5 due to a defect in the NAND flash memory 5. Therefore, the controller 4 may execute a read process to read data from the NAND flash memory 5 again as error processing. Alternatively, the controller 4 may notify the host 2 of the error as error processing.

[0276] In reality, damage to the mapping information of the L2P table 61 and malfunction of the NAND flash memory 5 rarely occur. For this reason, a configuration may be used in which only the flag is used to check whether the data read from the NAND flash memory 5 is correct, or a configuration may be used in which only the additional information is used to check whether the data read from the NAND flash memory 5 is correct.

[0277] Alternatively, the controller 4 can use both the flag and the additional information to check whether the data read from the NAND flash memory 5 is correct.

[0278] The controller 4 transmits the read data to the host 2 when the condition that the flag indicates that it is valid and the additional information acquired based on the LBA designated by the read command received from the host 2 matches the additional information included in the data read from the NAND flash memory 5 is satisfied. On the other hand, when this condition is not satisfied, the controller 4 does not transmit the read data to the host 2. In this way, the controller 4 determines whether or not to transmit the data read from the NAND flash memory 5 to the host 2 based on whether or not the condition that the flag indicates that it is valid and the additional information acquired based on the LBA designated by the read command received from the host 2 matches the additional information included in the data read from the NAND flash memory 5 is satisfied. In this way, even if either or both of the mapping information of the L2P table 61 is damaged or the NAND flash memory 5 malfunctions, the controller 4 can prevent erroneous data from being transmitted to the host 2 due to erroneous reading.

[0279] Furthermore, the controller 4 can generate a check code in the check code generation circuit 441 using the flag or the physical address, and can check whether the read data is correct using the generated check code.

[0280] In this case, the SSD 3 only needs to check the check code when checking the read data, and therefore the controller 4 does not need to check the flag and the PBA separately.

[0281] For this reason, when a check code is generated using a flag and a physical address, the SSD 3 does not require a special hardware circuit (for example, the flag check circuit 443 and the PBA check circuit 444 shown in FIG. 1) for checking read data. Furthermore, even in the case of an erroneous read caused by a malfunction of the NAND flash memory 5, reading of erroneous data can be detected without writing a physical address to the NAND flash memory 5, so that the physical storage space of the NAND flash memory 5 can be used more effectively.

[0282] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0283] 1. Information processing system 2. Host 3…SSD 4. Controller 5. NAND flash memory 6…DRAM 7…Bus 20…Internal bus 21…Processor 22…Memory 40…Internal bus 41...Host interface 42…SRAM 43…CPU 44...Inspection circuit 45...Error correction circuit 46…NAND interface 47…DRAM interface 61…L2P table 62...Valid flag table 63…Active block list 64...Free block list 431...Lead processing section 432...Light processing unit 433…Flash PBA Allocation Section 441...Check code generation circuit 442...Check code check circuit 443...Flag inspection circuit 444…PBA inspection circuit 445...LBA inspection circuit

Claims

1. 1. A memory system connectable to a host, comprising: A non-volatile memory; a controller configured to control the non-volatile memory; The controller: managing, using a first management table, mapping information indicating mapping between a plurality of logical addresses for the host to access the memory system and a plurality of physical addresses of the non-volatile memory; managing a plurality of flags associated with the plurality of physical addresses using a second management table, and setting, in the plurality of flags, either a first value indicating that data stored in a memory location of the non-volatile memory corresponding to the plurality of physical addresses is valid data or a second value indicating that data is invalid data; in response to receiving a write command from the host specifying a first logical address, assigning a first physical address to the first logical address, writing first data associated with the write command to a first storage location of the non-volatile memory corresponding to the first physical address, and setting a first flag corresponding to the first physical address to the first value; When the first data is made invalid by updating or deleting the first data, the first flag is set to the second value; the read / write control unit is configured to, in response to receiving a read command specifying the first logical address from the host, obtain from the first management table a physical address that is mapped to the first logical address at the time of executing the read command, read data from the non-volatile memory based on the obtained physical address, and determine whether or not to transmit the read data to the host based on whether a current state of a flag corresponding to the obtained physical address is set to the first value or the second value. Memory system.

2. The controller: when writing the first data to the non-volatile memory, writing both the first data and the first physical address to the first storage location; when reading the first data from the non-volatile memory, reading both the data and the physical address from the non-volatile memory based on the physical address acquired from the first management table; and determining whether or not to transmit the data read from the non-volatile memory to the host based on whether or not a condition is satisfied that a current state of the flag corresponding to the physical address obtained from the first management table is set to the first value, and the physical address read from the non-volatile memory matches the physical address obtained from the first management table.

2. The memory system of claim 1.

3. The controller: obtaining, from the second management table, the flag corresponding to the physical address obtained from the first management table; determining whether the acquired flag value is set to the first value or the second value; and determining whether or not to transmit the data read from the non-volatile memory to the host based on a result of the determination.

2. The memory system of claim 1.

4. The controller: generating a first check code using the first data and the flag having the first value to check consistency of information including the first data and the flag having the first value when writing the first data to the non-volatile memory; writing both the first data and the first check code to the first storage location; when reading the first data from the nonvolatile memory, reading both the data and the check code from the nonvolatile memory based on the physical address acquired from the first management table; obtaining, from the second management table, the flag corresponding to the physical address obtained from the first management table; generating a second check code for checking the consistency of information including the acquired flag and the read data by using the acquired flag and the read data; and determining whether or not to transmit the read data to the host based on whether or not the second check code matches the read check code.

2. The memory system of claim 1.

5. The controller: generating a first check code for checking consistency of information including the first data, the flag having the first value, and the first physical address when writing the first data to the non-volatile memory, using the first data, the flag having the first value, and the first physical address; writing both the first data and the first check code to the first storage location; when reading the first data from the nonvolatile memory, reading both the data and the check code from the nonvolatile memory based on the physical address acquired from the first management table; obtaining, from the second management table, the flag corresponding to the physical address obtained from the first management table; generating a second check code for checking consistency of information including the acquired flag, the physical address acquired from the first management table, and the read data, using the acquired flag, the physical address acquired from the first management table, and the read data; and determining whether or not to transmit the read data to the host based on whether or not the second check code matches the read check code.

2. The memory system of claim 1.

6. 1. A memory system connectable to a host, comprising: A non-volatile memory; a controller configured to control the non-volatile memory; The controller: managing, using a first management table, mapping information indicating mapping between a plurality of logical addresses for the host to access the memory system and a plurality of physical addresses of the non-volatile memory; in response to receiving a write command from the host specifying a first logical address, assigning a first physical address to the first logical address, and writing first data associated with the write command and first additional information determined directly or indirectly from the first physical address to a first storage location of the non-volatile memory corresponding to the first physical address; in response to receiving a read command specifying the first logical address from the host, acquiring from the first management table a physical address that is mapped to the first logical address at the time of executing the read command, and reading both the data and additional information from the non-volatile memory based on the acquired physical address; and determining whether or not to transmit the read data to the host based on whether or not the read additional information matches additional information determined directly or indirectly from the physical address acquired from the first management table. Memory system.

7. The controller: managing a plurality of flags associated with the plurality of physical addresses using a second management table, and setting, in the plurality of flags, either a first value indicating that data stored in a memory location of the non-volatile memory corresponding to the plurality of physical addresses is valid data or a second value indicating that data is invalid data; in response to writing both the first data and the first additional information to the first storage location, setting a first flag corresponding to the first physical address to the first value; When the first data is made invalid by updating or deleting the first data, the first flag is set to the second value; and determining whether or not to transmit the read data to the host based on whether or not the following conditions are satisfied: the read additional information matches the additional information determined directly or indirectly from the physical address obtained from the first management table, and the current state of a flag corresponding to the physical address obtained from the first management table is set to the first value.

7. The memory system of claim 6.

8. each of the first additional information and the read additional information is a physical address; The controller: when writing the first data to the non-volatile memory, writing both the first data and the first physical address to the first storage location; when reading the first data from the non-volatile memory, reading both the data and the physical address from the non-volatile memory based on the physical address acquired from the first management table; and determining whether or not to transmit the read data to the host based on whether or not the read physical address matches the physical address acquired from the first management table.

7. The memory system of claim 6.

9. each of the first additional information and the read additional information is a check code; The controller: generating a first check code using the first data and the first physical address to check consistency of information including the first data and the first physical address when writing the first data to the non-volatile memory; writing both the first data and the first check code to the first storage location; when reading the first data from the nonvolatile memory, reading both the data and the check code from the nonvolatile memory based on the physical address acquired from the first management table; generating a second check code for checking consistency of information including the physical address obtained from the first management table and the read data, using the physical address obtained from the first management table and the read data; and determining whether to transmit the read data to the host based on whether the second check code matches the read check code.

7. The memory system of claim 6.

10. each of the first additional information and the read additional information is a physical address; The controller: managing a plurality of flags associated with the plurality of physical addresses using a second management table, and setting, in the plurality of flags, either a first value indicating that data stored in a memory location of the non-volatile memory corresponding to the plurality of physical addresses is valid data or a second value indicating that data is invalid data; in response to writing both the first data and the first additional information to the first storage location, setting a first flag corresponding to the first physical address to the first value; When the first data is made invalid by updating or deleting the first data, the first flag is set to the second value; generating a first check code for checking consistency of information including the first data, the flag having the first value, and the first physical address, using the first data, the flag having the first value, and the first physical address, when writing the first data to the non-volatile memory; writing both the first data and the first check code to the first storage location; when reading the first data from the nonvolatile memory, reading both the data and the check code from the nonvolatile memory based on the physical address acquired from the first management table; obtaining, from the second management table, a flag corresponding to the physical address obtained from the first management table; generating a second check code for checking consistency of information including the physical address acquired from the first management table, the acquired flag, and the read data, using the physical address acquired from the first management table, the acquired flag, and the read data; and determining whether to transmit the read data to the host based on whether the second check code matches the read check code.

7. The memory system of claim 6.

11. A method for controlling a memory system including a non-volatile memory, comprising: managing, using a first management table, mapping information indicating mapping between a plurality of logical addresses for a host to access the memory system and a plurality of physical addresses of the non-volatile memory; managing a plurality of flags associated with the plurality of physical addresses using a second management table; and setting, in the plurality of flags, either a first value indicating that data stored in a memory location of the non-volatile memory corresponding to the plurality of physical addresses is valid data or a second value indicating that data is invalid data; in response to receiving a write command from the host specifying a first logical address, assigning a first physical address to the first logical address, writing first data associated with the write command to a first storage location of the non-volatile memory corresponding to the first physical address, and setting a first flag corresponding to the first physical address to the first value; setting the first flag to the second value in response to the first data being invalidated by updating or deleting the first data; in response to receiving a read command specifying the first logical address from the host, acquiring from the first management table a physical address mapped to the first logical address at the time of executing the read command, reading data from the non-volatile memory based on the acquired physical address, and determining whether or not to transmit the read data to the host based on whether a current state of a flag corresponding to the acquired physical address is set to the first value or the second value. Control methods.

12. A method for controlling a memory system including a non-volatile memory, comprising: managing, using a first management table, mapping information indicating mapping between a plurality of logical addresses for a host to access the memory system and a plurality of physical addresses of the non-volatile memory; in response to receiving a write command from the host specifying a first logical address, assigning a first physical address to the first logical address, and writing first data associated with the write command and first additional information determined directly or indirectly from the first physical address to a first storage location of the non-volatile memory corresponding to the first physical address; in response to receiving a read command specifying the first logical address from the host, acquiring from the first management table a physical address that is mapped to the first logical address at the time of executing the read command, and reading both the data and additional information from the non-volatile memory based on the acquired physical address; determining whether or not to transmit the read data to the host based on whether the read additional information matches additional information determined directly or indirectly from the physical address acquired from the first management table; Control methods.

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