Memory chip and semiconductor package including the same

Abstract

To provide a memory chip and a semiconductor package including the same with increased integration density.SOLUTION: A memory chip includes a cell chip and a core peripheral chip that are vertically arranged and electrically connected to each other. The cell chip includes cell regions each including a memory cell layer. The core peripheral chip includes a core group region and a peripheral region adjacent to each other in a first direction. The core group region includes core regions arranged in a row along a second direction intersecting the first direction. Each of the core regions includes a core bank including a core circuit and a neural processing unit (NPU) block including an NPU.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a memory chip and a semiconductor package including the same. [Background technology]

[0002] A memory chip includes a number of circuit regions therein. For example, a memory chip includes a cell region that performs a memory function, and a core region and a peripheral region in which circuits for driving the cell region and inputting and outputting data are formed. Meanwhile, in order to highly integrate a memory chip, it is required to form more circuits in a limited chip region. Therefore, various researches are being conducted to develop a memory chip and a semiconductor package including the same that have improved performance while reducing the form factor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 1,105,6454 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned conventional techniques, and an object of the present invention is to provide a memory chip with improved integration density and a semiconductor package including the same. Another object of the present invention is to provide a memory chip with improved performance and a semiconductor package including the same.

[0005] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those having ordinary skill in the art from the following description. [Means for solving the problem]

[0006] A memory chip according to one aspect of the present invention, which has been made to achieve the above object, may include a cell chip and a core-periphery chip, which are vertically arranged and electrically connected to each other. The cell chip may include cell regions, each including a memory cell layer. The core-periphery chip may include a core group region and a peripheral region adjacent to each other in a first direction. The core group region may include core regions arranged in a row along a second direction intersecting the first direction. Each of the core regions may include a core bank including a core circuit and an NPU block including an NPU (neural processing unit).

[0007] According to an aspect of the present invention, a semiconductor package includes a cell chip and a core peripheral chip alternately stacked with each other, and a through-silicon via (TSV) electrically connecting the cell chip and the core peripheral chip. Each of the cell chips includes a cell region for storing data. Each of the core peripheral chips includes an NPU block for performing data calculations.

[0008] A semiconductor package according to one aspect of the present invention made to achieve the above object may include a plurality of memory chips stacked vertically on one another, and TSVs electrically connecting the plurality of memory chips. Each of the plurality of memory chips may include a cell chip and a core peripheral chip arranged vertically on one another. The cell chip may include cell regions each including a memory cell layer. The core peripheral chip may include a core group region and a peripheral region adjacent to each other in a first direction. The core group region may include core regions arranged in a row along a second direction intersecting the first direction. Each of the core regions may include a core bank including a core circuit, and an NPU block including an NPU.

[0009] A semiconductor package according to another aspect of the present invention, which has been made to achieve the above object, may include a package substrate, a host structure on the package substrate, and a memory structure horizontally spaced apart from the host structure on the package substrate and electrically connected to the host structure. The memory structure may include a plurality of memory chips stacked vertically on one another. Each of the plurality of memory chips may include a cell chip and a core peripheral chip arranged vertically and electrically connected to each other. The cell chip may include a cell region each including a memory cell layer. The core peripheral chip may include a core group region and a peripheral region adjacent to each other in a first direction. The core group region may include core regions arranged in a row along a second direction intersecting the first direction. Each of the core regions may include a core bank including a core circuit and an NPU block including an NPU. Effect of the Invention

[0010] According to the present invention, the core peripheral chip and the cell chip can be arranged vertically to each other, thereby improving the integration density of the memory chip per unit area and the semiconductor package including the same.

[0011] In addition, since the core peripheral chip includes an NPU block, the NPU block can be disposed adjacent to the cell region. This minimizes the data transfer distance between the NPU block and the cell region, thereby improving the data processing speed of the memory chip. As a result, the performance of the memory chip and the semiconductor package including the memory chip can be improved. [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 is a perspective view of a memory chip according to some embodiments of the present invention. [Diagram 2] FIG. 2 is a perspective view of a memory chip according to some embodiments of the present invention. [Diagram 3]FIG. 2 is a plan view illustrating a core periphery chip of a memory chip according to some embodiments of the present invention. [Figure 4] FIG. 2 is a plan view illustrating a core periphery chip of a memory chip according to some embodiments of the present invention. [Diagram 5] 1 is a plan view illustrating a core periphery chip of a memory chip according to some embodiments of the present invention. [Figure 6] FIG. 2 is a plan view illustrating a core periphery chip of a memory chip according to some embodiments of the present invention. [Figure 7] FIG. 2 is a plan view illustrating a core periphery chip of a memory chip according to some embodiments of the present invention. [Figure 8] FIG. 2 is a plan view illustrating a core periphery chip of a memory chip according to some embodiments of the present invention. [Figure 9] FIG. 2 is a plan view illustrating a core periphery chip of a memory chip according to some embodiments of the present invention. [Figure 10] FIG. 2 is a plan view illustrating a core periphery chip of a memory chip according to some embodiments of the present invention. [Figure 11] FIG. 2 is a plan view illustrating a cell chip of a memory chip according to some embodiments of the present invention. [Figure 12] FIG. 2 is a plan view illustrating a cell chip of a memory chip according to some embodiments of the present invention. [Figure 13] FIG. 2 is a plan view illustrating a cell chip of a memory chip according to some embodiments of the present invention. [Figure 14] FIG. 2 is a plan view illustrating a cell chip of a memory chip according to some embodiments of the present invention. [Figure 15A] 1 illustrates a cross-sectional view of a memory chip according to some embodiments of the present invention. [Figure 15B] 1 illustrates a cross-sectional view of a memory chip according to some embodiments of the present invention. [Figure 16A] 1 illustrates a cross-sectional view of a memory chip according to some embodiments of the present invention. [Figure 16B] 1 illustrates a cross-sectional view of a memory chip according to some embodiments of the present invention. [Figure 17A]1 illustrates a cross-sectional view of a memory chip according to some embodiments of the present invention. [Figure 17B] 1 illustrates a cross-sectional view of a memory chip according to some embodiments of the present invention. [Figure 18] 1 illustrates a cross-sectional view of multiple memory chips according to some embodiments of the present invention. [Figure 19] 1 is a cross-sectional view illustrating a semiconductor package including a memory chip according to some embodiments of the present invention. [Figure 20] 1 is a cross-sectional view illustrating a semiconductor package including a memory chip according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory chip and a semiconductor package according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0014] 1 and 2 are perspective views each illustrating a memory chip according to some embodiments of the present invention.

[0015] 1 and 2, a memory chip 1000 includes a core-periphery chip 10 and a cell chip 20 arranged in a vertical direction VD. The core-periphery chip 10 and the cell chip 20 are vertically stacked on each other. As an example, as shown in FIG 1, the cell chip 20 is stacked on the core-periphery chip 10. As another example, as shown in FIG 2, the core-periphery chip 10 is stacked on the cell chip 20.

[0016] In a plan view, the core peripheral chip 10 includes a core region COR and a peripheral region PR. The core regions COR and the peripheral region PR are adjacent to each other in the horizontal direction. Each of the core regions COR includes a core bank COB, which will be described later, and the core bank COB includes core circuits such as a sub-word line driver, a sense amplifier, a row decoder, a column decoder, and a read / write circuit. The peripheral region PR includes peripheral circuits such as a timing register, an address register, a data input register, a data output register, and a data input / output terminal.

[0017] In a plan view, the cell chip 20 includes cell regions CR. The cell regions CR are adjacent to each other in the horizontal direction. Each of the cell regions CR vertically overlaps at least a portion of each of the core regions COR. Each of the cell regions CR includes a memory cell layer 210, which will be described later, and the memory cell layer 210 stores data.

[0018] The planar layout of the components within the core peripheral chip 10 and the cell chip 20 will be described in more detail below.

[0019] 3 to 10 are plan views showing core peripheral chips of memory chips according to some embodiments of the present invention.

[0020] 3 to 10, the core peripheral chip 10 has a first side surface 10a facing a first direction D1, a second side surface 10b facing the first side surface 10a, a third side surface 10c facing a second direction D2, and a fourth side surface 10d facing the third side surface 10c. The first direction D1 and the second direction D2 are parallel to the bottom surface of the core peripheral chip 10 and intersect with each other.

[0021] Each of the core regions COR includes a core bank COB and an NPU block NB. The NPU block NB includes an NPU (Neural Processing Unit) that performs data calculations. As an example, one core region COR includes one core bank COB and one NPU block NB, and one core bank COB and one NPU block NB are adjacent to each other in a first direction D1 or a second direction D2. As the core region COR includes the NPU block NB, the memory chip 1000 can function as a PIM (Processing in Memory) that can perform data calculations.

[0022] The peripheral region PR is located in the center of the core peripheral chip 10. The center of the core peripheral chip 10 is defined as a region of the core peripheral chip 10 that is equally spaced from the first side 10a and the second side 10b of the core peripheral chip 10 and is also equally spaced from the third side 10c and the fourth side 10d of the core peripheral chip 10. The peripheral region PR is a region that extends in an elongated manner in the second direction D2 at the center of the core peripheral chip 10.

[0023] The core region COR includes a row of core regions COR arranged in sequence along the second direction D2. The row of core regions COR constitutes a core group region COG. The core group region COG is adjacent to the peripheral region PR in the first direction D1 or the opposite direction.

[0024] A plurality of core group regions COG are provided. The plurality of core group regions COG are arranged in order along the first direction D1. In other words, a row of core regions COR is provided, and another row of core regions COR is arranged adjacent to the row of core regions COR in the first direction D1.

[0025] As an example, the core group region COG includes a first group COG1 adjacent to the peripheral region PR in a first direction D1 and a second group COG2 adjacent to the peripheral region PR in the opposite direction to the first direction D1. The first group COG1 and the second group COG2 are spaced apart from each other in the first direction D1 via the peripheral region PR. The first group COG1 is located between the peripheral region PR and a first side 10a of the core peripheral chip 10. The second group COG2 is located between the peripheral region PR and a second side 10b of the core peripheral chip 10.

[0026] 3, the core banks COB and NPU blocks NB are arranged symmetrically with respect to a line perpendicular to the first direction D1 with respect to the peripheral region PR. As an example, the NPU blocks NB and core banks COB of the first group COG1 are arranged in order from the peripheral region PR along the first direction D1. The NPU blocks NB and core banks COB of the second group COG2 are arranged in order from the peripheral region PR along the opposite direction to the first direction D1. In other words, the core banks COB and NPU blocks NB of the first group COG1 and the second group COG2 are arranged symmetrically with respect to the peripheral region PR.

[0027] 4, the core banks COB and NPU blocks NB are arranged asymmetrically with respect to a line perpendicular to the first direction D1 with respect to the peripheral region PR. As an example, the NPU blocks NB and core banks COB of the first group COG1 are arranged in sequence from the peripheral region PR along the first direction D1. The core banks COB and NPU blocks NB of the second group COG2 are arranged in sequence from the peripheral region PR along the opposite direction to the first direction D1. In other words, the NPU blocks NB and core banks COB of each of the first group COG1 and the second group COG2 are arranged in sequence along the first direction D1. As an example, the arrangement order of the NPU blocks NB and core banks COB is the same in the first group COG1 and the second group COG2.

[0028] 5 and 6, in one core region COR, the core bank COB and the NPU block NB are adjacent to each other in the second direction D2.

[0029] 5, a pair of core regions COR are adjacent to each other in the second direction D2, and the core banks COB and NPU blocks NB of each of the pair of core regions COR are arranged in sequence along the second direction D2. In other words, the core banks COB and NPU blocks NB of the pair of core regions COR are arranged asymmetrically with respect to a line perpendicular to the second direction D2. As an example, the arrangement order of the core banks COB and NPU blocks NB is the same in the pair of core regions COR.

[0030] 6, one of the core banks COB and the NPU block NB in ​​the pair of core regions COR is arranged in sequence along the second direction D2, and the other of the core banks COB and the NPU block NB in ​​the pair of core regions COR is arranged in sequence along the opposite direction of the second direction D2. In other words, the core banks COB and the NPU block NB in ​​the pair of core regions COR are arranged symmetrically with respect to a line perpendicular to the second direction D2. As an example, the arrangement order of the core banks COB and the NPU block NB in ​​the pair of core regions COR is opposite with respect to the second direction D2.

[0031] 7 to 9, a plurality of core group regions COG are located between the peripheral region PR and the first side 10a of the core peripheral chip 10, and a plurality of other core group regions COG are located between the peripheral region PR and the second side 10b of the core peripheral chip 10. As an example, as shown in FIG. 7 to FIG. 9, the plurality of core group regions COG include first to fourth groups COG1, COG2, COG3, and COG4. The first group COG1 is located between the peripheral region PR and the first side 10a of the core peripheral chip 10. The second group COG2 is located between the peripheral region PR and the second side 10b of the core peripheral chip 10. The third group COG3 is located between the first group COG1 and the first side 10a of the core peripheral chip 10, and is adjacent to the first group COG1 in the first direction D1. The fourth group COG4 is located between the second group COG2 and the second side 10b of the core peripheral chip 10, and is adjacent to the second group COG2 in the first direction D1. However, this is by way of example only and the concept of the present invention is not limited thereto, and the multiple core group regions COG may further include additional groups, such as a fifth and sixth group (not shown).

[0032] 7, the core banks COB and NPU blocks NB are arranged symmetrically with respect to a line perpendicular to the first direction D1 with respect to the peripheral region PR. The core banks COB and NPU blocks NB of the first group COG1 are arranged in sequence along the first direction D1. The core banks COB and NPU blocks NB of the second group COG2 are arranged in sequence along the opposite direction to the first direction D1. Therefore, the second group COG2 has a symmetrical structure with respect to the first group COG1 with respect to the peripheral region PR.

[0033] The NPU blocks NB and the core banks COB of the third group COG3 are arranged in sequence along the first direction D1, so that the third group COG3 is arranged symmetrically to the first group COG1 with respect to a line perpendicular to the first direction D1.

[0034] The NPU blocks NB and the core banks COB of the fourth group COG4 are arranged in sequence in the opposite direction to the first direction D1. Therefore, the fourth group COG4 is arranged symmetrically to the second group COG2 with respect to a line perpendicular to the first direction D1. The fourth group COG4 also has a symmetrical structure to the third group COG3 with respect to the peripheral region PR.

[0035] 8, as in FIG. 7, the core banks COB and the NPU blocks NB are arranged symmetrically with respect to a line perpendicular to the first direction D1 with respect to the peripheral region PR. However, unlike FIG. 7, the NPU blocks NB and the core banks COB of the first group COG1 are arranged in order along the first direction D1, and the NPU blocks NB and the core banks COB of the second group COG2 are arranged in order along the opposite direction to the first direction D1. Therefore, the third group COG3 is arranged asymmetrically with respect to the line perpendicular to the first direction D1 with respect to the first direction D1, and the fourth group COG4 is arranged asymmetrically with respect to the second group COG2. For example, the arrangement order of the NPU blocks NB and the core banks COB is the same in the first group COG1 and the third group COG3. For example, the arrangement order of the NPU blocks NB and the core banks COB is the same in the second group COG2 and the fourth group COG4.

[0036] 9, the core banks COB and NPU blocks NB are arranged asymmetrically with respect to a line perpendicular to the first direction D1 with respect to the peripheral region PR. As an example, the NPU blocks NB and core banks COB of each of the first to fourth groups COG1, COG2, COG3, and COG4 are arranged in order along the first direction D1. In other words, the arrangement order of the NPU blocks NB and core banks COB is the same in the first to fourth groups COG1, COG2, COG3, and COG4. The third group COG3 is arranged asymmetrically with respect to the line perpendicular to the first direction D1 with respect to the first group COG1, and the fourth group COG4 is arranged asymmetrically with respect to the second group COG2.

[0037] Referring to FIG. 10, the core peripheral chip 10 further includes a TSV (through-silicon via) 30 located in its center. The TSV 30 is located inside the peripheral region PR. The TSV 30 is located between the first group COG1 and the second group COG2. The TSVs 30 are distributed in a region extending in a thin shape in the second direction D2 at the center of the core peripheral chip 10. Each of the TSVs 30 extends vertically inside the core peripheral chip 10, and for example, penetrates at least a portion of the core peripheral chip 10. The TSVs 30 of the core peripheral chip 10 are electrically connected to the TSVs 30 of the cell chip 20 (see FIG. 14). In other words, the core peripheral chip 10 and the cell chip 20 of the memory chip 1000 are electrically connected to each other.

[0038] 11 to 14 are plan views showing cell chips of memory chips according to some embodiments of the present invention.

[0039] 11 to 14, the cell chip 20 has a first side 20a facing a first direction D1, a second side 20b opposite the first side 20a, a third side 20c facing a second direction D2, and a fourth side 20d opposite the third side 20c.

[0040] Each of the cell regions CR includes a cell bank CB. The cell bank CB includes a memory cell layer 210, which will be described later, and the memory cell layer 210 stores data. As an example, each of the cell regions CR vertically overlaps at least a portion of each of the NPU blocks NB of the core peripheral chip 10. Therefore, the distance between the cell regions CR and the NPU blocks NB is shortened compared to when they are not overlapped. As a result, the data processing speed of the memory chip 1000 is improved. In addition, the memory chip 1000 is driven with low power, and issues such as noise and heat generation are improved.

[0041] The cell regions CR are arranged adjacent to each other in the first direction D1 and the second direction D2. As an example, the cell region CR includes a row of cell regions CR arranged in sequence along the second direction D2. The row of cell regions CR constitutes a cell group region CG. A plurality of cell group regions CG are provided, and the cell group regions CG are adjacent to each other in the first direction D1.

[0042] As an example, the cell group region CG includes a first group CG1 adjacent to the center of the cell chip 20 in the first direction D1 and a second group CG2 adjacent to the center of the cell chip 20 in the opposite direction to the first direction D1. The center of the cell chip 20 is defined as a region of the cell chip 20 that is equally spaced from the first side 20a and the second side 20b of the cell chip 20 and is also equally spaced from the third side 20c and the fourth side 20d of the cell chip 20. The first group CG1 and the second group CG2 are spaced apart from each other in the first direction D1 across the center of the cell chip 20. The first group CG1 is located between the first side 20a and the center of the cell chip 20. The second group CG2 is located between the second side 20b and the center of the cell chip 20. As an example, the cell group region CG further includes additional groups such as a third and a fourth group (not shown). The third group is located between the first group CG1 and the first side surface 20a of the cell chip 20, and the fourth group is located between the second group CG2 and the second side surface 20b of the cell chip 20.

[0043] 12 and 13, each of the cell regions CR further includes an NPU buffer NBF. The NPU buffer NBF includes an NPU buffer memory used to drive the NPU. The NPU buffer memory includes at least one of a new memory such as a phase-change RAM (PRAM), a spin transfer torque magnetic RAM (STT-MRAM), a ferroelectric RAM (FeRAM), and an SRAM.

[0044] As an example, one cell region CR includes one cell bank CB and one NPU buffer NBF. The cell bank CB and the NPU buffer NBF are arranged adjacent to each other in a horizontal direction (e.g., a first direction D1 or a second direction D2). As the NPU buffer NBF is located on the cell region CR, the area of ​​the NPU block NB in ​​the core peripheral chip 10 is reduced. Therefore, the integration density in the core peripheral chip 10 and the cell chip 20 can be appropriately adjusted through the NPU buffer NBF to maximize the integration density of the memory chip 1000.

[0045] 12, the cell banks CB and the NPU buffers NBF are arranged asymmetrically with respect to a line perpendicular to the first direction D1 based on the center of the cell chip 20. For example, the arrangement order of the cell banks CB and the NPU buffers NBF is the same in all cell regions CR.

[0046] 13, the cell banks CB and NPU buffers NBF are arranged symmetrically with respect to a line perpendicular to the first direction D1 with respect to the center of the cell chip 20. As an example, the NPU buffers NBF and cell banks CB of the first group CG1 are arranged in order from the center of the cell chip 20 along the first direction D1, and the NPU buffers NBF and cell banks CB of the second group CG2 are arranged in order from the center of the cell chip 20 along the opposite direction to the first direction D1. In other words, the NPU buffers NBF and cell banks CB of the first group CG1 and the second group CG2 are arranged symmetrically with respect to the center of the cell chip 10.

[0047] 14, the cell chip 20 further includes a TSV 30 located in its center. The TSV 30 is located between the first group CG1 and the second group CG2. The TSVs 30 are distributed in a region extending in a second direction D2 from the center of the cell chip 20. Each of the TSVs 30 extends vertically inside the cell chip 20, for example, penetrating at least a portion of the cell chip 20. The TSVs 30 of the cell chip 20 are electrically connected to the TSVs 30 of the core peripheral chip 10. The TSVs 30 of the core peripheral chip 10 and the cell chip 20 are electrically connected to an external device, and can transmit electrical signals from the external device to each chip.

[0048] 15A to 17B are cross-sectional views showing memory chips according to some embodiments of the present invention.

[0049] 15A to 17B, the core peripheral chip 10 includes a driving layer 11 and a core peripheral wiring layer 12. The core peripheral wiring layer 12 is provided on the driving layer 11.

[0050] The driving layer 11 includes a core peripheral semiconductor layer 100 and a core peripheral transistor 110 on the core peripheral semiconductor layer 100. The core peripheral semiconductor layer 100 includes a semiconductor material. As an example, the core peripheral semiconductor layer 100 is a semiconductor substrate including a semiconductor material such as a silicon single crystal substrate, a silicon-germanium substrate, or an SOI substrate. As another example, the core peripheral semiconductor layer 100 is a semiconductor epitaxial layer including a semiconductor material. The core peripheral transistor 110 is a transistor provided in a core circuit, a peripheral circuit, and an NPU. As an example, the core peripheral transistor 110 is illustrated as a planar type transistor, but is not limited thereto, and various types of transistors can be applied.

[0051] The core peripheral wiring layer 12 includes a core peripheral circuit wiring 12a and a core peripheral contact plug 12b that electrically connects the core peripheral transistor 110 and the core peripheral circuit wiring 12a.

[0052] The cell chip 20 includes a data storage layer 21 and a cell wiring layer 22. The data storage layer 21 includes a cell semiconductor layer 200 and a memory cell layer 210. The cell semiconductor layer 200 includes a first surface 201 and a second surface 202 that face each other in the vertical direction VD. The first surface 201 of the cell semiconductor layer 200 is the front surface of the cell semiconductor layer 200, and the memory cell layer 210 is formed on the front surface of the cell semiconductor layer 200. The second surface 202 of the cell semiconductor layer 200 is the back surface of the cell semiconductor layer 200.

[0053] The cell semiconductor layer 200 includes a semiconductor material. For example, the cell semiconductor layer 200 is a semiconductor substrate including a semiconductor material, such as a silicon single crystal substrate, a silicon-germanium substrate, or an SOI substrate. For another example, the cell semiconductor layer 200 is a semiconductor epitaxial layer including a semiconductor material. The memory cell layer 210 includes at least one of various types of memory semiconductors. For example, the memory cell layer 210 includes a two-dimensional (2D) memory such as a DRAM having a Buried Channel Array Transistor (BCAT) or a Vertical Channel Transistor (VCT) structure. For another example, the memory cell layer 210 includes a three-dimensional (3D) memory such as a Vertically Stacked DRAM (VSDRAM), a 3D Ferroelectric FET (FeFET), or a 3D Monolithic memory.

[0054] 15A, 16A, and 17A, the memory cell layer 210 includes a DRAM having a BCAT structure including an active region ACT, a bit line node contact DC, a bit line BL, a storage node contact BC, and a capacitor CAP, etc. At this time, a word line (not shown) crosses the active region ACT below the upper surface of the active region ACT.

[0055] For example, as shown in FIGS. 15B, 16B, and 17B, the memory cell layer 210 includes a DRAM having a VCT structure including bit lines BL, channel patterns CH, word lines WL, and capacitors CAP. In this case, the channel pattern CH includes at least one of single crystal silicon, polysilicon, an oxide semiconductor material (e.g., InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, InxGayO, etc.), and a two-dimensional material (e.g., graphene, a transition metal dichalcogenide (TMD) including a transition metal element (Mo, W, V, Nb, Ta, Ti, etc.) and a chalcogen element (S, Se, Te, etc.), etc.).

[0056] The cell wiring layer 22 includes a cell circuit wiring 22a and a cell contact plug 22b that electrically connects the memory cell layer 210 and the cell circuit wiring 22a.

[0057] 15A and 15B, the data storage layer 21 is disposed on the core peripheral chip 10, and the cell wiring layer 22 is disposed on the data storage layer 21. The data storage layer 21 is disposed between the core peripheral chip 10 and the cell wiring layer 22.

[0058] The memory cell layer 210 and the cell wiring layer 22 are provided in this order on the first surface 201 of the cell semiconductor layer 200. The core peripheral chip 10 is provided on the second surface 202 of the cell semiconductor layer 200. In other words, the cell semiconductor layer 200, the memory cell layer 210, and the cell wiring layer 22 are sequentially located on the core peripheral chip 10. The chip insulating layer 60 is interposed between the second surface 202 of the cell semiconductor layer 200 and the core peripheral chip 10.

[0059] The through conductive pattern 50 electrically connects the core peripheral chip 10 and the cell chip 20. The through conductive pattern 50 penetrates the cell chip 20 and the chip insulating layer 60 along the vertical direction VD and extends to the core peripheral chip 10. For example, the through conductive pattern 50 is electrically connected to the data storage layer 21 through the cell wiring layer 22 and electrically connected to the driving layer 11 through the core peripheral wiring layer 12.

[0060] As an example, in manufacturing the memory chip 1000, the cell chip 20 is sequentially formed on the core peripheral chip 10. In other words, the cell semiconductor layer 200, the memory cell layer 210, and the cell wiring layer 22 are sequentially formed on the core peripheral chip 10. At this time, preferably, the cell semiconductor layer 200 is a semiconductor epitaxial layer. As another example, in manufacturing the memory chip 1000, the data storage layer 21 may be formed through a manufacturing process separate from the core peripheral chip 10 and then bonded onto the core peripheral chip 10. At this time, preferably, the cell semiconductor layer 200 is a semiconductor substrate. However, the above description of the manufacturing of the memory chip 1000 is merely illustrative, and the concept of the present invention is not limited thereto.

[0061] 16A and 16B, as in Figures 15A and 15B, the data storage layer 21 is disposed on the core peripheral chip 10, and the cell wiring layer 22 is disposed on the data storage layer 21. The data storage layer 21 is disposed between the core peripheral chip 10 and the cell wiring layer 22.

[0062] 15A and 15B, the memory cell layer 210 is disposed between the first surface 201 of the cell semiconductor layer 200 and the core peripheral chip 10, and the cell wiring layer 22 is disposed on the second surface 202 of the cell semiconductor layer 200. In other words, the memory cell layer 210, the cell semiconductor layer 200, and the cell wiring layer 22 are sequentially disposed on the core peripheral chip 10. The chip insulating layer 60 is disposed on the first surface 201 of the cell semiconductor layer 200 and is interposed between the memory cell layer 210 and the core peripheral chip 10. The through conductive pattern 50 electrically connects the core peripheral chip 10 and the cell chip 20.

[0063] As an example, in manufacturing the memory chip 1000, the data storage layer 21 is formed through a manufacturing process separate from the core peripheral chip 10, and then bonded onto the core peripheral chip 10. At this time, the cell semiconductor layer 200 is preferably a semiconductor substrate. As an example, the data storage layer 21 is bonded upside down onto the core peripheral chip 10. However, the above description of the manufacturing of the memory chip 1000 is merely illustrative, and the concept of the present invention is not limited thereto.

[0064] 17A and 17B, unlike in FIGS. 15A to 16B, the cell wiring layer 22 is disposed on the core peripheral chip 10, and the data storage layer 21 is disposed on the cell wiring layer 22. The cell wiring layer 22 is disposed between the data storage layer 21 and the core peripheral chip 10.

[0065] The memory cell layer 210 is disposed between the first surface 201 of the cell semiconductor layer 200 and the core peripheral chip 10, and the cell wiring layer 22 is disposed between the memory cell layer 210 and the core peripheral chip 10. The cell wiring layer 22, the memory cell layer 210, and the cell semiconductor layer 200 are sequentially located on the core peripheral chip 10.

[0066] The core peripheral wiring layer 12 includes a core peripheral bonding pad 15. The cell wiring layer 22 includes a cell bonding pad 25. The core peripheral chip 10 and the cell chip 20 are electrically connected to each other by coupling the core peripheral bonding pad 15 and the cell bonding pad 25. As an example, each of the core peripheral bonding pad 15 and the cell bonding pad 25 includes, but is not limited to, copper (Cu).

[0067] As an example, in manufacturing the memory chip 1000, the cell chip 20 is formed through a manufacturing process separate from the core peripheral chip 10, and then bonded onto the core peripheral chip 10. When the core peripheral chip 10 is formed, one surface of the core peripheral bonding pad 15 is exposed to the outside. When the cell chip 20 is formed, one surface of the cell bonding pad 25 is exposed to the outside. Through the bonding process, the exposed surface of the core peripheral bonding pad 15 and the exposed surface of the cell bonding pad 25 come into contact with each other, and the core peripheral bonding pad 15 and the cell bonding pad 25 are bonded to each other. As an example, the cell chip 20 is bonded upside down onto the core peripheral chip 10. However, the above description of the manufacturing of the memory chip 1000 is merely illustrative, and the concept of the present invention is not limited thereto.

[0068] FIG. 18 is a cross-sectional view illustrating multiple memory chips according to some embodiments of the present invention.

[0069] 18, a plurality of memory chips 1000 are arranged vertically to each other. The memory chip 1000 is one of the memory chips 1000 described above. Each of the memory chips 1000 includes a core peripheral chip 10 and a cell chip 20 arranged vertically to each other. The core peripheral chip 10 and the cell chip 20 each include a TSV 30. A plurality of core peripheral chips 10 and a plurality of cell chips 20 are stacked alternately to each other. Although two memory chips 1000 are illustrated in FIG. 18, the present invention is not limited thereto, and three or more memory chips 1000 may be stacked.

[0070] The memory chips 1000 are electrically connected to each other through the TSVs 30. The TSVs 30 of the memory chip 1000 include the TSVs 30 of the core peripheral chip 10 and the TSVs 30 of the cell chip 20. In FIG. 18, the TSVs 30 of the core peripheral chip 10 and the TSVs 30 of the cell chip 20 are illustrated as being physically connected to each other, but are not limited thereto, and may be connected to each other through separate contacts (not shown) provided therebetween.

[0071] The TSVs 30 of a pair of memory chips 1000 arranged vertically to each other are electrically connected through a first contact pad CP1 and a second contact pad CP2. The first contact pad CP1 and the second contact pad CP2 are in contact with each other. Each of the first and second contact pads CP1 and CP2 is a conductive pad or a conductive bump, independently of each other.

[0072] FIG. 19 is a cross-sectional view illustrating a semiconductor package including a memory chip according to some embodiments of the present invention.

[0073] 19, a semiconductor package 2000 includes a base chip 1100 and a plurality of memory chips 1000, 1000' on the base chip 1100. The base chip 1100 is electrically connected to the plurality of memory chips 1000, 1000' and includes a host core or a buffer die. The host core includes a processor that performs various arithmetic processing. The buffer die receives commands, data, signals, etc. transmitted from the outside and transmits them to the plurality of memory chips 1000, 1000'. In other words, the plurality of memory chips 1000, 1000' are connected to the base chip 1100 and are used to perform various processes according to signals received therefrom.

[0074] The memory chips 1000, 1000' are electrically connected to a base chip 1100 through TSVs 30. As an example, the base chip 1100 includes a base contact pad CPh at the top end, and the TSVs 30 are connected to the base chip 1100 through the base contact pad CPh. As an example, but not limited to, the TSVs 30 are not provided in the topmost memory chip 1000'.

[0075] FIG. 20 is a cross-sectional view illustrating a semiconductor package including a memory chip according to some embodiments of the present invention.

[0076] 20, the semiconductor package 1 includes package substrates 400, 500, a memory structure 3000, and a host structure 800. The memory structure 3000 and the host structure 800 are provided on the package substrates 400, 500 and are horizontally spaced apart from each other. The memory structure 3000 and the host structure 800 are electrically connected to each other through the package substrates 400, 500.

[0077] As an example, the package substrates 400, 500 include a first package substrate 400 and a second package substrate 500. The first package substrate 400 is located on the second package substrate 500, and the memory structure 3000 and the host structure 800 are located on the first package substrate 400. The first package substrate 400 is an interposer, and the second package substrate 500 is a printed circuit board PCB. The first connection terminals 440 electrically connect the first package substrate 400 and the second package substrate 500. The second connection terminals 540 electrically connect the semiconductor package 1 to an external device (e.g., a main board).

[0078] The memory structure 3000 includes a base chip 300, a plurality of memory chips 1000, 1000' on the base chip 300, a first molding film MD1 surrounding the plurality of memory chips 1000, 1000', and memory connection terminals 340 between the base chip 300 and package substrates 400, 500. The base chip 300 corresponds to the base chip 1100 of FIG.

[0079] The base chip 300 includes a base layer 310, an upper wiring layer 330 formed on one surface (e.g., the upper surface) of the base layer 310, and a lower base pad 320 exposed by the other surface (e.g., the lower surface) of the base layer 310. The upper wiring layer 330 includes an upper base pad 332 and a base protective layer 334 surrounding the upper base pad 332.

[0080] The base chip 300 rewires a plurality of memory chips 1000, 1000'. The upper base pad 332 and the lower base pad 320 are electrically connected by circuit wiring in the base layer 310, and together with the circuit wiring form a rewiring circuit. The memory connection terminals 340 are located between the lower base pad 320 and the package substrates 400, 500. The memory connection terminals 340 include solder balls or solder bumps. The first molding film MD1 includes an insulating material. For example, the first molding film MD1 includes an epoxy molding compound EMC.

[0081] The host structure 800 is a data processing device. The host connection terminals 840 are interposed between the host structure 800 and the package substrates 400 and 500. The host connection terminals 840 electrically connect the host structure 800 and the package substrates 400 and 500. A second molding film MD2 surrounds the memory structure 3000 and the host structure 800 on the package substrates 400 and 500.

[0082] According to the concept of the present invention, the core peripheral chip 10 and the cell chip 20 are arranged perpendicular to each other, so that the core region COR and the peripheral region PR are defined on a plane located at a different level from the cell region CR. Therefore, the integration density per unit area of ​​the memory chip 1000 can be improved compared to the case where the cell region CR, the core region COR, and the peripheral region PR are defined on the same plane.

[0083] In addition, since the core peripheral chip 10 includes the NPU block NB, the NPU block NB is disposed adjacent to the cell region CR. Therefore, the data movement distance between the NPU block NB and the cell region CR is minimized, and the data processing speed of the memory chip 1000 can be improved. In addition, the memory chip 1000 can be driven with low power, and issues such as noise and heat generation can be improved. As a result, the performance of the memory chip 1000 can be improved.

[0084] Although the embodiments of the present invention have been described above with reference to the drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting. [Explanation of symbols]

[0085] 10 Core Peripheral Chip 11 Driving Layer 12 Core peripheral wiring layer 100 Core peripheral semiconductor layer 110 Core peripheral transistor 20 Cell Chip 30 TSV 21 Data Storage Layer 22 Cell wiring layer 50 Conductive through pattern 60 Chip insulation layer 200 Cell Semiconductor Layer 210 Memory Cell Layer 400, 500 Package substrate 800 Host Structures 1000 memory chips 2000, 3000 memory structures CR Cell Area COR Core Area PR Peripheral Areas CB Cell Bank COB Core Bank NB NPU block NBF NPU Buffer

Claims

1. The cell chip and the core-periphery chip are arranged vertically and electrically connected to each other, the cell chip includes cell regions each including a memory cell layer; the core peripheral chip includes a core group region and a peripheral region adjacent to each other in a first direction, The core group region includes core regions arranged in a row along a second direction intersecting the first direction, Each of the core regions includes a core bank including a core circuit and an NPU (neural processing unit) block including an NPU.

2. The memory chip of claim 1 , wherein the core bank and the NPU block are arranged symmetrically with respect to a line perpendicular to the first direction with respect to the peripheral region.

3. The memory chip of claim 1 , wherein the core bank and the NPU block are arranged asymmetrically with respect to a line perpendicular to the first direction with respect to the peripheral region.

4. the core peripheral chip includes a side surface facing the first direction, The memory chip of claim 1 , wherein the core group regions include core group regions adjacent to each other in the first direction between the side of the core peripheral chip and the peripheral region.

5. The memory chip of claim 1 , wherein each of the cell regions further comprises an NPU buffer.

6. 6. The memory chip of claim 5, wherein the NPU buffer includes at least one of a New Memory and an SRAM.

7. 10. The memory chip of claim 1, wherein the memory cell layer includes at least one of a 2D memory and a 3D memory.

8. The memory chip of claim 1 , wherein each of the cell regions vertically overlaps at least a portion of each of the NPU blocks.

9. Each of the cell chip and the core peripheral chip further includes a through-silicon via (TSV), The memory chip of claim 1 , wherein the TSV of the cell chip and the TSV of the core periphery chip are electrically connected to each other.

10. 2. The memory chip of claim 1, wherein the cell chip and the core peripheral chip are electrically connected to each other through a through conductive pattern passing through the cell chip and the core peripheral chip.

11. The cell chip further includes a cell bonding pad; The core periphery chip further includes a core periphery bonding pad; 2. The memory chip of claim 1, wherein the cell bonding pad and the core periphery bonding pad are coupled to each other to electrically connect the cell chip and the core periphery chip.

12. The cell chip further includes a cell semiconductor layer including a semiconductor material; The memory chip of claim 1 , wherein the cell semiconductor layer is located between the core peripheral chip and the memory cell layer.

13. The cell chip further includes a cell semiconductor layer including a semiconductor material; The memory chip of claim 1 , wherein the memory cell layer is located between the core peripheral chip and the cell semiconductor layer.

14. a plurality of memory chips stacked vertically on one another; and a through-silicon via (TSV) electrically connecting the plurality of memory chips; Each of the plurality of memory chips includes a cell chip and a core periphery chip arranged perpendicular to each other, the cell chip includes cell regions each including a memory cell layer; the core peripheral chip includes a core group region and a peripheral region adjacent to each other in a first direction, The core group region includes core regions arranged in a row along a second direction intersecting the first direction, Each of the core regions includes a core bank including a core circuit and an NPU (neural processing unit) block including an NPU.

15. Further comprising a base chip including a host core or a buffer die; The semiconductor package of claim 14 , wherein the plurality of memory chips are provided on the base chip.

16. The semiconductor package according to claim 14 , wherein the TSV passes through central portions of the memory chips.

17. A package substrate; a host structure on the package substrate; a memory structure horizontally spaced apart from the host structure on the package substrate and electrically connected to the host structure; the memory structure includes a plurality of memory chips vertically stacked on one another; Each of the plurality of memory chips includes: The cell chip and the core peripheral chip are arranged vertically and electrically connected to each other, the cell chip includes cell regions each including a memory cell layer; the core peripheral chip includes a core group region and a peripheral region adjacent to each other in a first direction, The core group region includes core regions arranged in a row along a second direction intersecting the first direction, Each of the core regions includes a core bank including a core circuit and an NPU (neural processing unit) block including an NPU.

18. 20. The semiconductor package of claim 17, wherein the memory structure further comprises through-silicon vias (TSVs) electrically connecting the plurality of memory chips.

19. 20. The semiconductor package of claim 17, wherein the memory structure comprises a plurality of horizontally spaced apart memory structures.

20. 20. The semiconductor package of claim 17, wherein the memory cell layer includes at least one of a 2D memory and a 3D memory.

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