Semiconductor device

Abstract

To provide stable electrical characteristics to a semiconductor device using an oxide semiconductor film to make a semiconductor device having high reliability.SOLUTION: In a semiconductor device, by utilizing a difference in an atomic weight among a plurality of kinds of atoms included in a target for an oxide semiconductor, and preferentially depositing zinc having a small atomic weight on an oxide insulation film a zinc-containing seed crystal is formed, and depositing tin, indium and the like having a large atomic weight while crystal growing tin, indium and the like, a crystalline oxide semiconductor film is formed without undergoing a plurality of processes. Further, with a core of a seed crystal having a crystal containing zinc with a hexagonal crystal structure as the seed crystal, by forming the crystalline oxide semiconductor film by crystal growth, the crystalline oxide semiconductor film of a single crystal or a substantially single crystal is formed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] A semiconductor device having a circuit including at least one semiconductor element such as a transistor. For example, the present invention relates to a power device mounted on a power supply circuit, a memory , thyristors, converters, image sensors, and other semiconductor integrated circuits, and liquid crystal display devices. Electronic equipment that incorporates electro-optical devices or light-emitting display devices having light-emitting elements as components Regarding.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] As typified by liquid crystal display devices, transistors formed on glass substrates are amorphous. It is made of amorphous silicon, polycrystalline silicon, etc. Although the resulting transistor has low field-effect mobility, it can be used on large glass substrates. In addition, the field effect mobility of a transistor using polycrystalline silicon is high, but the field effect mobility of a transistor using glass is low. It has the disadvantage that it is not suitable for large-area substrates.

[0004] A transistor using an oxide semiconductor is manufactured in place of a transistor using silicon. The technology is attracting attention for its application to electronic and optical devices. For example, oxide semiconductors A transistor was fabricated using zinc oxide and In-Ga-Zn-O oxide, and a display device was Technologies used for pixel switching elements, etc. are disclosed in Patent Documents 1 and 2. .

[0005] Regarding the oxide semiconductor used in such transistors, The film is insensitive to metal impurities, and there is no problem even if the film contains a large amount of metal impurities. "So we can use inexpensive soda-lime glass that contains a large amount of alkali metals." (See non-patent document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Non-patent literature]

[0007] [Non-Patent Document 1] Kamiya, Nomura, and Hosono, "Physical properties of amorphous oxide semiconductors and the current status of device development," Solid State Physics, September 2009, Vol. 44, pp. 621-633 Summary of the Invention [Problem to be solved by the invention]

[0008] During the device manufacturing process, oxide semiconductors are contaminated with hydrogen and water, which are carrier sources. When this occurs, the electrical conductivity of the oxide semiconductor may change. This can cause fluctuations in the electrical characteristics of the transistors used.

[0009] In addition, a semiconductor device using an oxide semiconductor can exhibit improved electrical characteristics when irradiated with visible light or ultraviolet light. is likely to change.

[0010] In view of such problems, a method for imparting stable electrical characteristics to a semiconductor device using an oxide semiconductor film is provided. Another object of the present invention is to manufacture a highly reliable semiconductor device.

[0011] In addition, large substrates such as mother glass are used to mass-produce highly reliable semiconductor devices. Another object of the present invention is to provide a manufacturing process of a semiconductor device that can perform the above-mentioned steps. [Means for solving the problem]

[0012] According to one embodiment of the present invention, a method for manufacturing an oxide semiconductor device includes the steps of: By taking advantage of the difference in atomic weight of the multiple types of atoms contained in the material, zinc, which has a smaller atomic weight, is preferentially used to form oxide insulation. The zinc-containing hexagonal crystal structure is formed on the surface of the deposited film during the deposition process. A seed crystal is formed and tin, indium, or other elements with large atomic weights are grown on the seed crystal. By depositing the oxide semiconductor film while removing the oxide film, a crystalline oxide semiconductor film can be formed without going through multiple steps. The seed crystals containing zinc are not limited to the surface of the deposition film during the film formation, but may also be formed on the oxide insulating film. A seed crystal may be formed from the interface of the zinc-containing hexagonal crystal structure. By growing crystals from crystals as nuclei to form a crystalline oxide semiconductor film, a single crystal or The gist of the present invention is to form a crystalline oxide semiconductor film that is substantially single crystal.

[0013] In another embodiment of the present invention, a semiconductor device is provided that is formed by sputtering an oxide insulating film over a substrate. By this, a seed crystal having a hexagonal structure containing zinc is formed, and the seed crystal is used as a nucleus to form a A crystalline oxide semiconductor film having crystals with a hexagonal crystal structure is formed by crystal growth. The present invention relates to a method for manufacturing a transistor using a compound semiconductor film.

[0014] The crystalline oxide semiconductor film is subjected to a first heat treatment at a temperature of 250° C. or higher and 350° C. or lower in an atmosphere containing oxygen. The first heat treatment is performed by sputtering. In the sputtering apparatus used for the above-mentioned film formation, The distance between the substrate and the substrate is set so that elements with small atomic weights can arrive preferentially on the substrate. As a result, zinc is preferentially deposited on the oxide insulating film, and the deposited zinc is oxidized. The seed crystal has a hexagonal crystal structure containing zinc, typically zinc oxide having a hexagonal crystal structure. Therefore, a seed crystal is formed by crystal growth from the surface of the oxide insulating film. In addition, by performing sputtering, a hexagonal crystal structure containing zinc can be formed. The seed crystal having the crystal structure is used as a nucleus to grow the crystal, and the a -b plane has bonds with a hexagonal lattice, and the substrate plane is approximately parallel to the ab plane. To form a crystalline oxide semiconductor film having crystals with a hexagonal crystal structure having a perpendicular c-axis can be done.

[0015] It has bonds with a hexagonal lattice in the ab plane and has a c-axis perpendicular to the substrate plane. A crystalline oxide semiconductor film having crystals with a hexagonal structure has a highly regular crystal structure. A planar TEM photograph of the conductive oxide semiconductor film is shown in FIG. 17. A part of the photograph is enlarged, and a hexagonal lattice is formed. For ease of understanding, atoms are surrounded by white lines in Figure 18. A transistor including a semiconductor film has stable electrical characteristics and is highly reliable.

[0016] One of the reasons why a transistor including a crystalline oxide semiconductor film has high reliability will be described below. .

[0017] Crystalline oxide semiconductors have a higher metal-oxygen bond (-M) than amorphous oxide semiconductors. -OM-, where O is an oxygen atom and M is a metal atom) is regular. In other words, oxide semiconductors In the case of an amorphous structure, the coordination number may differ for each metal atom. In the case of a crystalline oxide semiconductor, the oxygen vacancies are almost constant. , hydrogen atoms (including hydrogen ions) and alkali metal atoms in "space" as described below This has the effect of reducing charge transfer and instability due to desorption.

[0018] On the other hand, in the case of an amorphous structure, the coordination number varies depending on the individual metal atoms, so The concentration of oxygen and oxygen atoms becomes microscopically uneven, and there are places where no atoms exist (" In such a "space", for example, hydrogen atoms (hydrogen ions) may exist. It is believed that atoms of alkali metals (including fluorine) are captured and, in some cases, bond with oxygen. It is also possible for those atoms to move through such "space."

[0019] Such atomic movement leads to fluctuations in the characteristics of the oxide semiconductor. The presence of atoms poses a major reliability problem. In particular, the movement of such atoms can be affected by high electric fields and This phenomenon occurs when light energy is applied, so using an oxide semiconductor under such conditions In other words, the reliability of amorphous oxide semiconductors is affected by the Therefore, the conductivity of the oxide semiconductor is inferior to that of the oxide semiconductor.

[0020] Below, we present the results of different reliability of the transistors (samples 1 and 2) that were actually obtained. However, the sample 2 actually obtained as described below was formed at a film-forming temperature of 200° C. After the material film is formed, it is heated at 450°C in a nitrogen atmosphere, and the second material is heated at a film formation temperature of 200°C. After the film was formed, it was heated at 450° C. in a dry air atmosphere to form a crystalline oxide semiconductor film. Sample 2 is a crystalline semiconductor in which the first material film and the second material film are the same. It goes without saying that the same can be said about membranes even in different cases. Sample 1 used for comparison was a single-layer material film heated to 650°C by RTA and then dried. Heating was performed at 450° C. in an air atmosphere to obtain a crystalline oxide semiconductor film.

[0021] As a method for inspecting reliability, the gate and source voltages of the transistor are measured while irradiating light. The drain and source electrodes of a transistor when the voltage (Vg) between the electrodes is changed The Id-Vg curve of a transistor is obtained by measuring the current (Id) flowing between the Note that a transistor including an oxide semiconductor film was subjected to a -BT test while being irradiated with light. In other words, applying a negative gate bias changes the threshold voltage of the transistor. This degradation is called negative bias light irradiation degradation.

[0022] FIG. 19 shows the negative bias stress stress photodegradation of Samples 1 and 2.

[0023] In FIG. 19, sample 2 has a smaller change in Vth than sample 1.

[0024] Next, the transistor of sample 1 (L / W=3μm / 50μm) was exposed to light (wavelength 400nm, irradiation intensity 3.5mW / cm 2 The photoresponse was measured before and after irradiation. A graph of the photoresponse (photocurrent time dependency graph) created from the results is shown in FIG. 20(A). Note that Vd is 0.1V.

[0025] In addition, the transistor of sample 2 (L / W=3μm / 50μm) was exposed to light (wavelength 400nm, irradiation intensity 3.5mW / cm 2 The photoresponse was measured before and after irradiation. A graph of the photoresponse (photocurrent time dependency graph) created from the results is shown in FIG. 20(B).

[0026] In addition, the transistor was fabricated under the same conditions as sample 2, but with a larger W width (L / W=30 μm / 10000 μm) or by increasing the W width of a transistor fabricated under the same conditions as sample 2. Measurements were also performed under the same conditions with Vd increased (Vd = 15 V), and fitting was performed. The two relaxation times (τ1 and τ2) were calculated and the maximum current value was calculated. (Imax) is shown in Table 1.

[0027] [Table 1]

[0028] The two types of relaxation times (τ1 and τ2) depend on the trap density. The method for calculating τ2 is called the light response defect evaluation method.

[0029] As shown in Table 1, sample 2, which shows smaller negative bias photodegradation than sample 1, has a higher photoresponse From these results, it can be seen that the smaller the negative bias light photodegradation, the faster the photoresponse. The relationship can be found.

[0030] One of the reasons is that if a deep donor level exists and holes are trapped in the donor level, If this is the case, the negative bias light photodegradation occurs due to the negative bias applied to the gate. This results in a fixed charge, which may result in a longer relaxation time of the current value in the photoresponse. A transistor using a crystalline oxide semiconductor film has low degradation due to negative bias light irradiation and The reason for the fast response is that the density of the donor levels that trap the above-mentioned holes is small. This is expected to be due to the above. Figure 21 shows a schematic diagram of the predicted donor levels.

[0031] In addition, low-temperature PL measurements were performed to investigate the changes in the donor level depth and density. The substrate temperature during deposition of the nitride semiconductor film was 400°C, while the oxide semiconductor film was deposited at 100°C. FIG. 22 shows the case where the substrate temperature is 200°C.

[0032] From FIG. 22, when the substrate temperature during the deposition of the oxide semiconductor film is 400° C., the The peak intensity around the substrate temperature is significantly reduced compared to that at a substrate temperature of 200°C. The results suggest that the donor levels remain unchanged in depth but are significantly reduced in density.

[0033] In addition, the substrate temperature conditions during the formation of the oxide semiconductor film were changed and compared, and the evaluation of the single film was performed. The evaluation was carried out.

[0034] Sample A is a quartz substrate (thickness 0.5 mm) on which an oxide semiconductor film with a thickness of 50 nm is formed. The oxide semiconductor film was formed under the following conditions: -Ga-Zn-O oxide semiconductor target (In2O3:Ga2O3:ZnO=1: 1:2 [molar ratio]), the distance between the substrate and the target was 60 mm, and the substrate temperature 200℃, pressure 0.4Pa, direct current (DC) power supply 0.5kW, argon (30sccm) The atmosphere was a mixture of oxygen (15 sccm) and nitrogen (15 sccm).

[0035] ESR (electron spin resonance) was measured at room temperature (300K) and microwave (frequency 9.5GHz) was used. z) from the magnetic field value (H0) at which absorption occurs, using the formula g = hv / βH0, the parameter g is calculated. Here, h is the Planck constant and β is the Bohr magneton, both of which are constants. It is.

[0036] A graph showing the g value of sample A is shown in FIG.

[0037] In addition, after deposition under the same conditions as sample A, the sample was heated at 450°C for 1 hour in a nitrogen atmosphere. This was performed to obtain a sample B. A graph showing the g value of sample B is shown in FIG.

[0038] In addition, after deposition under the same conditions as sample A, the sample was heated at 450°C in a mixed atmosphere of nitrogen and oxygen. Heat for 1 hour to obtain sample C. The g value of sample C is shown in Figure 23(C). show.

[0039] In the graph of the g value of sample B, a signal of g=1.93 can be confirmed, and the spin density is 1.8×10 18 [spins / cm 3 On the other hand, the ESR result for sample C is As a result, the signal at g=1.93 cannot be confirmed. This is due to dangling bonds of metal in the oxide semiconductor film.

[0040] Samples D, E, F, and G are made of 100 nm thick acid film on a quartz substrate (0.5 mm thick). The oxide semiconductor film was formed under the following conditions: Target for In-Ga-Zn-O oxide semiconductor (In2O3:Ga2 O3:ZnO = 1:1:2 [molar ratio]) was used, and the distance between the substrate and the target 60 mm, pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, argon (30 sccm) Samples D, E, F, and G were placed in a mixed atmosphere of 1000 nm and 15 sccm of oxygen. The substrate temperatures during film formation are different for each sample. Sample D is room temperature, Sample E is 200°C, Sample F is at 300°C and sample G is at 400°C.

[0041] The ESR spectra of samples D, E, F, and G are shown in Figure 24.

[0042] In sample G, where the substrate temperature during film formation (denoted as Tsub) is 400°C, g=1.93 The spin density is 1.3×10 18 [spins / cm 3 ] The spin density is the same as that of the signal with g = 1.93 obtained in sample B. It's about the same.

[0043] In Figure 25, which shows the results of ESR measurement of sample B, the magnetic field was perpendicular to the substrate surface. The spectrum is shown by the solid line when the θ is applied parallel to the substrate surface (dotted line). This represents the difference in g-values ​​(anisotropy) between the spectra shown in

[0044] In addition, after deposition under the same conditions as sample G, the sample was heated at 450°C for 1 hour in a nitrogen atmosphere. The results of ESR measurement of sample H are shown in FIG. 26. The spectrum shown is perpendicular to the surface (solid line) and parallel to the substrate surface. This shows the difference in g value (anisotropy) when a voltage is applied (spectrum shown by dotted line).

[0045] Comparing Figures 25 and 26, it was found that at a substrate temperature of 200°C, the change in g-value due to anisotropy, Δg, was 0 At a substrate temperature of 400°C, Δg was ~0.003. In general, the better the crystallinity (the more uniform the orbitals are), the greater the anisotropy. It is known that the film with a substrate temperature of 400°C has a higher The direction of the dangling bonds of the metal formed by heating at 450℃ for 1 hour in a nitrogen atmosphere was It is concluded that the crystals are well-ordered, i.e., have good crystallinity.

[0046] In addition, ESR measurements were performed while changing the thickness of the oxide semiconductor film. The intensity change of the g=1.93 signal is shown in FIG. 27, and the total number of spins is shown in FIG. 28. 28, the intensity of the g=1.93 signal increases with increasing thickness of the oxide semiconductor film. This indicates that the g=1.93 signal is caused by the dangling. The ring bond is not at the interface between the quartz substrate and the oxide semiconductor film or on the surface of the oxide semiconductor film, but in the bulk. suggests that it exists.

[0047] These results show that the dangling bonds of metal have anisotropy, and that the anisotropy depends on the deposition temperature. The higher the value, the better the crystallinity, and the larger the crystal size. It can be seen that the bonds exist in the bulk, not at interfaces or surfaces.

[0048] From these results, the g value, which is thought to be due to the improvement of crystallinity when the substrate temperature during film formation is increased, The increase in anisotropy of the g = 1.93 signal was also confirmed. The band is dependent on the thickness and is due to the dangling bonds in the IGZO bulk. This suggests that there is.

[0049] Note that the oxide insulating film in contact with the crystalline oxide semiconductor film releases part of oxygen by heating. It is preferable to form the insulating film using an oxide insulating film. As the insulating film, an oxide insulating film containing more oxygen than the stoichiometric ratio is used. It is preferable that the crystalline oxide semiconductor film is formed and then subjected to a second heat treatment. Oxygen contained in the oxide insulating film is mixed with the crystalline oxide semiconductor film or with the oxide insulating film. The oxygen vacancies in the crystalline oxide semiconductor film can be reduced by diffusing the oxygen to the interface with the oxide semiconductor film. The second heat treatment is performed at a temperature of 150° C. or higher and lower than the distortion point of the substrate, preferably 250° C. or higher and 45° C. or higher. The temperature should be below 0℃.

[0050] In addition, by setting the pressure in the processing chamber of the sputtering device to 0.4 Pa or less, the deposition surface and It is possible to reduce the inclusion of impurities such as alkali metals and hydrogen in the film-forming object. Hydrogen contained in the film can exist as hydrogen atoms, hydrogen molecules, water, hydroxyl groups, or hydrides. It may be included.

[0051] In addition, the distance between the targets (TS distance) is set to 40 mm or more and 300 mm or less (preferably The greater the distance between TSs, the greater the oxide semiconductor spars. Among the metallic elements contained in the target, zinc has the smallest atomic weight and is the most abundant element among the other elements. The elements with larger molecular weight preferentially deposit on the substrate side, forming bonds with a hexagonal lattice. Therefore, it is preferable that the distance between TSs is large.

[0052] In addition, when forming a film by sputtering, the temperature of the film-forming surface is preferably 250° C. or higher. The temperature must be below the upper limit of the heat treatment temperature for the substrate. 250°C is to prevent impurities such as water and hydrogen from entering the substrate. This is the temperature at which impurities are released into the gas phase in the chamber while preventing the inclusion of sputtering. The upper limit of the temperature of the surface to be filmed during film formation by the annealing method is the upper limit of the heat treatment temperature of the substrate or the upper limit of the temperature of the film formation. The upper limit temperature of the material (the temperature above which the components in the film undergo significant changes).

[0053] In addition, the leak rate of the sputtering equipment processing chamber was set to 1×10 -10 Pa·m 3 / second or less By this, it is possible to prevent the crystalline oxide semiconductor film from being damaged during the film formation by sputtering. It is possible to reduce the inclusion of impurities such as potassium metals and hydrides. By using a vacuum pump with a mounting type, alkali metals, hydrogen atoms, hydrogen molecules, water, The backflow of impurities such as hydroxyl radicals or hydrides can be reduced.

[0054] In addition, by setting the purity of the target to 99.99% or more, it is possible to mix the target with the crystalline oxide semiconductor film. By reducing the amount of alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, hydrides, etc. that enter the In addition, by using the target, it is possible to form a crystalline oxide semiconductor film. The concentrations of alkali metals such as lithium, sodium, and potassium can be reduced.

[0055] By forming a crystalline oxide semiconductor film under the above film formation conditions, the material can be refined during the film formation. The concentration of alkali metals was 5×10 16 atoms / cm 3 Below, the concentration of hydrogen is 1× 10 19 atoms / cm 3 A crystalline oxide semiconductor film having extremely reduced impurities, By reducing impurities in the crystalline oxide semiconductor film, the seed crystal and The crystal growth of the crystalline oxide semiconductor film is further promoted, and the film is single-crystalline or substantially single-crystalline. A crystalline oxide semiconductor film can be formed.

[0056] In addition, the transistor structure can be classified into top-gate and bottom-gate transistors. A top-gate transistor can be appropriately used. In this case, a hexagonal oxide film containing zinc is deposited on the oxide insulating film formed on the insulating surface by a sputtering method. A seed crystal having a cubic structure is formed, and the seed crystal is grown as a nucleus to form a hexagonal crystal. A crystalline oxide semiconductor film having a cubic crystal structure is formed, and the crystalline oxide semiconductor film is subjected to heat treatment. After the heat treatment, the crystalline oxide semiconductor film is selectively etched. A pair of electrodes is formed on the crystalline oxide semiconductor film, and the resulting crystalline oxide semiconductor film is selectively etched. A gate insulating film is formed over the crystalline oxide semiconductor film and the pair of electrodes, and a gate insulating film is formed over the gate insulating film. One of the features is that a bottom-gate transistor is fabricated. In this case, a gate electrode is formed on an insulating surface, and a gate insulating film including an oxide insulating film is formed on the gate electrode. A hexagonal crystal structure containing zinc is formed on the gate insulating film by sputtering. and growing a crystal using the seed crystal as a nucleus to form a crystal having a hexagonal structure. The crystalline oxide semiconductor film is subjected to heat treatment, and then heated. The treated crystalline oxide semiconductor film is selectively etched to obtain a selectively etched crystalline oxide semiconductor film. One of the features of the present invention is that a pair of electrodes is formed over the conductive oxide semiconductor film. Effect of the Invention

[0057] The bond has a hexagonal lattice in the ab plane, and the bond is approximately parallel to the substrate plane that is approximately parallel to the ab plane. A crystalline oxide semiconductor film having crystals with a hexagonal crystal structure having a substantially perpendicular c-axis is formed in a channel region. By fabricating a transistor having a birefringent region, the transistor can be irradiated with light or the birefringent region can be formed. The change in the threshold voltage of the transistor is small even before and after the thermal stress (BT) test. It is possible to manufacture a transistor having stable electrical characteristics. By setting the first heat treatment and the second heat treatment at 450°C or less, it is possible to form a large By using such a large substrate, highly reliable semiconductor devices can be mass-produced. [Brief description of the drawings]

[0058] [Figure 1] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 2] 1A to 1C are top views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Diagram 3] FIG. 2 is a schematic diagram illustrating a sputtering apparatus. [Figure 4] FIG. 2 is a schematic diagram illustrating the crystal structure of a seed crystal. [Diagram 5] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C are top views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C are top views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C are top views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 13] FIG. 2 is an example of a top view of a manufacturing apparatus for manufacturing one embodiment of the present invention. [Figure 14] 1A to 1C are a cross-sectional view, a top view, and a circuit diagram illustrating one embodiment of the present invention. [Figure 15] 1A and 1B are a block diagram and a circuit diagram illustrating one embodiment of the present invention. [Figure 16] 1A to 1C are external views of an electronic device illustrating one embodiment of the present invention. [Figure 17] This is a planar TEM photograph. [Figure 18] This is an enlarged view of a portion of Figure 17, with one of the hexagons indicated by a white line. [Figure 19] 1A and 1B are diagrams illustrating negative bias stress stress photodeterioration. [Figure 20] FIG. 13 is a graph illustrating the time dependence of photocurrent. [Figure 21] FIG. 2 is a schematic diagram illustrating a donor level. [Figure 22] FIG. 1 is a diagram illustrating the results of low-temperature PL measurements. [Diagram 23] FIG. 1 is a diagram illustrating the measurement results of ESR. [Figure 24] FIG. 1 is a diagram illustrating the measurement results of ESR. [Diagram 25] FIG. 1 is a diagram illustrating the measurement results of ESR. [Figure 26] FIG. 1 is a diagram illustrating the measurement results of ESR. [Figure 27] FIG. 1 is a diagram illustrating the measurement results of ESR. [Figure 28] FIG. 1 is a diagram illustrating the measurement results of ESR. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0059] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in the following manner. The present invention is not limited to the above-described embodiment. In the configuration, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. will be used throughout and a repeated explanation will be omitted.

[0060] In each figure described in this specification, the size, layer thickness, or area of ​​each component is not clearly indicated. may be exaggerated for clarity and are not necessarily limited to scale .

[0061] In addition, the terms "first," "second," "third," etc., used in this specification are used interchangeably to avoid confusion of components. The number is not limited to the number of the first one. For example, "first one" can be changed to " The terms "second" or "third" can be used interchangeably to explain the present invention.

[0062] (Embodiment 1) In this embodiment, a manufacturing method of a crystalline oxide semiconductor and a transistor using the oxide semiconductor will be described. A method for manufacturing a transistor will be described with reference to FIGS. 1 and 2. FIG. 1 shows the structure of a semiconductor device. 2 is a cross-sectional view showing a manufacturing process of a transistor according to one embodiment of the present invention; The cross-sectional view corresponds to FIG. 1(E). In this embodiment, a transistor having a top gate structure is I will use this to explain.

[0063] As shown in FIG. 1(A), an oxide insulating film 53 is formed on a substrate 51 .

[0064] The substrate 51 must have at least sufficient heat resistance to withstand subsequent heat treatments. When a glass substrate is used as the substrate 51, a substrate having a distortion point of 730° C. or higher is used. The glass substrate is preferably made of, for example, aluminosilicate glass, aluminoborate glass, or the like. Glass materials such as barium borosilicate glass and barium borosilicate glass are used. It is preferable to use a glass substrate containing more BaO. In this case, the size of the board is 1st generation (320mm x 400mm), 2nd generation (400mm x 5 00mm), 3rd generation (550mm x 650mm), 4th generation (680mm x 880mm , or 730mm x 920mm), 5th generation (1000mm x 1200mm or 11 00mm×1250mm), 6th generation (1500mm×1800mm), 7th generation (19 00mm×2200mm), 8th generation (2160mm×2460mm), 9th generation (24 00mm x 2800mm, or 2450mm x 3050mm), 10th generation (2950 Mother glass is used because the processing temperature is high and the processing If the time is long, the glass will shrink significantly, so if you use mother glass for mass production, the manufacturing process The heat treatment temperature is preferably 600° C. or less, more preferably 450° C. or less.

[0065] Instead of the above glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material can be used. Alternatively, crystallized glass can be used. Furthermore, the surface of a semiconductor substrate such as a silicon wafer or the surface of a conductive substrate made of a metal material can be It is also possible to use a substrate having an insulating film formed on its surface.

[0066] The oxide insulating film 53 is formed using an oxide insulating film from which part of oxygen is released by heating. As the oxide insulating film from which part of the oxygen is released by heating, the oxygen content is higher than that of the stoichiometric ratio. It is preferable to use an oxide insulating film that contains a lot of oxygen. The oxide insulating film can diffuse oxygen into the crystalline oxide semiconductor film by heating. The oxide insulating film 53 is typically made of silicon oxide, silicon oxynitride, or silicon nitride oxide. , aluminum oxide, aluminum oxynitride, gallium oxide, hafnium oxide, yttrium oxide It can be formed from thorium or the like.

[0067] When an oxide insulating film contains more oxygen than the stoichiometric ratio, some of the oxygen is removed by heating. The amount of oxygen released at this time is called the Thermal Desorptio Spectroscopy: Thermal Desorption Spectroscopy) analysis was performed to determine the amount of oxygen converted into oxygen atoms. The amount of emitted material is 1.0×10 18 atoms / cm 3 More than 1.0×10 20 a toms / cm 3 More preferably, 3.0×10 20 atoms / cm 3 That's all. .

[0068] Here, we will explain how to measure the amount of released oxygen when converted into oxygen atoms using TDS analysis. , as explained below.

[0069] The amount of gas released during TDS analysis is proportional to the integral value of the spectrum. The amount of gas released is calculated by the ratio of the integral value of the spectrum of the insulating film to the reference value of the standard sample. The standard value of the standard sample is the spectrum of the sample containing the specified atom. is the ratio of the atomic density to the integral value of

[0070] For example, the results of a TDS analysis of a silicon wafer containing a standard sample of hydrogen with a given density, From the results of TDS analysis of the oxide insulating film, the amount of oxygen molecules released from the oxide insulating film (N(O2)) can be calculated using Equation 1. Here, the mass number of 32 detected by TDS analysis is We assume that all the spectra are from oxygen molecules. The mass number of 32 is CH3OH. However, they are unlikely to exist and are not considered here. For oxygen molecules containing oxygen atoms with mass numbers 17 and 18, It is not taken into consideration because its presence in the environment is extremely small.

[0071] N(O2)=N(H2) / S(H2)×S(O2)×α (Math. 1)

[0072] N(H2) is the density of hydrogen molecules desorbed from the standard sample. S(H2) is is the integral value of the spectrum when the standard sample is analyzed by TDS. The value is N(H2) / S(H2). S(O2) is the value obtained by TDS analysis of the oxide insulating film. α is the coefficient that affects the spectral intensity in TDS analysis. For details of the formula 1, please refer to Japanese Patent No. 3298974. The amount of oxygen released from the oxide insulating film was measured using a thermal desorption analyzer EMD-WA manufactured by Electro-Science Corporation. 1000S / W was used, and 1×10 16 atoms / cm 3 Contains hydrogen atoms The measurement is performed using a silicon wafer containing the

[0073] In addition, some of the oxygen is detected as oxygen atoms in the TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen molecules is included in the calculation, the amount of oxygen atoms released can be calculated by evaluating the amount of oxygen molecules released. It is possible to estimate even if

[0074] Note that N(O2) is the amount of released oxygen molecules. In the case of an oxide insulating film, When this occurs, the amount of oxygen released is twice the amount of oxygen molecules released.

[0075] The oxide insulating film 53 has a thickness of 50 nm or more, preferably, 200 nm or more and 500 nm or less. By increasing the thickness of the oxide insulating film 53, the amount of oxygen released from the oxide insulating film 53 can be increased. The increase in the amount of the oxide insulating film 53 and the oxide semiconductor film to be formed later can be prevented. It is possible to reduce defects at the interface with the film.

[0076] The oxide insulating film 53 is formed by a sputtering method, a CVD method, or the like. The oxide insulating film from which part of the oxygen is released can be easily formed by a sputtering method. This is preferable.

[0077] When an oxide insulating film that releases some oxygen by heating is formed by a sputtering method, The amount of oxygen in the deposition gas is preferably high, and oxygen or a mixture of oxygen and a rare gas is preferably used. Typically, the oxygen concentration in the deposition gas is set to 6% or more and 100% or less. It is preferable that

[0078] A silicon oxide film is formed as a representative example of an oxide insulating film that releases some of the oxygen when heated. In this case, quartz (preferably synthetic quartz) is used as the target, and the substrate temperature is set to 30°C or higher and 450°C or higher. (preferably 70°C or higher and 200°C or lower), the distance between the substrate and the target (TS distance ) to 20mm or more and 400mm or less (preferably 40mm or more and 200mm or less), and the pressure is 0 0.1 Pa to 4 Pa ​​(preferably 0.2 Pa to 1.2 Pa), high frequency power supply at 0 .5kW or more and 12kW or less (preferably 1kW or more and 5kW or less), O2 / ( O2 + Ar) ratio is 1% or more and 100% or less (preferably 6% or more and 100% or less), It is preferable to form a silicon oxide film by RF sputtering. Preferably, a silicon target can be used in place of the synthetic quartz target. Alternatively, only oxygen may be used as the deposition gas.

[0079] When using a glass substrate containing impurities such as alkali metals, it is necessary to use a material that prevents the intrusion of alkali metals. For the purpose of preventing the formation of the oxide insulating film 53, a silicon nitride film or a nitride film is formed between the substrate 51 and the oxide insulating film 53 as a nitride insulating film. The nitride insulating film may be formed by a CVD method, a sputtering method, or the like. Alkali metals such as lithium, sodium, and potassium can be formed by impurity. Since it is a substance, it is preferable to reduce the content.

[0080] Next, a thick film was formed on the oxide insulating film 53 by a sputtering method using a sputtering apparatus. An oxide semiconductor film having a thickness of 30 nm to 50 μm is formed.

[0081] Here, the processing chamber of the sputtering device will be described with reference to FIG. The processing chamber 31 is connected to an exhaust means 33 and a gas supply means 35. A plate support 40 and a target 41 are provided. The target 41 is connected to a power supply 37. will be done.

[0082] The processing chamber 31 is grounded. The leak rate of the processing chamber 31 is set to 1×10 -10 Pa m 3 / sec or less, the inclusion of impurities in the film formed by sputtering is reduced. It can be reduced.

[0083] To reduce the leak rate, it is necessary to reduce not only external leaks but also internal leaks. An external leak is when gas enters the vacuum system from outside due to a tiny hole or poor seal. Internal leaks are leaks from partitions such as valves in the vacuum system or leaks from internal components. Caused by released gas. Leak rate is 1×10 -10 Pa·m 3 To achieve a maximum of 1 / second Therefore, measures must be taken to prevent both external and internal leaks.

[0084] To reduce external leakage, it is advisable to seal the opening and closing parts of the processing chamber with metal gaskets. Tal gaskets are coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets are preferable. Metal gaskets have higher adhesion than O-rings and are suitable for external rings. In addition, the passivation of iron fluoride, aluminum oxide, chromium oxide, etc. By using a metal material coated with fluorine, the gas released from the metal gasket, including hydrogen, is reduced. This suppresses the internal leakage and reduces the internal leakage.

[0085] The material constituting the inner wall of the processing chamber 31 is aluminum, which emits less gas including hydrogen, and quartz. The material may be selected from the group consisting of chromium, titanium, zirconium, nickel, and vanadium. It may be used by coating an alloy material containing iron, chromium, nickel, etc. The alloy material containing nickel is rigid, heat-resistant, and easy to process. If the surface roughness of the component is reduced by polishing or other methods to reduce the surface area, the amount of gas released will decrease. Alternatively, the above-mentioned film forming apparatus components can be replaced with iron fluoride, aluminum oxide, chlorine oxide, etc. It may be coated with a passivating material such as ROM.

[0086] It is preferable that the members provided inside the processing chamber 31 are made of metal materials as much as possible. For example, When installing a viewing window made of quartz, etc., the surface should be covered with a foil to suppress gas emission. A thin coating of a passivating material such as iron fluoride, aluminum oxide, or chromium oxide may be used.

[0087] Furthermore, a sputtering gas refiner is provided immediately before the sputtering gas is introduced into the processing chamber 31. In this case, the length of the pipe from the refiner to the treatment chamber is preferably 5 m or less, more preferably 1 m or less. The length of the piping should be 5m or less, or 1m or less, to prevent gases from being released from the piping. The effect of can be reduced depending on the length.

[0088] The pipes for flowing sputtering gas from the cylinder to the processing chamber 31 are filled with iron fluoride and aluminum oxide. It is preferable to use metal piping whose inside is coated with a passivating material such as aluminum or chromium oxide. The aforementioned piping, for example, emits less hydrogen than SUS316L-EP piping. It is possible to reduce the amount of impurities mixed into the deposition gas. In addition, the joints of the piping are made of high-performance ultra-small metal gas. It is recommended to use a skewer joint (UPG joint). In addition, the piping material should be made entirely of metal. This reduces the effects of released gas and external leaks compared to when resin is used. This is preferable.

[0089] The adsorbates present inside the processing chamber 31 are adsorbed to the inner wall and therefore affect the pressure in the processing chamber. However, it can cause gas emission when the processing chamber is evacuated. Therefore, the leak rate and exhaust speed Although there is no correlation with the degree of exhaust, it is recommended to use a pump with high exhaust capacity to remove as much of the adsorbed matter as possible from the treatment chamber. It is important to desorb the adsorbed substances by evacuating the air beforehand. The chamber may be baked. This will increase the desorption rate of the adsorbed substances by about 10 times. Baking can be performed at temperatures between 100°C and 450°C. By removing adsorbed substances while introducing activated gas, water and other substances that are difficult to remove by exhausting alone can be removed. The desorption rate can be further increased.

[0090] The exhaust means 33 exhausts impurities from the processing chamber 31 and controls the pressure in the processing chamber 31. It is preferable that the exhaust means 33 is an adsorption type vacuum pump. For example, It is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. By using the above-mentioned adsorption type vacuum pump, the amount of hydrogen contained in the oxide semiconductor film can be reduced. It is possible.

[0091] The exhaust of the processing chamber 31 is performed by a roughing pump such as a dry pump, a sputter ion pump, a turbo pump, etc. It is advisable to appropriately combine a high vacuum pump such as a polymer pump or a cryopump. While turbomolecular pumps excel at pumping large molecules, they have low pumping capabilities for hydrogen and water. Therefore, we developed a cryopump with high pumping capacity for water and a sputter ion pump with high pumping capacity for hydrogen. Combining pumps is effective.

[0092] Note that hydrogen contained in the oxide semiconductor film can be a hydrogen molecule, water, a hydroxyl group, or the like in addition to a hydrogen atom. It may also be included as a hydride.

[0093] The gas supply means 35 supplies gas for sputtering the target into the processing chamber 31. The gas supply means 35 includes a cylinder filled with gas, a pressure regulator, a stroke valve, and a The gas supply means 35 is composed of a step valve, a mass flow controller, etc. By providing the purification device, it is possible to reduce impurities contained in the gas introduced into the processing chamber 31. The gases used to sputter the target are helium, neon, argon, and A rare gas such as fluorine or krypton is used. Alternatively, a mixture of one of the rare gases and oxygen is used. can be used.

[0094] The power supply 37 may be an RF power supply, an AC power supply, a DC power supply, or the like. Although not shown, a magnet is attached to the inside or outside of a target support that supports the target. By providing a net, it is possible to confine high-density plasma around the target, which increases the deposition rate. The method can improve the plasma quality and reduce plasma damage to the substrate. Furthermore, in the magnetron sputtering method, a magnet is By making it rotatable, the bias of the magnetic field can be reduced, which increases the utilization efficiency of the target and The variation in film quality within the surface of the substrate can be reduced.

[0095] The substrate support 40 is grounded. A heater is provided on the substrate support 40. The heater heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. There is a heating device, such as an electric furnace or GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Anneal) equipment l) Use of RTA (Rapid Thermal Anneal) equipment such as LRTA devices can be used with halogen lamps, metal halide lamps, and xenon arc lamps. The radiation emitted from lamps such as high-pressure sodium lamps, carbon arc lamps, and high-pressure mercury lamps The GRTA device heats the object to be treated by radiating light (electromagnetic waves) that This is an apparatus that performs heat treatment using gas.

[0096] The target 41 may be a metal oxide target containing zinc. A representative example of Get 41 is the In-Sn-Ga-Zn-O system, which is a quaternary metal oxide. Metal oxides, ternary metal oxides such as In-Ga-Zn-O, In-Sn- Zn-O metal oxide, In-Al-Zn-O metal oxide, Sn-Ga-Zn-O gold metal oxides, Al-Ga-Zn-O metal oxides, Sn-Al-Zn-O metal oxides, Binary metal oxides such as In-Zn-O metal oxides and Sn-Zn-O metal oxides A target of the above can be used.

[0097] As an example of the target 41, a metal oxide target containing In, Ga, and Zn is used. The composition ratio is n2O3:Ga2O3:ZnO=1:1:1 [molar ratio]. A target having a composition ratio of 2O3:Ga2O3:ZnO=1:1:2 [molar ratio], Or a tantalum oxide having a composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [molar ratio] The target has a composition ratio of In2O3:Ga2O3:ZnO=2:1:8 [molar ratio]. A target having a different structure can also be used.

[0098] The distance between the target 41 and the substrate 51 (TS distance) is set so that elements with small atomic weights are preferentially grown. The distance is set to be such that the oxide insulating film 53 on the substrate 51 can be reached first.

[0099] Next, a method for forming a crystalline oxide semiconductor film over an oxide insulating film will be described.

[0100] As shown in FIG. 3A, a substrate 51 having an oxide insulating film 53 formed on a substrate support 40 is Then, the gas is supplied from the gas supply means 35 to the processing chamber 31 of the sputtering device. A gas for sputtering the target 41 is introduced into the chamber 1. The purity of the target 41 is 9. The target 41 is then contacted with the ion exchange resin 44. As a result, the gas supply means 35 supplies the gas to the processing chamber 31. The ions 43 and electrons of the introduced sputtering gas sputter the target 41. In this embodiment, the distance between the target 41 and the substrate 51 is set to 100 mm. This is the interval at which the metal particles can preferentially reach and deposit on the oxide insulating film 53 on the substrate 51. Therefore, as shown in FIG. 3B, the elements contained in the target 41 have small atomic weights. The element 45 that is not present moves toward the substrate preferentially over the element 47 that has a larger atomic weight.

[0101] In the target 41 shown in this embodiment, zinc has a higher atomic number than tin and indium. Therefore, zinc is preferentially deposited on the oxide insulating film 53. The atmosphere contains oxygen, and the substrate support 40 is provided with a heater for heating the substrate and the deposited film during film formation. Therefore, zinc deposited on the oxide insulating film 53 is oxidized, and a hexagonal structure containing zinc is formed. A seed crystal 55a having a crystal of zinc oxide, typically a seed crystal having a hexagonal crystal structure, is formed. can be.

[0102] In addition, when the target 41 contains atoms having a smaller atomic weight than zinc, such as aluminum, Along with zinc, aluminum also deposits preferentially on the oxide insulating film 53 .

[0103] The seed crystal 55a has bonds with a hexagonal lattice in the ab plane, and is approximately flat on the ab plane. The crystal has a hexagonal structure containing zinc and has a c-axis approximately perpendicular to the substrate plane. , the ab plane has bonds with a hexagonal lattice, and the substrate plane is approximately parallel to the ab plane. The hexagonal crystal structure containing zinc with a c-axis roughly perpendicular to the Here, we will explain using zinc oxide as a representative example of a hexagonal crystal containing zinc. The black circles represent zinc and the white circles represent oxygen. Figure 4(A) shows the oxidation of a hexagonal crystal structure in the ab plane. FIG. 4(B) is a schematic diagram of zinc oxide with a hexagonal crystal structure, with the c-axis direction being the vertical direction. As shown in FIG. 4(A), zinc and an oxide are bonded to each other on the upper surface of the ab-plane. As shown in Figure 4(B), the bonds between zinc and oxygen are hexagonal. Layers having bonds with a hexagonal lattice are stacked, and the c-axis direction is perpendicular to the ab plane.

[0104] The seed crystal 55a has a layer having bonds with a hexagonal lattice on the ab plane, and is grown in a direction parallel to the c axis. It has at least an atomic layer.

[0105] The sputtering gas may be a rare gas (typically argon), oxygen gas, or a rare gas and oxygen. The sputtering gas may contain hydrogen, water, hydroxyl or water. It is preferable to use a high-purity gas from which impurities such as chlorines have been removed.

[0106] Subsequently, the target 41 is sputtered with a sputtering gas to form a seed crystal 5. Atoms contained in the target are deposited on the surface of the seed crystal 55a. In order to grow, a crystalline oxide semiconductor film 55b having a hexagonal crystal structure is formed on the seed crystal 55a. The substrate 51 can be heated by a heater provided on the substrate support 40. Since the heating is performed at a constant rate, the atoms deposited on the surface are oxidized and crystallized from the seed crystal 55a. As a result, a crystalline oxide semiconductor film can be formed.

[0107] At this time, the heating temperature of the substrate by the heater is 200° C. or more and 400° C. or less, preferably 250° C. or less. ℃ or more and 350 ℃ or less. 200 ℃ or more and 400 ℃ or less, preferably 250 ℃ or more and 350 ℃ or less. The first heat treatment is performed by heating the substrate to a temperature of 0.5 to 1000° C. or less while forming the film. The temperature of the surface to be deposited during sputtering must be 250°C or higher and below the upper limit of the heat treatment temperature of the substrate. do.

[0108] The crystalline oxide semiconductor film 55b is formed by growing the seed crystal 55a as a nucleus on the surface of the target 41. The heavy atoms and the light atoms sputtered after the formation of the seed crystal 55a Since the crystal grows while the atoms are oxidized, the ab-plane of the hexagonal crystal is formed in the same manner as the seed crystal 55a. It has bonds with a lattice and has a c-axis approximately perpendicular to the substrate plane which is approximately parallel to the ab-plane. The seed crystal 55a and the crystalline oxide semiconductor film 5 The crystalline oxide semiconductor film 55 formed by the oxide insulating film 53 has an ab plane parallel to the surface of the oxide insulating film 53. The bond has a hexagonal lattice in the ab plane and is approximately perpendicular to the substrate plane that is approximately parallel to the ab plane. The crystalline oxide shown in this embodiment has a hexagonal crystal structure containing zinc having a c-axis. The semiconductor film 55 is not an amorphous structure but a crystalline structure, ideally a single crystal structure, and A crystalline oxide semiconductor with a c-axis roughly perpendicular to the plate plane (C Axis Alignment d Crystal; also known as CAAC OS.

[0109] The pressure in the processing chamber containing the substrate support 40 and the target 41 is set to 0.4 Pa or less. This prevents impurities such as alkali metals and hydrogen from being mixed into and on the surface of the crystalline oxide semiconductor film. This can reduce the amount of contamination.

[0110] In addition, the leak rate of the sputtering equipment processing chamber was set to 1×10 -10 Pa·m 3 / second or less By this, it is possible to prevent the crystalline oxide semiconductor film from being damaged during the film formation by sputtering. It is possible to reduce the inclusion of impurities such as potassium metals, hydrogen, water, hydroxyl groups, and hydrides. In addition, by using an adsorption type vacuum pump for the exhaust system, alkali metals and water are removed from the exhaust system. It is possible to reduce backflow of impurities such as nitrogen, water, hydroxyl radicals, and hydrides.

[0111] In addition, by setting the purity of the target 41 to 99.99% or more, a crystalline oxide semiconductor film It is possible to reduce the amount of alkali metals, hydrogen, water, hydroxyl groups, hydrides, etc., that are mixed into the catalyst. In addition, by using the target, the crystalline oxide semiconductor film 55 can be Concentration 5×10 15 cm -3 Less than or equal to 1×10 15 cm -3 The following is sodium Concentration 5×10 16 cm -3 Less than or equal to 1×10 16 cm -3 The following is more preferable: 1×10 15 cm -3 The potassium concentration is 5×10 15 cm -3 The following is preferably is 1×10 15 cm -3 It can be as follows:

[0112] Alkali metals and alkaline earth metals are harmful impurities for crystalline oxide semiconductors. In particular, sodium, among alkali metals, is in contact with crystalline oxide semiconductors. The sodium ions (Na + ) In addition, crystalline oxide semiconductor In the conductor, it breaks the bonds between metal and oxygen or breaks into the bonds. Degradation of transistor characteristics (e.g., normally on (negative shift of threshold voltage), mobility In addition, it can also cause variations in characteristics. This becomes noticeable when the concentration of hydrogen in the crystalline oxide semiconductor is sufficiently low. The hydrogen concentration in the crystalline oxide semiconductor is 5×10 19 cm -3 Below, especially 5×10 18 cm -3 If it is below this value, it is highly desirable to have the alkali metal concentration be set to the above value.

[0113] By forming a crystalline oxide semiconductor film under the above conditions, the concentration of the alkali metal is 5× 10 16 atoms / cm 3 Below, the concentration of hydrogen is 1×10 19 atoms / cm 3 Below and A crystalline oxide semiconductor film with extremely reduced impurities can be formed. By reducing impurities in the oxide semiconductor film, crystal growth of the seed crystal and the crystalline oxide semiconductor film can be promoted. and forming a crystalline oxide semiconductor film that is single-crystalline or substantially single-crystalline. It is possible.

[0114] In a crystalline oxide semiconductor, oxygen that bonds to a metal element is more likely to be bonded to the metal element than in an amorphous oxide semiconductor. Since the reactivity with hydrogen is low, the generation of defects is reduced. The transistor with the channel region has a threshold voltage change before and after light irradiation and BT testing. It has low capacitance and stable electrical characteristics.

[0115] In addition, in the process of forming a crystalline oxide semiconductor film, the pressure in a treatment chamber, the temperature of a surface on which the film is to be formed, One or more of the leak rate of the treatment chamber and the purity of the target, preferably all of them, are set under the above conditions. By setting the above, hydrogen and an alkali metal contained in the oxide insulating film and the crystalline oxide semiconductor film can be prevented from being mixed. In addition, the intrusion of hydrogen from the oxide insulating film into the crystalline oxide semiconductor film can be reduced. The hydrogen contained in the oxide semiconductor can reduce the diffusion of the metal and the alkali metal. The oxygen reacts with the atoms to form water, and the lattice from which the oxygen is removed (or Defects are formed in the treated area.

[0116] Therefore, in the process of forming a crystalline oxide semiconductor film, impurities can be significantly reduced. Therefore, defects in the crystalline oxide semiconductor film can be reduced. The transistor that uses an oxide semiconductor film as a channel region has a threshold voltage of 100 V before and after light irradiation and BT testing. The change in voltage is small and the electrical characteristics are stable.

[0117] In this embodiment, the atomic weight of the target is determined in the same sputtering process. Taking advantage of this difference, zinc, which has a small atomic weight, is preferentially deposited on the oxide insulating film to form seed crystals. At the same time, tin, indium, and other elements with large atomic weights are deposited on the seed crystal while growing as crystals. Therefore, a crystalline oxide semiconductor film can be formed without going through multiple steps. A seed crystal having a hexagonal crystal structure containing zinc is used, and an oxide semiconductor having a hexagonal crystal structure is deposited on the seed crystal. Therefore, a crystalline oxide semiconductor film that is single crystal or substantially single crystal can be formed. can.

[0118] Note that a metal oxide that can be used for the crystalline oxide semiconductor film 55 has an energy gap The peak voltage is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By using metal oxides with a wide band gap, the off-state current of transistors can be reduced. It is possible.

[0119] In this embodiment, an In-Ga-Zn-O metal oxide target is used, and sputtering is performed. Crystalline oxide was prepared by sputtering using a mixture of argon and oxygen as the ionizing gas. A semiconductor film 55 is formed.

[0120] Next, the substrate 51 is subjected to a heat treatment to release hydrogen from the crystalline oxide semiconductor film 55. In both cases, part of oxygen contained in the oxide insulating film 53 is oxidized to the crystalline oxide semiconductor film 55 and the oxide The oxide semiconductor film 55 is diffused into the insulating film 53 in the vicinity of the interface with the crystalline oxide semiconductor film 55 .

[0121] The heat treatment temperature is set so that hydrogen is released from the crystalline oxide semiconductor film 55 and the oxide insulating film A part of the oxygen contained in the oxide semiconductor film 53 is released and diffused into the crystalline oxide semiconductor film 55. A temperature of 150° C. or higher and below the strain point of the substrate 51 is preferred, and is typically 250° C. or higher. The heat treatment temperature is set to be higher than or equal to 450° C. and lower than or equal to the deposition temperature of the crystalline oxide semiconductor film. By increasing the temperature, part of oxygen contained in the oxide insulating film 53 can be released in a larger amount. Cut.

[0122] The heat treatment is preferably carried out in an inert gas atmosphere, typically helium, neon, It is preferable to carry out the treatment in an atmosphere of a rare gas such as argon, xenon, or krypton, or in a nitrogen atmosphere. It may also be performed in a reduced pressure atmosphere.

[0123] By the heat treatment, hydrogen is released from the crystalline oxide semiconductor film 55 and the oxide insulating film 56 is formed. Part of the oxygen contained in the insulating film 53 is transferred to the crystalline oxide semiconductor film 55 and the oxide insulating film 53. The crystalline oxide semiconductor film 55 can be diffused into the vicinity of the interface of the crystalline oxide semiconductor film 55. In this way, oxygen vacancies in the crystalline oxide semiconductor film 55 can be reduced, and the oxidation The oxide semiconductor film 55 is formed by diffusing the crystalline oxide semiconductor film 55 into the insulating film. As a result, the hydrogen concentration and the defects at the interface of the oxide insulating film can be reduced. A crystalline oxide semiconductor film in which oxygen vacancies are reduced can be formed.

[0124] Next, a mask is formed over the heat-treated crystalline oxide semiconductor film, and then the mask is used to The crystalline oxide semiconductor film that has been subjected to the heat treatment is selectively etched to obtain a crystalline oxide semiconductor. A film 59 is formed. After that, the mask is removed (see FIG. 1(C)).

[0125] A mask for etching the crystalline oxide semiconductor film 55 is formed by a photolithography process. An ink-jet method, a printing method, or the like can be appropriately used. The etching in step 5 can be wet etching or dry etching as appropriate. .

[0126] Next, as shown in FIG. 1D, a pair of electrodes 61 in contact with the crystalline oxide semiconductor film 59 are formed. Complete.

[0127] The pair of electrodes 61 function as a source electrode and a drain electrode.

[0128] The pair of electrodes 61 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, etc. A metal element selected from stainless steel, or an alloy containing the above-mentioned metal elements, or the above-mentioned alloys It can be formed by using an alloy of a combination of metal elements. Alternatively, a metal element selected from one or more of the following may be used: The electrode 61 may have a single-layer structure or a laminated structure of two or more layers. Single-layer aluminum film structure, double-layer aluminum film with titanium film laminated on top, titanium nitride Two-layer structure with a titanium film laminated on a titanium nitride film, and two-layer structure with a tungsten film laminated on a titanium nitride film. The structure is a two-layer structure in which a tungsten film is laminated on a tantalum nitride film, and a titanium film and For example, a three-layer structure is available in which an aluminum film is laminated on top and a titanium film is further formed on top of that.

[0129] The pair of electrodes 61 is made of indium oxide containing indium tin oxide and tungsten oxide. Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide , Indium tin oxide containing titanium oxide, Indium zinc oxide, silicon oxide added A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the light-transmitting conductive material and the metal element may also be used.

[0130] The pair of electrodes 61 are formed by a printing method or an inkjet method. After forming a conductive film by a ring method, a CVD method, a vapor deposition method, or the like, a mask is formed on the conductive film to form a conductive layer. The conductive film is etched and formed. The mask formed on the conductive film is printed or inkjet printed. For this purpose, a photolithography method can be appropriately used.

[0131] Here, a conductive film is formed over the crystalline oxide semiconductor film 59 and the oxide insulating film 53. The conductive film is etched into a predetermined shape to form a pair of electrodes 61 .

[0132] After a conductive film is formed on the crystalline oxide semiconductor film that has been subjected to heat treatment, a multi-tone photomass A mask having a concave and convex shape is formed by a mask, and a crystalline oxide is obtained by heat treatment using the mask. After etching the semiconductor film and the conductive film, the uneven mask is separated by ashing. The conductive film is selectively etched using the separated mask, thereby forming a crystalline oxide semiconductor. By this process, the number of photomasks and the number of photoelectrons can be reduced. The number of lithography steps can be reduced.

[0133] Next, a gate insulating film 63 is formed over the crystalline oxide semiconductor film 59 and the pair of electrodes 61 .

[0134] Next, a gate electrode 6 is formed on the gate insulating film 63 so as to overlap with the crystalline oxide semiconductor film 59. Form 5.

[0135] After that, an insulating film 69 may be formed as a protective film (see FIG. 1(E)). After forming contact holes in the insulating film 63 and the insulating film 69, a pair of electrodes 61 are connected. Wiring may also be formed.

[0136] The gate insulating film 63 is made of silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide. Aluminum oxide, aluminum oxide nitride, or gallium oxide in a single layer or multilayer Note that the gate insulating film 63 is in contact with the crystalline oxide semiconductor film 59. It is particularly preferable that the insulating film 53 be made of a material that is easily heated and has a thickness that is not too thin. The silicon oxide film is formed from an oxide insulating film that releases oxygen more efficiently. Since oxygen can be diffused into the conductive oxide semiconductor film 59, the characteristics can be improved.

[0137] The gate insulating film 63 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium Silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminum Neate (HfAl x O y N z ), hafnium oxide, yttrium oxide and other high-k By using high-k materials, gate leakage can be reduced. Silicon, silicon oxynitride, silicon nitride, silicon oxynitride, aluminum oxide, oxide It can have a laminated structure with at least one of aluminum nitride and gallium oxide. The thickness of the gate insulating film 63 is preferably 1 nm to 300 nm, more preferably 5 nm to 500 nm. It is advisable to set it to 0 nm or less.

[0138] Before forming the gate insulating film 63, the surface of the crystalline oxide semiconductor film 59 is etched with oxygen, oxynitride, or tetrahydrofuran. The surface of the crystalline oxide semiconductor film 59 is exposed to a plasma of an oxidizing gas such as nitrous oxide or dinitrogen monoxide. may be oxidized to reduce oxygen vacancies.

[0139] The gate electrode 65 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or the like. A metal element selected from stainless steel, or an alloy containing the above-mentioned metal elements, or the above-mentioned alloys It can be formed by using an alloy of a combination of metal elements. The metal element may be selected from one or more of the following: The electrode 65 may have a single-layer structure or a laminated structure of two or more layers. Single-layer aluminum film structure, double-layer aluminum film with titanium film laminated on top, titanium nitride Two-layer structure with a titanium film laminated on a titanium nitride film, and two-layer structure with a tungsten film laminated on a titanium nitride film. The structure is a two-layer structure in which a tungsten film is laminated on a tantalum nitride film, and a titanium film and For example, a three-layer structure is available in which an aluminum film is laminated on top and a titanium film is further formed on top of that.

[0140] The gate electrode 65 is made of indium oxide, indium tin oxide, or indium oxide containing tungsten oxide. Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide , Indium tin oxide containing titanium oxide, Indium zinc oxide, silicon oxide added A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the light-transmitting conductive material and the metal element may also be used.

[0141] The insulating film 69 can be formed using any of the insulating films listed for the gate insulating film 63 as appropriate. In addition, a silicon nitride film formed by sputtering or CVD is used as the insulating film 69. When formed, it is possible to prevent the intrusion of moisture and alkali metals from the outside, and the crystalline The amount of impurities contained in the oxide semiconductor film can be reduced.

[0142] After the gate insulating film 63 or the insulating film 69 is formed, a heat treatment may be performed. By the heat treatment, oxygen is diffused from the gate insulating film 63 to the crystalline oxide semiconductor film. As a result, the higher the temperature of the heat treatment, the lower the threshold value of the BT test under light irradiation. The amount of change in the value is suppressed.

[0143] Through the above steps, a transistor 120 having a crystalline oxide semiconductor film in a channel region is manufactured. It can be made by forming a hexagonal lattice bond on the ab plane and ab plane. A crystalline oxide semiconductor having crystals with a hexagonal structure with a c-axis approximately perpendicular to the substrate plane approximately parallel to the substrate plane. The transistor 120 having a conductive film in the channel region has a threshold voltage before and after light irradiation and BT testing. Since the change in the value voltage is small, it is possible to fabricate a transistor with stable electrical characteristics. can be done.

[0144] (Embodiment 2) In this embodiment, a method for manufacturing a transistor having a structure different from that in Embodiment 1 will be described with reference to FIG. 6. In this embodiment, an oxide insulating film and a crystalline oxide semiconductor film The difference from the first embodiment is that a pair of electrodes is provided between the dashed and dotted lines CD and The cross-sectional view corresponds to FIG.

[0145] As shown in FIG. 5A, an oxide insulating film 53 is formed on a substrate 51 in the same manner as in the first embodiment. Next, a pair of electrodes 71 is formed on the oxide insulating film 53. A crystalline oxide semiconductor film 73 is formed over the oxide insulating film 53 .

[0146] The pair of electrodes 71 are formed of the same material and by the same method as the pair of electrodes 61 shown in the first embodiment. It can be formed using.

[0147] The crystalline oxide semiconductor film 73 is made of a material similar to that of the crystalline oxide semiconductor film 55 described in Embodiment 1. The material and manufacturing method can be appropriately used.

[0148] Next, the substrate 51 is heated in the same manner as in the first embodiment, and as a result, the hydrogen concentration and oxygen vacancies are reduced. After the formation of the crystalline oxide semiconductor film, a crystalline oxide semiconductor film having reduced hydrogen concentration and oxygen vacancies is formed. A mask is formed on the semiconductor film, and a crystalline oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced is selected. The crystalline oxide semiconductor film 75 is formed by selectively etching the crystalline oxide semiconductor film 75. After that, the mask is removed. (See FIG. 5(B)).

[0149] Next, as shown in FIG. 5C, a gate electrode is formed on the pair of electrodes 71 and the crystalline oxide semiconductor film 75. Next, a crystalline oxide semiconductor film 77 is formed on the gate insulating film 77. 5 to form a gate electrode 79. Next, An insulating film 81 may be formed as a protective film.

[0150] The gate insulating film 77 is formed using the same material and method as the gate insulating film 63 described in Embodiment 1. It can be formed by using appropriate materials.

[0151] The gate electrode 79 is formed of the same material and by the same method as the gate electrode 65 shown in the first embodiment. It can be formed using.

[0152] The insulating film 81 is formed using the same material and method as the insulating film 69 shown in Embodiment 1. It can be achieved.

[0153] Next, a mask is formed on the insulating film 81, and then the gate insulating film 77 and a part of the insulating film 81 are etched. Then, a pair of electrodes is connected through the contact holes. Wiring 83 is formed to connect to pole 71 .

[0154] The wiring 83 can be formed by appropriately using the same material and manufacturing method as the pair of electrodes 71. do.

[0155] Through the above steps, a transistor having a crystalline oxide semiconductor film in a channel region is manufactured. The bond on the ab plane has a hexagonal lattice, and the bond on the ab plane is roughly flat. A crystalline oxide semiconductor having a hexagonal crystal structure with its c-axis approximately perpendicular to the substrate plane. The transistors with a thin film in the channel region showed a change in threshold voltage before and after light irradiation and BT testing. Because the amount of change is small, it is possible to manufacture transistors with stable electrical characteristics. .

[0156] Note that this embodiment mode can be appropriately combined with other embodiment modes.

[0157] (Embodiment 3) In this embodiment, a transistor different from those in Embodiments 1 and 2 will be described with reference to FIG. 8. In this embodiment, a bottom gate electrode is provided on the substrate side. The difference from the first and second embodiments is that the transistor has a gate structure. The cross-sectional view taken along dashed line EF of FIG. 8 corresponds to FIG.

[0158] As shown in FIG. 7A, an oxide insulating film 53 is formed on a substrate 51. Next, an oxide insulating film 53 is formed on the substrate 51. A gate electrode 91 is formed on the oxide insulating film 53. Next, A gate insulating film 93 is formed. Next, a crystal is formed on the gate insulating film 93 in the same manner as in the first embodiment. Then, a conductive oxide semiconductor film 95 is formed.

[0159] The gate electrode 91 can be formed in a manner similar to that of the gate electrode 65 shown in the first embodiment.

[0160] The gate insulating film 93 can be formed in a manner similar to that of the gate insulating film 63 described in Embodiment 1. do.

[0161] The crystalline oxide semiconductor film 95 has a shape similar to that of the crystalline oxide semiconductor film 55 described in Embodiment 1. It can be achieved.

[0162] Next, in a manner similar to that of Embodiment 1, the crystalline oxide semiconductor film 95 is heated to determine the concentration of hydrogen and oxygen. A crystalline oxide semiconductor film in which defects are reduced is formed.

[0163] Next, a mask is formed over the crystalline oxide semiconductor film in which the hydrogen concentration and the oxygen vacancy are reduced, The crystalline oxide semiconductor film in which the hydrogen concentration and the oxygen vacancy are reduced is selectively etched to form a crystalline oxide semiconductor film. A crystalline oxide semiconductor film 99 is formed. Then, the mask is removed (see FIG. 7B).

[0164] Next, as shown in FIG. 7C, a pair of electrodes 101 is formed on the crystalline oxide semiconductor film 99. Next, the insulating film 103 is formed over the crystalline oxide semiconductor film 99 and the pair of electrodes 101. do.

[0165] The pair of electrodes 101 is formed using the same material and method as the pair of electrodes 61 described in the first embodiment. It can be formed as desired.

[0166] The insulating film 103 can be formed in a manner similar to that of the gate insulating film 63 described in Embodiment 1.

[0167] After this, a heat treatment may be carried out.

[0168] Through the above steps, a transistor having a crystalline oxide semiconductor film in a channel region is manufactured. The bond on the ab plane has a hexagonal lattice, and the bond on the ab plane is roughly flat. A crystalline oxide semiconductor having a hexagonal crystal structure with its c-axis approximately perpendicular to the substrate plane. The transistors with a thin film in the channel region showed a change in threshold voltage before and after light irradiation and BT testing. Because the amount of change is small, it is possible to manufacture transistors with stable electrical characteristics. .

[0169] Note that this embodiment mode can be appropriately combined with other embodiment modes.

[0170] (Embodiment 4) In this embodiment mode, a bottom-gate transistor different from that in Embodiment 3 will be described with reference to FIG. 9 and 10. In this embodiment, the gate insulating film and the oxide semiconductor film The difference from the third embodiment is that a pair of electrodes is provided between the first and second electrodes. The cross-sectional view corresponds to FIG.

[0171] As shown in FIG. 9A, an oxide insulating film 53 is formed on a substrate 51. Next, an oxide insulating film 53 is formed on the substrate 51. A gate electrode 91 is formed on the oxide insulating film 53. Next, A gate insulating film 93 is formed. Next, a pair of electrodes 105 is formed on the gate insulating film 93. do.

[0172] The pair of electrodes 105 is formed using the same material and method as the pair of electrodes 61 described in the first embodiment. It can be formed as desired.

[0173] Next, as shown in FIG. 9B, a crystalline oxide film is formed on the gate insulating film 93 in the same manner as in the first embodiment. Then, a compound semiconductor film 107 is formed.

[0174] The crystalline oxide semiconductor film 107 is formed in the same manner as the crystalline oxide semiconductor film 55 described in Embodiment 1. It can be formed.

[0175] Next, in a manner similar to that of Embodiment 1, the crystalline oxide semiconductor film 107 is heated to measure the hydrogen concentration and the acid concentration. A crystalline oxide semiconductor film in which atomic vacancies are reduced is formed.

[0176] Next, a mask is formed over the crystalline oxide semiconductor film in which the hydrogen concentration and the oxygen vacancy are reduced, The crystalline oxide semiconductor film in which the hydrogen concentration and the oxygen vacancy are reduced is selectively etched to form a crystalline oxide semiconductor film. A crystalline oxide semiconductor film 109 is formed. Then, the mask is removed (see FIG. 9C).

[0177] Next, as shown in FIG. 9D, a A protective film 111 is formed.

[0178] The protective film 111 can be formed in a manner similar to that of the gate insulating film 63 described in the first embodiment.

[0179] After this, a heat treatment may be carried out.

[0180] Through the above steps, a transistor having a crystalline oxide semiconductor film in a channel region is manufactured. The bond on the ab plane has a hexagonal lattice, and the bond on the ab plane is roughly flat. A crystalline oxide semiconductor having a hexagonal crystal structure with its c-axis approximately perpendicular to the substrate plane. The transistors with a thin film in the channel region showed a change in threshold voltage before and after light irradiation and BT testing. Because the amount of change is small, it is possible to manufacture transistors with stable electrical characteristics. .

[0181] Note that this embodiment mode can be appropriately combined with other embodiment modes.

[0182] (Embodiment 5) In this embodiment, the semiconductor device having a plurality of gate electrodes in any of the first to fourth embodiments is A transistor will be described. Here, the transistor described in Embodiment 3 will be used. It will be apparent that the present invention can be applied to the first, second and fourth embodiments as appropriate.

[0183] As in the third embodiment, as shown in FIG. 11, an oxide insulating film 53 is formed on a substrate 51. A gate electrode 91 and a gate insulating film 93 are formed on the oxide insulating film 53. A crystalline oxide semiconductor film 99, a pair of electrodes 101, and an insulating film 103 are formed thereover.

[0184] Next, a back gate electrode is formed over the insulating film 103 and overlaps with the crystalline oxide semiconductor film 99. Next, a protective film is formed on the insulating film 103 and the back gate electrode 113. A border membrane 115 may be formed.

[0185] The back gate electrode 113 may be formed in the same manner as the gate electrode 65 shown in the first embodiment. can.

[0186] The insulating film 103 functions as a gate insulating film on the back gate electrode 113 side. The insulating film 5 can be formed in a similar manner to the insulating film 69 shown in the first embodiment.

[0187] The gate electrode 91 and the back gate electrode 113 may be connected. Since the electrode 91 and the back gate electrode 113 have the same potential, the channel region is a crystalline oxide. Since the semiconductor film 99 is formed on the gate insulating film 93 side and the insulating film 103 side, The on-state current and field effect mobility of the semiconductor device can be improved.

[0188] Alternatively, the gate electrode 91 and the back gate electrode 113 are not connected and different potentials are applied to them. In this case, the threshold voltage of the transistor can be controlled.

[0189] In this embodiment, the pair of electrodes 101 is formed by the crystalline oxide semiconductor film 99 and the insulating film 10. 3, it may be formed between the gate insulating film 93 and the crystalline oxide semiconductor film 99. good.

[0190] Through the above steps, a transistor having a plurality of gate electrodes can be manufactured.

[0191] (Embodiment 6) In this embodiment, compared with Embodiments 1 to 5, a crystalline oxide semiconductor film and A method for manufacturing a transistor in which the contact resistance between a pair of electrodes can be reduced will be described.

[0192] As in the first embodiment, a semiconductor layer is formed on the oxide insulating film 53 by the steps shown in FIGS. The crystalline oxide semiconductor film 55 is formed. Next, the crystalline oxide semiconductor film 55 is heated to remove hydrogen. A crystalline oxide semiconductor film in which the concentration and oxygen vacancies are reduced is formed. As shown in FIG. 1, an n-type crystalline oxide semiconductor film 57 having a reduced hydrogen concentration and oxygen vacancy is formed on the crystalline oxide semiconductor film 57. A buffer 84 having a conductivity type is formed.

[0193] The buffer 84 having an n-type conductivity may be made of indium oxide, indium tin oxide, A metal oxide selected from indium zinc oxide, tin oxide, zinc oxide, and tin zinc oxide. or the metal oxide is a compound selected from the group consisting of aluminum, gallium, and silicon. This allows the use of a material that contains one or more elements. a pair of electrodes functioning as a source electrode and a drain electrode, and a crystalline oxide semiconductor film The contact resistance can be reduced.

[0194] Here, the crystalline oxide semiconductor film is heated to release hydrogen from the crystalline oxide semiconductor film. At the same time, oxygen is diffused from the oxide insulating film to the crystalline oxide semiconductor film, and then the crystalline oxide semiconductor film is In order to form a buffer 84 having an n-type conductivity on the semiconductor film, a crystalline oxide semiconductor Hydrogen can be sufficiently released from the film. It is possible to reduce the concentration of oxygen and oxygen vacancies, and the threshold voltage of the transistor is reduced. The shift can be reduced.

[0195] Next, a mask is formed on the buffer 84 having n-type conductivity, and then the hydrogen concentration and oxygen deficiency are measured. The crystalline oxide semiconductor film with reduced loss and the buffer 84 having n-type conductivity are etched. As a result, a crystalline oxide semiconductor film 59 and a buffer 85 having n-type conductivity are formed. After that, the mask is removed (see FIG. 12(B)).

[0196] Next, as shown in FIG. 12C, a crystalline oxide semiconductor film 59 and an n-type A pair of electrodes 61 are formed on the buffer 85. In this case, in order to maintain the quality of the gate insulating film, For the pair of electrodes 61, it is preferable to use a material that does not extract oxygen from the gate insulating film. The pair of electrodes 61 may be made of a material such as tungsten or molybdenum. However, tungsten and molybdenum are not suitable for use in a crystalline oxide semiconductor film and a gate insulating film. In the contact area, a highly resistive metal oxide is formed. By providing a buffer having an n-type conductivity between the conductive film 59 and the pair of electrodes 61, The contact resistance between the crystalline oxide semiconductor film 59 and the pair of electrodes 61 can be reduced.

[0197] Next, a mask (not shown) is formed on the pair of electrodes 61 to provide n-type conductivity. The exposed portion of the buffer 85 is etched to form a pair of n-type buffers 87. (See FIG. 12(D)).

[0198] After removing the mask formed on the pair of electrodes 61, the pair of electrodes 61 was used as a mask to Then, the exposed portion of the buffer 85 having n-type conductivity is etched to form a pair of n-type A buffer 87 having the following structure may be formed.

[0199] When the buffer 85 having n-type conductivity is etched, the crystalline oxide semiconductor film 59 The condition under which the buffer 85 having n-type conductivity is selectively etched without being etched. It is preferable to use a condition in which the etching selectivity is high. When the etching selectivity of the buffer 85 having n-type conductivity and the buffer 59 having n-type conductivity is low, When etching the buffer 85 having the electrolytic type, a part of the crystalline oxide semiconductor film 59 is also etched. The surface may be molded to have a groove (recess).

[0200] According to this embodiment, an n-type conductivity type is formed between the crystalline oxide semiconductor film 59 and the pair of electrodes 61. Since the buffer 87 having the above structure is provided, the crystalline oxide semiconductor film 59 and the pair of electrodes 61 can be connected to each other. As a result, the reduction in the on-current of the transistor can be suppressed. In addition, the BT test can measure the on-state current before and after applying negative gate bias stress. This can suppress the change in the on current (Ion deterioration).

[0201] Next, in the same manner as in the first embodiment, a gate insulating film 63, a gate electrode 65, and an insulating film 69 are formed. (See FIG. 12E). In addition, contact holes are formed in the gate insulating film 63 and the insulating film 69. After the formation of the hole, wiring connected to the pair of electrodes 61 may be formed.

[0202] Through the above steps, a transistor having a crystalline oxide semiconductor film in a channel formation region is manufactured. It can be manufactured.

[0203] According to this embodiment, an n-type conductive film that reduces contact resistance between an oxide semiconductor film and a pair of wirings is formed. In order to form a buffer having an electric type, the reduction in the on-state current of the transistor is suppressed, and The change in on-current before and after applying negative gate bias stress in the BT test ( Ion degradation can be suppressed.

[0204] This embodiment mode can be freely combined with other embodiment modes.

[0205] (Embodiment 7) In this embodiment, the heat treatment is performed after the formation of the oxide insulating film 53 described in Embodiment 1. The process up to the formation of the conductive film that will become the source electrode or drain electrode is performed without exposure to air. An example of a manufacturing device that can perform this process continuously is shown in FIG.

[0206] The manufacturing apparatus shown in FIG. 13 is a single-wafer multi-chamber apparatus, and has three sputtering apparatuses 10. a, 10b, 10c, a substrate supply chamber having three cassette ports 14 for accommodating substrates to be processed The system includes load lock chambers 11, 12a and 12b, a transfer chamber 13, a substrate heating chamber 15, etc. In addition, the substrate supply chamber 11 and the transfer chamber 13 are provided with a transfer robot for transferring the substrate to be processed. The sputtering devices 10a, 10b, and 10c, the transfer chamber 13, and the substrate The heating chamber 15 is provided with an atmosphere containing almost no hydrogen or moisture (an inert atmosphere, a reduced pressure atmosphere, a dry atmosphere, etc.). It is preferable to control the temperature under a dew point of -40°C. Hereinafter, a dry nitrogen atmosphere with a dew point of -50°C or less is preferably used.

[0207] In one example of a manufacturing process using the manufacturing apparatus of FIG. 13, a substrate to be processed is first fed from the substrate supply chamber 11. The plate is transported through the load lock chamber 12a and the transport chamber 13 to the substrate heating chamber 15. In the heating chamber 15, moisture adhering to the substrate is removed by heat treatment in a vacuum atmosphere, and then Thereafter, the substrate is transferred to the sputtering device 10c via the transfer chamber 13, and The oxide insulating film 53 is formed in the wafer transport device 10c without being exposed to the air. The substrate to be processed is transferred to the sputtering device 10a via the chamber 13. In the 0a region, zinc is preferentially deposited on the oxide insulating film 53, and then oxidized to form a zinc-containing hexagonal A seed crystal 55a having a crystal with a crystal structure is formed, and then the seed crystal 55a is sputtered in the same sputtering apparatus. By sputtering, a crystal is grown using the seed crystal 55a as a nucleus. The crystalline oxide semiconductor film 55b having a crystal structure is formed. The substrate is transferred to the substrate heating chamber 15 via the transfer chamber 13 and then heated. The substrate to be processed is then transported through the transport chamber 13 to the sputtering device 10b without being exposed to the atmosphere. The source electrode and the drain electrode are formed by moving the sputtering device 10b using a metal target. A conductive film for forming a rain electrode is formed over the crystalline oxide semiconductor film 55b.

[0208] In this way, by using the manufacturing apparatus of FIG. 13, the transistor can be manufactured without being exposed to the atmosphere. This allows for some advances in the data fabrication process.

[0209] This embodiment mode can be freely combined with other embodiment modes.

[0210] (Embodiment 8) In this embodiment, the transistor including an oxide semiconductor described in any of Embodiments 1 to 7 is used. It is possible to retain memory contents even when power is not supplied, and there is no limit to the number of times it can be written to. An example of a semiconductor device having a new structure without the above will be described.

[0211] The transistors including an oxide semiconductor described in any of Embodiments 1 to 7 have extremely low off-state current. Therefore, it is possible to retain memory contents for an extremely long period of time by using this. In other words, refresh operations are not required or the frequency of refresh operations is extremely low. Since the power consumption can be reduced by a small amount, the power consumption can be reduced sufficiently. Even if there is no power supply, the stored contents can be retained for a long period of time.

[0212] FIG. 14 shows an example of the configuration of a semiconductor device. FIG. 14(A) shows a cross section of the semiconductor device. 14(B) shows a plan view of the semiconductor device. This corresponds to the cross sections taken along lines E1-E2 and F1-F2 in FIG. 14(A) and FIG. 1(B). The semiconductor device shown in FIG. 4(B) includes a transistor 26 using a material other than an oxide semiconductor in the lower portion. 0 and a transistor 120 using an oxide semiconductor therein. Since the resistor 120 is the same as that in the first embodiment, in Figs. The same parts as those in FIG. 1(E) will be described using the same reference numerals.

[0213] The transistor 260 is disposed on a substrate 200 that includes a semiconductor material (such as silicon). A channel forming region 216 is formed by arranging impurity Region 214 and high-concentration impurity region 220 (collectively referred to as "impurity region"). a gate insulating film 208 provided on the channel forming region 216; A gate electrode 210 is provided on the semiconductor substrate 200, and a source electrode or drain electrode is provided on the semiconductor substrate 200. The source electrode or drain electrode is electrically connected to the impurity region. The pixel has a drain electrode 230a and a source or drain electrode 230b.

[0214] Here, a sidewall insulating film 218 is provided on the side surface of the gate electrode 210. In addition, the sidewall insulating film 218 does not overlap the substrate 200 when viewed from a direction perpendicular to the surface of the substrate 200. The region has a high-concentration impurity region 220, and a metal compound A region 224 is formed on the substrate 200. The region 224 surrounds the transistor 260. A separation insulating film 206 is provided, and an interlayer insulating film 226 is provided to cover the transistor 260. and an interlayer insulating film 128. and the source electrode or drain electrode 230b are formed by the interlayer insulating film 226 and the interlayer insulating film 12 8, the metal compound region 224 is electrically connected to the metal compound region 224. , source or drain electrode 230a, and source or drain electrode 230 b is connected to the high concentration impurity region 220 and the impurity region 214 via the metal compound region 224 In addition, in order to integrate the transistor 260, In some cases, the insulating film 218 is not formed.

[0215] The transistor 120 shown in FIG. 14 includes a crystalline oxide semiconductor film 59, a source electrode or a drain electrode, The gate electrode includes a pair of electrodes 61 that function as gate electrodes, a gate insulating film 63, and a gate electrode 65. The transistor 120 can be obtained by the process shown in the first embodiment.

[0216] In FIG. 14, the flatness of the interlayer insulating film 128 on which the crystalline oxide semiconductor film 59 is to be formed is By increasing the thickness of the crystalline oxide semiconductor film 59, the thickness distribution of the crystalline oxide semiconductor film 59 can be made uniform. The characteristics of the transistor 120 can be improved. However, the channel length is short. The thickness of the interlayer insulating film 128 is, for example, 0.8 μm or 3 μm. and are made of the same material.

[0217] 14. The capacitor 265 shown in FIG. 14 has one of a pair of electrodes 61 and a The gate insulating film 63 and the electrode 248 form a capacitance.

[0218] In addition, an insulating film 69 is provided over the transistor 120 and the capacitor 265. A protective insulating film 110 is provided on the insulating film 69 .

[0219] In addition, wirings 242a and 242b are provided which are formed in the same process as the pair of electrodes 61. The wiring 242a is electrically connected to the source or drain electrode 230a. 2b is electrically connected to the source or drain electrode 230b.

[0220] FIG. 14C shows a circuit configuration. Note that in the circuit diagram, To indicate that it is a transistor, the symbol OS may also be added.

[0221] In FIG. 14C, the first wiring (1st Line) and the source of the transistor 260 The electrodes are electrically connected to the second wiring (2nd Line) and the transistor 260. The drain electrode is electrically connected. Also, the third wiring (3rd Line) The source electrode or the drain electrode of the transistor 120 is electrically connected to the The fourth line and the gate electrode of the transistor 120 are electrically connected. The gate electrode of the transistor 260 and the source The other of the drain electrode and the drain electrode is electrically connected to one of the electrodes of the capacitor 265. The fifth line and the other electrode of the capacitor element 265 are electrically connected. do.

[0222] In the semiconductor device shown in FIG. 14C, the potential of the gate electrode of the transistor 260 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows: .

[0223] First, the writing and holding of information will be explained. The transistor 120 is turned on by applying a potential that turns the transistor 120 on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 260 and the That is, a predetermined charge is applied to the gate electrode of the transistor 260. Here, the charge that gives two different potential levels (hereafter, Low level) is Then, a fourth charge (called a low-level charge or a high-level charge) is applied. The potential of the wiring is set to a potential at which the transistor 120 is turned off. By turning off the transistor 260, the charge applied to the gate electrode of the transistor 260 is held. will be held (retained).

[0224] The off-state current of the transistor 120 is extremely small, specifically, the off-state current at room temperature ( is the value per unit channel width (1 μm)) is 100zA / μm (1zA (zeptoampere A) is 1 x 10 -21 A) or less, preferably 10zA / μm or less, so The charge in the gate electrode of the transistor 260 is held for a long time. A back gate electrode may be provided as shown in FIG. 1, and a voltage is applied to the back gate electrode. This preferably ensures that transistor 120 is normally off.

[0225] The substrate 200 is a semiconductor substrate called silicon-on-insulator (SO Alternatively, a SOI substrate may be used as the substrate 200. A substrate having an SOI layer formed on a glass substrate may be used. For example, a thin single-crystal silicon layer is formed on a glass substrate using hydrogen ion implantation delamination. Specifically, an ion doping device is used to + By irradiating A glass substrate having an insulating film on its surface, and a separation layer formed at a predetermined depth from the surface of the silicon substrate. The material is pressed against the surface of the silicon substrate and adhered to it, and separation is performed within the separation layer or at the interface. The heat treatment is performed at a temperature below the temperature at which the separation layer becomes weak. A part of the semiconductor substrate is separated from the silicon substrate at a layer or an interface, and then the glass substrate is An SOI layer is formed on the substrate.

[0226] This embodiment can be combined with any one of the first to seventh embodiments.

[0227] (Embodiment 9) In this embodiment, at least a part of the driver circuit and a transistor disposed in the pixel portion are formed on the same substrate. An example of how to fabricate a transistor is described below.

[0228] The transistor disposed in the pixel portion is formed according to any one of the first to seventh embodiments. In addition, since the transistors described in any of the embodiments 1 to 7 are n-channel TFTs, A part of the driver circuit that can be configured with n-channel TFTs is The transistor is formed on the same substrate.

[0229] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 includes a signal line driver circuit 5303 and a signal line driver circuit 5304. are arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in a first scanning line driver circuit The scanning lines and the signal line driver circuit 5303 are arranged. At the intersections with the lines, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is a flexible printed circuit board (FPC). It is connected to a timing control circuit (also called a controller or control IC) through a connection such as Connected.

[0230] In FIG. 15A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of external components such as drive circuits, and therefore reduces costs. In addition, when a driving circuit is provided outside the substrate 5300, it becomes necessary to extend the wiring, and the wiring The number of connections increases. If a driver circuit is provided on the same board 5300, the number of connections between the wiring can be reduced. This can reduce the amount of damage, thereby improving reliability and yield.

[0231] An example of the circuit configuration of the pixel section is shown in FIG. 15(B). Here, a VA type liquid crystal display panel 4 shows the pixel structure.

[0232] This pixel structure has multiple pixel electrodes in one pixel, and each pixel electrode has a transistor. Each transistor is configured to be driven by a different gate signal. That is, in a pixel with a multi-domain design, the voltage applied to each pixel electrode is The signal is independently controlled.

[0233] The gate wiring 602 of the transistor 628 and the gate wiring 603 of the transistor 629 are , are separated so that different gate signals can be applied. On the other hand, The functioning source or drain electrode 616 is connected to transistor 628 and transistor 62 9. Transistor 628 and transistor 629 are the same as those in the first embodiment. Any one of the transistors described above can be used as appropriate.

[0234] A first pixel electrode electrically connected to the transistor 628 and a second pixel electrode electrically connected to the transistor 629 The second pixel electrode, which connects to V, has a different shape and is separated by a slit. The second pixel electrode is formed so as to surround the outside of the first pixel electrode that extends in a U-shape. The timing of the voltages applied to the first pixel electrode and the second pixel electrode is controlled by the transistor 628 and the transistor The alignment of the liquid crystal is controlled by changing the polarity of the transistor 629. 28 is connected to the gate wiring 602, and the transistor 629 is connected to the gate wiring 603. By applying different gate signals to the gate wiring 602 and the gate wiring 603, the transistor The operation timing of the transistor 628 and the transistor 629 can be made different.

[0235] In addition, a capacitance wiring 690, a gate insulating film functioning as a dielectric, and a first pixel electrode or A storage capacitor is formed by the second pixel electrode and a capacitor electrode electrically connected thereto.

[0236] The first pixel electrode, the liquid crystal layer, and the counter electrode are overlapped to form a first liquid crystal element 651. In addition, the second pixel electrode, the liquid crystal layer, and the counter electrode are overlapped, so that the second liquid crystal pixel A first liquid crystal element 651 and a second liquid crystal element 652 are formed in one pixel. 2 is a multi-domain structure.

[0237] Note that the pixel configuration shown in FIG. 15(B) is not limited to this. The pixels are now equipped with new switches, resistors, capacitors, transistors, sensors, logic circuits, etc. Any of the above may be added.

[0238] An example of the circuit configuration of the pixel section is shown in FIG. 15(C). 2 shows a pixel structure of a display panel.

[0239] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0240] FIG. 15C shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. FIG.

[0241] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The figure shows an n-channel transistor that uses an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0242] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, The switching transistor 64 has a light emitting element 6404 and a capacitor element 6403. 01, the gate electrode is connected to the scanning line 6406, and the first electrode (the source electrode and the drain electrode) is connected to the scanning line 6406. The second electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405. ) is connected to the gate electrode of the driving transistor 6402. 402, the gate electrode is connected to the power supply line 6407 via the capacitance element 6403, and the first electrode The first electrode is connected to a power line 6407, and the second electrode is connected to a first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. 408 is electrically connected to a common potential line formed on the same substrate.

[0243] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0244] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to set the gate capacitance of the driving transistor 6402 as A capacitance may be formed between the region and the gate electrode.

[0245] In the case of a voltage input voltage driving method, the gate electrode of the driving transistor 6402 is In this case, the driving transistor 6402 is in two states, either fully on or off. In other words, the driving transistor 6402 is operated in a linear region. In order to operate the driving transistor 6402 in a linear region, the voltage of the power supply line 6407 is higher than that of the driving transistor 6402. A voltage higher than the voltage at the gate electrode of the driving transistor 6402 is applied to the gate electrode of the driving transistor 6402. A voltage equal to or higher than (power supply line voltage+Vth of driving transistor 6402) is applied to 5.

[0246] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 15(C) can be used.

[0247] When analog gradation driving is performed, the gate electrode of the driving transistor 6402 is connected to the light emitting element 64 A voltage equal to or higher than the forward voltage of 04 plus the Vth of the driving transistor 6402 is applied. The forward voltage of 6404 refers to the voltage required to achieve the desired brightness. Incidentally, the driving transistor 6402 is designed to operate in the saturation region. By inputting a video signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is set to The gate potential of the transistor 6402 is set higher than that of the transistor 6403. Analog gray scale driving can be performed by passing a current according to a video signal through the element 6404 .

[0248] Note that the pixel configuration shown in FIG. 15C is not limited to this. The pixels are now equipped with new switches, resistors, capacitors, sensors, transistors, logic circuits, etc. may be added.

[0249] (Embodiment 10) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), ), portable game machines, personal digital assistants, audio playback devices, pachinko machines and other large game machines, etc. Examples of electronic devices including the semiconductor device described in the above embodiment will be described. Reveal.

[0250] FIG. 16A shows a portable information terminal, which includes a main body 3001, a housing 3002, a display unit 300 The display unit 3003b is a touch panel. The screen can be operated by touching keyboard buttons 3004 displayed on the display unit 3003b. Of course, the display unit 3003a can be configured as a touch panel. The transistor described in Embodiment 1 may be used as a switching element in a liquid crystal panel or By fabricating an organic light-emitting panel and applying it to the display units 3003a and 3003b, reliability is improved. It can be a highly portable information terminal.

[0251] Figure 16(A) shows a function to display various information (still images, videos, text images, etc.), The function to display the date, time, etc. on the display unit, and to operate or edit the information displayed on the display unit It has the function of collecting information, controlling processing by various software (programs), etc. In addition, there are external connection terminals (earphone terminal, USB terminal) on the back and sides of the housing. The configuration may include a recording medium insertion portion, etc.

[0252] The portable information terminal shown in FIG. 16(A) can also be configured to transmit and receive information wirelessly. You can wirelessly purchase and download the desired book data from the electronic book server. It is also possible to configure it in this way.

[0253] FIG. 16B shows a portable music player. The main body 3021 has a display unit 3023 and a A fixing part 3022 for mounting, a speaker, an operation button 3024, and an external memory slot The transistor described in the first embodiment is used as a switching element. By using the same to manufacture a liquid crystal panel or an organic light-emitting panel and applying it to the display unit 3023, It can be a highly reliable portable music player.

[0254] Furthermore, the portable music player shown in FIG. 16(B) has an antenna, a microphone function, and a wireless function. In addition, by linking it with a mobile phone, you can enjoy wireless hands-free driving while driving a passenger car. Conversation by telephone is also possible.

[0255] FIG. 16C shows a mobile phone, which is composed of two housings, a housing 2800 and a housing 2801. The housing 2801 includes a display panel 2802, a speaker 2803, a microphone, and a 2804, pointing device 2806, camera lens 2807, external connection terminal The housing 2800 also includes a solar panel for charging the portable information terminal. It is equipped with a battery cell 2810, an external memory slot 2811, etc. The transistor described in Embodiment 1 is incorporated in the display panel 28 By applying this to 02, it will be possible to create a highly reliable mobile phone.

[0256] The display panel 2802 is equipped with a touch panel, and in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also implements a boost circuit to boost the input voltage to the voltage required for each circuit.

[0257] For example, the power transistor used in a power supply circuit such as a booster circuit is also shown in the first embodiment. The thickness of the crystalline oxide semiconductor film 59 of the transistor 120 is set to 2 μm or more and 50 μm or less. It can be formed by

[0258] The display direction of the display panel 2802 changes appropriately depending on the usage mode. Since it has a camera lens 2807 on the same surface as 2802, video telephony is possible. The speaker 2803 and the microphone 2804 are not limited to voice calls, but can also be used for video calls, Recording and playback are possible. Furthermore, the housing 2800 and the housing 2801 can be slid. As shown in 16(C), the device can be folded from the unfolded state to the overlapped state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0259] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. A recording medium can be inserted into the memory slot 2811 to accommodate larger amounts of data storage and transfer. do.

[0260] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0261] FIG. 16D shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In addition, the CPU is mounted on the stand 9605, which is also a housing. The transistor described in Embodiment 1 is used to support the display portion 96 03, a highly reliable television device 9600 can be obtained. .

[0262] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. The remote control can also be operated by the remote control. A display unit for displaying the output information may be provided.

[0263] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0264] The television device 9600 also includes an external connection terminal 9604 and a storage medium playback / recording unit 96 02, external memory slot. The external connection terminal 9604 is for connecting USB cables, etc. It can be connected to various cables, enabling data communication with a personal computer, etc. In the storage medium playback / recording unit 9602, a disk-shaped recording medium is inserted and recorded on the recording medium. It is possible to read data stored in the external memory and write data to the recording medium. Displays images and videos stored in the external memory 9606 inserted in the slot. It is also possible to display it on the display unit 9603.

[0265] In addition, the semiconductor device shown in the eighth embodiment can be applied to the external memory 9606 and the CPU. As a result, the television device 9600 can be highly reliable and consumes less power. can. [Explanation of symbols]

[0266] 11 Substrate supply room 13 Transport Room 14 Cassette port 15 Substrate heating chamber 31 Processing Room 33 Exhaust means 35 Gas supply means 37 Power supply 40 Substrate support 41 Target 43 Aeon 51 Substrate 53 Oxide insulating film 55 Crystalline oxide semiconductor film 57 Crystalline oxide semiconductor film 59 Crystalline oxide semiconductor film 61 Electrode 63 Gate insulating film 65 Gate electrode 69 Insulating Film 71 Electrode 73 Crystalline oxide semiconductor film 75 Crystalline oxide semiconductor film 77 Gate insulating film 79 Gate electrode 81 Insulating film 83 Wiring 84 Buffers 85 Buffer 87 Buffer 91 Gate electrode 93 Gate insulating film 95 Crystalline oxide semiconductor film 99 Crystalline oxide semiconductor film 101 Electrode 103 Insulating film 105 Electrode 107 Crystalline oxide semiconductor film 109 Crystalline oxide semiconductor film 10a Sputtering equipment 10b Sputtering equipment 10c Sputtering equipment 110 Protective insulating film 111 Protective film 113 Backgate electrode 115 Insulating film 120 Transistor 128 Interlayer insulating film 12a Load lock chamber 200 boards 206 Element isolation insulating film 208 Gate insulating film 210 Gate electrode 214 Impurity region 216 Channel formation region 218 Sidewall insulating film 220 High concentration impurity region 224 Metal compound area 226 Interlayer insulating film 248 Electrode 260 Transistors 265 Capacitive Element 55a seed crystal 55b Crystalline oxide semiconductor film 602 Gate wiring 603 Gate wiring 616 Source or drain electrode 628 Transistor 629 Transistor 651 Liquid crystal element 652 Liquid crystal element 690 Capacitance wiring 230a source electrode or drain electrode 230b source electrode or drain electrode 242a Wiring 242b Wiring 2800 Chassis 2801 Case 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 Solar Cell 2811 External memory slot 3001 Main unit 3002 Case 3004 Keyboard Buttons 3021 Main unit 3022 Fixed part 3023 Display section 3024 Operation button 3025 External Memory Slot 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 6400 pixels 6401 Switching transistor 6402 Driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common electrode 9600 Television Equipment 9601 Case 9602 Storage media playback and recording unit 9603 Display section 9604 External connection terminal 9605 Stand 9606 External Memory 3003a Display section 3003b Display section

Claims

1. a first transistor having silicon in a channel formation region; a second transistor having an oxide semiconductor in a channel formation region, a gate electrode of the first transistor and one of a source electrode and a drain electrode of the second transistor are electrically connected to each other, a first insulating layer located above a channel formation region of the first transistor; a first conductive layer located above the first insulating layer and having a region that functions as a gate electrode of the first transistor; a second insulating layer located above the first conductive layer and having a region that functions as a gate insulating layer of the second transistor; an oxide semiconductor layer having a region in contact with a lower surface of the second insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the first conductive layer and having a region functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive layer located above the second conductive layer and having an area overlapping the second conductive layer; a channel length direction of the first transistor and a channel length direction of the second transistor intersect with each other, the first conductive layer contacts the second conductive layer in a first region; a channel formation region of the first transistor does not overlap with the first region.

2. a first transistor having silicon in a channel formation region; a second transistor having an oxide semiconductor in a channel formation region, a gate electrode of the first transistor and one of a source electrode and a drain electrode of the second transistor are electrically connected to each other, a first insulating layer located above a channel formation region of the first transistor; a first conductive layer located above the first insulating layer and having a region that functions as a gate electrode of the first transistor; a second insulating layer located above the first conductive layer and having a region that functions as a gate insulating layer of the second transistor; an oxide semiconductor layer having a region in contact with a lower surface of the second insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the first conductive layer and having a region functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive layer located above the second conductive layer and having an area overlapping the second conductive layer; a third insulating layer having a region in contact with a lower surface of the second conductive layer; a fourth conductive layer having a region in contact with a top surface of the third insulating layer and functioning as one of a source electrode and a drain electrode of the first transistor; a channel length direction of the first transistor and a channel length direction of the second transistor intersect with each other, the first conductive layer contacts the second conductive layer in a first region; a channel formation region of the first transistor does not overlap with the first region; The second conductive layer and the fourth conductive layer have the same material.

Images