Multilayer structure and semiconductor device

Abstract

Provided are a multilayer structure and a semiconductor device in which electrical characteristics are stable from the surface of the semiconductor layer to deep regions thereof. The present disclosure provides a multilayer structure comprising a first semiconductor layer and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer include a crystalline oxide containing gallium. The second semiconductor layer is disposed on the first semiconductor layer directly or via another layer. The lower limit of the carrier density at a depth of 1.0 μm or more from the surface of the second semiconductor layer is at least half of the carrier density at a depth of 1.0 μm from the surface.

Description

Multilayer body and semiconductor device

[0001] The present disclosure relates to a multilayer body including a first semiconductor layer and a second semiconductor layer, and a semiconductor device.

[0002] Non-Patent Document 1 describes a stacked n － Type α-Ga ２ O ３ Crystal layer and n ＋ Type α-Ga ２ O ３ The electrical characteristics of a Schottky diode formed by providing a Schottky electrode and an ohmic electrode on a crystal layer are disclosed. － Type α-Ga ２ O ３ The donor concentration is 8×10 at a depth of 0.1 μm to 0.4 μm from the Schottky electrode in the crystal layer. １６ cm -３ The trap level densities at energy levels of 2.0 eV, 2.5 eV, and 3.2 eV from the bottom of the conduction band are approximately 3.5 × 10 １４ cm -３ , 3.6 × 10 １４ cm -３ , and 6.2 × 10 １５ cm -３ An example is disclosed in which

[0003] Hitoshi Takane et al, "Analysis of Deep Traps in Mist Chemical Vapor Deposition-Grown n-Type α-Ga2O3 by Photocapacitance Method" Phys. Status Solidi b 258, 2000622 (2021)

[0004] The electrical characteristics of a semiconductor device including a semiconductor layer (e.g., a power semiconductor such as a Schottky diode) generally change as the depth from the surface of the semiconductor layer increases. For this reason, it is preferable that the electrical characteristics are stable not only in a shallow region of about 0.1 μm to 0.4 μm from the surface of the semiconductor layer, but also in a deep region, for example, about 3 μm deep from the surface of the semiconductor layer.

[0005] An object of the present disclosure is to provide a multilayer body and a semiconductor device having stable electrical characteristics from the surface to a deep region of a semiconductor layer.

[0006] In order to solve the above problem, in one aspect of the present disclosure, a multilayer body includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer and the second semiconductor layer include a crystalline oxide containing gallium, the second semiconductor layer is disposed on the first semiconductor layer directly or via another layer, and a lower limit value of the carrier density at a depth of 1.0 μm or more from the surface of the second semiconductor layer is equal to or greater than half of the carrier density at a depth of 1.0 μm from the surface.

[0007] In order to solve the above-described problems, in one aspect of the present disclosure, a multilayer body includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer and the second semiconductor layer include a crystalline oxide containing gallium, the second semiconductor layer is disposed on the first semiconductor layer directly or via another layer, and has an electron trap level with an energy level of 2.3 to 4.1 eV from the lower limit of the conduction band, and the density of the electron trap level is 1.0 × 10 at a depth of 1.0 μm or more from the surface of the second semiconductor layer. １６ / cm ３ The following is the result.

[0008] In order to solve the above problem, in one aspect of the present disclosure, a semiconductor device includes an n-type semiconductor layer including a crystalline oxide semiconductor containing gallium, and an electrode, and exhibits a current reduction rate of 10% or less when operated under high-temperature reverse bias test conditions including application of an average electric field of 1 MV / cm for 6 minutes in an atmosphere of the maximum junction temperature (Tjmax).

[0009] In order to solve the above problem, in one aspect of the present disclosure, the second semiconductor layer in the multilayer body has a carrier density of 2.0 × 10 １６ / cm ３ That's all.

[0010] In order to solve the above problem, in one aspect of the present disclosure, a semiconductor device includes an n-type semiconductor layer including a crystalline oxide semiconductor containing gallium, and at least two electrodes connected to the n-type semiconductor layer, and exhibits a current reduction rate of 10% or less when operated under high-temperature reverse bias test conditions including a condition in which an average electric field of 1 MV / cm is applied to the electrodes for 6 minutes in an atmosphere of a maximum junction temperature (Tjmax).

[0011] In order to solve the above problem, in one aspect of the present disclosure, a semiconductor device includes an n-type semiconductor layer including a crystalline oxide semiconductor containing gallium, and at least two electrodes connected to the n-type semiconductor layer, and exhibits a carrier density reduction rate of 10% or less when operated under high-temperature reverse bias test conditions including a condition in which an average electric field of 1 MV / cm is applied to the electrodes for 6 minutes in an atmosphere of a maximum junction temperature (Tjmax).

[0012] In order to solve the above problem, in one aspect of the present disclosure, a semiconductor device includes an n-type semiconductor layer including a crystalline oxide semiconductor containing gallium, and at least two electrodes connected to the n-type semiconductor layer, and exhibits a current reduction rate of 30% or less when operated under high-temperature reverse bias test conditions including a condition in which a reverse bias of 0.8 times the maximum rated voltage is applied to the electrodes for 1000 hours in an atmosphere of a maximum junction temperature (Tjmax).

[0013] According to the present disclosure, it is possible to provide a multilayer body and a semiconductor device having stable electrical characteristics from the surface to the deep region of the semiconductor layer.

[0014] FIG. 1A is a perspective view schematically illustrating the overall configuration of a multilayer film 1 according to an embodiment of the present disclosure, and FIG. 1B is a cross-sectional view taken along the line A-A of FIG. 1A. It is a diagram illustrating a schematic configuration of a film-forming apparatus (mist CVD apparatus) 4 used in manufacturing the multilayer film 1. It is a flowchart illustrating an example of a manufacturing method of the multilayer film 1. FIG. 4A is a diagram illustrating a state in which a first crystal layer 2 is formed on a substrate 5, FIG. 4B is a diagram illustrating a state in which an uneven portion 21 is formed on the upper surface of the first crystal layer 2, and FIG. 4C is a diagram illustrating a state in which a second crystal layer 3 grows on the first crystal layer 2. It is a diagram illustrating a schematic configuration of a Schottky barrier diode (SBD) 6 formed using the multilayer film 1. It is a schematic cross-sectional view illustrating an example of a high electron mobility transistor (HEMT) according to an embodiment of the present disclosure. It is a schematic cross-sectional view illustrating an example of a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present disclosure. It is a schematic cross-sectional view illustrating an example of a junction field effect transistor (JFET) according to an embodiment of the present disclosure. FIG. 1 is a schematic cross-sectional view showing an example of an insulated gate bipolar transistor (IGBT) according to an embodiment of the present disclosure; FIG. 2 is a schematic cross-sectional view showing an example of a light emitting diode (LED) according to an embodiment of the present disclosure; FIG. 3 is a schematic cross-sectional view showing an example of a light emitting diode (LED) according to an embodiment of the present disclosure; FIG. 4 is a schematic cross-sectional view showing an example of a junction barrier Schottky diode (JBS) according to an embodiment of the present disclosure; FIG. 5 is a schematic cross-sectional view showing an example of a junction barrier Schottky diode (JBS) according to an embodiment of the present disclosure; FIG. 6 is a schematic cross-sectional view showing an example of a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present disclosure; FIG. 7 is a block configuration diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present disclosure; FIG. 8 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present disclosure;FIG. 19A is a graph showing the relationship between depth from the surface and carrier density, FIG. 19B is a graph showing the relationship between depth from the surface and carrier mobility (calculated values), FIG. 19C is a graph showing forward current-forward voltage characteristics, and FIG. 19D is a graph showing the correlation between carrier density and carrier mobility. FIGS. 20A to 20C are graphs showing the relationship between depth from the surface and carrier density for Samples A to C according to the example, respectively, and FIGS. 20D to 20F are graphs showing the relationship between depth from the surface and carrier density for Samples V to X according to the comparative example, respectively. These graphs are schematic diagrams showing changes in carrier density during the manufacturing process of a semiconductor device. FIG. 22A is a graph showing the current decline rate after a high-temperature reverse bias test (175°C, 350V, 6 minutes), and FIG. 22B is a graph showing the current decline rate after a high-temperature reverse bias test (175°C, 270V, 6 minutes). FIG. 23A is a graph showing the relationship between stress time and forward voltage drop Vf, and FIG. 23B is a graph showing the relationship between stress time and current decline rate. 24A and 24B are graphs showing the relationship between stress time and the variation in forward voltage drop Vf and the current decline rate ΔIf / If under reliability test conditions (175°C, 280V). FIGS. 25A and 25B show the carrier density distributions in the depth direction of Samples D and E according to the example, respectively, and FIGS. 25C and 25D show the forward current-forward voltage characteristics of Samples D and E according to the example. FIGS. 26A and 26B show the carrier density distributions in the depth direction of Samples Y and Z according to the comparative example, respectively, and FIGS. 26C and 26D show the forward current-forward voltage characteristics of Samples Y and Z according to the comparative example. FIG. 27 is a graph showing the change in carrier density upon irradiation with green light and UV radiation. FIG. 28A shows the distribution of trap level density in the depth direction, and FIG. 28B shows the distribution of trap rate in the depth direction.

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings, but the invention according to the claims is not limited to these embodiments. Furthermore, not all of the combinations of the configurations described in the embodiments are necessarily required to solve the problems. Furthermore, each configuration of the present disclosure is described to the extent that it does not interfere with the solution of the problems of the present disclosure. Note that identical components are designated by the same reference numerals to avoid redundant description.

[0016] Additionally, as will be apparent to those skilled in the art, features shown in the drawings are not necessarily drawn to scale, even if not otherwise stated herein. It should also be noted that one feature of one embodiment may be used in another embodiment. Descriptions of well-known elements and processing techniques may be omitted so as not to unnecessarily obscure the embodiments of the present disclosure. The examples used herein are merely intended to aid in the understanding of the present disclosure and further enable those skilled in the art to practice the embodiments of the present disclosure. Therefore, the embodiments and examples herein should not be construed as limiting the scope of the present disclosure, which is defined solely by the appended claims and applicable law.

[0017] Terms such as "first," "second," and the like are used to describe various elements used herein, but the elements are not limited by these terms. Terms such as first, second, and the like are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and a second element could be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any or all combinations of one or more of the listed items.

[0018] In the present disclosure, one side in a direction parallel to the thickness direction Z of the multilayer film (see FIG. 1 ) will be described as "upper" and the other side as "lower." In particular, "upper" and "lower" are defined by referring to the second crystal layer 3 side as viewed from the first crystal layer 2 of the multilayer film 1 in FIG. 1 as the upper side, and the first crystal layer 2 side as viewed from the second crystal layer 3 as the lower side. Of the two main surfaces of a layer, substrate, or other member, the upper surface will be described as the upper surface, and the lower surface will be described as the lower surface. These "upper" and "lower" directions are not limited to the direction of gravity or the mounting direction to a substrate or the like when mounting a semiconductor device. In addition, in the present disclosure, the direction perpendicular to the thickness direction Z of the multilayer film and in which the concave and convex portions extend will be described as the front-rear direction Y. In addition, in the present disclosure, the direction perpendicular to the thickness direction Z and the front-rear direction Y will be described as the left-right direction X. Note that although the present specification uses the term "top view," this may be rephrased as "planar view."

[0019] When an element, such as a layer, region, or substrate, is referred to as being "on" another element, it is understood that it can be directly on the other element, or intervening elements may be present. When an element is referred to as being "connected" or "coupled" to another element, it is understood that it can be directly connected or coupled to the other element, or intervening elements may be present.

[0020] The terms used herein are intended to describe particular embodiments only and are not intended to limit the disclosure. As used herein, the terms "comprise" and "include" refer to the presence of stated elements but do not exclude the presence of one or more other elements.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Terms used herein should be interpreted to have a meaning that is consistent with the meaning in the context of the present specification and the related art. Furthermore, unless defined herein, it should be understood that terms used herein should not be interpreted in an idealized or overly formal sense.

[0022] FIG. 1A is a perspective view schematically illustrating a general configuration of a multilayer film 1 according to an embodiment of the present disclosure, and FIG. 1B is a cross-sectional view taken along the line A-A in FIG. 1A. The multilayer film 1 includes at least a first crystal layer 2 (corresponding to a first semiconductor layer) and a second crystal layer 3 (corresponding to a second semiconductor layer). The multilayer film 1 is used, for example, as a semiconductor film in a semiconductor device or the like. For convenience of explanation, FIGS. 1A and 1B illustrate the multilayer film 1 in a rectangular parallelepiped shape. The illustrated multilayer film 1 may be, for example, a part of a disk-shaped multilayer film.

[0023] (First Crystalline Layer 2) The first crystal layer 2 is, for example, an n-type semiconductor layer. The first crystal layer 2 is, for example, an epitaxially grown film heteroepitaxially grown on a sapphire substrate. The first crystal layer 2 contains a crystalline oxide semiconductor as a main component. Note that a crystalline oxide semiconductor is an example of a crystalline oxide. The first crystal layer 2 may be a film grown via another layer, such as a buffer layer, provided on the sapphire substrate.

[0024] The crystalline oxide semiconductor contained in the first crystal layer 2 has a corundum structure. In this embodiment, the a-axis direction of the crystalline oxide semiconductor is along the left-right direction X, the c-axis direction is along the front-rear direction Y, and the m-axis direction is along the thickness direction Z. That is, the plane orientation of the main surface of the first crystal layer 2 is an m-plane in a region where the normal is along the thickness direction Z. Note that in the first embodiment, the left-right direction X may be referred to as the a-axis direction, the front-rear direction Y as the c-axis direction, and the thickness direction as the m-axis direction. Alternatively, the c-axis direction of the crystalline oxide semiconductor may be along the left-right direction X, and the a-axis direction may be along the front-rear direction Y. Alternatively, the c-axis direction and the a-axis direction of the crystalline oxide semiconductor may be tilted with respect to the left-right direction X and the front-rear direction Y within the upper surface.

[0025] The crystalline oxide semiconductor contained in the first crystal layer 2 contains gallium. The crystalline oxide semiconductor may be a metal oxide containing, in addition to gallium, for example, one or more metals selected from aluminum, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the embodiment of the present disclosure, the crystalline oxide semiconductor preferably further contains, in addition to gallium, at least one metal selected from aluminum and indium, and α-Ga ２ O ３ According to the present disclosure, for example, α-Ga, which is in a thermally metastable phase, ２ O ３ Even when the mixed crystal is used, a multilayer film with reduced dislocations can be obtained.

[0026] The term "main component" refers to, for example, a crystalline oxide semiconductor containing Ga. ２ O ３ In this case, the atomic ratio of gallium in all the metal elements in the first crystal layer 2 is 0.5 or more, and Ga is contained in the first crystal layer 2. ２ O ３ In the present disclosure, the atomic ratio of gallium to all metal elements in the first crystalline layer 2 is preferably 0.7 or more, and more preferably 0.9 or more. In this embodiment, the first crystalline layer 2 is single crystal, but may also be polycrystalline.

[0027] The carrier density of the first crystal layer 2 can be set appropriately by adjusting the doping amount. The first crystal layer 2 preferably contains a dopant. The dopant may be a known one. In an embodiment of the present disclosure, when the first crystal layer 2 is mainly composed of a crystalline oxide semiconductor containing gallium, suitable examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium. In an embodiment of the present disclosure, the n-type dopant is preferably Sn, Ge, or Si. The content of the dopant in the composition of the first crystal layer 2 is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic %. More specifically, the concentration of the dopant is typically about 1×10 １６ / cm ３ ~1 x 10 ２２ / cm ３ The dopant concentration may be, for example, about 1×10 １７ / cm ３ The following low concentrations may be used:

[0028] The first crystal layer 2 has an uneven portion 21 on its upper portion. The uneven portion 21 is composed of recesses 21a and protrusions 21b, and is arranged in the a-axis direction. The uneven portion 21 has a stripe shape and extends along the c-axis direction (front-back direction Y). The recesses 21a and protrusions 21b are adjacent to each other. Adjacent recesses 21a and protrusions 21b are continuous and equally spaced along the a-axis direction (left-right direction X).

[0029] The recess 21a is formed by, for example, subjecting the first crystal layer 2 to an etching process, selective epitaxial growth, or laser processing. In this case, the uneven portion 21 does not include other materials such as a mask, but is formed by processing the shape of the first crystal layer 2 itself. The recess 21a has multiple growth surfaces along which the second crystal layer 3 grows. In this embodiment, the recess 21a has a first growth surface 21aa, a second growth surface 21ab, and a third growth surface 21ac. The first growth surface 21aa and the second growth surface 21ab are lateral growth crystal growth surfaces, and the third growth surface 21ac is a vertical growth crystal growth surface.

[0030] The first growth surface 21aa and the second growth surface 21ab are planes extending in the front-rear direction Y and the thickness direction Z. The first growth surface 21aa and the second growth surface 21ab are, for example, a-planes. The third growth surface 21ac is a plane extending in the front-rear direction Y and the left-right direction X. The third growth surface 21ac is, for example, an m-plane. The third growth surface 21ac is located between the first growth surface 21aa and the second growth surface 21ab. The first growth surface 21aa is located to the left of the third growth surface 21ac, and the second growth surface 21ab is located to the right of the third growth surface 21ac. In the present disclosure, the first growth surface 21aa, the second growth surface 21ab, and the third growth surface 21ac are part of the upper part of the first crystal layer 2. In FIG. 1B, the points where the third growth surface 21ac and the first growth surface 21aa or the second growth surface 21ab are connected are shown as corners, but they may also have other shapes such as arcs.

[0031] The first growth surface 21aa and the second growth surface 21ab may each have an angle of 60 degrees or more with respect to the upper surface of the convex portion 21b. In this embodiment, the angles between the first growth surface 21aa and the second growth surface 21ab and the upper surface of the convex portion 21b are 90 degrees. The angles between the first growth surface 21aa and the second growth surface 21ab and the third growth surface 21ac are also 90 degrees. However, this is not limited to the configuration according to this embodiment.

[0032] (Second Crystal Layer 3) The second crystal layer 3 is, for example, an n-type semiconductor layer. The second crystal layer 3 is disposed directly on the first crystal layer 2. The second crystal layer 3 is in contact with the uneven portion 21 of the first crystal layer 2. The second crystal layer 3 has the same conductivity type as the first crystal layer 2. The second crystal layer 3 is, for example, an epitaxially grown film that is homoepitaxially grown on the first crystal layer 2. The second crystal layer 3 contains a crystalline oxide semiconductor as a main component. Note that the crystalline oxide semiconductor is an example of a crystalline oxide.

[0033] The crystalline oxide semiconductor contained in the second crystal layer 3 has a corundum structure. The crystalline oxide semiconductor has the same structure as the crystalline oxide semiconductor contained in the first crystal layer 2. In this embodiment, the a-axis direction of the crystalline oxide semiconductor contained in the second crystal layer 3 is along the left-right direction X. The c-axis direction of the crystalline oxide semiconductor is along the front-back direction Y. The m-axis direction of the crystalline oxide semiconductor is along the thickness direction Z. That is, the plane orientation of the main surface of the second crystal layer 3 is an m-plane in the region where the normal is along the thickness direction Z.

[0034] The crystalline oxide semiconductor contained in the second crystal layer 3 contains gallium. The crystalline oxide semiconductor may be a metal oxide containing, in addition to gallium, one or more metals selected from aluminum, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. The crystalline oxide semiconductor is preferably the same metal oxide as the crystalline oxide semiconductor contained in the first crystal layer 2. In an embodiment of the present disclosure, the crystalline oxide semiconductor contained in the second crystal layer 3 preferably contains, in addition to gallium, at least one metal selected from aluminum and indium, and α-Ga ２ O ３ According to the present disclosure, for example, α-Ga, which is in a thermally metastable phase, ２ O ３ Even when the mixed crystal is used, a multilayer film with reduced dislocations can be obtained.

[0035] The term "main component" refers to, for example, the crystalline oxide semiconductor containing Ga ２ O ３In this case, the atomic ratio of gallium in all the metal elements in the second crystal layer 3 is 0.5 or more, and Ga is contained in the second crystal layer 3. ２ O ３ In the present disclosure, the atomic ratio of gallium to all metal elements in the second crystalline layer 3 is preferably 0.7 or more, and more preferably 0.9 or more. In this embodiment, the second crystalline layer 3 is single crystal, but may be polycrystalline.

[0036] The carrier density of the second crystal layer 3 can be appropriately set by adjusting the doping amount. The carrier density of the second crystal layer 3 may be different from, but preferably similar to, the carrier density of the first crystal layer 2. The second crystal layer 3 preferably contains a dopant. The dopant may be a known dopant. The dopant may be different from, but preferably the same as, the dopant contained in the first crystal layer 2. In an embodiment of the present disclosure, when the second crystal layer 3 is mainly composed of a crystalline oxide semiconductor containing gallium, suitable examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium. In an embodiment of the present disclosure, the n-type dopant is preferably Sn, Ge, or Si. The content of the dopant in the composition of the second crystal layer 3 is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic %. More specifically, the concentration of the dopant is usually about 1×10 １６ / cm ３ ~1 x 10 ２２ / cm ３ The dopant concentration may be, for example, about 1×10 １７ / cm ３ The following low concentrations may be used:

[0037] 1B , the second crystal layer 3 has a lower portion 3 a bonded to the upper portion of the first crystal layer 2. The lower portion 3 a of the second crystal layer 3 has an uneven portion 31 having a shape corresponding to the uneven portion 21 of the upper portion of the first crystal layer 2. The uneven portion 31 is made up of a plurality of recesses 31 a and protrusions 31 b arranged in the a-axis direction, and has a striped shape. The uneven portion 31 of the second crystal layer 3 is in contact with the uneven portion 21 of the first crystal layer 2, and is also the interface between the second crystal layer 3 and the first crystal layer 2.

[0038] The recess 31 a is formed, for example, as a result of the formation of the protrusion 31 b. The internal space of the recess 31 a is filled with the protrusion 21 b. The second crystal layer 3 located above the recess 31 a is, for example, an epitaxially grown film grown on the upper surface of the protrusion 21 b.

[0039] The protrusion 31b is formed in the internal space of the recess 21a. The protrusion 31b is, for example, an epitaxially grown film grown from the growth surface of the recess 21a. In this case, the protrusion 31b includes laterally grown films 31ba and 31bb and a vertically grown film 31bc. The laterally grown film 31ba is a film grown in the lateral direction (a-axis direction) from the first growth surface 21aa of the recess 21a. The laterally grown film 31bb is a film grown in the lateral direction (a-axis direction) from the second growth surface 21ab of the recess 21a. The growth direction of the laterally grown film 31ba is opposite to that of the laterally grown film 31bb. The vertically grown film 31bc is a film grown in the thickness direction Z (vertical direction) from the third growth surface 21ac, and its growth direction is upward.

[0040] The thickness of the second crystal layer 3 is preferably 3 μm or more. The thickness of the second crystal layer 3 is preferably greater than the depth of the recess 31 a, i.e., the depth of the recess 21 a, and in this embodiment, it is approximately twice as great. However, the thickness of the second crystal layer 3 is not limited to this. In the embodiment of the present disclosure, the thickness of the second crystal layer 3 refers to the length along the thickness direction Z from the lower end of the protrusion 31 b to the upper surface of the second crystal layer 3.

[0041] This configuration allows a multilayer film to be formed with reduced dislocations extending along the thickness direction Z. Specifically, the laterally grown films 31ba and 31bb can meet within the recesses 21a. Therefore, the grain boundary 32a, which is the interface between the laterally grown films 31ba and 31bc, and the grain boundary 32b, which is the interface between the laterally grown films 31bb and 31bc, can be continuous. The grain boundary 32a and the grain boundary 32b are formed to cover the entire vertically grown film 31bc. Therefore, even if dislocation lines inherent in the first crystal layer 2 cause dislocation lines in the vertically grown film 31bc, dislocation lines extending along the thickness direction Z can be prevented from being generated in the laterally grown films 31ba and 31bb. Furthermore, dislocations extending along the thickness direction Z can be prevented from occurring in the regions directly above the protrusions 31b. Furthermore, since the direction of dislocations in the laterally grown films 31ba and 31bb is horizontal, upward propagation of the second crystal layer 3 can be suppressed, and dislocations extending along the thickness direction Z can be reduced.

[0042] (Method for Manufacturing Multilayer Film 1) Next, an example of a method for manufacturing the multilayer film 1 will be described. Fig. 2 shows a schematic configuration of a film formation apparatus (mist CVD apparatus) 4 used for manufacturing the multilayer film 1. The film formation apparatus 4 includes at least carrier gas supply units 41a, 41b, flow rate control valves 42a, 42b, an atomized droplet generation source 43, a container 44, an ultrasonic vibrator 45, a film formation chamber 46, a susceptor 47, and a heater 48.

[0043] The carrier gas supply unit 41a is configured to supply a carrier gas. The carrier gas supply unit 41b is configured to supply a diluted carrier gas. The flow rate control valves 42a and 42b are configured to adjust the flow rates of the carrier gases sent out from the carrier gas supply units 41a and 41b, respectively. The atomized droplet generating source 43 is configured to contain a raw material solution 43a.

[0044] An example of the raw material solution 43a is a solution obtained by mixing gallium acetylacetonate and tin (II) chloride in a predetermined ratio to form an aqueous solution to which hydrochloric acid or the like is appropriately added. However, the composition of the raw material solution 43a is not limited to this.

[0045] The container 44 is configured to contain water 44a. The ultrasonic vibrator 45 is attached to the bottom of the container 44. The film formation chamber 46 is configured from a quartz tube and is provided with an exhaust port 46a for discharging atomized droplets and exhaust gas after the reaction. The susceptor 47 is configured from quartz and has a surface on which the substrate 5 is placed that is inclined from the horizontal plane. The heater 48 is installed on the periphery of the film formation chamber 46. By making both the film formation chamber 46 and the susceptor 47 from quartz, impurities originating from the apparatus are prevented from being mixed into the film formed on the substrate 5.

[0046] 3 is a flowchart showing an example of a method for manufacturing the multilayer film 1. As shown in FIG. 3, the manufacturing of the multilayer film 1 includes a first crystal layer 2 forming step (S1), a concave-convex portion 21 forming step (S2), a second crystal layer 3 forming step (S3), and a substrate 5 removing step (S4). The first crystal layer 2 forming step (S1) and the second crystal layer 3 forming step (S3) are preferably performed in a film forming apparatus 4. However, other methods than the mist CVD method, such as CVD, MOCVD, MOVPE, mist epitaxy, MBE, HVPE, pulse growth, or ALD, can also be used.

[0047] First, in step S1, as shown in FIG. 4A , a first crystal layer 2 is laminated on a substrate 5. The substrate 5 is, for example, a plate-shaped sapphire substrate. The substrate 5 may be any substrate capable of epitaxially growing a semiconductor film and supporting the semiconductor film. The substrate 5 may be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate. The substrate 5 is preferably an insulating substrate, and is also preferably a substrate having a metal film on its surface. Examples of the substrate 5 include a base substrate containing as its main component a substrate material having a corundum structure, a base substrate containing as its main component a substrate material having a β-gallia structure, or a base substrate containing as its main component a substrate material having a hexagonal crystal structure. Here, "main component" means that a substrate material having a specific crystal structure preferably accounts for 50% or more, more preferably 70% or more, and even more preferably 90% or more, in atomic ratio, of the total components of the substrate material, and may be 100%.

[0048] The material used for the substrate 5 may be a known material. Examples of the substrate material having a corundum structure include α-Al ２ O ３ (sapphire substrate) or α-Ga ２ O ３ Preferred examples of the substrate include an a-plane sapphire substrate, an m-plane sapphire substrate, an r-plane sapphire substrate, a c-plane sapphire substrate, and an α-type gallium oxide substrate (a-plane, m-plane, or r-plane). ２ O ３ Substrate, or Ga ２ O ３ and Al ２ O ３ and Al ２ O ３ % or more and 60 wt % or less. Examples of the base substrate mainly composed of a substrate material having a hexagonal crystal structure include a SiC substrate, a ZnO substrate, and a GaN substrate.

[0049] In step S1, raw material solution 43a, which is the raw material for first crystal layer 2, is atomized to form suspended droplets, and the atomized droplets are then transported by a carrier gas onto substrate 5. The atomized droplets that reach the vicinity of substrate 5 undergo a thermal reaction to be sequentially layered (deposited) on substrate 5 as first crystal layer 2. First crystal layer 2 is a semiconductor film having a corundum structure and containing, as a main component, a crystalline oxide semiconductor containing gallium.

[0050] Subsequently, in step S2, as shown in FIG. 4B , a concave-convex portion 21 is formed on the upper portion of the first crystal layer 2. The concave-convex portion 21 is formed, for example, by performing an etching process or the like on the upper surface of the first crystal layer 2 laminated on the substrate 5. When forming the concave-convex portion 21, it is preferable to use a known photolithography technique to cover the upper surface of the first crystal layer 2 with a resist having a desired pattern shape, and then perform the etching process. The etching process may be dry etching or wet etching. In addition to the etching process, for example, electron beam lithography, laser patterning, selective growth, etc. may also be used.

[0051] 4C, the second crystal layer 3 is deposited on the first crystal layer 2 on which the concave-convex portion 21 is formed. The second crystal layer 3 can be deposited by the same method as the first crystal layer 2. The second crystal layer 3 is formed, for example, from the same material and to the same composition as the first crystal layer 2. The second crystal layer 3 is formed, for example, to have the same conductivity type as the first crystal layer 2, i.e., n-type.

[0052] In step S3, the convex portions 31b of the second crystal layer 3 are formed in the internal spaces of the concave portions 21a of the first crystal layer 2. As a result, the concave-convex portions 31 are formed in the lower portion 3a of the second crystal layer 3 according to the shape of the concave-convex portions 21 of the first crystal layer 2.

[0053] At this time, the laterally grown film 31ba of the convex portion 31b of the second crystal layer 3 grows rightward from the first growth surface 21aa of the concave portion 21a. The laterally grown film 31bb of the convex portion 31b grows leftward from the second growth surface 21ab of the concave portion 21a. The vertically grown film 31bc of the convex portion 31b grows upward from the third growth surface 21ac of the concave portion 21a. Since the laterally grown films 31ba, 31bb and the vertically grown film 31bc grow simultaneously from different growth surfaces, a grain boundary 32a is generated between the laterally grown film 31ba and the vertically grown film 31bc, and a grain boundary 32b is generated between the laterally grown film 31bb and the vertically grown film 31bc, and these become continuous.

[0054] After the second crystal layer 3 is formed, known means such as polishing may be used to make the upper surface of the second crystal layer 3 flat.

[0055] In step S4, the substrate 5 is removed, leaving the multilayer film 1 shown in Figures 1A and 1B. The substrate 5 is removed by known means such as polishing.

[0056] According to this manufacturing method, when the second crystal layer 3 is formed, SiO ２ Since no mask is used, there is no need to remove the mask in the multilayer film 1. Since there is no loss of a portion of each crystal layer due to removal of the mask, the yield is superior compared to when a mask is used.

[0057] Furthermore, since the grain boundaries 32 a and 32 b are continuous in the internal space of the recess 21 a of the first crystal layer 2, dislocations in the vertically grown film 31 bc can be prevented from extending beyond the grain boundaries 32 a and 32 b along the thickness direction Z. As a result, the device characteristics of a semiconductor device using the multilayer film 1 can be improved.

[0058] 5 shows a schematic configuration of a Schottky barrier diode (SBD) 6 as an example of a semiconductor device using the multilayer film 1. In this example, the second crystalline layer 3 of the multilayer film 1 is n － The first crystal layer 2 constitutes an n-type semiconductor layer. ＋ A Schottky electrode 61 is provided on the upper surface of the second crystal layer 3, and an ohmic electrode 62 is provided on the lower surface of the first crystal layer 2.

[0059] The material of the Schottky electrode 61 and the ohmic electrode 62 may be a known electrode material, and examples thereof include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures and laminates thereof.

[0060] The Schottky electrode 61 and the ohmic electrode 62 can be formed by known means such as vacuum deposition or sputtering. More specifically, when forming a Schottky electrode using two types of metals, a first metal and a second metal, among the above-mentioned metals, a layer made of the first metal and a layer made of the second metal are stacked, and the layer made of the first metal and the layer made of the second metal are patterned using a photolithography technique.

[0061] When a reverse bias (reverse voltage) is applied to the Schottky barrier diode (SBD) 6, a depletion layer (not shown) spreads into the second crystal layer 3, resulting in a high breakdown voltage Schottky barrier diode (SBD) 6. When a forward voltage (forward bias) is applied, a current flows from the Schottky electrode 61 to the ohmic electrode 62. The Schottky barrier diode (SBD) 6 using the multilayer film 1 in this way is excellent for high breakdown voltage and large current applications, has a fast switching speed, and is excellent in breakdown voltage and reliability. Note that when the second crystal layer 3 is n － type semiconductor layer and n ＋ As a two-layer structure of n-type semiconductor layer, ＋ The n-type semiconductor layer is bonded to the first crystalline layer 2, － The type semiconductor layer may be a layer into which the depletion layer of the SBD 6 expands.

[0062] Of course, the multilayer film 1 can be used in semiconductor devices other than the Schottky barrier diode (SBD) 6, such as a junction barrier Schottky diode (JBS), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), and a light emitting diode (LED), and in these cases, the multilayer film 1 also exhibits excellent switching performance, voltage resistance, and reliability.

[0063] Examples of the use of the multilayer film 1 in semiconductor devices such as junction barrier Schottky diodes (JBS), high electron mobility transistors (HEMT), metal oxide semiconductor field effect transistors (MOSFET), junction field effect transistors (JFET), insulated gate bipolar transistors (IGBT), and light emitting diodes (LED) are shown below. In this case, the multilayer film 1 may be used to form one n-type semiconductor layer. Alternatively, the multilayer film 1 may be used such that the first crystal layer 2 corresponds to one of the n-type semiconductor layers, and the second crystal layer 3 corresponds to another n-type semiconductor layer stacked with the n-type semiconductor layer.

[0064] 6 shows an example of a high electron mobility transistor (HEMT) according to an embodiment of the present disclosure. The HEMT in FIG. 6 includes an n-type semiconductor layer 421 a having a wide bandgap, an n-type semiconductor layer 421 b having a narrow bandgap, an n+ type semiconductor layer 421 c, a semi-insulating layer 424, a buffer layer 428, a gate electrode 425 a, a source electrode 425 b, and a drain electrode 425 c.

[0065] (MOSFET) An example of a case where the semiconductor device according to the present disclosure is a MOSFET is shown in Fig. 7. The MOSFET in Fig. 7 is a trench MOSFET, and includes an n-type semiconductor layer 431a, n+ type semiconductor layers 431b and 431c, a p-type semiconductor layer 432, a gate insulating film 434, a gate electrode 435a, a source electrode 435b, and a drain electrode 435c.

[0066] (JFET) FIG. 8 shows a preferred example of a junction field effect transistor (JFET) including an n-type semiconductor layer 441a, a first n+ type semiconductor layer 441b, a second n+ type semiconductor layer 441c, a gate electrode 445a, a source electrode 445b, and a drain electrode 445c.

[0067] (IGBT) FIG. 9 shows a preferred example of an insulated gate bipolar transistor (IGBT) including an n-type semiconductor layer 451, an n-type semiconductor layer 451a, an n+ type semiconductor layer 451b, a p-type semiconductor layer 452, a gate insulating film 454, a gate electrode 455a, an emitter electrode 455b, and a collector electrode 455c.

[0068] (LED) An example of a case where the semiconductor device of the present disclosure is a light-emitting diode (LED) is shown in Figure 10. The semiconductor light-emitting element of Figure 10 includes an n-type semiconductor layer 461 on a second electrode 465b, and a light-emitting layer 463 is stacked on the n-type semiconductor layer 461. A p-type semiconductor layer 462 is stacked on the light-emitting layer 463. A translucent electrode 467 that transmits light generated by the light-emitting layer 463 is provided on the p-type semiconductor layer 462, and a first electrode 465a is stacked on the translucent electrode 467. Note that the semiconductor light-emitting element of Figure 10 may be covered with a protective layer except for the electrode portion.

[0069] Examples of materials for the translucent electrode include conductive oxide materials containing indium (In) or titanium (Ti). ２ O ３ , ZnO, SnO ２ , Ga ２ O ３ , TiO ２ , CeO ２ Alternatively, a mixed crystal of two or more of these materials or a doped material thereof may be used. A translucent electrode can be formed by applying these materials by a known method such as sputtering. After the formation of the translucent electrode, thermal annealing may be performed to make the translucent electrode transparent.

[0070] In the semiconductor light-emitting element of Figure 10, the first electrode 465a is a positive electrode and the second electrode 465b is a negative electrode, and by passing a current through these electrodes to the p-type semiconductor layer 462, the light-emitting layer 463, and the n-type semiconductor layer 461, the light-emitting layer 463 emits light.

[0071] Examples of materials for the first electrode 465a and the second electrode 465b include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), or indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrole; or mixtures thereof. The method for forming the electrodes is not particularly limited, and they can be formed on the substrate according to a method appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into consideration their suitability for the material.

[0072] Another embodiment of the light-emitting element is shown in Fig. 11. In the light-emitting element of Fig. 11, an n-type semiconductor layer 461 is laminated on a substrate 469, and a p-type semiconductor layer 462, a light-emitting layer 463, and a portion of the n-type semiconductor layer 461 are cut away to expose the n-type semiconductor layer 461. A second electrode 465b is laminated on a portion of the exposed semiconductor layer surface of the n-type semiconductor layer 461.

[0073] FIG. 12 shows a junction barrier Schottky diode (JBS) according to a preferred embodiment of the present disclosure. The JBS shown in FIG. 12 includes an n-type semiconductor layer 401a, an n+-type semiconductor layer 401b, a p-type semiconductor layer 402, a Schottky electrode 405a, and an ohmic electrode 405b. In this embodiment of the present disclosure, the p-type semiconductor layers 402 are preferably provided at regular intervals, and more preferably, the p-type semiconductor layers 402 are provided between both ends of the Schottky electrode 405a and the n-type semiconductor layer 401a. This preferred embodiment allows the JBS to be configured to have superior thermal stability and adhesion, reduced leakage current, and superior semiconductor properties such as breakdown voltage.

[0074] 12 may be formed by any known method without particular limitation as long as it does not impede the objectives of the present disclosure, such as forming a film by vacuum deposition, CVD, sputtering, various coating techniques, or the like, followed by patterning by photolithography, or directly patterning by printing or the like.

[0075] Fig. 13 shows a junction barrier Schottky diode (JBS) according to a preferred embodiment of the present disclosure. The semiconductor device shown in Fig. 13 differs from the semiconductor device shown in Fig. 12 in that a guard ring is provided around the outer periphery of the Schottky electrode 405a, and the guard ring is made up of multiple p-type semiconductor layers 423. This configuration provides a semiconductor device with superior semiconductor characteristics, such as high breakdown voltage.

[0076] The guard rings may be made of a material with a high barrier height. Examples of materials used for the guard rings include conductive materials with a barrier height of 1 eV or more, which may be the same as the electrode material. The shape of the guard rings is not particularly limited, and examples include a square shape, a circle, a U-shape, an L-shape, and a strip shape. The number of guard rings is also not particularly limited, but is preferably three or more, and more preferably six or more.

[0077] 14 shows a preferred example of a metal oxide semiconductor field effect transistor (MOSFET) including an n-type semiconductor layer 431a, a first n+ type semiconductor layer 431b, a second n+ type semiconductor layer 431c, a p-type semiconductor layer 432, a p+ type semiconductor layer 432a, a gate insulating film 434, a gate electrode 435a, a source electrode 435b, and a drain electrode 435c. The p+ type semiconductor layer 432a may be a p-type semiconductor layer or may be the same as the p-type semiconductor layer 432. The p-type semiconductor may be made of the same material as the n-type semiconductor and contain a p-type dopant, or may be a different p-type semiconductor.

[0078] The multilayer film or semiconductor device according to the present disclosure can be applied to power conversion devices such as inverters and converters to achieve the above-described functions. More specifically, the multilayer film or semiconductor device can be applied as a diode built into an inverter or converter, or as a switching element such as a thyristor, power transistor, IGBT (Insulated Gate Bipolar Transistor), or MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). FIG. 15 is a block diagram showing an example of a control system using a semiconductor device according to an embodiment of the present disclosure, and FIG. 16 is a circuit diagram of the same control system. This control system is particularly suitable for installation in an electric vehicle.

[0079] As shown in Fig. 15, the control system 500 includes a battery (power source) 501, a boost converter 502, a buck converter 503, an inverter 504, a motor (drive target) 505, and a drive control unit 506, all of which are mounted on an electric vehicle. The battery 501 is a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and stores power by charging at a power supply station or by regenerating energy during deceleration, and can output a DC voltage required for operation of the electric vehicle's traction system and electrical equipment systems. The boost converter 502 is a voltage conversion device equipped with, for example, a chopper circuit, and can boost a DC voltage of, for example, 200 V supplied from the battery 501 to, for example, 650 V using the switching operation of the chopper circuit, and output the boosted voltage to the traction system, such as the motor. The step-down converter 503 is also a voltage conversion device equipped with a chopper circuit, but by stepping down the DC voltage of, for example, 200 V supplied from the battery 501 to, for example, about 12 V, it can output the voltage to the electrical system, including the power windows, power steering, and on-board electrical equipment.

[0080] Inverter 504 converts the DC voltage supplied from boost converter 502 into a three-phase AC voltage by switching operation and outputs it to motor 505. Motor 505 is a three-phase AC motor that constitutes the driving system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from inverter 504, and transmits the rotational driving force to the wheels of the electric vehicle via a transmission or the like (not shown).

[0081] Meanwhile, various sensors (not shown) measure actual values ​​such as wheel rotation speed, torque, and accelerator pedal depression (acceleration amount) from the electric vehicle while it is running, and these measurement signals are input to the drive control unit 506. At the same time, the output voltage value of the inverter 504 is also input to the drive control unit 506. The drive control unit 506 functions as a controller, equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory. It generates a control signal using the input measurement signal and outputs it as a feedback signal to the inverter 504, thereby controlling the switching operation of the switching elements. This instantly corrects the AC voltage provided by the inverter 504 to the motor 505, enabling accurate operation control of the electric vehicle and ensuring safe and comfortable operation of the electric vehicle. The output voltage to the inverter 504 can also be controlled by providing a feedback signal from the drive control unit 506 to the boost converter 502.

[0082] 16 shows the circuit configuration of FIG. 15 , excluding the step-down converter 503, i.e., showing only the configuration for driving the motor 505. As shown in the figure, the semiconductor device of the present disclosure is used, for example, as a Schottky barrier diode in a step-up converter 502 and an inverter 504 to provide switching control. In the step-up converter 502, it is incorporated into a chopper circuit to perform chopper control, and in the inverter 504, it is incorporated into a switching circuit including an IGBT to perform switching control. Note that current is stabilized by interposing an inductor (such as a coil) in the output of the battery 501, and voltage is stabilized by interposing capacitors (such as an electrolytic capacitor) between the battery 501, the step-up converter 502, and the inverter 504.

[0083] 16, the drive control unit 506 includes a calculation unit 507 consisting of a CPU (Central Processing Unit) and a storage unit 508 consisting of a non-volatile memory. Signals input to the drive control unit 506 are given to the calculation unit 507, which performs the necessary calculations to generate feedback signals for each semiconductor element. The storage unit 508 also temporarily stores the results of calculations performed by the calculation unit 507, and accumulates physical constants and functions required for drive control in the form of a table and outputs them to the calculation unit 507 as appropriate. The calculation unit 507 and storage unit 508 can be configured as known units, and their processing capabilities can also be selected as desired.

[0084] As shown in Figures 15 and 16, in the control system 500, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the switching operations of a boost converter 502, a buck converter 503, and an inverter 504. These semiconductor elements are made of gallium oxide (Ga ２ O ３ ), especially corundum-type gallium oxide (α-Ga ２ O ３ ) as the material, the switching characteristics are significantly improved. Furthermore, by applying the semiconductor device etc. according to the present disclosure, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized. That is, the effects of the present disclosure can be expected for each of the boost converter 502, the buck converter 503, and the inverter 504, and the effects of the present disclosure can be expected for any one of these, any combination of two or more of these, or any form including the drive control unit 506.

[0085] The control system 500 described above can be applied not only to the control system of an electric vehicle using the semiconductor device of the present disclosure, but also to control systems for all kinds of purposes, such as stepping up or stepping down power from a DC power source, or converting power from DC to AC, etc. Also, a power source such as a solar cell can be used as the battery.

[0086] FIG. 17 is a block diagram showing another example of a control system employing a semiconductor device according to an embodiment of the present disclosure, and FIG. 18 is a circuit diagram of the same control system, which is suitable for installation in infrastructure equipment, home appliances, and the like that operate on power from an AC power source.

[0087] As shown in FIG. 17 , a control system 600 receives power from an external, e.g., three-phase AC power source (power source) 601. The control system 600 includes an AC / DC converter 602, an inverter 604, a motor (drive target) 605, and a drive control unit 606, which can be mounted in various devices (described later). The three-phase AC power source 601 is, for example, a power generation facility (such as a thermal power plant, a hydroelectric power plant, a geothermal power plant, or a nuclear power plant) operated by an electric power company. The output of the three-phase AC power source 601 is stepped down via a substation and supplied as AC voltage. Alternatively, the AC / DC converter 602 may be installed in a building or a nearby facility and supplied with power via a power cable in the form of a private generator, for example. The AC / DC converter 602 is a voltage conversion device that converts AC voltage to DC voltage. It converts the 100 V or 200 V AC voltage supplied from the three-phase AC power source 601 to a predetermined DC voltage. Specifically, the voltage conversion converts the DC voltage to a commonly used desired voltage, such as 3.3 V, 5 V, or 12 V. If the drive target is a motor, the voltage conversion to 12 V is performed. It is also possible to use a single-phase AC power supply instead of a three-phase AC power supply, and in that case, a similar system configuration can be achieved by using an AC / DC converter with a single-phase input.

[0088] Inverter 604 converts the DC voltage supplied from AC / DC converter 602 into a three-phase AC voltage by switching operation and outputs it to motor 605. Motor 605 has a different form depending on the controlled object, but is a three-phase AC motor for driving wheels if the controlled object is a train, pumps and various power sources if the controlled object is factory equipment, or compressors etc. if the controlled object is a home appliance, and is rotationally driven by the three-phase AC voltage output from inverter 604, and transmits the rotational driving force to a driven object (not shown).

[0089] Note that, for example, among home appliances, there are many devices to be driven that can be supplied with the DC voltage output from AC / DC converter 602 as is (for example, personal computers, LED lighting equipment, video equipment, audio equipment, etc.), in which case inverter 604 is not required in control system 600, and the DC voltage is supplied to the device to be driven from AC / DC converter 602, as shown in Fig. 17. In this case, for example, a personal computer or the like is supplied with a DC voltage of 3.3 V, and an LED lighting equipment or the like is supplied with a DC voltage of 5 V.

[0090] Meanwhile, various sensors (not shown) are used to measure actual values ​​such as the rotation speed and torque of the driven object, or the temperature and flow rate of the environment surrounding the driven object, and these measurement signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measurement signals, the drive control unit 606 provides a feedback signal to the inverter 604 to control the switching operation of the switching elements. This allows the AC voltage provided by the inverter 604 to be instantly corrected, thereby enabling accurate operation control of the driven object and achieving stable operation of the driven object. Furthermore, as described above, if the driven object can be driven by a DC voltage, it is also possible to feedback control the AC / DC converter 602 instead of feedback to the inverter.

[0091] FIG. 18 shows an example of the circuit configuration of FIG. 17 . As shown in the figure, the semiconductor device of the present disclosure is used, for example, as a Schottky barrier diode in an AC / DC converter 602 and an inverter 604 to provide switching control. The AC / DC converter 602 uses, for example, a bridge-shaped circuit configuration of Schottky barrier diodes, and performs DC conversion by converting the negative voltage component of the input voltage into a positive voltage and rectifying it. The inverter 604 is also incorporated into a switching circuit of an IGBT to perform switching control. Note that an inductor (e.g., a coil) is interposed between the three-phase AC power supply 601 and the AC / DC converter 602 to stabilize the current, and a capacitor (e.g., an electrolytic capacitor) is interposed between the AC / DC converter 602 and the inverter 604 to stabilize the voltage.

[0092] 18, the drive control unit 606 includes a calculation unit 607 consisting of a CPU and a storage unit 608 consisting of a non-volatile memory. Signals input to the drive control unit 606 are given to the calculation unit 607, which performs the necessary calculations to generate feedback signals for each semiconductor element. The storage unit 608 also temporarily stores the results of calculations performed by the calculation unit 607, and accumulates physical constants and functions necessary for drive control in the form of a table and outputs them to the calculation unit 607 as appropriate. The calculation unit 607 and storage unit 608 can be configured as known units, and their processing capabilities can also be selected as desired.

[0093] In this control system 600, as in the control system 500 shown in Fig. 15 and Fig. 16, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the rectification and switching operations of the AC / DC converter 602 and inverter 604. These semiconductor elements are made of gallium oxide (Ga ２ O ３ ), especially corundum-type gallium oxide (α-Ga ２ O ３) as the material, the switching characteristics are improved. Furthermore, by applying the semiconductor film and semiconductor device according to the present disclosure, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be realized. That is, the effects of the present disclosure can be expected for each of the AC / DC converter 602 and the inverter 604, and the effects of the present disclosure can be expected in any one of them, a combination thereof, or a form including the drive control unit 606.

[0094] 17 and 18 show a motor 605 as an example of a device to be driven, but the device is not necessarily limited to a mechanically operated device, and can be many devices that require AC voltage. The control system 600 can be applied as long as it receives power from an AC power source to drive the device to be driven, and can be installed for drive control of devices such as infrastructure equipment (for example, power equipment in buildings and factories, communication equipment, traffic control equipment, water and sewage treatment equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (for example, refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.).

[0095] (Examples: Samples A to E) (Preparation of raw material solution) A gallium aqueous solution and ultrapure water were mixed to prepare an aqueous solution having a gallium concentration of 0.10 mol / L. At this time, the aqueous solution was adjusted to contain 10% hydrobromic acid by volume, and tin (II) bromide was mixed therein to prepare an aqueous solution having an atomic ratio of tin to gallium of 0.04 mol / L, and this was designated raw material solution 43a.

[0096] (Preparation for Film Formation) The obtained raw material solution 43a was placed in the atomized droplet generating source 43. Next, as the substrate 5, an α-Ga ２ O ３An m-plane sapphire substrate on which a film (non-doped) was laminated was placed on a susceptor 47, and a heater 48 was operated to raise the temperature inside the film formation chamber 46 to 460°C. Next, flow control valves 42a and 42b were opened to supply carrier gas from carrier gas supply units 41a and 41b, which are carrier gas sources, into the film formation chamber 46. After the atmosphere inside the film formation chamber 46 was sufficiently replaced with the carrier gas, the flow rates of the carrier gas and the carrier gas (diluted) were adjusted to 1.4 L / min and 0.5 L / min, respectively. Nitrogen was used as the carrier gas.

[0097] (Semiconductor film formation) Next, the ultrasonic vibrator 45 was vibrated at 2.4 MHz, and the vibration was propagated to the raw material solution 43a through the water 44a, thereby atomizing the raw material solution 43a to generate raw material fine particles. These raw material fine particles were introduced into the film formation chamber 46 by a carrier gas, and the mist reacted in the film formation chamber 46 at 460°C under atmospheric pressure, forming the first crystal layer 2 on the substrate 5. The film thickness was 3.5 μm, and the film formation time was 120 minutes.

[0098] Next, an etching process was performed on the first crystal layer 2 to form multiple recesses 21a extending in the Y-axis direction, each 1.5 μm deep in the Z-axis direction and 2.5 μm wide in the X-axis direction, spaced 0.25 μm apart from each other (the width of the protrusions 21b was 0.25 μm).

[0099] Furthermore, a second crystal layer 3 having a thickness of 3.5 μm was formed in the same manner on the first crystal layer 2. After removing the substrate 5, Ti electrodes serving as a Schottky electrode 61 and an ohmic electrode 62 were formed on the resulting multilayer film 1 by vacuum deposition.

[0100] (Comparative Example: Samples V to Z) As in the above-described examples, a first crystal layer 2 was formed on a substrate 5, and a second crystal layer 3 was formed on the first crystal layer 2 without providing the uneven portion 21 on the first crystal layer 2. In addition, Ti electrodes to serve as a Schottky electrode 61 and an ohmic electrode 62 were formed by vacuum deposition in a similar manner.

[0101] FIG. 19A shows a carrier density distribution model in the depth direction of the samples obtained in the example and comparative example, and FIG. 19B shows the carrier mobility distribution (calculated values) in the depth direction of the samples obtained in the example and comparative example. Also, FIG. 19C shows the measurement results of the forward current-forward voltage characteristics of the samples obtained in the example and comparative example. In these figures, the results shown as "model 1" are for the sample obtained in the comparative example. In "model 1," the carrier density decreases significantly as the depth increases from the surface of the N-type semiconductor layer to a depth of 3 μm. For example, at a depth of 0.5 μm, the carrier density is approximately 3×10 １６ cm －３ At a depth of 1.0 μm, the carrier density is approximately 2.5×10 １６ cm －３ At a depth of 3.0 μm, the carrier density is about 1×10 １６ cm －３ As shown in Figure 19D, since carrier mobility depends on carrier density, if the difference in carrier concentration in the depth direction of the N-type semiconductor layer is large, the resistance of the low concentration region becomes very large, and the current decreases significantly.

[0102] For the second crystal layer 3 formed on the first crystal layer 2, the lower limit of the carrier density at a depth of 1.0 μm or more from the surface is preferably at least half of the carrier density at a depth of 1.0 μm from the surface. The multilayer film 1 obtained in the example is shown as "model 2", and the lower limit of the carrier density at a depth of 1.0 μm or more from the surface of the second crystal layer 3 (about 1.6×10 １６ cm －３ ) is the carrier density (approximately 2.3 × 10 １６ cm －３ ) is about 70%, or more than half. That is, the carrier concentration difference in the depth direction of the N-type semiconductor layer is kept relatively small, and the occurrence of regions where it is difficult for current to flow is suppressed.

[0103] 20A to 20C are diagrams showing the relationship between depth from the surface and carrier density for Samples A to C according to the example, respectively, and FIGS. 20D to 20F are diagrams showing the relationship between depth from the surface and carrier density for Samples V to X according to the comparative examples. In these diagrams, "after epi" indicates the carrier density at the stage when a multilayer body (multilayer film 1) is formed by epitaxial film formation, and is indicated by A1 to D1 in FIGS. 20A to 20D, respectively. Irradiating this multilayer body (multilayer film 1) with UV light causes the release (detrapping) of carriers (electrons) captured in trap levels, increasing the carrier density. This increased carrier density is indicated by "after UV" in FIG. 20 and indicated by A2 to D2 in FIGS. 20A to 20D, respectively.

[0104] This increase in carrier density is represented by arrow a in FIG. 21 , and this increase is used to measure the trap level density. The multilayer body (multilayer film 1) is fabricated into a semiconductor device (here, a Schottky barrier diode (SBD) 6). In FIG. 20 , "SBD complete" indicates the carrier density after fabrication into a device, and is indicated by A3 to D3 in FIGS. 20A to 20D , respectively. Before a stress test (here, a high-temperature reverse bias test at 175° C., 350 V, and 6 minutes) is performed on the semiconductor device, the carrier density does not change due to UV light irradiation (e in FIG. 21 ), and therefore the trap level density cannot be measured.

[0105] On the other hand, in the semiconductor device after the stress test, carriers (electrons) are captured in the trap levels. In Figure 20, "After Stress" indicates the carrier density after the stress test, and is indicated by A4 to D4 in Figures 20A to 20D, respectively. For convenience, in Figures 20E and 20F, the carrier density distribution before the stress test is indicated by E3 and F3, respectively, and the carrier density distribution after the stress test is indicated by E4 and F4, respectively.

[0106] When carriers (electrons) are trapped in the trap levels, UV light irradiation causes the trapped carriers (electrons) to be released (detrapped), resulting in an increase in carrier density. The increase in carrier density at this time is indicated by arrow b in FIG. 21, and this increase can be used to measure the trap level density. From the results shown in FIG. 20, it can be seen that the carrier concentration difference in the depth direction of the N-type semiconductor layer is kept small in Samples A to C of the example compared to Samples V to X of the comparative example.

[0107] The wavelength of the irradiated light was changed to observe detrapping. Specifically, the wavelength λ was changed from 300 nm to 540 nm. From the photon energy hc / λ corresponding to these wavelengths, the second crystal layer 3 has electron trap levels with energy levels of 2.3 to 4.1 eV from the lower limit of the conduction band, and the density of the electron trap levels is 1.0×10 at a depth of 1.0 μm or more from the surface of the second crystal layer 3. １６ / cm ３ The electron trap level density at a depth of 1.0 μm or more from the surface of the second crystal layer 3 was found to be 3.0×10 １５ / cm ３ or less or 1.0 x 10 １５ / cm ３ More preferably, it is:

[0108] The carrier density of the second crystalline layer 3 was measured by a photocapacitance method and found to be 2.0×10 １６ / cm ３ That was all.

[0109] FIG. 22A shows the current drop rate after a high-temperature reverse bias test (175°C, 350V, 6 minutes) under voltage acceleration conditions. In this high-temperature reverse bias test, an average electric field of 1 MV / cm is applied to the electrode for 6 minutes in an atmosphere at the maximum junction temperature (Tjmax). As shown in the figure, the sample according to the embodiment achieves a post-test current drop rate of 0.1 or less (10% or less). A larger current drop rate increases the forward voltage drop Vf, potentially increasing the amount of heat generated during circuit operation. However, if the post-test current drop rate ΔIf / If is ≦0.1, it can be said that there are no problems even after a 1000-hour reliability test (absolute maximum rating). Note that the term "average electric field" in this disclosure refers to the average electric field strength within the electrode plane. In the case of a Schottky barrier diode, this electric field strength is the electric field strength at the interface between the Schottky electrode and the n-type semiconductor layer.

[0110] 22B is a graph showing the current decrease rate after a high-temperature reverse bias test (175° C., 350 V, 6 minutes) under voltage acceleration conditions. ２ O ３ (N － For a 3.5 μm thick semiconductor layer, the average electric field strength is 1 MV / cm. The voltage acceleration conditions are voltage conditions at the absolute maximum rated temperature. As shown in FIG. 22B , for samples A and B according to the example, the current reduction rate after a stress time of 6 minutes (0.1 h) is 10% or less (ΔIf / If≦0.1). On the other hand, for samples C and D according to the comparative example, the current reduction rate after a stress time of 6 minutes (0.1 h) exceeds 10% (ΔIf / If>0.1).

[0111] 23A is a graph showing the relationship between stress time and forward voltage drop Vf. As shown in the figure, as the stress time increases, the current decrease rate ΔIf / If increases, and as a result, the forward voltage drop Vf increases.

[0112] FIG. 23B shows the relationship between stress time and the current drop rate. The time dependence of the current drop rate can be represented by a semi-logarithmic line (time axis). Therefore, once two points are determined, the OK / NG line indicated by L1 in the figure can be determined. Here, two points, 3 h and 2000 h, are selected. The high-temperature reverse bias test under voltage acceleration conditions (175°C, 350 V, 6 minutes) is assumed to accelerate the degradation rate 30 times compared to the normal high-temperature reverse bias test (175°C, 270 V). This setting is also appropriate in terms of the relationship between the current drop rate ΔIf / If and the reverse voltage Vr. When the reverse voltage Vr is increased by 1.3 times, the current drop rate ΔIf / If increases by 0.1. Therefore, in the high-temperature reverse bias test under voltage acceleration conditions, the current drop rate ΔIf / If≦0.1 corresponds to the point in FIG. 23B where the stress time is 3 h and the current drop rate ΔIf / If is 0.1.

[0113] A stress time of 2000 hours is the standard setting for high-temperature reverse bias testing, and corresponds to a current drop rate ΔIf / If≦0.3. If the initial forward current-forward voltage characteristics and current drop rate ΔIf / If are determined, the forward voltage drop Vf after 2000 hours can be calculated. Since the heat generation temperature and power consumption during actual drive circuit operation are known, it is possible to set a current drop rate ΔIf / If that corresponds to these.

[0114] 24A and 24B show the relationship between stress time and the change in forward voltage drop Vf and the current drop rate ΔIf / If under reliability test conditions (175°C, 280V). The voltage of 280V corresponds to 0.8 times the absolute maximum rated voltage Vr (350V). Under reliability test conditions where the voltage is 0.8 times the absolute maximum rated voltage, the lifetime is said to be 10 times longer. In other words, the drop rate (degradation rate) under a 10-hour stress time under the reliability test conditions is said to be the same as that under a 1-hour stress time under the voltage acceleration conditions. If ΔIf / If≦0.1 under the voltage acceleration conditions for 6 minutes (0.1 hours), the current drop rate over 1000 hours of the reliability test is 0.3 or less, and the Vf upper limit of 2.1V (the maximum specification value indicated by L2 in FIG. 24A) is not exceeded. Furthermore, as shown in FIG. 24B , it can be seen that Samples A and B according to the embodiment have a current reduction rate of 30% or less when operated under high-temperature reverse bias test conditions that include applying a reverse bias of 0.8 times the absolute maximum rated voltage for 1000 hours in an atmosphere of the maximum junction temperature (Tjmax) (indicated by L3 in the figure).

[0115] The current decrease due to the stress of the high-temperature reverse bias test is caused by a decrease in carrier density. Even if the number of carriers (electrons) captured in the electron trap level is the same, the lower the original carrier density, the greater the rate of decrease in carrier density. For this reason, it is important to pay attention to the rate of decrease in carrier density.

[0116] The rate of decrease in carrier density is preferably 10% or less when operated under high-temperature reverse bias test conditions including application of an average electric field of 1 MV / cm for 6 minutes in an atmosphere of the maximum junction temperature (Tjmax). The rate of decrease in carrier density here refers to the average carrier density in a depth of 1 μm or more from the surface of the second crystal layer 3. However, the rate of decrease in carrier density may also be the rate of decrease in carrier density at the depth where the carrier density is lowest.

[0117] 25A and 25B show the carrier density distributions in the depth direction of Samples D and E according to the example, respectively, and FIGS. 25C and 25D show the forward current-forward voltage characteristics of Samples D and E according to the example. In FIGS. 25A and 25B, D1 and E1 show the carrier density distributions before the high-temperature reverse bias test, respectively, and D2 and E2 show the carrier density distributions after the high-temperature reverse bias test, respectively. It can be seen that in Samples D and E according to the example, the rate of decrease in carrier density is suppressed to 10% or less over a wide range in the depth direction, and the rate of decrease in current is also suppressed to 10% or less.

[0118] 26A and 26B show the carrier density distributions in the depth direction of samples Y and Z according to the comparative example, respectively, and FIGS. 26C and 26D show the forward current-forward voltage characteristics of samples Y and Z according to the comparative example. In FIGS. 26A and 26B, Y1 and Z1 respectively show the carrier density distributions before the high-temperature reverse bias test, and Y2 and Z2 respectively show the carrier density distributions after the high-temperature reverse bias test. It can be seen that in samples Y and Z according to the comparative example, the rate of decrease in carrier density greatly exceeds 10%, particularly in the depth region of 0.5 μm to 2.5 μm, and the rate of decrease in current also greatly exceeds 10%.

[0119] FIG. 27 shows the change in carrier density when irradiated with green light and UV radiation. In the figure, the carrier density distribution in the non-irradiated state is denoted by Nd1, and the carrier density distribution after irradiation with green light and UV radiation is denoted by Nd2 and Nd3, respectively. In this embodiment, the trap level density is defined as the carrier density after irradiation with UV light (300 nm, 20 minutes) minus the carrier density after irradiation with green light (550 nm, 1 minute). When measuring the trap level density, first, CV measurement of the sample is performed without irradiating it with light. Next, the sample is irradiated with green light, and CV measurement of the sample is performed. Furthermore, the sample is irradiated with UV light, and CV measurement of the sample is performed. The standard CV measurement voltage is 0 to 100 V.

[0120] Because the depletion widths at each voltage obtained from the CV characteristics after UV light irradiation and after green light irradiation differ, the carrier density at the same depletion layer width is calculated, and then the concentration difference is determined. It is known that the trap level is located 3 to 4 eV from the bottom of the conduction band, and electrons are stable in a state captured in the trap level at thermal equilibrium. Therefore, after electron release (detrapping) by UV light irradiation (300 nm, 20 minutes), the electrons are gradually returned to a trapped state in the trap level. Because it usually takes several hours or more for electrons to return to a trapped state in the trap level, CV measurements are performed immediately after UV light irradiation. Green light irradiation is performed to prevent capacitance reduction in the low-voltage region when the N+ contact of the peripheral electrode of the double Schottky structure is insufficient. In basic evaluation methods, because trap levels at energy levels that can be detrapped by visible light irradiation such as green light are hardly detected, the CV characteristics are basically similar to those without light irradiation.

[0121] 28A shows the distribution of trap state density in the depth direction, and FIG. 28B shows the distribution of trap rate in the depth direction. In this embodiment, the trap rate is a value obtained by dividing the trap state density by the carrier density at each depth. That is, it is expressed as trap rate = trap density @ each depth (depth) / carrier density @ each depth (depth). Here, the carrier density is defined as the carrier density in an untrapped state, i.e., after UV light irradiation.

[0122] Furthermore, when comparing samples, the comparison is made using average values ​​to make it easier to see the relationship with carrier density. The following formula defines the average carrier density (Nd_mean). The average trap density and trap rate are also calculated using the same definition. Wd is a variable in the depth direction. Wd@0V is the extension of the depletion layer when 0V is applied (however, the extension width when 0V is applied is 0 μm), and Wd@100V is the extension of the depletion layer when 100V is applied. The integral value of the denominator on the right side means the value of the extension of the depletion layer when 100V is applied.

[0123] In the sample obtained in the example, the expansion of dislocations is suppressed by the crystal grain boundaries 32a and 32b formed in the internal space of the recess 21a in the first crystal layer 2. For example, even if defects occur due to lattice mismatch or the like when the first crystal layer 2 is epitaxially grown on the substrate 5, they are unlikely to affect the second crystal layer 3. It is believed that the second crystal layer 3 has few defects such as dislocations from the surface to the deep regions, and the density of electron trap levels is suppressed to be low from the surface to the deep regions.

[0124] In the second crystal layer 3, no reduction in carrier density is observed from the surface to the deep region. Furthermore, in the second crystal layer 3, deep level electron traps (2.3 to 4.1 eV) on the bottom side can be reduced. A semiconductor device using such a second crystal layer 3 (N-type semiconductor layer) can exhibit excellent results in a high-temperature reverse bias test. Similarly, the device also exhibits excellent results in a high-temperature reverse bias test under voltage acceleration conditions.

[0125] The following additional notes are provided regarding this disclosure.

[0126] (Supplementary Note 1) A multilayer body comprising a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer comprise a crystalline oxide containing gallium, the second semiconductor layer is disposed on the first semiconductor layer directly or via another layer, and a lower limit of the carrier density at a depth of 1.0 μm or more from the surface of the second semiconductor layer is equal to or greater than half of the carrier density at a depth of 1.0 μm from the surface.

[0127] (Supplementary Note 2) A semiconductor device comprising a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer contain a crystalline oxide containing gallium, the second semiconductor layer is disposed on the first semiconductor layer directly or via another layer, and has an electron trap level with an energy level of 2.3 to 4.1 eV from the lower limit of the conduction band, and the density of the electron trap level is 1.0×10 at a depth of 1.0 μm or more from the surface of the second semiconductor layer. １６ / cm ３ The following is a multilayer body.

[0128] (Supplementary Note 3) The multilayer body according to Supplementary Note 1 or Supplementary Note 2, wherein the second semiconductor layer has a carrier density of 2.0×10 １６ / cm ３ A multilayer body that is the above.

[0129] (Appendix 4) A semiconductor device comprising: an n-type semiconductor layer including a crystalline oxide semiconductor containing gallium; and at least two or more electrodes connected to the n-type semiconductor layer, wherein the semiconductor device exhibits a current reduction rate of 10% or less when operated under high-temperature reverse bias test conditions including a condition in which an average electric field of 1 MV / cm is applied to the electrodes for 6 minutes in an atmosphere of a maximum junction temperature (Tjmax).

[0130] (Appendix 5) A semiconductor device comprising: an n-type semiconductor layer including a crystalline oxide semiconductor containing gallium; and at least two electrodes connected to the n-type semiconductor layer, wherein the semiconductor device exhibits a carrier density reduction rate of 10% or less when operated under high-temperature reverse bias test conditions including a condition in which an average electric field of 1 MV / cm is applied to the electrodes for 6 minutes in an atmosphere of a maximum junction temperature (Tjmax).

[0131] (Appendix 6) A semiconductor device comprising: an n-type semiconductor layer including a crystalline oxide semiconductor containing gallium; and at least two or more electrodes connected to the n-type semiconductor layer, wherein the semiconductor device exhibits a current reduction rate of 30% or less when operated under high-temperature reverse bias test conditions including a condition in which a reverse bias of 0.8 times the maximum rated voltage is applied to the electrodes for 1000 hours in an atmosphere of the maximum junction temperature (Tjmax).

[0132] 1: Multilayer film 2: First crystal layer 3: Second crystal layer 3a: Lower part 3h: Stress time 4: Film formation apparatus 5: Substrate 13: Substrate 21: Uneven portion 21a: Concave portion 21aa: First growth surface 21ab: Second growth surface 21ac: Third growth surface 21b: Convex portion 26: Film formation chamber 31: Uneven portion 31a: Concave portion 31b: Convex portion 31ba: Laterally grown film 31bb: Laterally grown film 31bc: Vertically grown film 32a: Crystal grain boundary 32b: Crystal grain boundary 41a: Carrier gas supply unit 41b: Carrier gas supply unit 42a: Flow rate control valve 42b: Flow rate control valve 43: Atomized droplet generation source 43a : Raw material solution 44 : Container 44a : Water 45 : Ultrasonic vibrator 46 : Film formation chamber 46a : Exhaust port 47 : Susceptor 48 : Heater 61 : Schottky electrode 62 : Ohmic electrode 401a n － Type semiconductor layer 401b n ＋n-type semiconductor layer 402 p-type semiconductor layer 405a Schottky electrode 405b Ohmic electrode 421a Wide band gap n-type semiconductor layer 421b Narrow band gap n-type semiconductor layer 421c N+ type semiconductor layer 423 p-type semiconductor layer 424 Semi-insulating layer 425a Gate electrode 425b Source electrode 425c Drain electrode 428 Buffer layer 431a n- type semiconductor layer 431b First n+ type semiconductor layer 431c Second n+ type semiconductor layer 432 p-type semiconductor layer 432a p+ type semiconductor layer 434 Gate insulating film 435a Gate electrode 435b Source electrode 435c Drain electrode 441a n- type semiconductor layer 441b First n+ type semiconductor layer 441c Second n+ type semiconductor layer 445a Gate electrode 445b Source electrode 445c Drain electrode 451 n-type semiconductor layer 451a n-type semiconductor layer 451b n+ type semiconductor layer 452 p-type semiconductor layer 454 Gate insulating film 455a Gate electrode 455b Emitter electrode 455c Collector electrode 461 n-type semiconductor layer 462 p-type semiconductor layer 463 Light-emitting layer 465a First electrode 465b Second electrode 467 Translucent electrode 469 Substrate 500 Control system 501 Battery (power source) 502 Step-up converter 503 Step-down converter 504 Inverter 505 Motor (drive object) 506 Drive control unit 507 Arithmetic unit 508 Memory unit 600 Control system 601 Three-phase AC power supply (power source) 602 AC / DC converter 604 Inverter 605 Motor (drive object) 606 Drive control unit 607 Calculation unit 608 Storage unit

Claims

1. A multilayer body comprising a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer comprise a crystalline oxide containing gallium, the second semiconductor layer is disposed on the first semiconductor layer directly or via another layer, and the lower limit of the carrier density at a depth of 1.0 μm or more from the surface of the second semiconductor layer is at least half of the carrier density at a depth of 1.0 μm from the surface.

2. A semiconductor device comprising a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer contain a crystalline oxide containing gallium, the second semiconductor layer is disposed on the first semiconductor layer directly or via another layer, and has an electron trap level with an energy level of 2.3 to 4.1 eV from the lower limit of the conduction band, and the density of the electron trap level is 1.0 x 10 at a depth of 1.0 μm or more from the surface of the second semiconductor layer. １６ / cm ３ The following is a multilayer body.

3. The second semiconductor layer has a carrier density of 2.0×10 １６ / cm ３ The multilayer body according to claim 1 or 2, wherein the above-mentioned 4. A semiconductor device comprising: an n-type semiconductor layer containing a crystalline oxide semiconductor containing gallium; and at least two electrodes connected to the n-type semiconductor layer, wherein the current reduction rate is 10% or less when operated under high-temperature reverse bias test conditions including applying an average electric field of 1 MV / cm to the electrodes for 6 minutes in an atmosphere at the maximum junction temperature (Tjmax).

5. A semiconductor device comprising: an n-type semiconductor layer containing a crystalline oxide semiconductor containing gallium; and at least two electrodes connected to the n-type semiconductor layer, wherein the rate of decrease in carrier density is 10% or less when operated under high-temperature reverse bias test conditions including the application of an average electric field of 1 MV / cm to the electrodes for 6 minutes in an atmosphere at the maximum junction temperature (Tjmax).

6. A semiconductor device comprising: an n-type semiconductor layer containing a crystalline oxide semiconductor containing gallium; and at least two electrodes connected to the n-type semiconductor layer; wherein the current reduction rate is 30% or less when operated under high-temperature reverse bias test conditions including applying a reverse bias of 0.8 times the maximum rated voltage to the electrodes for 1,000 hours in an atmosphere at the maximum junction temperature (Tjmax).

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