Light emitting device

Abstract

To provide a light emitting device capable of suppressing a variation in brightness between pixels due to a variation in the threshold voltage of a transistor.SOLUTION: There is provided a light emitting device including a transistor having a first gate and a second gate that overlap each other via a semiconductor film, a first capacitive element that holds a potential difference between one of the source and drain of the transistor and the first gate, a second capacitive element that holds a potential difference between one of the source and drain of the transistor and the second gate, a switch that controls the conduction state between the second gate of the above transistor and the wires, and a light emitting element to which the drain current of the above transistor is supplied.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. , manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a memory device, a data processing device, In particular, one aspect of the present invention relates to a semiconductor device, a driving method thereof, and a manufacturing method thereof. Device, display device, light emitting device, power storage device, storage device, driving method thereof, or manufacturing method thereof It relates to the manufacturing method. [Background technology]

[0002] The specific configuration of an active matrix display device using a light emitting element is as follows: Although it varies by manufacturer, it usually consists of at least a light-emitting element and a video signal input to the pixel. The transistor to be controlled (switching transistor) and the current value to be supplied to the light emitting element A transistor (drive transistor) that controls the pixel is provided in each pixel.

[0003] By making all the transistors in the pixel have the same polarity, In the manufacturing process, a process such as adding an impurity element that gives one conductivity to the semiconductor film is performed. In the following Patent Document 1, a pixel is formed by only n-channel transistors. A constructed light emitting device display is described. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2003-195810 A Summary of the Invention [Problem to be solved by the invention]

[0005] In a light emitting device, the drain current of a driving transistor is supplied to a light emitting element. Therefore, if there is a variation in the threshold voltage of the driving transistor between pixels, the brightness of the light-emitting element may decrease. Therefore, the threshold voltage variation is reflected in the driving The proposal for a pixel configuration that can correct the current value of a transistor will improve the image quality of light-emitting devices. This is an important issue in terms of

[0006] Based on the above technical background, pixel defects due to variations in the threshold voltage of the driving transistor It is an object of the present invention to provide a light-emitting device in which variation in luminance between adjacent pixels can be suppressed.

[0007] Note that an object of one embodiment of the present invention is to provide a novel semiconductor device or the like. The description of these problems does not preclude the existence of other problems. It is not necessary to solve all of these problems. Problems other than these may be solved in the specification. The contents of the specification, drawings, claims, etc. are self-evident. It is possible to extract other issues from the descriptions in paragraphs etc. [Means for solving the problem]

[0008] The light-emitting device according to one aspect of the present invention includes a first gate and a second gate electrode overlapping each other via a semiconductor film. a transistor having a second gate; and one of a source and a drain of the transistor; a first capacitance element for holding a potential difference between the first gate and the second gate of the transistor; a second capacitance element for holding a potential difference between one of the source and drain and the second gate; a switch that controls a conductive state between the second gate of the transistor and a wiring; and a light emitting element to which the drain current of the transistor is supplied. Effect of the Invention

[0009] According to one aspect of the present invention, the brightness variation between pixels due to the variation in the threshold voltage of the transistor is reduced. It is possible to provide a light emitting device in which the deterioration is suppressed.

[0010] According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. The description of these effects does not preclude the existence of other effects. It is not necessary to have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a diagram showing the configuration of a pixel. [Diagram 2] FIG. 2 is a diagram showing the configuration of a pixel. [Diagram 3] FIG. 2 is a diagram showing the configuration of a pixel. [Figure 4] FIG. 2 is a diagram showing the configuration of a pixel. [Diagram 5] 4 is a timing chart showing the operation of a pixel. [Figure 6] FIG. [Figure 7] FIG. [Figure 8] 4 is a timing chart showing the operation of a pixel. [Figure 9] FIG. 1 is a diagram showing the relationship between Vbg and Vth. [Figure 10]FIG. 2 shows a configuration of a pixel portion. [Figure 11] FIG. 2 is a diagram showing the configuration of a pixel portion and a selection circuit. [Figure 12] Schematic diagram of the monitor circuit. [Figure 13] FIG. 2 is a diagram showing the configuration of a pixel. [Figure 14] FIG. 2 is a diagram showing the configuration of a pixel. [Figure 15] FIG. 2 is a diagram showing the configuration of a pixel. [Figure 16] 4 is a timing chart showing the operation of a pixel. [Figure 17] FIG. 2 is a diagram showing the configuration of a pixel. [Figure 18] FIG. 2 is a diagram showing the configuration of a pixel. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light-emitting device. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light-emitting device. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light-emitting device. [Figure 22] FIG. [Diagram 23] FIG. [Figure 24] Electronic devices illustration. [Diagram 25] FIG. [Figure 26] 1A and 1B are diagrams illustrating a configuration of an information processing device using a light-emitting device. [Figure 27] FIG. 1 is a top view showing a structure of a transistor. [Figure 28] 1 is a cross-sectional view illustrating a structure of a transistor. [Figure 29] FIG. 1 is a top view showing a structure of a transistor. [Diagram 30] 1 is a cross-sectional view illustrating a structure of a transistor. [Diagram 31] FIG. 1 is a top view showing a structure of a transistor. [Diagram 32] 1 is a cross-sectional view illustrating a structure of a transistor. [Diagram 33] FIG. 2 is a diagram showing the configuration of a pixel. [Diagram 34] 1 is a cross-sectional view illustrating a structure of a transistor. [Diagram 35] FIG. 2 is a diagram showing the configuration of a pixel. [Diagram 36] FIG. 2 is a diagram showing the configuration of a pixel. [Figure 37] FIG. 2 is a diagram showing the configuration of a pixel. [Figure 38] FIG. 2 is a diagram showing the configuration of a pixel. [Figure 39] FIG. 2 is a diagram showing the configuration of a pixel. [Diagram 40] FIG. 2 shows a configuration of a pixel portion. [Diagram 41] FIG. 2 shows a configuration of a pixel portion. [Diagram 42] FIG. 13 shows characteristics of a transistor. [Diagram 43] 1A and 1B are diagrams showing the configuration and operation of a pixel. [Diagram 44] FIG. 1 is a diagram showing a configuration of a display device. [Diagram 45] FIG. 4 is a diagram showing a display photograph of a display device. [Diagram 46] FIG. 13 shows characteristics of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiment.

[0013] In this specification, a light-emitting device refers to a panel in which a light-emitting element is formed in each pixel, a driving circuit, A module in which an IC or controller, etc., is mounted on the panel, Further, the light-emitting device according to one embodiment of the present invention includes a process for manufacturing the light-emitting device. The term "element substrate" includes, in its category, an element substrate that corresponds to one form before the light-emitting element is completed in the process, and The element substrate has a plurality of transistors and pixel electrodes to which a voltage is supplied via the transistors. A number of pixels are provided.

[0014] The source of a transistor is a source region that is a part of the semiconductor film that functions as an active layer. The term "transistor" refers to a transistor region, or a source electrode electrically connected to the semiconductor film. The drain of the transistor is a drain region that is a part of the semiconductor film, or a region where an electric current is applied to the semiconductor film. "Gate" means a gate electrode that is electrically connected to the gate electrode.

[0015] The source and drain of a transistor are determined by the conductivity type of the transistor and the terminals. The name is changed depending on the potential that is applied. Generally, n-channel transistors In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In addition, in a p-channel transistor, the terminal to which a low potential is applied is called the drain. The terminal to which the high potential is applied is called the input, and the terminal to which the high potential is applied is called the source. Explain the connection relationship of a transistor, assuming that the source and drain are fixed. In some cases, the names of the source and drain are interchangeable according to the above potential relationship. do.

[0016] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be described in the drawings or text. do.

[0017] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0018] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0019] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0020] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. and the case where they are electrically connected to each other.

[0021] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) When X and Y are functionally connected (i.e., when X and Y are connected), (When there is a functional connection between X and Y via another circuit in between) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is deemed to be disclosed in the present specification. If it is explicitly stated that it is connected, The same contents are deemed to be disclosed in the present specification and the like.

[0022] Example of pixel configuration FIG. 1 shows an example of the configuration of a pixel 10 in a light-emitting device according to one embodiment of the present invention. The pixel 10 includes a transistor 11, a switch 16, a capacitance element 13, and a capacitance element 18. , and a light-emitting element 14.

[0023] The light emitting element 14 is a light emitting diode (LED) or an organic light emitting diode (OLED). current or voltage, such as a photovoltaic (Pb) or photovoltaic (Pb) light emitting diode (Pb) The category includes devices whose luminance is controlled by the light emitting diode (ELD) layer. For example, an OLED includes an EL layer and The device has at least an anode and a cathode. The EL layer is a single layer or a multilayer structure provided between the anode and the cathode. The light-emitting device is composed of a plurality of layers, and among these layers, at least one light-emitting layer containing a light-emitting substance is included. The EL layer is a layer that is turned on when the potential difference between the cathode and the anode is equal to or greater than the threshold voltage Vthe of the light emitting element 14. When the electrode is turned on, electroluminescence is obtained by supplying a current. There are two types of luminescence: luminescence (fluorescence) when returning from a singlet excited state to the ground state and luminescence (fluorescence) when returning from a triplet excited state to the ground state. This includes light emission (phosphorescence) occurring when returning from an excited state to the ground state.

[0024] In addition, one of the anode and cathode of the light emitting element 14 functions as a pixel electrode, and the other In FIG. 1, the anode of the light-emitting element 14 is used as a pixel electrode, and the light-emitting element 14 is Illustrated is a configuration of pixel 10 in which the cathode of photoelement 14 is used as a common electrode.

[0025] The transistor 11 has a normal gate (first gate) and an upper gate with a semiconductor film interposed therebetween. The first gate is designated as G1 in FIG. 1 and the second gate is shown as G2.

[0026] The potential of the first gate of the transistor 11 is changed according to an image signal supplied from the wiring SL. The switch 16 is controlled by connecting the wiring B It has the function of controlling the supply of L potential.

[0027] The switch 16 may be configured using a single transistor or a plurality of transistors. Alternatively, the switch 16 may include a capacitive element in addition to one or more transistors. It is okay to use it.

[0028] The capacitance element 13 is connected to the second gate of the transistor 11 and the source and drain of the transistor 11. The capacitor 18 has a function of holding a potential difference between one of the drains and the other of the drains. The potential difference between the first gate of the transistor 11 and one of the source and drain of the transistor 11 is , and has the function of holding.

[0029] In FIG. 1, the transistor 11 is an n-channel type. One of the source and drain of the transistor 11 is electrically connected to the anode of the light emitting element 14. The other of the source and drain of the transistor 11 is electrically connected to the wiring VL. The cathode of the light-emitting element 14 is electrically connected to the wiring CL. The potential of the wiring VL is determined by multiplying the potential of the wiring CL by the threshold voltage Vthe of the light emitting element 14 and the The potential is set to be higher than the potential obtained by adding the threshold voltage Vth of the transistor 11. When the value of the drain current of the transistor 11 is determined according to the signal, the drain current becomes the light emitting element. When supplied to the element 14, the light emitting element 14 is put into a light emitting state.

[0030] If the transistor 11 is a p-channel type, as shown in FIG. One of the source and drain is electrically connected to the cathode of the light-emitting element 14. The other of the source and the drain of the transistor 11 is electrically connected to a wiring VL. The anode of the light emitting element 14 is electrically connected to the wiring CL. The potential is determined by multiplying the potential of the wiring VL by the threshold voltage Vthe of the light emitting element 14 and the threshold voltage Vth of the transistor 11. The potential is set to be higher than the sum of the voltage Vth and the n-channel transistor 11. In the same manner as in the case of the p-channel type, when the transistor 11 is a p-channel type, the image signal When the drain current of the transistor 11 is determined according to the above, the drain current When the light is supplied to 14, the light emitting element 14 is put into a light emitting state.

[0031] In one embodiment of the present invention, the value of the drain current of the transistor 11 is changed according to an image signal. Before determining the voltage between the source or drain of the transistor 11 and the second gate, By controlling the voltage Vbg, the threshold voltage Vth of the transistor 11 is corrected, and This prevents the threshold voltage Vth of the transistor 11 from varying.

[0032] Specifically, the potential of the wiring BL is applied to the second gate of the transistor 11 via the switch 16. By supplying the voltage, the transistor 11 is normally on. For example, when the transistor 11 is In the case of an n-channel type, increasing the voltage Vbg shifts the threshold voltage Vth in the negative direction. In addition, the transistor 11 is a p-channel type. In this case, lowering the voltage Vbg shifts the threshold voltage Vth in the positive direction, Sta. 11 will be normally on.

[0033] FIG. 9 shows the relationship between the voltage Vbg and the threshold voltage Vth when the transistor 11 is an n-channel type. The relationship is as follows: When the voltage Vbg is 0, the threshold voltage Vth of the transistor 11 is Vth0. Then, if the voltage Vbg is shifted from 0 in the positive direction to Vbg1, the threshold voltage Vth shifts in the negative direction from Vth0 to Vth1 (Vth1<0).

[0034] When the transistor 11 is in a normally-on state, the first gate of the transistor 11 and The gate voltage Vgs, which is the potential difference between the source and the drain, is kept constant. The drain current of the transistor 11 flows through the second gate of the transistor 11 and the capacitance element 1 The configuration will flow as follows: 3.

[0035] With the above configuration, the charge stored in the second gate of the transistor 11 and the capacitor 13 is A charge is transferred, and the potential of one of the source and drain of the transistor 11 shifts. As the potential of one of the source and drain of the transistor 11 shifts, the voltage Vb As g changes, the threshold voltage of the transistor 11 shifts in the direction toward normally off. For example, if the transistor 11 is an n-channel type, the voltage Vbg is As a result, the threshold voltage Vth shifts in the positive direction. In the case of a p-channel type, the voltage Vbg shifts in the positive direction, so the threshold voltage Vth Shift in the negative direction.

[0036] Finally, the threshold voltage Vth of the transistor 11 is maintained at a constant gate voltage. As the drain current approaches the voltage Vgs, the drain current converges to 0 and the transistor 11 turns off. At this time, the threshold voltage Vth of the transistor 11 is Vth2. As shown in FIG. When the voltage Vbg becomes Vbg2, the gate voltage Vgs of the transistor is kept constant. The drain current of MOSFET 11 converges to 0. As a result, the threshold voltage Vth is corrected to Vth2. The potential difference ΔV0 is held in the capacitance element 13.

[0037] In one embodiment of the present invention, the above-described configuration prevents the threshold voltage of the transistor 11 generated between the pixels 10 from increasing. To prevent the variation of the drain voltage from affecting the value of the drain current of the transistor 11. As a result, the luminance variation between pixels can be reduced.

[0038] In FIG. 1, a gap is formed between one of the source and drain of the transistor 11 and the second gate. By controlling the voltage Vbg, the threshold voltage Vth of the transistor 11 can be corrected. The configuration of the pixel 10 in which one of the source and drain of the transistor 11 can be connected is shown. , the threshold voltage Vt of the transistor 11 is controlled by controlling the voltage Vgs between the first gate and the second gate. It may be possible to correct h.

[0039] FIG. 33 shows that the threshold voltage Vth of the transistor 11 can be corrected by controlling the voltage Vgs. The configuration of the pixel 10 shown in FIG. 33 is an example. The potential of the second gate is controlled in accordance with an image signal supplied from a line SL. A reference numeral 16 denotes a transistor that controls the supply of a potential of the wiring BL to a first gate of the transistor 11. The capacitor 13 has a function of The capacitor 18 has a function of holding a potential difference between the source and the drain of the , the second gate of the transistor 11, and one of the source and drain of the transistor 11; In one embodiment of the present invention, the above-described structure is used to generate an image signal. Before determining the value of the drain current of transistor 11 according to the By controlling the voltage Vgs between the first gate and either the source or drain, the transistor The threshold voltage Vth of the transistor 11 is corrected, and the threshold voltage Vth of the transistor 11 is adjusted between the pixels 10. This can prevent variations from occurring.

[0040] 〈Pixel configuration example 1〉 FIG. 2A shows an example of a specific configuration of the pixel 10 shown in FIG.

[0041] A pixel 10 shown in FIG. 2A includes a transistor 11, a switch 12, a capacitor 13, and a light emitting element. In addition to the optical element 14, it includes switches 15 to 17 and a capacitive element 18.

[0042] Specifically, in the pixel 10 shown in FIG. 2A, the line SL is connected to a transistor via a switch 15. The line SL is electrically connected to the first gate of the switch 15 and the and via the switch 12, the light emitting element 14 is electrically connected to a pixel electrode of the light emitting element 14. The transistor 11 has one of a source and a drain electrically connected to a pixel electrode of the light-emitting element 14. The other of the source and drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode of the light emitting element 14 is electrically connected to the wiring IL via the switch 17. The capacitor 13 has a pair of electrodes, one of which is connected to the second gate of the transistor 11. and the other end is electrically connected to the pixel electrode of the light-emitting element 14. One of the pair of electrodes of the capacitor 18 is electrically connected to the first gate of the transistor 11. The other end is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode 4 is electrically connected to the wiring CL.

[0043] Next, FIG. 2B shows, as an example, another specific configuration of the pixel 10 shown in FIG.

[0044] The pixel 10 shown in FIG. 2(B) is different from the pixel 10 shown in FIG. 2(A) in that it further includes a switch 19. The pixel 10 has a different configuration.

[0045] Specifically, in the pixel 10 shown in FIG. 2B, the line SL is connected to a transistor via a switch 15. The line SL is electrically connected to the first gate of the switch 15, Through the switch 12 and the switch 19, the light emitting element 14 is electrically connected to a pixel electrode. The transistor 11 has one of its source and drain connected to a ground potential via a switch 19. The other of the source and drain is electrically connected to the pixel electrode of the light emitting element 14 through a wiring The second gate of the transistor 11 is electrically connected to the line VL. The pixel electrode of the light-emitting element 14 is electrically connected to the wiring BL via a switch. The capacitor 13 is electrically connected to the wiring IL via the transistor 17 and the switch 19. One of the pair of electrodes is electrically connected to the second gate of the transistor 11, and the other The first electrode is electrically connected to the pixel electrode of the light emitting element 14 via a switch 19. One of the pair of electrodes of 18 is electrically connected to the first gate of the transistor 11. The other end is electrically connected to the pixel electrode of the light-emitting element 14 via a switch 19. The common electrode of the light emitting element 14 is electrically connected to the wiring CL.

[0046] Next, in the pixel 10 shown in FIG. 2A, a transistor is used for each switch. A configuration example of a pixel will now be described. A pixel 10 shown in FIG. The configuration of the pixel 10 when transistors are used as the switches 15 to 17. An example is shown in Figure 3(A).

[0047] A pixel 10 shown in FIG. 3A has a function as a transistor 11 and a switch 12. Transistor 12t and transistors 15 to 17 each having the function of a switch The transistors 15t to 17t, the capacitors 13 and 18, and the light-emitting element Has 14 children.

[0048] Specifically, the transistor 15t has a gate connected to the wiring GLa and a source or drain The other of the source and the drain is connected to the first gate of the transistor 11. The transistor 12t has a gate connected to the wiring GLb, and a source and drain connected to the wiring GLb. One of the source and drain is connected to the pixel electrode of the light emitting element 14, and the other is connected to the transistor 1 The transistor 11 is electrically connected to the source and the first gate of the transistor 1. One of the source and drain is connected to the pixel electrode of the light emitting element 14, and the other of the source and drain is connected to the wiring VL. The transistor 16t has a gate connected to the wiring GLb and a so One of the source and drain is connected to a wiring BL, and the other of the source and drain is connected to a transistor 11. The transistor 17t has a gate electrically connected to the second gate of the transistor 17t. One of the source and drain is connected to the line GLd, and the other of the source and drain is connected to the wiring IL. The pixel electrodes of the elements 14 are electrically connected to each other.

[0049] The capacitor 13 has a pair of electrodes, one of which is connected to the second gate of the transistor 11. The other end is electrically connected to the pixel electrode of the light-emitting element 14. One of the pair of electrodes of the element 18 is electrically connected to the first gate of the transistor 11. The other end is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode is electrically connected to the wiring CL.

[0050] Next, in the pixel 10 shown in FIG. 2B, a transistor is used for each switch. Next, a configuration example of a pixel will be described. When transistors are used for the switches 15 to 17 and the switch 19, An example of the configuration of the pixel 10 is shown in FIG.

[0051] The pixel 10 shown in FIG. 3B has a function as a transistor 11 and a switch 12. Transistor 12t and transistors 15 to 17 each having the function of a switch A transistor 15t to a transistor 17t, and a transistor having a function as a switch 19 The pixel includes a resistor 19t, a capacitance element 13, a capacitance element 18, and a light-emitting element 14.

[0052] Specifically, the transistor 15t has a gate connected to the wiring GLa and a source or drain The other of the source and the drain is connected to the first gate of the transistor 11. The transistor 12t has a gate connected to the wiring GLb, and a source and drain connected to the wiring GLb. One of the drains is connected to one of the source and drain of the transistor 19t. The other of these is electrically connected to the first gate of the transistor 11. The transistor 11 has a source and a drain that are connected to the source and drain of the transistor 19t. One of the two is electrically connected to the wiring VL. The transistor 16t has a gate connected to the wiring GLb, a source or a drain connected to the wiring BL, The other of the source and drain is electrically connected to a second gate of the transistor 11. The transistor 17t has a gate connected to the wiring GLd and a source and a drain connected to one of the wirings GLd and GLd. The other of the source and drain is connected to the wiring IL, and the other of the source and drain is connected to the source and drain of the transistor 19t. The gate of the transistor 19t is electrically connected to the wiring GLc The other of the source and drain is electrically connected to the pixel electrode of the light emitting element 14. is.

[0053] The capacitor 13 has a pair of electrodes, one of which is connected to the second gate of the transistor 11. the other is electrically connected to one of the source and drain of the transistor 19t. The capacitor 18 has a pair of electrodes, one of which is connected to the first The other is electrically connected to the source and drain of the transistor 19t. The common electrode of the light emitting element 14 is electrically connected to the wiring CL. It is being done.

[0054] Next, the switch 12 and the switches 15 to 17 of the pixel 10 shown in FIG. FIG. 4A shows another example of the configuration of the pixel 10 when transistors are used for the .

[0055] In the pixel 10 shown in FIG. 4A, one of the source and drain of the transistor 16t is connected to a wiring 3B in that it is electrically connected to the wiring VL instead of the BL. The configuration is different from 0.

[0056] Next, the switch 12 and the switches 15 to 17 of the pixel 10 shown in FIG. 1 and 2 are another example of a pixel 10 configuration in which a transistor is used as the switch 19. is shown in Figure 4(B).

[0057] In the pixel 10 shown in FIG. 4B, the gate of the transistor 17t is connected to the wiring GLd. The pixel 10 shown in FIG. 3B has a different configuration from the pixel 10 shown in FIG. do.

[0058] 〈Specific pixel operation example 1〉 Next, the pixel 10 shown in FIG. 3B will be taken as an example to explain the pixel structure of the light-emitting device according to one embodiment of the present invention. The basic operation will now be described.

[0059] FIG. 5 is a timing chart of potentials input to the wirings GLa to GLd and 5 shows a timing chart of the potential of the image signal Vdata input to the The timing chart shown in FIG. 3B assumes that all the transistors included in the pixel 10 are n-type. In addition, Fig. 6 and Fig. 7 show the image in each period. 6 and 7 show the operation of the pixel 10 in an easy-to-understand manner. For simplicity, transistors other than transistor 11 are illustrated as switches.

[0060] First, in a period t1, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the line GLc is applied to the line GLd, a low-level potential is applied to the line GLc, and a high-level potential is applied to the line GLd. Therefore, as shown in FIG. 6A, the transistor 12t The transistor 16t and the transistor 17t are turned on, and the transistor 15t and the transistor Zista 19t is off.

[0061] In addition, the wiring VL is at a potential Vano, the wiring BL is at a potential V0, and the wiring IL is at a potential V1. A potential Vcat is applied to the wiring CL electrically connected to the common electrode of the light emitting element 14, Therefore, the first gate of the transistor 11 (designated as node A) is supplied with a potential V1 is applied to the second gate of the transistor 11 (designated as node B), and a potential V0 is applied to the second gate of the transistor 11 (designated as node B). One of the source and drain of the transistor 11 (referred to as node C) is supplied with a potential V1 is given.

[0062] The potential Vano is a potential Vcat plus the threshold voltage Vthe of the light emitting element 14 and the transistor 11 It is desirable to set the potential higher than the sum of the threshold voltage Vth of the potential V0 is set to a value at node C such that the threshold voltage Vth of transistor 11 is shifted in the negative direction. Specifically, as shown in FIG. When g is 0, the threshold voltage Vth of the transistor 11 is Vth0. The voltage Vbg corresponding to the potential difference between node A and node B is Vbg1. In this case, the threshold voltage Vth of the transistor 11 becomes Vth1. Since the transistor 11 is normally on, the potential difference between node A and node C, that is, Transistor 11 can be turned on even though the gate voltage of 11 is 0.

[0063] When the transistor 11 is a p-channel type, the potential V0 is The potential is sufficiently low with respect to node C so as to shift the value voltage Vth in the positive direction. With the above configuration, the transistor 11 is normally on, so that the node Even if the potential difference between node A and node C, i.e., the gate voltage of transistor 11, is 0, Transistor 11 can be turned on.

[0064] Next, in a period t2, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A high-level potential is applied to the wiring GLc, a low-level potential is applied to the wiring GLd, Therefore, as shown in FIG. 6B, the transistors 12t and The transistor 16t is turned on, and the transistors 15t, 17t, and Zista 19t is off.

[0065] A potential Vano is applied to the wiring VL, and a potential V0 is applied to the wiring BL. Therefore, the state in which the potential V0 is applied to the node B is maintained, and at the start of the period t2, Since the threshold voltage Vth of transistor 11 remains shifted in the negative direction from Vth1, During the period t2, the transistor 11 is on. The current path is interrupted by switch 17, so that the drain current of transistor 11 The potentials of nodes A and C start to rise. When the potential of node C rises, the potential of node B The voltage Vbg corresponding to the potential difference between node A and node B becomes lower, and the threshold voltage Vt h shifts in the positive direction. And finally, the threshold voltage Vt When h approaches 0, the transistor 11 turns off. When Vth is 0, the potential difference between node B and node C is V0-V2.

[0066] That is, when the potential difference between the nodes B and C is V0-V2, the transistor 11 , the threshold voltage Vth is set to 0 so that the drain current converges to 0 for a gate voltage of 0. The potential difference V0-V2 between the nodes B and C is applied to the capacitance element 13. will be done.

[0067] Next, in a period t3, a high-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A low-level potential is applied to the wiring GLc, a high-level potential is applied to the wiring GLd, Therefore, as shown in FIG. 7A, the transistor 15t and the transistor The transistor 17t is turned on, and the transistors 12t, 16t, and Zista 19t is off.

[0068] In addition, the wiring VL is connected to a potential Vano, and the wiring SL is connected to a potential Vdata including image information. However, the potential V1 is applied to the wiring IL. And the node B is floating. Since the node C is in a low-voltage state, the capacitance element 13 As a result, the potential of node B changes from V0 to V0+V1-V2. Since the potential difference V0-V2 is maintained at In addition, a potential Vdata is applied to the node A, and the gate of the transistor 11 is maintained. The output voltage is Vdata-V1.

[0069] Next, in a period t4, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A low level potential is applied to the wiring GLc, a high level potential is applied to the wiring GLd, Therefore, as shown in FIG. 7B, the transistor 19t is turned on. The transistors 12t, 15t, 16t, and Sta 17t will be off.

[0070] The wiring VL is connected to a potential Vano, and the wiring VL is connected to a common electrode of the light-emitting element 14. A potential Vcat is applied to the transistor CL. When the potential of node C changes to V3, node A is at the potential Vd Node A is at potential V0-V2+V3, and node B is at potential V0-V2+V3. Even if the potential of node C changes, the potential difference V0-V2 is held in the capacitance element 13. The capacitance element 18 holds a potential difference Vdata-V1. A drain current flows between L and the gate voltage of the transistor 11. The luminance of the element 14 is determined according to the value of the drain current.

[0071] In the light-emitting device having the pixel 10 shown in FIG. Since the other of the drains is electrically isolated from the second gate of the transistor 11, The potentials of the transistors 11 and 12 can be controlled individually. When the transistor 11 is on, i.e., when the original threshold voltage Vth0 of the transistor 11 is negative, In the case where the transistor 11 has a source or drain voltage in the period t2, Charge can be stored in the capacitance element 13 until the potential of the capacitance element 13 becomes higher than the potential V0 of the second gate. Therefore, in the light-emitting device according to one embodiment of the present invention, the transistor 11 is a normally-on transistor. Even if the gate voltage is zero, the drain current converges to zero during the period t2. In addition, the threshold voltage Vth can be corrected to zero.

[0072] Therefore, the other of the source and drain of the transistor 11 and the second The gate of the pixel 1 shown in FIG. 3(A), FIG. 3(B), and FIG. 4(B) is electrically isolated from the gate of the pixel 1 In the case of a light-emitting device having the above-mentioned structure, for example, when an oxide semiconductor is used for the semiconductor film of the transistor 11, Even if the transistor 11 is normally on, the display unevenness can be reduced and high image quality can be achieved. The following display can be made.

[0073] Note that although examples of the circuit configuration are shown in FIG. 2A and FIG. 2B, one embodiment of the present invention For example, but not limited to, the switch may be located in various places. For example, in the case of FIG. 6(A), the configuration is as shown in FIG. 36(A), and in the case of FIG. 6(B), In the case of FIG. 7(A), the configuration is as shown in FIG. 37(A). In the case of FIG. 7(B), the configuration is as shown in FIG. 37(B). In each case, the switches should be adjusted in the appropriate places to achieve this configuration. It should be placed in place.

[0074] The above is the correction of the threshold voltage in the pixel 10 (hereinafter referred to as internal correction). 0 operation example. Next, in addition to the internal correction, pixel correction caused by the variation in threshold voltage When the brightness variation between the 10 pixels is suppressed by correcting the image signal (hereinafter referred to as external correction) The operation of the pixel 10 will now be described.

[0075] Taking the pixel 10 shown in FIG. 3B as an example, when external correction is performed in addition to internal correction, A timing chart of potentials input to the wirings GLa to GLd and a timing chart of potentials input to the wirings SL FIG. 8 shows a timing chart of the potential of the image signal Vdata. The timing chart shows that all the transistors included in the pixel 10 shown in FIG. This is an example of the case where the hexagonal structure is of the hexagonal type.

[0076] First, from the period t1 to the period t4, the above-mentioned The pixel 10 operates according to the description.

[0077] Next, in a period t5, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A low-level potential is applied to the wiring GLc, a high-level potential is applied to the wiring GLd, Therefore, the transistor 17t is turned on, and the transistor 12 t, transistor 15t, transistor 16t, and transistor 19t are turned off.

[0078] A potential Vano is applied to the wiring VL, and a potential V1 is applied to the wiring IL. Furthermore, the wiring IL is electrically connected to a monitor circuit.

[0079] By the above operation, the drain current of the transistor 11 is The monitor circuit detects the drain current flowing through the line IL. A signal including the value of the drain current as information is generated using the above-mentioned. In the light emitting device according to the embodiment, the potential V of the image signal supplied to the pixel 10 is controlled by using the above signal. The data value can be corrected.

[0080] It should be noted that the external correction operation performed during the period t5 does not always need to be performed after the period t4. For example, in a light emitting device, after the operation of the period from t1 to t4 is repeated several times, The operation for the period t5 may be performed in the pixels 10 of one row. After this operation, an image signal corresponding to the minimum gradation value 0 is written to the pixels 10 in the row in which this operation was performed. After the light-emitting element 14 is put into a non-emitting state by writing, the pixel 10 in the next row is The operation of t5 may be performed.

[0081] Even if external correction is performed without internal correction, the transistors between the pixels 10 In addition to the variation in the threshold voltage of the transistor 11, other characteristics of the transistor 11 such as mobility, etc. It is possible to correct the variation in electrical characteristics. However, in addition to external correction, internal correction is also possible. When this is done, the negative or positive shift of the threshold voltage is corrected by internal correction. Therefore, in the external correction, the mobility and other factors other than the threshold voltage of the transistor 11 are used. Therefore, in addition to external correction, internal correction is also performed. In this case, the amplitude of the potential of the image signal after correction is set to be, as compared with the case where only external correction is performed, Therefore, the amplitude of the potential of the image signal is too large, and the gray scale value The potential difference between the image signals becomes larger, and the brightness changes in the image become a smooth gradation. This prevents the situation where it becomes difficult to express the image in a certain way, and reduces the deterioration of image quality. This can prevent this from happening.

[0082] In the case of the pixel 10 shown in FIG. 3A, the wiring GLa and the wiring GL b, the wiring GLd, and the wiring SL according to the timing chart of the potentials applied to the wiring GLd and the wiring SL. However, in the case of the pixel 10 shown in FIG. In order to prevent the drain current of the transistor 11 from flowing to the light emitting element 14, the potential V0 is set to the The threshold voltage Vthe of the element 14 and the threshold voltage Vth of the transistor 15t are set to a potential Vca It is desirable to make it lower than the potential added to t.

[0083] In the case of the pixel 10 shown in FIG. 4A, the wiring GLa and the wiring GL According to the timing chart of the potentials applied to the wirings GLc, GLd, and SL, can be operated in the same manner.

[0084] In the case of the pixel 10 shown in FIG. 4B, the wiring GLa and the wiring GL Similarly, according to the timing chart of potentials applied to the wirings GLc and SL, It can be made to work.

[0085] For example, if external compensation is not performed, the wiring IL can be connected to the wiring CL. Alternatively, the wiring IL and the wiring CL can be combined into one, thereby eliminating the wiring IL. This can reduce the number of wirings. FIG. 38(A) shows an example in which the wiring IL is omitted. Similarly, FIG. 2(B) shows An example of this case is shown in Figure 38(B). The same can be applied to other figures.

[0086] Example of pixel section and selection circuit configuration Next, FIG. 10 shows an example of a structure of a pixel portion of a light-emitting device according to one embodiment of the present invention. In FIG. 10, a pixel section 40 has a plurality of pixels 10 arranged in a matrix. In addition, the pixel section 40 includes a wiring GL, a wiring SL, a wiring VL, a wiring BL, a wiring IL, and a wiring CL. Each of the pixels 10 has at least one of the wirings GL. At least one of the wirings SL, at least one of the wirings VL, and at least one of the wirings BL The first wiring IL is electrically connected to at least one of the wirings IL and the wiring CL.

[0087] The type and number of the wirings are determined based on the configuration, number and arrangement of the pixels 10. Specifically, in the case of the pixel section 40 shown in FIG. 10, the pixels 10 are arranged in a matrix of x columns and y rows. The wiring GL1 to the wiring GLy are electrically connected in a shape of a wiring GL A plurality of wirings SL indicated by wirings SL1 to SLx and a plurality of wirings VL1 to VLx A plurality of wirings VL, a plurality of wirings BL indicated by wirings BL1 to BLx, and wirings IL1 to ILx. A plurality of wirings IL indicated by wirings ILx and one wiring CL are arranged in the pixel section 40. This provides an example of a case where

[0088] Each wiring GL shown in FIG. 10 is a wiring GLa, a wiring GLb, a wiring GLc, or a wiring GLd, or any combination thereof.

[0089] As shown in FIG. 10, when the pixels 10 are connected in a matrix, For example, when the operations shown in FIG. 6(A), FIG. 6(B), FIG. 7(B), etc. are being performed, In the row of FIG. 6(A), for example, the operation of FIG. 7(A) can be performed. 6B and the like can be executed for a sufficiently long period of time. Therefore, correction can be performed with high accuracy.

[0090] In addition, the operations of FIG. 6(A), FIG. 6(B), etc. and the operations of FIG. 7(A), etc. are performed simultaneously in different rows. In the case where the wiring BL is not connected to the wiring SL, for example, In addition, the wiring BL and the wiring SL may be combined into one wiring, thereby eliminating the wiring BL. As a result, the number of wirings can be reduced. An example of the case where the filter is omitted is shown in FIG. 39(A). Similarly, an example of the case where the filter is applied to FIG. 2(B) is shown in FIG. As shown in Figure 39(B), the same can be applied to other figures.

[0091] In FIG. 7A and the like, during the period in which the potential Vdata of the image signal is input, 6(B), a potential difference V0-V2 between nodes B and C is applied to the capacitance element 13. In order to prevent this, in FIG. 7A and the like, the potential Vdata of the image signal is changed dot-sequentially. An example of this case is shown in FIG. Switch 60B, switch 60C, etc. are turned on in sequence under the control of circuit 61. As a result, it is possible to perform point sequential driving. Here, the circuit 61 shifts one by one. For example, the circuit 61 has a shift register. Therefore, the switch 60A, the switch 60B, and the switch 6 0C, the circuit 61 can also be said to have a function as a source line driver circuit.

[0092] Alternatively, as another example, in the plurality of wirings SL indicated by the wirings SL1 to SLx, Among the multiple wirings in the image sensor, one of the wirings is selected and the potential Vdata of the image signal is input. For example, the wiring SL1 and the wiring SL2 may be connected to the switch 62A. The wiring SL3 and the wiring SL4 are selected by the switch 62C and the switch 62B. An example of the selection between 2D and 3D is shown in FIG. 41. In FIG. 41, the wiring 63A is selected. As a result, the switches 62A and 62C are turned on, and the wiring 63B is selected. As a result, the switches 62B and 62D are turned on. However, one embodiment of the present invention is not limited to this. Furthermore, one wiring may be selected from among many wirings SL.

[0093] Next, the connection structure of the pixel section 40 and the selection circuit 41 of the light emitting device having the function of performing external correction is An example of the configuration is shown in FIG. 11. The selection circuit 41 includes a wiring 42 to which a potential V1 is applied and a monitor The selected wiring 42 and the connection terminal TER have a function of selecting one of them. It is possible to bring either one of the connection terminal TER and the wiring IL into a conductive state.

[0094] Specifically, the selection circuit 41 shown in FIG. 11 supplies the potential V1 of the wiring 42 to one wiring IL. and a switch 43 for controlling the conduction state between the one wiring IL and the connection terminal TER. and a switch 44 for switching the input / output terminals.

[0095] <Monitor circuit configuration example> Next, a configuration example of the monitor circuit 45 is shown in FIG. 12. The monitor circuit 45 shown in FIG. It includes an operational amplifier 46, a capacitive element 47, and a switch 48.

[0096] One of the pair of electrodes of the capacitance element 47 is connected to the inverting input terminal (-) of the operational amplifier 46. The other of the pair of electrodes of the capacitance element 47 is connected to the output terminal of the operational amplifier 46. The switch 48 has a function of discharging the charge stored in the capacitance element 47. Specifically, the function of controlling the electrical conduction state between a pair of electrodes of the capacitor element 47 is The non-inverting input terminal (+) of the operational amplifier 46 is connected to the wiring 49. 49 is supplied with a potential V1.

[0097] In one embodiment of the present invention, a potential V1 is supplied to the wiring IL of the pixel 10 in order to perform internal correction. In this case, the monitor circuit 45 is made to function as a voltage follower. When the switch 48 is turned on, the potential V1 supplied to the wiring 49 is The current can be supplied to the wiring IL.

[0098] In addition, when a current is extracted from the pixel 10 through the wiring IL in order to perform external correction, First, the monitor circuit 45 is made to function as a voltage follower, so that a potential V After supplying the signal 1, the monitor circuit 45 is made to function as an integrating circuit to obtain the signal 1 taken from the pixel 10. Specifically, by turning on the switch 48, the current output from the wire 4 is converted into a voltage. The potential V1 supplied to the switch 9 is supplied to the wiring IL via the monitor circuit 45. With switch 48 in the off state, the drain taken from pixel 10 When an in-current is supplied to the wiring TER, charge is stored in the capacitance element 47, and the capacitance element 47 A voltage is generated between a pair of electrodes having a drain current TER. Since the current is proportional to the total current of the operational amplifier 46, the output of the operational amplifier 46 is connected to the OUT wiring. A potential corresponding to the total amount of drain current during the period is applied.

[0099] Specific pixel configuration example 2 FIG. 13A shows an example of a specific configuration of the pixel 10 shown in FIG.

[0100] A pixel 10 shown in FIG. 13A includes a transistor 11, a capacitor 13, and a light-emitting element 14. In addition, it includes switches 15 to 17 and a capacitive element 18 .

[0101] Specifically, in the pixel 10 shown in FIG. 13A, the line SL is connected to a transistor via a switch 15. The transistor 11 is electrically connected to a first gate of the transistor 11. The transistor 11 has a source and One of the drains is electrically connected to the pixel electrode of the light emitting element 14, and the source and drain The other input of the transistor 11 is electrically connected to the wiring VL. The pixel of the light-emitting element 14 is electrically connected to the wiring BL via the switch 16. The electrode is electrically connected to the wiring IL via the switch 17. One of the pair of electrodes is electrically connected to the second gate of the transistor 11, and the other The pair of electrodes of the capacitance element 18 are electrically connected to the pixel electrodes of the light emitting element 14. The electrode is electrically connected to the first gate of the transistor 11 on one side and to the light-emitting element 12 on the other side. The common electrode of the light emitting element 14 is electrically connected to the wiring CL. are electrically connected.

[0102] Next, FIG. 13B shows another specific configuration of the pixel 10 shown in FIG. .

[0103] The pixel 10 shown in FIG. 13(B) is similar to the pixel 10 shown in FIG. 13(A) in that it further includes a switch 19. 1. The pixel 10 shown in FIG.

[0104] Specifically, in the pixel 10 shown in FIG. 13B, the line SL is connected to a transistor via a switch 15. The transistor 11 is electrically connected to a first gate of the transistor 11. The transistor 11 has a source and One of the drains is electrically connected to the pixel electrode of the light emitting element 14 via a switch 19. The other of the source and the drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode of the element 14 is electrically connected to the wiring IL via the switch 17 and the switch 19. The capacitor 13 has a pair of electrodes, one of which is connected to the second The other is electrically connected to the pixel electrode of the light-emitting element 14 via a switch 19. The capacitor 18 has a pair of electrodes, one of which is electrically connected to a transistor. The other terminal is electrically connected to the first gate of the light-emitting element 1 through the switch 19. The common electrode of the light emitting element 14 is electrically connected to the wiring CL. is connected to

[0105] Next, in the pixel 10 shown in FIG. 13A, when transistors are used for each switch, An example of the pixel configuration will be described. An example of the configuration of the pixel 10 when transistors are used as the switches 17 is shown in FIG. As shown in A).

[0106] A pixel 10 shown in FIG. 14A includes a transistor 11 and switches 15 to 17. The transistors 15t to 17t each have a function as a capacitance element 1 3, a capacitance element 18, and a light-emitting element 14.

[0107] Specifically, the transistor 15t has a gate connected to the wiring GLa and a source or drain The other of the source and the drain is connected to the first gate of the transistor 11. The transistor 11 is electrically connected to the light-emitting element 1. The other of the source and drain of the pixel electrode 4 is electrically connected to the wiring VL. The transistor 16t has a gate connected to the wiring GLb and one of a source and a drain connected to the wiring GLb. BL, and the other of the source and drain is electrically connected to the second gate of the transistor 11. The transistor 17t has a gate connected to the wiring GLd, and a source and a drain connected to the wiring GLd. One of the electrodes is connected to the wiring IL, and the other of the source and drain is connected to the pixel electrode of the light emitting element 14. and are electrically connected.

[0108] The capacitor 13 has a pair of electrodes, one of which is connected to the second gate of the transistor 11. The other end is electrically connected to the pixel electrode of the light-emitting element 14. One of the pair of electrodes of the element 18 is electrically connected to the first gate of the transistor 11. The other end is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode is electrically connected to the wiring CL.

[0109] Next, in the pixel 10 shown in FIG. 13B, when transistors are used for the switches, A configuration example of the pixel will be described. The switches 15 to 16 of the pixel 10 shown in FIG. Pixel 10 when transistors are used as switches 17 and 19 A configuration example is shown in FIG.

[0110] The pixel 10 shown in FIG. 14B includes a transistor 11 and switches 15 to 17. Transistors 15t to 17t each having a function as a switch 1 9, a capacitor 13, a capacitor 18, and a light emitting and element 14.

[0111] Specifically, the transistor 15t has a gate connected to the wiring GLa and a source or drain The other of the source and the drain is connected to the first gate of the transistor 11. The transistor 11 has a source and a drain that are electrically connected to each other. One of the source and drain of the capacitor 19t is connected to the wiring VL, and the other of the source and drain is connected to the wiring VL. The transistor 16t has a gate connected to the wiring GLb, and a source and One of the source and drain is connected to a wiring BL, and the other of the source and drain is connected to a second The gate of the transistor 17t is electrically connected to the wiring GL d, one of the source and drain is connected to the wiring IL, and the other of the source and drain is connected to the transistor The transistors 19t and 19t are electrically connected to one of the source and drain of the transistor 19t. The gate of the transistor 19t is connected to the wiring GLc, and the other of the source and drain is connected to the pixel electrode of the light emitting element 14. The electrodes are electrically connected to the respective

[0112] The capacitor 13 has a pair of electrodes, one of which is connected to the second gate of the transistor 11. the other is electrically connected to one of the source and drain of the transistor 19t. The capacitor 18 has a pair of electrodes, one of which is connected to the first The other is electrically connected to the source and drain of the transistor 19t. The common electrode of the light emitting element 14 is electrically connected to the wiring CL. It is being done.

[0113] Next, the switches 15 to 17 of the pixel 10 shown in FIG. FIG. 15A shows another example of the configuration of the pixel 10 when a transistor is used.

[0114] In the pixel 10 shown in FIG. 15A, one of the source and drain of the transistor 16t is At the point where the line VL is electrically connected instead of the line BL, the image shown in FIG. The configuration is different from element 10.

[0115] Next, the switches 15 to 17 and the switch 1 of the pixel 10 shown in FIG. FIG. 15B shows another example of the configuration of the pixel 10 when transistors 9 and 10 are used. As shown in.

[0116] In the pixel 10 shown in FIG. 15B, the gate of the transistor 17t is connected to the At the point where the pixel is electrically connected to the wiring GLa, the pixel has the same configuration as the pixel 10 shown in FIG. different.

[0117] Specific pixel operation example 2 Next, taking the pixel 10 shown in FIG. 14B as an example, The operation of the pixel will now be described.

[0118] FIG. 16 is a timing chart of potentials input to the wirings GLa to GLd and a timing chart of potentials input to the wirings S FIG. 1 shows a timing chart of the potential of the image signal Vdata input to the input terminal L. The timing chart shown in FIG. 6 is based on the transistor included in the pixel 10 shown in FIG. This is an example in which all are n-channel types.

[0119] First, in a period t1, a high-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the line GLc is applied to the line GLd, a low-level potential is applied to the line GLc, and a high-level potential is applied to the line GLd. Therefore, the transistors 15t, 16t, and Transistor 17t is turned on and transistor 19t is turned off.

[0120] In addition, the wiring SL is applied with a potential V4, the wiring VL is applied with a potential Vano, and the wiring BL is applied with a potential V0. The wiring IL is connected to a potential V1, and the wiring CL is connected to a common electrode of the light-emitting element 14. The potential Vcat is applied to the first gate ( A potential V4 is applied to the second gate of the transistor 11 (denoted as node B A potential V0 is applied to one of the source and drain of the transistor 11 (node A potential V1 is applied to a terminal C.

[0121] The potential Vano is a potential Vcat plus the threshold voltage Vthe of the light emitting element 14 and the transistor 11 It is desirable to set the potential higher than the sum of the threshold voltage Vth of the potential V0 is set to a value at node C such that the threshold voltage Vth of transistor 11 is shifted in the negative direction. Specifically, as shown in FIG. If the threshold voltage Vth of the transistor 11 when g is 0 is Vth0, then during the period At t1, the voltage Vbg corresponding to the potential difference between node B and node C is Vbg1. Thus, the threshold voltage Vth of the transistor 11 is Vth1. Since transistor 11 is normally on, the potential difference between node A and node C, that is, Even if the gate voltage of transistor 11 is V4-V1, transistor 11 can still be turned on. Cut.

[0122] When the transistor 11 is a p-channel type, the potential V0 is The potential is sufficiently low with respect to node C so as to shift the value voltage Vth in the positive direction. With the above configuration, the transistor 11 is normally on, so that the node The potential difference between node A and node C, i.e., the gate voltage of transistor 11, is V4-V1. Also, transistor 11 can be turned on.

[0123] Next, in a period t2, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A high-level potential is applied to the wiring GLc, a low-level potential is applied to the wiring GLd, Therefore, the transistor 16t is turned on, and the transistor 15 t, transistor 17t, and transistor 19t are turned off.

[0124] A potential Vano is applied to the wiring VL, and a potential V0 is applied to the wiring BL. Therefore, the state in which the potential V0 is applied to the node B is maintained, and at the start of the period t2, Since the threshold voltage Vth of transistor 11 remains shifted in the negative direction from Vth1, During the period t2, the transistor 11 is on. The current path is interrupted by switch 17, so that the drain current of transistor 11 The potentials of nodes A and C start to rise. When the potential of node C rises, the potential of node B The voltage Vbg corresponding to the potential difference between node A and node B becomes lower, and the threshold voltage Vt h shifts in the positive direction. And finally, the threshold voltage Vt When h approaches the gate voltage V4-V1 of transistor 11, transistor 11 When the threshold voltage Vth of the transistor 11 is V4-V1, the voltage at the node B and the The potential difference of node C is V0-V2.

[0125] That is, when the potential difference between the nodes B and C is V0-V2, the transistor 11 , the threshold voltage Vt h is corrected to V4-V1. The potential difference V0-V2 between node B and node C is The signal is applied to the capacitance element 13.

[0126] Next, in a period t3, a high-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A low-level potential is applied to the wiring GLc, a high-level potential is applied to the wiring GLd, Therefore, the transistor 15t and the transistor 17t are turned on. As a result, the transistor 16t and the transistor 19t are turned off.

[0127] In addition, the wiring VL is connected to a potential Vano, and the wiring SL is connected to a potential Vdata including image information. However, the potential V1 is applied to the wiring IL. And the node B is floating. Since the node C is in a low-voltage state, the capacitance element 13 As a result, the potential of node B changes from V0 to V0+V1-V2. Since a potential difference V0-V2 is maintained between the transistors 11 and 12, the threshold voltage Vth of the transistor 11 is V4. A potential Vdata is applied to node A, and transistor 1 is maintained at −V1. The gate voltage of 1 is Vdata-V1.

[0128] Next, in a period t4, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A low level potential is applied to the wiring GLc, a high level potential is applied to the wiring GLd, Therefore, the transistor 19t is turned on, and the transistor 15 t, transistor 16t, and transistor 17t are turned off.

[0129] The wiring VL is connected to a potential Vano, and the wiring VL is connected to a common electrode of the light-emitting element 14. A potential Vcat is applied to the transistor CL. When the potential of node C changes to V3, node A is at the potential Vd Node A is at potential V0-V2+V3, and node B is at potential V0-V2+V3. Even if the potential of node C changes, the potential difference V0-V2 is held in the capacitance element 13. The capacitance element 18 holds a potential difference Vdata-V1. A drain current flows between L and the gate voltage of the transistor 11. The luminance of the element 14 is determined according to the value of the drain current.

[0130] In the light-emitting device having the pixel 10 shown in FIG. The other of the drains is electrically isolated from the second gate of the transistor 11. Therefore, the transistor 11 can be controlled to have a normal When the transistor 11 is turned on, that is, when the original threshold voltage Vth0 of the transistor 11 is a negative value, In the case where one of the source and drain of the transistor 11 is Charge is stored in the capacitance element 13 until the potential becomes higher than the potential V0 of the second gate. Therefore, in the light-emitting device according to one embodiment of the present invention, the transistor 11 is a normally-off transistor. Even in the case of the MOSFET, the drain current converges to 0 for the gate voltage V4-V1 during the period t2. In order to bundle, the threshold voltage Vth can be corrected to V4-V1.

[0131] Therefore, the other of the source and drain of the transistor 11 and the second The gate of the transistor is electrically isolated from the gate of the transistor shown in FIG. 14(A), FIG. 14(B), and FIG. 15(B). In a light-emitting device having a pixel 10, for example, an oxide semiconductor is used for the semiconductor film of a transistor 11. Even if the transistor 11 becomes normally on when the This allows for high quality display.

[0132] The above corresponds to an example of the operation of the pixel 10 including the internal correction. Next, in addition to the internal correction, When the brightness variation between pixels 10 caused by the variation in the threshold voltage is suppressed by external correction, The operation of the pixel 10 in this case will be described.

[0133] Taking the pixel 10 shown in FIG. 14B as an example, when external correction is performed in addition to internal correction, during the period From t1 to t4, the timing chart shown in FIG. 16 is the same as that shown in the above description. The pixel 10 operates in this manner.

[0134] Next, in a period t5 after the period t4, a low-level potential is applied to the line GLa, and A low-level potential is applied to the wiring Lb, a low-level potential is applied to the wiring GLc, and a low-level potential is applied to the wiring G A high-level potential is applied to Ld. This turns on the transistor 17t. Transistor 15t, transistor 16t, and transistor 19t are turned off.

[0135] A potential Vano is applied to the wiring VL, and a potential V1 is applied to the wiring IL. Furthermore, the wiring IL is electrically connected to a monitor circuit.

[0136] By the above operation, the drain current of the transistor 11 is The monitor circuit detects the drain current flowing through the line IL. A signal including the value of the drain current as information is generated using the above-mentioned. In the light emitting device according to the embodiment, the potential V of the image signal supplied to the pixel 10 is controlled by using the above signal. The data value can be corrected.

[0137] It should be noted that the external correction operation performed during the period t5 does not always need to be performed after the period t4. For example, in a light emitting device, after the operation of the period from t1 to t4 is repeated several times, The operation for the period t5 may be performed in the pixels 10 of one row. After this operation, an image signal corresponding to the minimum gradation value 0 is written to the pixels 10 in the row in which this operation was performed. After the light-emitting element 14 is put into a non-emitting state by writing, the pixel 10 in the next row is The operation of t5 may be performed.

[0138] In the case of the pixel 10 shown in FIG. 14A, the wiring GLa, the wiring GLb, and the wiring The operation is similar to that described above in accordance with the timing chart of the potentials applied to the line GLd and the wiring SL. In addition, the operation of external correction can be performed in the same manner as in the pixel shown in FIG. However, in the case of the pixel 10 shown in FIG. 14A, during the period t2, In order to prevent the drain current of the capacitor 11 from flowing to the light emitting element 14, the potential V0 is set to the threshold voltage of the light emitting element 14. The threshold voltage Vth of the transistor 15t is added to the potential Vcat. It is desirable to make the potential lower than the potential.

[0139] In the case of the pixel 10 shown in FIG. 15A, the wiring GLa, the wiring GLb, and the wiring According to the timing chart of the potentials applied to the line GLc, the wiring GLd, and the wiring SL, The operation of external correction can be performed in the same manner as the pixel shown in FIG. This can be done in the same way.

[0140] In the case of the pixel 10 shown in FIG. 15B, the wiring GLa, the wiring GLb, and the wiring The operation is similar to that described above in accordance with the timing chart of the potentials applied to the line GLc and the wiring SL. In addition, the operation of external correction can be performed in the same manner as in the pixel shown in FIG. can be done.

[0141] <Transistor configuration example 1> Next, a transistor in which a channel formation region is formed using an oxide semiconductor film (OS transistor This article explains about the gyroscope.

[0142] Figures 27(A), 27(B), and 27(C) show three transistors with different device structures. The top view (layout diagram) of the resistors (TA1, TA2, TB1) and their respective circuit symbols are shown below. FIG. 28 is a cross-sectional view of the transistors (TA1, TA2, and TB1). TA1 is a cross-sectional view taken along the lines a1-a2 and b1-b2. Cross-sectional views taken along lines a4 and b3-b4, and lines a5-a6 of transistor TB1; The cross-sectional views taken along the line b5-b6 are shown in FIG. 28(A) and FIG. 28(B). The cross-sectional structure in the channel length direction is shown in FIG. 28(A), and the cross-sectional structure in the channel width direction is shown in FIG. Shown in Figure 28(B).

[0143] As shown in FIG. 28(A) and FIG. 28(B), the transistors (TA1, TA2, TB1) are These transistors are integrated on the same insulating surface and are fabricated in the same manufacturing process. In order to clarify the device structure, the structure of each transistor is shown in Fig. Wiring for supplying potential and power to the gate (G), source (S), and drain (D) Electrical connections to the wires are omitted.

[0144] The transistor TA1 (FIG. 27(A)) and the transistor TA2 (FIG. 27(B)) have gates The transistor has a gate (G) and a back gate (BG). One of the gates (BG) corresponds to the first gate and the other corresponds to the second gate. The transistors TA1 and TA2 have a structure in which the back gate is connected to the gate. The transistor TB1 (FIG. 27(C)) is a transistor that does not have a BG. As shown in FIG. 28, these transistors (TA1, TA2, TB1) are The configuration of these transistors will be described below with reference to FIGS. 27 and 28. do.

[0145] (Transistor TA1) The transistor TA1 includes a gate electrode GE1, a source electrode SE1, a drain electrode DE1, and a The gate electrode BGE1 and the oxide semiconductor film OS1 are provided.

[0146] In the following description, the transistor TA1 is referred to as TA1, and the back gate is referred to as BG. The oxide semiconductor film OS1 is referred to as OS1 or film OS1, and the elements and components of the elements are omitted. Similarly, signals, potentials, circuits, and the like may also be abbreviated.

[0147] In this embodiment, the channel length of the OS transistor is determined by dividing the length of the source electrode and the drain electrode by the distance between the source electrode and the drain electrode. The channel width of the OS transistor is the distance between the oxide semiconductor film and the gate electrode. The width of the source electrode or drain electrode in the overlapping region is defined as the width of the The channel length is La1 and the channel width is Wa1.

[0148] The film OS1 overlaps with the electrode GE1 via the insulating film 34. A pair of electrodes (SE1, DE1) are formed in contact with the substrate. As shown in FIG. The membrane OS1 has a portion that does not overlap with the electrode GE1 and the pair of electrodes (SE1, DE1). The length of the film OS1 in the channel length direction is longer than the channel length La1, and The length in the width direction is longer than the channel width Wa1.

[0149] An insulating film 35 is formed to cover the film OS1, the electrode GE1, the electrode SE1, and the electrode DE1. An electrode BGE1 is formed on the insulating film 35. The electrode BGE1 is formed by a film OS1 and The electrode GE1 is provided so as to overlap with the electrode GE1. The electrode BGE1 is provided so as to be arranged at the same position as the insulating film. 34 is in contact with the electrode GE1 in an opening CG1 penetrating the insulating film 35 and the insulating film 36. This structure electrically connects the gate and back gate of the transistor TA1. .

[0150] By connecting the back gate electrode BGE1 to the gate electrode GE1, The on-current can be increased. By providing the back gate BGE1, The strength of the electrode BG can be improved against deformation such as bending of the substrate 30. E1 acts as a reinforcing member to make the transistor TA1 less likely to break.

[0151] The film OS1 including the channel formation region has a multi-layer structure. Here, as an example, three oxides are used. The semiconductor film OS1 has a three-layer structure consisting of oxide semiconductor films (31, 32, 33). The conductive film is preferably a metal oxide film containing at least one of the same metal elements, and In It is particularly preferable that the semiconductor film of the transistor contains In. Metal oxide films include In-Ga oxide film, In-M-Zn oxide film (where M is Al, Ga, The typical examples of the metal oxide film are Y, Zr, La, Ce, and Nd. Films containing added other elements or materials may also be used.

[0152] "32" is a film that constitutes the channel forming region of the transistor TA1. " constitutes the channel forming regions of the transistor TA2 and the transistor TB1 described later. Therefore, the required thickness of the transistor TA2 and the transistor TB1 is Depending on the electrical properties (e.g., field effect mobility, threshold voltage, etc.), oxides of appropriate composition are selected. For example, an oxide semiconductor film can be used so that a channel is formed at "33". It is preferable to adjust the composition of the metal elements that are the main components of the conductor films 31-32.

[0153] In the transistor TA1, a channel is formed at "32". This can prevent the panel formation region from contacting the insulating films 34 and 35. By making the body films 31 and 32 metal oxide films containing at least one of the same metal elements, At the interface between 『31』 and 『32』 and 『33』, interface scattering is unlikely to occur. This allows the field effect mobility of the transistor TA1 to be reduced. It can be made higher than TA2 and transistor TB1, and the drain voltage in the on state The current (on-current) can be increased.

[0154] (Transistor TA2) The transistor TA2 includes a gate electrode GE2, a source electrode SE2, a drain electrode DE2, and a The gate electrode BGE2 and the oxide semiconductor film OS2 are insulating The electrode GE2 is in contact with the opening CG2 penetrating the film 34 through the insulating film 36. The transistor TA2 is a modification of the transistor TA1, in which the film OS2 is not an oxide semiconductor film 33. The transistor TA1 is different from the transistor TA1 in that it has a single-layer structure. Then, the channel length La2 and the channel width Wa2 of the transistor TA2 are The channel length La1 and the channel width Wa1 of the first embodiment are set to be equal to those of the first embodiment.

[0155] (Transistor TB1) The transistor TB1 has a gate electrode GE3, a source electrode SE3, a drain electrode DE3 and a The transistor TB1 is a modified example of the transistor TA2. As in the transistor TA2, the film OS3 has a single-layer structure made of an oxide semiconductor film 33. The transistor TA1 differs from the transistor TA2 in that it does not have a back gate electrode. The layout of OS3 and electrodes (GE3, SE3, DE3) is different. As shown in the figure, the region of the membrane OS3 that does not overlap with the electrode GE3 is connected to the electrode SE3 or the electrode DE3. 3. Therefore, the channel width Wb1 of the transistor TB1 is The channel length Lb1 is determined by the width of the electrode SE, as in the transistor TA2. 3 and the electrode DE3, where the channel length La2 of the transistor TA2 is It's longer than that.

[0156] [Insulating film] The insulating films 34, 35 and 36 are formed on the transistors (TA1, TA2 , TB1) are formed in the entire region where the insulating film 34, the insulating film 35, and The insulating film 36 is formed of a single layer or multiple layers of insulating film. The insulating film 35 and the insulating film 36 are films that constitute the gate insulating film of the gate insulating film 35 (TA1, TA2, TB1). The insulating film 36 is a gate insulating film on the back channel side of the transistors (TA1, TA2, TB1). The insulating film 36 on the top surface is a film that constitutes an insulating film. It is preferable that the insulating film 36 is made of a material that functions as a protective film for the transistor. To insulate the third layer electrode BGE1 from the second layer electrodes (SE1, DE1), In addition, at least one insulating film may be present between them.

[0157] The insulating films 34 to 36 may be formed of a single layer insulating film or a multilayer insulating film having two or more layers. The insulating films 34 to 36 can be made of aluminum oxide. Aluminum, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, nitrogen silicon oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, Examples of the film include films made of lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. These insulating films can be formed by sputtering, CVD, MBE, ALD, or It can be formed by using a PLD method.

[0158] [Oxide semiconductor film] Here, an oxide semiconductor film which forms a semiconductor film of an OS transistor will be described. When the semiconductor film has a multi-layer structure as in OS1, the oxide semiconductor film constituting the multi-layer structure is small. It is preferable that the metal oxide film contains at least one of the same metal elements, and that the metal oxide film contains In. preferable.

[0159] For example, if "31" is an In-Ga oxide film, the atomic ratio of In is set higher than the atomic ratio of Ga. In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or In the case of Nd), the atomic ratio of In is made smaller than the atomic ratio of M. In this case, the atomic ratio of Zn The numerical ratio can be maximized.

[0160] For example, if the number of atoms of In is 32, the number of atoms of Ga is 32. In the case of an In-M-Zn oxide film, the atomic ratio of In is made larger than the atomic ratio of M. In the In-M-Zn oxide film, the atomic ratio of In is higher than the atomic ratios of M and Zn. It is preferable to make it larger.

[0161] For example, if "33" is an In-Ga oxide film, the atomic ratio of In is set to the same as the atomic ratio of Ga. In the case of an In-M-Zn oxide film, the ratio of the number of In atoms to the number of M atoms is increased or decreased. In this case, the atomic ratio of Zn should be larger than that of In and M. Here, "33" is the transistor TA2 and transistor TB1, which will be described later. It is also a film that constitutes the channel forming region.

[0162] The atomic ratio of the oxide semiconductor films 31 to 33 is In the case of CVD, this is possible by adjusting the atomic ratio of the target's constituent materials. When forming a film by this method, it is possible to adjust the flow rate ratio of the raw material gases. The semiconductor film 31 to the oxide semiconductor film 33 are formed by sputtering an In-M-Zn oxide The targets used in film formation are described below using the case of forming a thin film as an example. To deposit the film, a target made of In-M-Zn oxide is used.

[0163] The atomic ratio of the metal elements in the target "31" is In:M:Zn=x1:y1:z1. and 、 It is preferable that x1 / y1 is 1 / 6 or more and less than 1. Also, z1 / y1 is 1 / It is preferably 3 or more and 6 or less, and more preferably 1 or more and 6 or less.

[0164] Representative examples of the atomic ratio of the target metal elements are In:M:Zn=1:3:2, In :M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4: 6, In:M:Zn=1:4:7, In:M:Zn=1:4:8, In:M:Zn=1: 5:5, In:M:Zn=1:5:6, In:M:Zn=1:5:7, In:M:Zn= 1:5:8, In:M:Zn=1:6:8, etc.

[0165] The atomic ratio of the metal elements in the target "32" is In:M:Zn=x2:y2:z2. and 、 It is preferable that x2 / y2 is greater than 1 and equal to or less than 6. Also, z2 / y2 is greater than 1 and equal to or less than 6. The atomic ratio of the metal elements in the target is preferably greater than 6. is In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Z n=2:1:3, In:M:Zn=3:1:2, In:M:Zn=3:1:3, In:M :Zn=3:1:4 etc.

[0166] The atomic ratio of the metal elements in the target "33" is In:M:Zn=x3:y3:z3. and 、 It is preferable that x3 / y3 is 1 / 6 or more and 1 or less. Also, z3 / y3 is 1 / It is preferably 3 or more and 6 or less, and more preferably 1 or more and 6 or less. Representative examples of the molecular ratio are In:M:Zn=1:1:1 and In:M:Zn=1:1:1. 2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1: 3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In:M:Zn= 1:4:5, In:M:Zn=1:4:6, In:M:Zn=1:4:7, In:M:Z n=1:4:8, In:M:Zn=1:5:5, In:M:Zn=1:5:6, In:M :Zn=1:5:7, In:M:Zn=1:5:8, In:M:Zn=1:6:8 etc. do.

[0167] In the deposition target for the In-M-Zn oxide film, the atomic ratio of metal elements is In:M: When Zn=x:y:z, by setting 1≦z / y≦6, the In-M-Zn oxide film can be obtained. This is preferable because it is easy to form a CAAC-OS film. More details will be given later.

[0168] The oxide semiconductor films 31 to 33 are each formed of an oxide semiconductor having a low carrier density. For example, the oxide semiconductor films 31 to 33 are formed using oxide semiconductor films having a carrier density is 1×10 17 pieces / cm 3 Less than or equal to 1×10 15 pieces / cm 3 The following is more preferable: 1×10 13 pieces / cm 3 The following oxide semiconductor film is used. In particular, the oxide semiconductor film 31 The oxide semiconductor film 33 has a carrier density of 8×10 11 pieces / cm 3 Less than, better Preferably 1×10 11 pieces / cm 3 less than 1×10 10 pieces / cm 3 Less than Yes, and 1×10 -9 pieces / cm 3 It is preferable to use any of the above oxide semiconductor films.

[0169] The oxide semiconductor films 31 to 33 each have a low impurity concentration and a low density of defect states. By using a low-temperature oxide semiconductor film, a transistor with better electrical characteristics can be fabricated. Here, the impurity concentration is low and the defect level density is low (there is little oxygen vacancy). High purity authentic or substantially high purity authentic means that the Intrinsic oxide semiconductors have a low carrier density because they have few carrier generation sources. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film can be formed. The transistor has electrical characteristics in which the threshold voltage is negative (also called normally on). In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film is Since the defect level density is low, the trap level density may also be low. The oxide semiconductor film that is substantially intrinsic or highly pure has an extremely small off-state current and a large channel width. is 1×10 6 Even if the device has a channel length L of 10 μm, the source and drain electrodes When the electrode voltage (drain voltage) is in the range of 1V to 10V, the off-state current is Below the measurement limit of the meter analyzer, i.e. 1×10 -13 Obtaining a characteristic of A or lower Therefore, a transistor in which a channel region is formed in the oxide semiconductor film can be The fluctuation of electrical characteristics is small, resulting in a highly reliable transistor. The metals include elements such as elements of alkali metals, alkaline earth metals, and the like.

[0170] Hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water and an acid. Oxygen vacancies are formed in the lattice from which the atoms are desorbed (or in the part from which oxygen is desorbed). When hydrogen enters the electron carrier, it can generate electrons. When it bonds with oxygen, which bonds with a metal atom, it may generate electrons, which act as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen has normally-on characteristics. Easy to use.

[0171] As a result, hydrogen is generated in addition to oxygen vacancies in the oxide semiconductor films 31 to 33. Specifically, the oxide semiconductor films 31 to 32 are preferably In the film 33, secondary ion mass spectrometry (SIMS) was used. The hydrogen concentration obtained by ss Spectrometry was calculated as 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 at oms / cm 3 Less than 1 x 10 18 atoms / cm 3 More preferably, 5×10 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 The following applies.

[0172] The oxide semiconductor films 31 to 33 each contain silicon or carbon, which is one of Group 14 elements. If oxygen is contained in the film, oxygen vacancies in the film increase, and the film becomes n-type. The concentrations of silicon and carbon in the nitride semiconductor film 31 and the oxide semiconductor film 33 (secondary ion mass) The concentration obtained by quantitative analysis is 2 x 10 18 atoms / cm 3 Below, preferably 2 ×1017 atoms / cm 3 The following applies.

[0173] In addition, the oxide semiconductor films 31 to 33 were analyzed by secondary ion mass spectrometry. The resulting concentration of alkali metal or alkaline earth metal is expressed as 1×10 18 atoms / c m 3 Less than or equal to 2×10 16 atoms / cm 3 The following are the alkali metals and Alkaline earth metals can generate carriers when bonded to oxide semiconductors, which can lead to transistors. As a result, the off-state current of the oxide semiconductor film 31 to the oxide semiconductor film 32 may increase. It is preferable to reduce the concentration of alkali metal or alkaline earth metal in the semiconductor film 33 .

[0174] When nitrogen is contained in the oxide semiconductor films 31 to 33, the electrons acting as carriers can be easily This causes the formation of electrons, increases the carrier density, and makes it easier to convert to n-type. Since a transistor using a semiconductor tends to have normally-on characteristics, the oxide semiconductor film 31 The nitrogen content in the oxide semiconductor film 33 is preferably as low as possible. For example, the nitrogen concentration obtained by secondary ion mass spectrometry is 5 × 10 18 atoms / cm 3 Below Preferably, it is placed below.

[0175] Although the oxide semiconductor films 31 to 33 have been described above, the present invention is not limited to these. , the semiconductor characteristics and electrical characteristics of the required transistors (field effect mobility, threshold voltage In addition, an oxide semiconductor film having an appropriate composition may be used depending on the type of transistor required. In order to obtain semiconductor characteristics and electrical characteristics of the oxide semiconductor films 31 to 3 3. Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density It is preferable to set the degree, etc., appropriately.

[0176] The transistor TA1 is a Ga or M (M is Al, Ga, Y, Zr, La, Ce, or A channel is formed in the oxide semiconductor film 32 in which the atomic ratio of In is larger than the atomic ratio of Nd. This allows the field effect mobility to be increased. Typically, the field effect mobility is , 10cm 2 / Vs > 60cm 2 / Vs, preferably less than 15cm 2 / Vs or more 50cm 2 / Vs. Therefore, there is no possibility of causing a disturbance in the circuit of the active matrix display device. When the transistor TA1 is used, it is suitable for a drive circuit that requires high speed operation.

[0177] It is also preferable to provide the transistor TA1 in a light-shielded area. By providing a transistor TA1 having a high mobility in the drive circuit, the drive frequency can be increased. Therefore, a display device with higher resolution can be realized.

[0178] The transistors TA2 and TB1, in which the channel formation region is formed of the oxide semiconductor film 33, It has a lower field effect mobility than the transistor TA1 and its size is 3 cm 2 / Vs or more 10 cm 2 The transistors TA2 and TB1 have an oxide semiconductor film 32. Since it is not exposed to light, it is less susceptible to deterioration by light than the transistor TA1. The increase in current is small. Therefore, the channel formation region is formed in the oxide semiconductor film 33. The transistors TA2 and TB1 are suitable for a pixel portion that is irradiated with light.

[0179] The transistor TA1 has the following characteristics in comparison with the transistor TA2 that does not include the oxide semiconductor film 32: When light is irradiated, the current in the off state tends to increase. This is why it is suitable for peripheral driving circuits that are less affected by light than pixel areas where light cannot be sufficiently shielded. Of course, there are transistors with configurations like transistors TA2 and TB1. A capacitor may also be provided in the drive circuit.

[0180] The transistors (TA1, TA2, and TB1) and the oxide semiconductor film 31 to the oxide semiconductor film However, the present invention is not limited to this, and may be applied to any other film having the required semiconductor characteristics and The structure of the transistor may be changed depending on the electrical characteristics. For example, the back gate electrode The presence or absence of a gate electrode, a source electrode, and a drain electrode, a stacked structure of an oxide semiconductor film, The shape and arrangement of the rain electrodes can be changed as appropriate.

[0181] (Structure of oxide semiconductor) Next, the structure of the oxide semiconductor will be described.

[0182] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0183] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0184] Oxide semiconductor films are classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Alternatively, oxide semiconductors are divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. do.

[0185] As the non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductors made of crystalline oxides include semiconductors made of microcrystalline oxides and amorphous oxides. The materials include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Semiconductors, etc.

[0186] First, we will explain the CAAC-OS film.

[0187] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0188] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0189] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0190] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction approximately perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0191] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. From this, it can be seen that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. You can see that it is oriented vertically.

[0192] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0193] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0194] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0195] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0196] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0197] Next, a microcrystalline oxide semiconductor film will be described.

[0198] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0199] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nanobeam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. If you do this, you may see a circular (ring-shaped) area of ​​high brightness. When nanobeam electron diffraction was performed on the nc-OS film, multiple spots were observed within the ring-shaped region. It may be observed.

[0200] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0201] Next, the amorphous oxide semiconductor film will be described.

[0202] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0203] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0204] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0205] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Oxide Semiconductor (a-like OS) The conductor membrane is called the endothelium.

[0206] In the a-like OS film, voids are observed in the high-resolution TEM image. In addition, crystals may be clearly visible in high-resolution TEM images. The a-like OS film has a region in which a crystal part is not observed and a region in which a crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed in TEM observations, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the small amount of charge observed by TEM can be observed. Almost no crystallization due to electron irradiation was observed.

[0207] The size of the crystals in the a-like OS film and the nc-OS film was measured using a high-resolution T This can be done using EM images. For example, InGaZnO4 crystals have a layered structure, There are two Ga-Zn-O layers between the In-O layers. Unit cell of the InGaZnO4 crystal The layer has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. The spacing between adjacent layers is therefore the (009) plane. This is approximately the same as the lattice spacing (also called the d value), and crystal structure analysis has determined that this value is 0.29 nm Therefore, we focused on the lattice fringes in high-resolution TEM images and In the region where the distance is between 0.28 nm and 0.30 nm, the lattice fringes are InG aIt corresponds to the ab plane of the ZnO4 crystal.

[0208] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the membrane is known, the density can be determined by comparing it with that of a single crystal of the same composition. The structure of the oxide semiconductor film can be estimated. The density of the OS-like film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film was 92.3% or more. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is The film formation itself is difficult.

[0209] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor film that satisfies the ratio of the number of ZnO atoms to the number of ZnO atoms, single crystal InGaZnO4 with a rhombohedral crystal structure is The density of is 6.357g / cm 3Therefore, for example, In:Ga:Zn=1:1:1 In the oxide semiconductor film that satisfies the atomic ratio, the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1: In the oxide semiconductor film that satisfies the atomic ratio of 1, the density of the nc-OS film and the CAAC- The density of the OS film is 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0210] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, it is possible to calculate the density equivalent to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions. However, the density should be calculated using as few types of single crystals as possible. It is preferable to perform the calculation in combination.

[0211] Note that the oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a microcrystalline oxide semiconductor film. The semiconductor layer may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0212] As described above, the OS transistor can achieve extremely excellent off-state current characteristics.

[0213] [Substrate 30] The substrate 30 may be any of a variety of substrates and is not limited to any particular one. Examples of the substrate 30 include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI Substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel substrate, Substrate with stainless steel foil, tungsten substrate, tungsten foil A substrate having a fibrous material, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film Examples of glass substrates include barium borosilicate glass and aluminoborose glass. The materials used are fluoride glass, soda lime glass, etc. Flexible substrates, lamination films, substrates Examples of material films include the following: Polyethylene naphthalate (PET), Polyethylene naphthalate (PEN), Polyethersulfone ( One example is a plastic such as acrylic. Examples include polypropylene, polyester, and polyvinyl fluoride. Examples of the material include polyamide, polyimide, and polyvinyl chloride. Aramid, epoxy, inorganic deposition film, paper, etc. In particular, semiconductor substrates, single crystal By manufacturing transistors using a crystalline substrate or SOI substrate, the characteristics and size The transistors are small in size, have small variations in size and shape, and have high current capacity. When a circuit is constructed using such transistors, the circuit consumes less power. This allows for reduced power consumption and higher circuit integration.

[0214] Before forming the gate electrodes (GE1, GE2, GE3), a base insulating film is formed on the substrate 30. The base insulating film may be made of silicon oxide, silicon oxynitride, silicon nitride, or nitride. Silicon oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide The insulating film may be made of silicon nitride, gallium oxide, or aluminum oxide nitride. By using tantalum oxide, hafnium oxide, yttrium oxide, aluminum oxide, etc., the substrate 30 Impurities (typically alkali metals, water, hydrogen, etc.) are removed from the oxide semiconductor film (OS1-OS3 ) can be suppressed.

[0215] [Gate electrodes (GE1, GE2, GE3)] The gate electrodes (GE1, GE2, GE3) are made of a single layer of conductive film or a stack of two or more conductive films. It is a multi-layered film. It is formed as gate electrodes (GE1, GE2, GE3). The conductive film is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten. or an alloy containing the above-mentioned metal elements or the above-mentioned metal elements. It can be formed by using a combination of alloys, etc. Also, manganese, zirconium, etc. Alternatively, one or more metal elements selected from the above may be used. Select from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film or a nitride film made by combining one or more of the above may be used. Indium tin oxide, indium oxide with tungsten oxide, indium oxide with tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide Oxide, indium zinc oxide, indium tin oxide containing silicon oxide, etc. A conductive material that is suitable for the purpose may also be applied.

[0216] For example, the gate electrodes (GE1, GE2, GE3) are aluminum films containing silicon. When the gate electrodes (GE1, GE2, GE3) have a two-layer structure, For example, a titanium film is formed on an aluminum film, or a titanium film is formed on a titanium nitride film. forming a tungsten film on a titanium nitride film; forming a tantalum nitride film or a tungsten nitride film A tungsten film is formed on the tungsten film. The gate electrodes (GE1, GE2, GE 3) In the case of a three-layer structure, for example, a titanium film and an aluminum film on the titanium film are The titanium film may be formed on the first and second layers.

[0217] By sputtering, vacuum deposition, pulsed laser deposition (PLD), thermal CVD, etc. Gate electrodes (GE1, GE2, GE3) are formed.

[0218] The tungsten film can be formed using a film forming apparatus that uses ALD. In this case, WF6 gas and B2H6 gas are introduced in sequence to form the initial tungsten film. Then, WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. SiH4 gas may be used in place of 2H6 gas.

[0219] The gate electrodes GE1-GE3 can be formed by the above-mentioned method, as well as by electrolytic plating, printing, ink jet printing, etc. This can be done by the coujet method or the like.

[0220] [Insulating film 34 (gate insulating film)] An insulating film 34 is formed to cover the gate electrodes GE1-GE3. The insulating film 34 is a single-layer insulating film. The insulating film formed as the insulating film 34 is a multi-layer insulating film having a structure of two or more layers. Examples of the insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. In this specification, an oxynitride is a material that contains more oxygen than nitrogen. A peroxide is a material that contains more nitrogen than oxygen.

[0221] The insulating film formed as the insulating film 34 may be, for example, silicon oxide or silicon oxynitride. , silicon oxide nitride, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide Alternatively, an insulating film made of Ga-Zn-based metal oxide or the like can be formed. Hafnium silicate (HfSiO x ), nitrogen-added Hafniu HfSi x O y N z ), nitrogen-doped hafnium aluminate (Hf Al x O y N z ), hafnium oxide, yttrium oxide, and other high-k materials By using high-k materials, the gate leakage of transistors can be reduced. can be reduced.

[0222] The insulating film 34 is a film that constitutes a gate insulating film, and therefore is an oxide semiconductor film (OS1, OS2, In order to improve the interface characteristics between the OS3) and the gate insulating film, the insulating film 34 is The area in contact with (OS1, OS2, OS3) is formed with an oxide insulating film or an oxynitride insulating film. For example, the top layer of the insulating film 34 is preferably a silicon oxide film or an oxide A silicon nitride film may be used.

[0223] The thickness of the insulating film 34 may be, for example, 5 nm to 400 nm. Alternatively, it is 10 nm or more and 300 nm or less, and more preferably, it is 50 nm or more and 250 nm or less. It is.

[0224] When oxide semiconductor films (OS1, OS2, and OS3) are formed by sputtering, The power supply for generating the radiator can be an RF power supply, an AC power supply, a DC power supply, etc. It can be used.

[0225] The sputtering gas may be a rare gas (typically argon) atmosphere, an oxygen atmosphere, a rare gas and In the case of a mixed gas of rare gas and oxygen, the rare gas is It is preferable to increase the gas ratio of oxygen.

[0226] The target is selected according to the composition of the oxide semiconductor film (OS1, OS2, OS3) to be formed. It is sufficient to select an appropriate one based on the above.

[0227] Note that when a sputtering method is used to form the oxide semiconductor films (OS1, OS2, and OS3), In this case, the substrate temperature is set to 150° C. or higher and 750° C. or lower, preferably 150° C. or higher and 450° C. or lower, and The oxide semiconductor films 31 and 32 can be formed by heating at a temperature of preferably 200° C. or higher and 350° C. or lower. A CAAC-OS film can be formed.

[0228] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0229] By suppressing the inclusion of impurities during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be reduced. In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of 80° C. or less, preferably −100° C. or less, is used.

[0230] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and 100% by volume or more is preferably 100% by volume or more. Product % is more preferred.

[0231] The oxide semiconductor film is formed while being heated, or after the oxide semiconductor film is formed, By the heat treatment, the hydrogen concentration in the oxide semiconductor film was increased to 2 × 10 20 atoms / cm 3 Below Lower, preferably 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19 at oms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than 1 x 10 18 a toms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Below are some more Preferably 1×10 16 atoms / cm 3 It can be as follows:

[0232] The heat treatment is carried out at a temperature higher than 350°C and lower than 650°C, preferably at a temperature higher than 450°C and lower than 600°C. By carrying out the above steps, the CAAC conversion rate described below is 70% or more but less than 100%, preferably 80%. More preferably, the ratio is 90% or more and less than 100%, more preferably 95% or more and less than 98%. % or less. In addition, the content of hydrogen, water, and the like is reduced. That is, it is possible to obtain an oxide semiconductor film having a low impurity concentration and a low defect state density. In this way, an oxide semiconductor film with low thermal conductivity can be formed.

[0233] An oxide semiconductor film can be formed using a deposition system that uses ALD. For example, InG aZnO X When forming a (X>0) film, In(CH3)3 gas and O3 gas are sequentially repeated. Repeatedly introduce Ga(CH3)3 gas and O3 gas to form an InO2 layer. Then, Zn(CH3)2 gas and O3 gas are introduced at the same time to form a GaO layer. The ZnO layer is formed by the above-mentioned method. Note that the order of these layers is not limited to this example. By mixing the materials, InGaO2 layers, InZnO2 layers, GaInO layers, ZnInO layers, GaZnO layers, Alternatively, a mixed compound layer such as a SiO2 layer may be formed. Note that an inert gas such as Ar may be used instead of O3 gas. Although bubbled H2O gas may be used, it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2H5)3 gas may be used. In addition, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. n(CH3)2 gas may also be used.

[0234] The oxide semiconductor film 32 and the oxide semiconductor film 33 are used as a gate insulating film. The thickness of the film can be 3 nm or more and 200 nm or less. , preferably 3 nm to 100 nm, and more preferably 30 nm to 50 nm. The thickness of the oxide semiconductor film 31 is, for example, 3 nm to 100 nm. It is preferably 3 nm or more and 30 nm or less, and more preferably 3 nm or more and 15 nm or less. The oxide semiconductor film 31 is thinner than the oxide semiconductor film 32 and the oxide semiconductor film 33. It is preferable to form the

[0235] Here, the oxide semiconductor films 31, 32, and 33 are formed by sputtering In-Ga-Zn films. The atomic ratio of the metal elements in the targets used for these films (In:G a:Zn) is, for example, 1:3:6 for the oxide semiconductor film 31, and The oxide semiconductor film 33 has a thickness of 1:1:1.2 or 1:1:1. The oxide semiconductor films 31, 32, and 33 have thicknesses of 5 nm and 35 nm, respectively. m, 35 nm.

[0236] [Source electrode, drain electrode] The electrodes (SE1, DE1, SE2, DE2, SE3, DE3) are gate electrodes (GE1, GE 2, GE3) can be formed in the same manner.

[0237] For example, a copper-manganese alloy film having a thickness of 50 nm, a copper film having a thickness of 400 nm, and a copper film having a thickness of 100 nm m copper-manganese alloy film, and then these films are laminated by the sputtering method. It is possible to form a three-layer electrode (SE1, DE1, SE2, DE2, SE3, DE3). can.

[0238] Transistors that operate at high speed, such as those used in the driver circuits of light-emitting devices, The saturation transistors are transistors (TA1, TA2) or transistors (TA3, TA4, It is preferable to shorten the channel length, as in the case of TC1. The channel length is preferably less than 2.5 μm. For example, it is preferable to set the channel length to 2.2 μm or less. In the transistor of this embodiment, the channel length is the distance between the source electrode and the drain electrode. Therefore, the minimum channel length is determined by the number of electrodes (SE1, DE1, SE2, DE2, S The transistor of this embodiment is limited by the precision of processing the conductive film that becomes the transistor E3, DE3). For example, the channel length can be 0.5 μm or more, or 1.0 μm or more. do.

[0239] [Insulating film 35, 36] For example, a two-layer insulating film can be formed as "35". The first layer of the film of ".5" is called insulating film 35a, and the second layer is called insulating film 35b.

[0240] The insulating film 35a may be, for example, an oxide insulating film made of silicon oxide or the like, or a film containing nitrogen. It is possible to form an oxide insulating film containing nitrogen and having few defects. Typical examples of oxide insulating films with low oxidation resistance include a silicon oxynitride film and an aluminum oxynitride film. etc.

[0241] The oxide insulating film with few defects shows a high ESR spectrum below 100K. The first signal has a g value between 2.037 and 2.039, and the second signal has a g value between 2.001 and 2. A second signal with a g value of 0.003 or less, and a third signal with a g value of 1.964 to 1.966 or less. The split width of the first signal and the second signal, and the The split width of the first signal and the third signal is about 5 m in the X-band ESR measurement. T. The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2.0 A second signal with a g value between 1.01 and 2.003, and a second signal with a g value between 1.964 and 1.966, The total spin density of a third signal is 1×10 18 spins / cm 3 Less than , typically 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 less than It is.

[0242] In addition, in the ESR spectrum below 100K, the g value is between 2.037 and 2.039. The first signal, the second signal with a g value between 2.001 and 2.003, and the g value between 1. The third signal, between 964 and 1.966, is nitrogen oxides (NOx, where x is between 0 and 2). Representative examples of nitrogen oxides include: Nitric oxide, nitrogen dioxide, etc. That is, the first group has a g value of 2.037 or more and 2.039 or less. A signal with a g-value between 2.001 and 2.003, and a second signal with a g-value between 1.96 and 2.003. The smaller the sum of the spin densities of the third signals, which is greater than or equal to 4 and less than or equal to 1.966, the more likely the oxide is to have a high spin density. It can be said that the content of nitrogen oxides in the insulating film is small.

[0243] Since the insulating film 35a is a film with a low content of nitrogen oxides, the insulating film 35a and the layer (OS It is possible to reduce carrier traps at the interface with As a result, it is possible to reduce the shift in the threshold voltage of the transistor. This can reduce the fluctuation in the electrical characteristics of the transistor.

[0244] In order to improve the reliability of the transistor, the insulating film 35a is formed by SIMS (Secondary The nitrogen concentration measured by y Ion Mass Spectrometry is 6×10 2 0 / cm 3 This is because the insulating film 35 is This is because nitrogen oxides are less likely to be produced in a.

[0245] As an example of the insulating film 35a, an oxide insulating film containing nitrogen and having a small amount of defects is CV A silicon oxynitride film can be formed by the method D. In this case, the source gas is It is preferred to use a silicon-containing deposition gas and an oxidizing gas. Representative examples of oxidizing gases include silane, disilane, trisilane, and fluorinated silane. Examples of reactive gases include nitrous oxide and nitrogen dioxide.

[0246] The ratio of the oxidizing gas to the deposition gas is more than 20 times and less than 100 times, preferably 40 The pressure in the processing chamber is set to less than 100 Pa, preferably 50 Pa or less. By using the CVD method, the insulating film 35a is made of an oxide film containing nitrogen and having a small amount of defects. A material insulating film can be formed.

[0247] For example, the insulating film 35b is made of an oxide film containing more oxygen than the oxygen required for the stoichiometric composition. The insulating film can be formed by using a material having more oxygen than the stoichiometric composition. When the oxide insulating film containing oxygen is heated, part of the oxygen is released. The oxide insulating film containing more oxygen than The amount of desorption is 1.0×10 18 atoms / cm 3 More than 3.0×10 20 ato ms / cm 3 The oxide insulating film is as described above. The temperature is preferably in the range of 100°C to 700°C, or 100°C to 500°C. It is nice.

[0248] The insulating film 35b has a thickness of 30 nm to 500 nm, preferably 50 nm to 400 nm. The insulating film 35 may be made of silicon oxide, silicon oxynitride, or the like having a thickness of 00 nm or less. b) is formed by using an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. When the oxide insulating film is formed, the oxide insulating film contains more oxygen than the oxygen that satisfies the stoichiometric composition. The silicon nitride film can be formed by using a CVD method.

[0249] When a silicon oxide film or a silicon oxynitride film is formed as the insulating film 35b, the following is performed. The deposition can be performed under the following conditions. The substrate is heated to a temperature of 180° C. or higher and 280° C. or lower, more preferably 200° C. or higher and 240° C. or lower. The pressure in the processing chamber is maintained at 100 Pa or more and 250 Pa or less by introducing the raw material gas into the processing chamber. a or less, more preferably 100 Pa or more and 200 Pa or less, and 0.17W / cm at pole 2 More than 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 More than 0.35W / cm 2 The following high frequency power is supplied:

[0250] The insulating film 36 is made of a film having at least a blocking effect against hydrogen and oxygen. Furthermore, it is preferable to use a blocker such as oxygen, hydrogen, water, an alkali metal, or an alkaline earth metal. Typically, a nitride insulating film such as silicon nitride may be formed. In addition to silicon oxide films, silicon nitride films, aluminum nitride films, and aluminum nitride oxide films etc. can also be used.

[0251] In addition, the insulating film 36 is made of a material having a blocking effect against oxygen, hydrogen, water, etc. Such an oxide insulating film may be formed using an aluminum oxide or Aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, oxynitride Examples include yttrium, hafnium oxide, and hafnium oxynitride.

[0252] The thickness of the insulating film 36 may be set to 50 nm or more and 300 nm or less, and preferably 100 The insulating film has a blocking effect against oxygen, hydrogen, water, etc. The insulating film 36 is formed to prevent the oxide semiconductor films 31 to 33 from escaping from the oxide semiconductor films 31 to 33 to the outside. In addition, hydrogen and water are prevented from being diffused from the outside into the oxide semiconductor films 31 to 33. It is possible to prevent intrusions such as

[0253] When a silicon nitride film is formed as the insulating film 36 by the plasma CVD method, the silicon-containing It is preferable to use deposition gases such as nitrogen and ammonia as source gases. By using the source gas, ammonia dissociates in the plasma and active species are generated. The active species is the bond of silicon and hydrogen contained in the silicon-containing deposition gas, and the triple bond of nitrogen. This breaks the bonds between silicon and nitrogen, and between silicon and hydrogen. It is possible to form a dense silicon nitride film with few inclusions and defects. In the gas, if the amount of ammonia is high relative to nitrogen, the deposition gas containing silicon and nitrogen The decomposition of each element did not proceed, and silicon and hydrogen bonds remained, increasing the number of defects. In addition, a rough silicon nitride film is formed. The flow rate ratio of nitrogen to nitrogen is set to 5 or more and 50 or less, preferably 10 or more and 50 or less. preferable.

[0254] After the insulating film 35 is formed, heat treatment may be performed. The temperature of the heat treatment is typically 150°C or higher and lower than the substrate distortion point, preferably 200°C or higher and 450°C or lower, more preferably 3 The temperature is set to 00° C. or higher and 450° C. or lower. By this heat treatment, the oxide constituting the second layer of the insulating film 35 is Oxygen contained in the oxide insulating film is transferred to the oxide semiconductor films 31 to 33. The heat treatment can reduce the oxygen vacancies contained in these. The heating temperature is 350°C for one hour in a mixed gas atmosphere containing oxygen.

[0255] After the insulating film 36 is formed, hydrogen or the like is removed from the oxide semiconductor films 31 to 33. Heat treatment may be carried out in order to release nitrogen. The heating temperature may be 350° C. for 1 hour in a mixed gas atmosphere containing oxygen and nitrogen.

[0256] [Backgate electrode] The back gate electrodes (BGE1, BGE2) are the same as the gate electrodes (GE1, GE2, GE3). It can be formed in the same manner.

[0257] Below, some other examples of transistor configurations are shown.

[0258] (Transistors TA3 and TA4) FIG. 29(A) and FIG. 29(B) show the transistors TA3 and TA4, respectively. The top view (layout diagram) and its circuit symbol are shown in Fig. 30(A) and Fig. 30(B). 4 is a cross-sectional view of the transistor TA3 taken along the lines a7-a8 and b7-b8, and FIG. Cross-sectional views taken along lines a9-a10 and b9-b10 of A4 are shown.

[0259] The transistor TA3 includes a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, The transistor TA3 has a drain electrode DE4 and a back gate electrode BGE4. , a variant of the transistor TA1, in which the electrode BGE4 is located in the two openings CG4, CG5. The transistor TA1 is different from the transistor TA1 in that it is in contact with the electrode GE4. As shown in FIG. 30(B), the film OS4 is connected to the electrode GE4 in the channel width direction. and the electrode BGE4, which can further improve the strength of the transistor TA3. do.

[0260] The transistor TA4 includes a gate electrode GE5, an oxide semiconductor film OS5, a source electrode SE5, The transistor TA4 has a drain electrode DE5 and a back gate electrode BGE5. , a modified example of the transistor TA2, in which the electrode BGE5 is not connected to the electrode GE5, and the electrode BG E5 and electrode GE5 can be input with different signals or potentials. For example, A signal to control the conductive state of the transistor TA4 is input to the electrode BGE5. It is possible to input a signal or potential that corrects the threshold voltage of the transistor.

[0261] (Transistors TC1, TB2, TD1) 31(A), 31(B), and 31(C) show transistors TC1 and TC2, respectively. The top view (layout diagram) of the transistors TB2 and TD1 and their circuit symbols are shown below. 32(A) and 32(B) show the a11-a12 line and b Cross-sectional view taken along line 11b12, lines a13-a14 and b13-b1 of transistor TB2 A cross-sectional view taken along line 4, and lines a15-a16 and b15-b16 of transistor TD1 A cross-sectional view along a line is shown.

[0262] The transistor TC1 includes a gate electrode GE6, an oxide semiconductor film OS6, a source electrode SE6, The drain electrode DE6 and the back gate electrode BGE6 are provided. At G6, the transistor TC1 is in contact with the electrode GE6. This is an example of a two-layer structure of the OS6 membrane. The OS6 membrane consists of "32" and "33". Like the transistor TA1, the channel formation region of the transistor TC1 is also composed of "32". Therefore, the transistor TC1 is also a transistor that is connected to the transistor TA1. A transistor with a field effect mobility as high as 10 m 2 / Vs > 60cm 2 / Vs, preferably less than 15cm 2 / Vs or more 50cm 2 / Vs. Therefore, the transistor TC1 and the transistor TA1 Similarly, the present invention is suitable for transistors that are operated at high speeds, such as in driving circuits.

[0263] The transistor TB2 includes a gate electrode GE7, an oxide semiconductor film OS7, a source electrode SE7, The drain electrode DE7 and the back gate electrode BGE7 are provided. At G7, the transistor TB2 is in contact with the electrode GE7. This is an example, and differs from the transistor TB2 in that it has an electrode BGE7. 2 has an electrode BGE7 connected to the electrode GE7, so that the The on-state current is also high, and the mechanical strength is improved.

[0264] The transistor TD1 includes a gate electrode GE8, an oxide semiconductor film OS8, a source electrode SE8, and a drain electrode DE8. The transistor TD1 is a variant of the transistor TB1. In this example, the entire membrane OS8 overlaps the electrode GE8, and the part outside the edge of the electrode GE8 Thus, the transistor TD1 does not have a film OS8 that is connected to the transistor TB1. Since the SiO 2 film has a structure that is less exposed to light than the SiO 2 film, the SiO 2 film is suitable for use in a pixel portion.

[0265] The films constituting the transistors TA1, TA2 and TB1 are (Insulating film, oxide semiconductor film, metal oxide film, conductive film, etc.) are deposited by sputtering or chemical vapor deposition. Formed using deposition (CVD), vacuum deposition, or pulsed laser deposition (PLD) methods Alternatively, the film can be formed by a coating method or a printing method. The most representative methods are the galvanic deposition method and the plasma enhanced chemical vapor deposition (PECVD) method, but the thermal CVD method Examples of thermal CVD methods include MOCVD (metal organic chemical vapor deposition) and ALD (atomic layer deposition). The membrane method may also be used.

[0266] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The film is formed by feeding the gas into the chamber, reacting it near or on the substrate, and depositing it on the substrate. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that no defects are created due to damage.

[0267] In addition, in the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially Next, the gas is introduced into the chamber, and the gas introduction sequence is repeated to form a film. For example, By switching each switching valve (also called high-speed valve), two or more types of raw material gas can be The first and second source gases are supplied to the chamber in order to prevent the multiple source gases from mixing. At the same time or afterwards, an inert gas (argon, nitrogen, etc.) is introduced to If an inert gas is introduced at the same time, the inert gas is introduced as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. Instead of introducing an inert gas, the first source gas is discharged by evacuation, and then the second source gas is introduced. A source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer. The first monolayer is then reacted with the second source gas introduced later, and the second monolayer is formed on the first monolayer. The layers are then stacked together to form a thin film.

[0268] This gas introduction sequence is controlled and repeated several times until the desired thickness is achieved. The thickness of the thin film can be increased by repeating the gas introduction sequence. This allows precise film thickness control, making it possible to fabricate fine transistors. This is suitable for manufacturing.

[0269] Specific pixel configuration example 3

[0270] FIG. 17 shows an example of a specific configuration of the pixel 10 shown in FIG. 4A is different from the pixel 10 shown in FIG. In the pixel 10 shown in FIG. 17, a transistor 19t is connected to the wiring VL and the source of the transistor 11. The other of the source and drain of the transistor 16t is connected to the source and drain of the transistor 16t. The pixel 10 shown in FIG. 4(A) has a different configuration in that the pixel 10 is connected to the pixel 10 shown in FIG.

[0271] FIG. 18 shows an example of a specific configuration of the pixel 10 shown in FIG. The pixel 10 is different from the pixel 10 shown in FIG. In the pixel 10 shown in FIG. 18, the transistor 19t is connected to the wiring VL and the between the other of the source and drain of the transistor 16t and one of the source and drain of the transistor 16t The pixel 10 shown in FIG. 15A has a different configuration from the pixel 10 shown in FIG.

[0272] In the pixel 10 of the light-emitting device according to one embodiment of the present invention, transistors other than the transistor 11 are It is sufficient for the transistor to have a gate on at least one side of the semiconductor film. There may be another gate interposed therebetween and overlapping with the gate. When a transistor other than the transistor 11 has a pair of gates, one of the pair of gates If the back gate is set to the normal gate and the back gate, the same potential is applied. Alternatively, a fixed potential such as a ground potential may be applied only to the back gate. The threshold voltage of the transistor is controlled by controlling the level of the potential applied to the back gate. In addition, by providing a back gate, the channel forming region is increased, and the drain In addition, by providing a back gate, voids are formed in the semiconductor film. Since it becomes easier for a depleted layer to form, the S value can be improved.

[0273] <Transistor configuration example 2> The transistor used in the light-emitting device according to one embodiment of the present invention may be an amorphous, microcrystalline, or polycrystalline Alternatively, a semiconductor film or substrate of single crystal silicon or germanium is provided with a thin film of thief. In the case where a transistor is formed using a thin film of silicon, In this case, the thin film is formed by a vapor phase growth method such as a plasma CVD method or a sputtering method. The amorphous silicon is then crystallized by laser annealing or other processes. Polycrystalline silicon, which is made by injecting hydrogen ions into a single crystal silicon wafer, and single crystal silicon, which is made by peeling off the surface layer. Crystalline silicon or the like can be used.

[0274] FIG. 34 shows a thin silicon film that can be used in a light-emitting device according to one embodiment of the present invention. A cross-sectional view of the transistor used is shown in FIG. 34. and a p-channel transistor 71.

[0275] The transistor 70 is formed on a substrate 72 having an insulating surface, and a conductive film 73 serving as a gate. an insulating film 74 on the conductive film 73; and a semiconductor layer overlapping the conductive film 73 with the insulating film 74 interposed therebetween. A film 75, an insulating film 76 on the semiconductor film 75, and a semiconductor film 75 overlapping the insulating film 76 therebetween. The conductive films 77a and 77b function as gates, and the conductive films 77a and An insulating film 78 on the conductive film 77b, an insulating film 79 on the insulating film 78, and a film formed by insulating films 78 and 7 9 is electrically connected to the semiconductor film 75 through an opening provided in the The conductive film 80 and the conductive film 81 function as the drain.

[0276] The width of the conductive film 77b in the channel length direction is shorter than that of the conductive film 77a. The semiconductor film 75 and the conductive film 77b are laminated in this order from the insulating film 76 side. A channel forming region 82 is formed at a position where it overlaps with the film 77b, and the channel forming region 82 is sandwiched between the film 77b. A pair of LDD (Light Doped Drain) regions 83 located in the direction of the channel The semiconductor device has a pair of impurity regions 84 sandwiching an LDD region 83 therebetween. The pair of impurity regions 84 function as a source region or a drain region. The DD region 83 and the impurity region 84 are impurity sources that impart n-type conductivity to the semiconductor film 75. For example, boron (B), aluminum (Al), gallium (Ga), etc. are added. do.

[0277] The transistor 71 has a conductive layer functioning as a gate on a substrate 72 having an insulating surface. The conductive film 85 is overlapped with the insulating film 74 on the conductive film 85 via the insulating film 74. A semiconductor film 86, an insulating film 76 on the semiconductor film 86, and a semiconductor film 86 with the insulating film 76 interposed therebetween. A conductive film 87a and a conductive film 87b overlap with the conductive film 87 and function as a gate. a and the insulating film 78 on the conductive film 87b, an insulating film 79 on the insulating film 78, and The insulating film 79 is electrically connected to the semiconductor film 86 through an opening formed therein, and the source Alternatively, the conductive film 88 and the conductive film 89 function as a drain.

[0278] The conductive film 87b has a width in the channel length direction that is shorter than that of the conductive film 87a. The semiconductor film 75 and the conductive film 87b are laminated in this order from the insulating film 76 side. A channel forming region 90 is formed at a position where it overlaps with the film 87b, and the channel forming region 90 is sandwiched between the film 87b. The pair of impurity regions 91 are located as follows: The impurity region 91 functions as a drain region. Impurity elements such as phosphorus (P) and arsenic (As) are added to the silicon substrate.

[0279] The semiconductor film 75 or the semiconductor film 86 may be crystallized by various techniques. Crystallization methods include laser crystallization using laser light and crystallization using catalytic elements. Alternatively, the crystallization method using a catalytic element and the laser crystallization method can be used in combination. In addition, when a substrate having excellent heat resistance such as quartz is used as the substrate 72, the substrate can be heated in an electric furnace. The thermal crystallization method using a thermal annealing method using infrared light, the lamp annealing crystallization method using a catalytic element, A crystallization method in which a high-temperature annealing at about 950° C. is combined with the crystallization method may be used.

[0280] <Method 1 for manufacturing a light-emitting device> Next, a method for manufacturing the light-emitting device 400 according to one embodiment of the present invention will be described with reference to FIGS. This will be explained using:

[0281] First, an insulating film 420 is formed on a substrate 462, and a first element layer 410 is formed on the insulating film 420. (See FIG. 19A). The first element layer 410 is provided with a semiconductor element. Alternatively, the first element layer 410 may include a display element or a pixel electrode in addition to the semiconductor element. A part of the display element may be provided.

[0282] The substrate 462 must have at least sufficient heat resistance to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 4. It may also be used as 62.

[0283] When a glass substrate is used as the substrate 462, a silicon oxide film is formed between the substrate 462 and the insulating film 420. When an insulating film such as a silicon oxide nitride film, a silicon nitride film, or a silicon nitride oxide film is formed, the glass This is preferable because it can prevent contamination from the substrate.

[0284] The insulating film 420 may be made of, for example, epoxy resin, aramid resin, acrylic resin, or polyimide resin. An organic resin film such as a resin, a polyamide resin, or a polyamide-imide resin can be used. In particular, it is preferable to use a polyimide resin because of its high heat resistance. When a polyimide resin is used, the thickness of the polyimide resin is preferably 3 nm or more and 20 μm or less. The thickness is preferably 500 nm or more and 2 μm or less. In this case, the coating method may be a spin coating method, a dip coating method, a doctor blade method, or the like. For example, when a polyimide resin is used as the insulating film 420, By removing a portion of the film using the polyimide resin by the method, a film having a desired thickness can be obtained. An insulating film 420 can be obtained.

[0285] The first element layer 410 is fabricated at a temperature of room temperature or higher and 300° C. or lower. For example, the insulating film or conductive film using an inorganic material included in the first element layer 410 is preferably The conductive film is formed at a film formation temperature of 150°C to 300°C, and more preferably 200°C to 270°C. In addition, the organic resin material contained in the first element layer 410 is preferably used. The insulating film or the like is preferably formed at a film formation temperature of from room temperature to 100° C. or less.

[0286] In addition, the oxide semiconductor film of the transistor included in the first element layer 410 is It is preferable to use AC-OS for the oxide semiconductor film of the transistor. When S is used, for example, when the light emitting device 400 is bent, cracks are generated in the channel forming region. This makes it difficult for defects such as the above to enter the material, and makes it possible to increase resistance to bending.

[0287] The conductive film included in the first element layer 410 is made of indium tin oxide to which silicon oxide is added. If tin oxide is used, cracks or the like may occur in the conductive film when the light emitting device 400 is bent. This is preferable because it makes things more difficult.

[0288] Next, the first element layer 410 and a temporary support substrate 466 are bonded together using a peeling adhesive 464. Then, the insulating film 420 and the first element layer 410 are peeled off from the substrate 462. The first element layer 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 19B). .

[0289] The temporary support substrate 466 may be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, A metal substrate or the like can be used. In addition, a substrate having heat resistance capable of withstanding the processing temperature of this embodiment is also suitable. A plastic substrate having a thickness of 100 nm or a flexible substrate such as a film may be used. .

[0290] The peeling adhesive 464 may be soluble in water or solvent, or plasticized by exposure to ultraviolet light, etc. The temporary support substrate 466 and the element layer 410 can be bonded together as needed, for example. Use an adhesive that can be chemically or physically separated.

[0291] In addition, the transfer step onto the temporary support substrate 466 can be performed by using various methods as appropriate. For example, 19B, the side of the substrate 462 on which the insulating film 420 is not formed, that is, the lower side shown in FIG. By irradiating the insulating film 420 with the laser light 468, the insulating film 420 is weakened. The substrate 462 and the insulating film 420 can be peeled off by the laser beam 468. By adjusting the energy density, it is possible to obtain a region where the substrate 462 and the insulating film 420 have high adhesion and a region where the substrate 462 and the insulating film 420 have high adhesion. Alternatively, regions where the plate 462 and the insulating film 420 have low adhesion may be created and then peeled off.

[0292] In this embodiment, the method of peeling off the substrate 462 and the insulating film 420 at the interface is as follows. However, the present invention is not limited to this. For example, the boundary between the insulating film 420 and the first element layer 410 may be It may be peeled off at the surface.

[0293] In addition, a liquid is permeated into the interface between the substrate 462 and the insulating film 420 to remove the insulating film 420 from the substrate 462. Alternatively, a liquid may be permeated into the interface between the insulating film 420 and the first element layer 410. The first element layer 410 may be peeled off from the insulating film 420 by removing the liquid. For example, water, a polar solvent, or the like can be used. The liquid is formed at the interface between the plate 462 and the insulating film 420 or at the interface between the insulating film 420 and the first element layer 410. The electrostatic charge generated by the peeling applied to the first element layer 410 by penetrating the body The effects of heat and other factors can be suppressed.

[0294] Next, the first substrate 401 is bonded to the insulating film 420 using the adhesive layer 418 (FIG. 19( See C).

[0295] The release adhesive 464 is then dissolved or plasticized to remove the release adhesive from the first element layer 410. The adhesive 464 and the temporary support substrate 466 are removed (see FIG. 19(D)).

[0296] The peeling adhesive 464 is removed by removing water or a solvent so that the surface of the first element layer 410 is exposed. It is preferable to remove it.

[0297] Through the above steps, the first element layer 410 can be manufactured over the first substrate 401 .

[0298] Next, a second substrate 4 is formed by the same method as the steps shown in FIG. 19(A) to FIG. 19(D). 05, an adhesive layer 412 on the second substrate 405, an insulating film 440 on the adhesive layer 412, and An element layer 411 is formed (see FIG. 20A).

[0299] The insulating film 440 of the second element layer 411 is made of the same material as the insulating film 420. can be formed using an organic resin.

[0300] Next, a sealing layer 432 is filled between the first element layer 410 and the second element layer 411. The element layer 410 and the second element layer 411 are bonded to each other (see FIG. 20B).

[0301] The sealing layer 432 can provide, for example, solid sealing. The sealing layer 432 is preferably made of, for example, glass frit. Glass materials such as these, two-part resins that harden at room temperature, and photocurable resins For example, a resin material such as a thermosetting resin can be used.

[0302] In this manner, the light emitting device 400 can be manufactured.

[0303] <Method 2 for manufacturing a light-emitting device> Next, another method for manufacturing the light-emitting device 400 according to one embodiment of the present invention will be described with reference to FIG. In FIG. 21, an inorganic insulating film is used as the insulating film 420 and the insulating film 440. The configuration will be described below.

[0304] First, a separation layer 463 is formed over a substrate 462. Next, an insulating film 420 is formed over the separation layer 463. A first element layer 410 is formed over the insulating film 420 (see FIG. 21A).

[0305] The peeling layer 463 may be made of, for example, tungsten, molybdenum, titanium, tantalum, or niobium. , Nickel, Cobalt, Zirconium, Zinc, Ruthenium, Rhodium, Palladium, Os An element selected from the group consisting of tungsten, iridium, and silicon, an alloy material containing the element, or The material may be a compound material containing silicon, and may be a single layer or a laminated structure. In the case of a layer containing silicon, the crystal structure of the layer containing silicon may be amorphous, microcrystalline, polycrystalline, or the like. The crystal may be either a single crystal or a single crystal.

[0306] The release layer 463 can be formed by a sputtering method, a PECVD method, a coating method, a printing method, or the like. The coating method includes a spin coating method, a droplet ejection method, and a dispense method.

[0307] When the release layer 463 has a single layer structure, it is made of tungsten, molybdenum, or tungsten and molybdenum. It is preferable to form a layer containing a mixture of tungsten and butenone. a layer containing an oxynitride, a layer containing an oxide or oxynitride of molybdenum, or a layer containing tungsten A layer containing an oxide or oxynitride of a mixture of stainless steel and molybdenum may be formed. A mixture of tungsten and molybdenum is, for example, an alloy of tungsten and molybdenum. is equivalent to.

[0308] The peeling layer 463 may be a stack of a layer containing tungsten and a layer containing an oxide of tungsten. When forming a layered structure, a layer containing tungsten is formed, and an upper layer made of oxide is formed. By forming an insulating layer, tungsten oxide is formed at the interface between the tungsten layer and the insulating layer. In addition, the surface of the layer containing tungsten may be treated with a thermal acid. Chemical treatment, oxygen plasma treatment, nitrous oxide (N2O) plasma treatment, ozone water, etc. A layer containing tungsten oxide may be formed by treatment with a strong solution or the like. Zuma treatment and heat treatment can be performed using oxygen, nitrogen, or nitrous oxide alone or in combination with other gases. The above-mentioned plasma treatment or heat treatment may be performed under a mixed gas atmosphere. By changing the surface condition of the peeling layer 463, the adhesion between the peeling layer 463 and the insulating film 420 to be formed later can be improved. It is possible to control the

[0309] The insulating film 420 may be, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. An inorganic insulating film with low moisture permeability, such as a silicon film or an aluminum oxide film, can be used. The inorganic insulating film can be formed by using, for example, a sputtering method, a PECVD method, or the like. Cut.

[0310] Next, the first element layer 410 and a temporary support substrate 466 are bonded together using a peeling adhesive 464. Then, the insulating film 420 and the first element layer 410 are peeled off from the peeling layer 463. The film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 21(B)). ).

[0311] In addition, the transfer step onto the temporary support substrate 466 can be performed by using various methods as appropriate. For example, When a layer including a metal oxide film is formed at the interface between the peeling layer 463 and the insulating film 420, the metal The oxide film is weakened by crystallization, and the insulating film 420 can be peeled off from the peeling layer 463. In addition, when the peeling layer 463 is formed using a tungsten film, ammonia water and hydrogen peroxide are used. The tungsten film may be removed while being etched with a mixed solution of water.

[0312] In addition, a liquid is permeated into the interface between the peeling layer 463 and the insulating film 420 to remove the insulating film from the peeling layer 463. The liquid may be, for example, water, a polar solvent, or the like. At the interface where the insulating film 420 is peeled off, specifically, at the interface between the peeling layer 463 and the insulating film 420, By infiltrating the liquid, the static electricity generated by the peeling applied to the first element layer 410 is reduced. The effects of electricity, etc. can be suppressed.

[0313] Next, the first substrate 401 is bonded to the insulating film 420 using the adhesive layer 418 (FIG. 21(C) reference).

[0314] The release adhesive 464 is then dissolved or plasticized to remove the release adhesive from the first element layer 410. The adhesive 464 and the temporary support substrate 466 are removed (see FIG. 21(D)).

[0315] The peeling adhesive 464 is removed by removing water or a solvent so that the surface of the first element layer 410 is exposed. It is preferable to remove it.

[0316] Through the above steps, the first element layer 410 can be manufactured over the first substrate 401 .

[0317] Next, a second substrate 4 is formed by the same method as the steps shown in FIG. 21(A) to FIG. 21(D). 05, an adhesive layer 412 on the second substrate 405, an insulating film 440 on the adhesive layer 412, and Then, the first element layer 410 and the second element layer 411 are formed. A sealing layer 432 is filled in the gap, and the first element layer 410 and the second element layer 411 are bonded together. do.

[0318] Finally, the anisotropic conductive film 380 and the FPC 408 are attached to the connection electrodes 360. For example, an IC chip or the like may be mounted.

[0319] In this manner, the light emitting device 400 can be manufactured.

[0320] <Cross-sectional structure of light-emitting device> FIG. 22 illustrates an example of a cross-sectional structure of a pixel portion of a light-emitting device according to one embodiment of the present invention. 22, the transistor 11, the capacitor 18, and the like included in the pixel 10 shown in FIG. 1 and 2 show cross-sectional structures of the light-emitting element 14.

[0321] Specifically, the light emitting device shown in FIG. 22 has a transistor 11 and a capacitance element 18 on a substrate 500. The transistor 11 includes a conductive film 501 functioning as a first gate and a conductive film An insulating film 502 on the conductive film 501 and a semiconductor film overlapping the conductive film 501 with the insulating film 502 interposed therebetween. 503 and a conductor functioning as a source or drain electrically connected to the semiconductor film 503. The conductive film 504 and the conductive film 505, and the insulating film on the semiconductor film 503, the conductive film 504, and the conductive film 505 The insulating film 550 overlaps with the conductive film 501 with the insulating film 550 interposed therebetween, and functions as a second gate. and a conductive film 551 which can

[0322] The capacitor 18 includes a conductive film 501 functioning as an electrode, an insulating film 502 over the conductive film 501, and A conductive film 502 is sandwiched between the conductive film 501 and the insulating film 502, and the conductive film 502 functions as an electrode. 504.

[0323] The insulating film 502 may be made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, or the like. , silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, oxide One or more of zirconium, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide The insulating film including the above may be used as a single layer or a laminated layer. An oxynitride is a material whose composition contains more oxygen than nitrogen. refers to a material whose composition contains more nitrogen than oxygen.

[0324] In addition, an insulating film 511 is provided over the semiconductor film 503, the conductive film 504, and the conductive film 505. When an oxide semiconductor is used for the semiconductor film 503, the insulating film 511 is It is preferable to use a material capable of supplying oxygen to the insulating film 5. By using the insulating film 511 as the insulating film 512, oxygen contained in the insulating film 511 can be moved to the semiconductor film 503. Therefore, the amount of oxygen vacancies in the semiconductor film 503 can be reduced. The oxygen is transferred to the semiconductor film 503 by performing heat treatment after the insulating film 511 is formed. This can be done efficiently.

[0325] An insulating film 520 is provided on the insulating film 511, and a conductive film 524 is provided on the insulating film 520. The conductive film 524 is provided in the openings in the insulating film 511 and the insulating film 520. 5, the conductive film 504 is connected to the conductive film 504.

[0326] An insulating film 525 is provided over the insulating film 520 and the conductive film 524. The insulating film 525 is The insulating film 525 has an opening at a position overlapping with the conductive film 524. An insulating film 526 is provided at a position different from the opening of the insulating film 525. An EL layer 527 and a conductive film 528 are provided in this order over the insulating film 526. The conductive film 524 and the conductive film 528 overlap with each other with the EL layer 527 interposed therebetween. The conductive film 524 and the conductive film 528 function as the light-emitting element 14. one acts as a cathode and the other as a pole.

[0327] The light emitting device also includes a substrate 530 that faces the substrate 500 with the light emitting element 14 sandwiched therebetween. On the substrate 530, i.e., on the surface of the substrate 530 close to the light emitting element 14, a light shielding layer is provided. The shielding film 531 has a function of shielding the light emitting element 1. The substrate 53 has an opening in a region overlapping the light emitting element 14. On the glass substrate 50 is provided a colored layer 532 that transmits visible light in a specific wavelength range.

[0328] <Appearance of the light-emitting device> FIG. 23A is a perspective view illustrating an example of the appearance of a light-emitting device according to one embodiment of the present invention. The light emitting device shown in FIG. 23(A) includes a panel 1601, a controller, a power supply circuit, an image processing circuit, The circuit board 1602 has a circuit, an image memory, a CPU, etc., and a connection part 1603. The panel 1601 includes a pixel portion 1604 having a plurality of pixels and a display portion 1605 having a plurality of pixels arranged in rows. A driver circuit 1605 selects the pixel in the selected row and controls the input of an image signal Sig to the pixels in the selected row. and a driver circuit 1606 for controlling the same.

[0329] Various signals and a power supply potential are transmitted from the circuit board 1602 to the panel via the connection portion 1603. The connection part 1603 is connected to an FPC (Flexible Printer The FPC with the chip mounted on it is called CO This is called F tape, and the use of COF tape allows for higher density mounting in a smaller area. In addition, when a COF tape is used for the connection portion 1603, A part of the circuit, or a part of the driver circuit 1605 or the driver circuit 1606 of the panel 1601 The above is formed on a separately prepared chip and then the COF (Chip On Film) method is used. The chip may be connected to the COF tape in advance.

[0330] FIG. 23B is a perspective view showing an example of the appearance of a light-emitting device using the COF tape 1607. As shown in.

[0331] The chip 1608 is a semiconductor bare chip (such as an IC or LSI) having terminals such as bumps on its surface. In addition, CR components can also be mounted on the COF tape 1607, and the circuit board 1602 The wiring pattern of the flexible board corresponds to the terminals of the chip to be mounted. The chip 1608 is bonded to a substrate having a wiring pattern by a bonder device or the like. The chip is positioned and placed on a flexible substrate and then mounted by thermocompression bonding.

[0332] FIG. 23(B) shows an example of one COF tape 1607 on which one chip 1608 is mounted. However, it is not particularly limited. A single COF tape 1607 may have multiple rows of chips on one or both sides. However, to reduce costs, it is necessary to reduce the number of chips to be mounted. It is preferable to have a single row, and more preferably, to have only one.

[0333] <Example of circuit board configuration> 25 shows an external view of the circuit board 2003. The circuit board 2003 has a slit 2211. On the FPC2201, which has Bluetooth (registered trademark. IEEE802.15.1 ) standard communication device 2101, microcomputer 2102, storage device 2103, FPGA 2 104, a DA converter 2105, a charge control IC 2106, and a level shifter 2107 are provided. has the configured structure. Further, the circuit board 2003 is electrically connected to the light-emitting device according to one aspect of the present invention via the input / output connector 2108. Also, by providing the slit 2211 in the FPC 2201, the flexibility of the circuit board 2003 using the FPC 2201 is enhanced. The substrate having flexibility is used for the light-emitting device according to one aspect of the present invention, so that the light-emitting device can be curved together with the circuit board 2003. Therefore, the light-emitting device using the flexible substrate and the circuit board 2003 can be repeatedly deformed according to the shape of the mounting site, and thus are suitable for use in electronic devices that can be mounted on a body such as an arm or a leg. 〈Configuration Example of Information Processing Apparatus〉

[0334]

[0335]

[0336]

[0337]

[0338]

[0339] The position input unit 1001 or the display unit 1002 may be 0 may be provided on the bottom surface.

[0337] In addition to the position input unit 1001, the surface of the housing 1003 is provided with hardware buttons and external connectors. The insulating film may have a connection terminal or the like.

[0338] With this configuration, unlike the conventional information processing device, It is possible to display not only on the front surface but also on the side surface of the housing 1003. In addition, providing display areas along two or more sides of the housing 1003 can further increase the variety of displays. This is preferable.

[0339] A display area arranged along the front side of the information processing device and each display area arranged along the side Each of the display areas may be used as an independent display area to display different images, etc., or any two of the display areas may be used as a single display area. For example, an image may be displayed across two or more display areas of an information processing device. The image to be displayed in the display area arranged along the side of the information processing device is displayed on the display area arranged along the side of the information processing device. The display areas may be displayed continuously.

[0340] The arithmetic unit 1005 is provided inside the housing 1003. In FIG. The arithmetic unit 1005 is provided at a position separated from the display unit 1002. The arithmetic unit 1005 is disposed at a position overlapping the display unit 1002 .

[0341] The position input unit 1001 includes, for example, a first area 1001(1) and a second area 100 A second region 1001(2) facing the first region 1001(1) and a second region 1001(2) facing the first region 1001(1) and the second region 1001(2) facing the second region 1001(1) The third region 1001(3) is formed between the first region 1001(2) and the second region 1001(3). As another example, the first region has a flexibility that can be easily adjusted (see FIG. 26(B)). A region 1001(1), a third region 1001(3), and a region facing the third region 1001(3). and a fourth region 1001(4) that is flexible and can be folded so as to form (See FIG. 26(E)).

[0342] As another example, a third region 1001(3), a fifth region 1001(5), and a third region 1001(6) are provided. The third region 1001(3) is folded to form a fourth region 1001(4) facing the third region 1001(3). The substrate 1 may have flexibility so that it can be bent.

[0343] The arrangement of the second region 1001(2) facing the first region 1001(1) is The arrangement is not limited to facing the first area 1001(1), but may be inclined toward the first area 1001(1). Also, a fourth region facing the third region 1001(3) is included. The arrangement of the area 1001(4) is not limited to being directly opposite the third area 1001(3), but may be any arrangement other than the third area 1001(4). This also includes an arrangement in which the area faces the area 1001(3) at an angle.

[0344] The display unit 1002 includes at least a first area 1001(1), a second area 1001(2), Arranged so as to overlap a part of the third region 1001(3) or the fourth region 1001(4). will be done.

[0345] The information processing device 1000 includes a flexible position input unit 100 that detects an object in proximity or in contact with the object. 1. The position input unit 1001 is configured to include, for example, a first area 1001( 1), a second region 1001(2) facing the first region, and the first region 1001(1). A third area 1001(3) overlapping the display unit 1002 is disposed between the second area 1001(2). ) and can be folded so as to form a palm or hand. Either of the fingers is in the first area 1001(1) or the second area 1001(2), etc. This allows the user to know when the object is approaching the target. This results in a human interface with excellent operability. Alternatively, a novel information processing device with excellent operability can be provided.

[0346] The substrate used for the display unit 1002 can be made of a resin having a thickness sufficient to provide flexibility. Examples of resins include polyester, polyolefin, polyamide, polyimide, and a Examples of the resin include amide, epoxy, polycarbonate, and acrylic resin. In addition, typical substrates that do not have flexibility include glass substrates, quartz substrates, semiconductor substrates, etc. etc. can be used.

[0347] <Examples of electronic device configurations> The light-emitting device according to one embodiment of the present invention can be used in a display device, a notebook personal computer, a recording medium, Image playback devices equipped with a DVD player (typically DVD: Digital Versatile Digital Used for devices that play recording media such as ISC and have a display that can display the images. In addition, an electronic device in which the light-emitting device according to one embodiment of the present invention can be used As containers, mobile phones, portable game consoles, personal digital assistants, electronic books, video cameras, digital Cameras such as still cameras, goggle-type displays (head-mounted displays) , navigation systems, audio playback devices (car audio, digital audio players) Copiers, fax machines, printers, printer-combination machines, automated teller machines, Examples of electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 24. .

[0348] FIG. 24A shows a display device, which includes a housing 5001, a display unit 5002, a support stand 5003, etc. The light-emitting device according to one embodiment of the present invention can be used for the display portion 5002. Display devices include all information displays, such as those for personal computers, TV broadcast reception, and advertisement displays. A display device for displaying information is included.

[0349] FIG. 24B shows a portable information terminal, which includes a housing 5101, a display unit 5102, and operation keys 5103. The light-emitting device according to one embodiment of the present invention can be used in the display portion 5102.

[0350] FIG. 24C shows a display device having a curved housing 5701, a display portion 5702, etc. By using a flexible substrate in the light-emitting device according to one embodiment of the present invention, a curved case can be easily formed. The light emitting device can be used for a display portion 5702 supported by a body 5701. It is therefore possible to provide a display device that is compact, lightweight, and easy to use.

[0351] FIG. 24D shows a portable game machine. The portable game machine includes a housing 5301, a housing 5302, a display portion 5303, A display unit 5304, a microphone 5305, a speaker 5306, an operation key 5307, a star The light-emitting device according to one embodiment of the present invention includes a display portion 5303 or a display The display portion 5303 or the display portion 5304 may be used as one of the display devices of the present invention. By using the light emitting device according to the embodiment, the user experience is excellent and deterioration of quality is unlikely to occur. It is possible to provide a portable game machine that can be used with a portable game machine shown in FIG. The display device has two display areas 5303 and 5304. The number of display units is not limited to this.

[0352] FIG. 24E shows an electronic book having a housing 5601, a display portion 5602, and the like. The light-emitting device according to the embodiment can be used for the display portion 5602. By using a substrate, the light-emitting device can be made flexible, To provide a light and easy-to-use e-book.

[0353] FIG. 24F shows a mobile phone. A housing 5901 includes a display unit 5902, a microphone 5907, and a speaker. Speaker 5904, camera 5903, external connection part 5906, and operation button 5905 are provided. The light-emitting device according to one embodiment of the present invention can be used for the display portion 5902. In addition, when the light-emitting device according to one embodiment of the present invention is formed on a flexible substrate, The light-emitting device can be applied to a display portion 5902 having a curved surface as shown in FIG. do.

[0354] Example Example 1 This example describes a display device manufactured using the pixel shown in the above embodiment mode. .

[0355] First, the characteristics of the transistors used in the pixels were measured. The OS transistor is formed using an AC-OS film. The CAAC-OS film is an In-Ga The thin film was formed using -Zn oxide.

[0356] FIG. 42A shows the measurement results of the IV characteristics of an OS transistor. The measurement results are shown for drain-to-drain voltages (Vds) of 0.1 V and 10 V. The channel length L of the OS transistor is 6 μm, and the channel width W is 6 μm. In addition, the OS transistor has a back gate, and the voltage between the back gate and the source The measurements were performed with the voltage (Vbgs) at 0V.

[0357] The measurements were performed at 20 points on the same substrate. The median threshold voltage was 4.38 V, and the threshold voltage variation was 3σ = 0.88 V. .

[0358] By providing a back gate, DIBL (Drain Induced Back The MOSFET lowering effect is reduced. In the case of the 100-V structure, the channel length modulation coefficient is about 0.05V. -1 On the other hand, the back gate When using approx. 0.009V -1 As a result, the saturation property was improved.

[0359] Next, the measurement result of the Vbgs dependency of the threshold voltage Vth of the OS transistor is shown in FIG. FIG. 42B shows the state where the source potential of the OS transistor is fixed and Vbgs is The I-V characteristics were measured while changing the voltage, and the threshold voltage was calculated from the measurement results and plotted. FIG. 42B shows the measurement results when Vds=10V.

[0360] When Vbgs changes to the positive side, the threshold voltage shifts to the negative side, It can be seen that the threshold voltage shifts to the positive side when the Vth changes to the V It can be seen that the threshold voltage shifts linearly with respect to bgs. It also depends on the thickness of the interlayer film between the panel and the back gate and the dielectric constant of the interlayer film. The thicker the film thickness and the lower the dielectric constant, the smaller the effect of Vbgs on the threshold voltage. become.

[0361] A pixel was constructed using the above OS transistor. The circuit configuration of the pixel is shown in FIG. The pixel shown in FIG. 43(A) corresponds to the pixel 10 shown in FIG. 3(B) and FIG. 4(B). Then, the pixel shown in FIG. 43(A) is driven in accordance with the timing chart shown in FIG. The threshold voltage was corrected by driving the transistor in the same manner as described above. In Period I, G3 is a high level. Tr4 is on, and the source potential of the drive transistor DrTr is the CATHODE potential. OLED threshold Vth OLED The potential is the sum of the above.

[0362] The specifications of the display device manufactured using the above pixels are shown in Table 1. The resolution of the display device is 302 ppi and the aperture ratio was 61%. The scan driver was built into the glass, A COF is used for the source driver.

[0363] [Table 1]

[0364] The display device is a top-emission type that uses white EL elements and color filters (CF). The structure of the display device is shown in Figure 44(A).

[0365] The white EL element had a laminated structure as shown in FIG. A light-emitting unit made of a fluorescent material and a light-emitting unit made of green and red phosphorescent materials are connected in series. The device has a two-layer tandem structure.

[0366] Figure 45 shows a display image of the actual display device. There is no unevenness in the display image. You can see that it is displayed correctly.

[0367] FIG. 46 shows the measurement results when the threshold voltage of the drive transistor DrTr shown in FIG. 43(A) is changed. The calculation results are shown in Fig. 1. Here, ΔVth, which is the horizontal axis of the graph, is the change in Vth due to the correction of the threshold voltage. The vertical axis of the graph, Vgs-Vth, is the shift amount during the period IV in FIG. From the Vgs of the driving transistor DrTr during the light emission period, the driving transistor after the threshold voltage correction This is the value minus the threshold voltage of the transistor DrTr. If the threshold voltage correction is performed correctly, For example, the Vgs-Vth value does not depend on the threshold voltage, so the slope of the graph is 0.

[0368] From the calculation results shown in Figure 46, Vgs when ΔVth is in the range of -1.5V to +1.5V The variation in the -Vth value is suppressed to about 10% of the Vgs-Vth value at ΔVth=0. It is clear that this is being done.

[0369] In the pixel shown in FIG. 43(A), the threshold value of the OLED is Vth OLED Then, When the threshold voltage Vth of the driving transistor DrTr is a positive value, Vth=0 to V0 -(Cathode+Vth OLED ) is corrected to the positive side by the potential of When the threshold voltage of the driving transistor DrTr is a negative value, Vt The threshold voltage range from h=0 to the negative side by the potential of Anode-V0 In addition, the variation in the threshold voltage of the driving transistor DrTr can be corrected. If the voltage V is within the positive range, the V0 power supply can be used as the Anode. In this case, the number of power supply lines V0 in the pixel can be reduced by one.

[0370] As described above, by using the present invention, it is possible to correct the threshold voltage and obtain a display with reduced display unevenness. A device can be fabricated. [Explanation of symbols]

[0371] 10 pixels 11 Transistor 12 Switch 12t transistor 13 Capacitive element 14 Light emitting element 15 Switch 15t transistor 16 Switch 16t transistor 17 Switch 17t Transistor 18 Capacitive element 19 Switch 19t Transistor 30 Substrate 31 Oxide semiconductor film 31-32 Oxide semiconductor film 32 Oxide semiconductor film 33 Oxide Semiconductor Film 34 Insulating film 35 Insulating film 35a Insulating film 35b Insulating film 36 Insulating Film 40 Pixel section 41 Selection circuit 42 Wiring 43 Switch 44 Switch 45 Monitor circuit 46 Operational Amplifiers 47 Capacitive element 48 Switch 49 Wiring 60A Switch 60B Switch 60C Switch 61 Circuit 62A Switch 62B Switch 62C Switch 63A Wiring 63B Wiring 70 Transistor 71 Transistor 72 Substrate 73 Conductive Film 74 Insulating Film 75 Semiconductor Film 76 Insulating Film 77a Conductive film 77b Conductive film 78 Insulating Film 79 Insulating Film 80 Conductive Film 81 Conductive Film 82 Channel formation region 83 LDD area 84 Impurity region 85 Conductive Film 86 Semiconductor Film 87a Conductive film 87b Conductive film 88 Conductive Film 89 Conductive Film 90 Channel formation region 91 Impurity region 360 Connection electrode 380 Anisotropic Conductive Film 400 Light Emitting Device 401 Substrate 405 Substrate 408 FPC 410 Element Layer 411 Element Layer 412 Adhesive layer 418 Adhesive layer 420 Insulating film 432 Sealing layer 440 Insulating film 462 Substrate 463 Peeling layer 464 Peeling adhesive 466 Temporary Support Substrate 468 Laser Light 500 boards 501 Conductive film 502 Insulating film 503 Semiconductor Film 504 Conductive film 505 Conductive Film 511 Insulating film 520 Insulating film 524 Conductive Film 525 Insulating Film 526 Insulating Film 527 EL layer 528 Conductive Film 530 Substrate 531 Shielding membrane 532 Colored layer 550 Insulating film 551 Conductive film 802 IEEE 1000 Information processing device 1001 Position input section 1001(1) First Area 1001(2) Second Area 1001(3) The third area 1001(4) The Fourth Region 1002 Display section 1003 Case 1005 Arithmetic equipment 1601 Panel 1602 Circuit Board 1603 Connection 1604 Pixel section 1605 Drive circuit 1606 Drive circuit 1607 COF Tape 1608 Chip 2003 Circuit Board 2101 Communication equipment 2102 Microcomputer 2103 Storage device 2104 FPGA 2105 DA Converter 2106 Charge control IC 2107 Level Shifter 2108 Input / Output Connector 2201 FPC 2211 Slit 5001 Case 5002 Display section 5003 Support stand 5101 Case 5102 Display section 5103 Operation key 5301 Case 5302 Case 5303 Display section 5304 Display section 5305 Microphone 5306 Speaker 5307 Operation key 5308 Stylus 5601 Case 5602 Display section 5701 Case 5702 Display section 5901 Case 5902 Display section 5903 Camera 5904 Speaker 5905 Button 5906 External connection part 5907 Mike

Claims

1. A light-emitting device including a transistor, first to fifth switches, a first capacitor, a second capacitor, and a light-emitting element, the first switch has one terminal electrically connected to a first wiring and the other terminal electrically connected to a first gate of the transistor; one of a source and a drain of the transistor is electrically connected to a second wiring, and the other of the source and the drain is electrically connected to one of the terminals of the fifth switch; the second switch has one terminal electrically connected to the first gate of the transistor and the other terminal electrically connected to one terminal of the fifth switch; the third switch has one terminal electrically connected to a third wiring and the other terminal electrically connected to the second gate of the transistor; the fourth switch has one terminal electrically connected to a fourth wiring and the other terminal electrically connected to one terminal of the fifth switch; the first capacitance element has a first electrode electrically connected to a first gate of the transistor and a second electrode electrically connected to the other of the source and the drain of the transistor; the second capacitance element has a first electrode electrically connected to a second gate of the transistor and a second electrode electrically connected to the other of the source and the drain of the transistor; the fifth switch has the other terminal electrically connected to a first electrode of the light-emitting element; The light emitting element has a second electrode electrically connected to the fourth wiring, a first period during which the third switch is in an on state and the fourth switch is in an off state; a second period during which the third switch is in an off state and the fourth switch is in an on state; the first wiring has a function of supplying an image signal; The second wiring has a function of supplying a first potential, the third wiring has a function of supplying a second potential; The fourth wiring of the light-emitting device has a function of supplying a third potential.

2. A light-emitting device including a transistor, first to fifth switches, a first capacitor, a second capacitor, and a light-emitting element, the first switch has one terminal electrically connected to a first wiring and the other terminal electrically connected to a first gate of the transistor; one of a source and a drain of the transistor is electrically connected to a second wiring, and the other of the source and the drain is electrically connected to one of the terminals of the fifth switch; the second switch has one terminal electrically connected to the first gate of the transistor and the other terminal electrically connected to one terminal of the fifth switch; the third switch has one terminal electrically connected to a third wiring and the other terminal electrically connected to the second gate of the transistor; the fourth switch has one terminal electrically connected to a fourth wiring and the other terminal electrically connected to one terminal of the fifth switch; the first capacitance element has a first electrode electrically connected to a first gate of the transistor and a second electrode electrically connected to the other of the source and the drain of the transistor; the second capacitance element has a first electrode electrically connected to a second gate of the transistor and a second electrode electrically connected to the other of the source and the drain of the transistor; the fifth switch has the other terminal electrically connected to a first electrode of the light-emitting element; The light emitting element has a second electrode electrically connected to the fourth wiring, a first period during which the third switch is in an on state and the fourth switch is in an off state; a second period during which the third switch is in an off state and the fourth switch is in an on state; the first wiring has a function of supplying an image signal; The second wiring has a function of supplying a first potential, the third wiring has a function of supplying a second potential; the fourth wiring has a function of supplying a third potential; The transistor is a light-emitting device having an oxide semiconductor film in a channel formation region.

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