Power supply control device and switching power supply device

Abstract

To improve noise characteristics while suppressing reduction in power supply efficiency.SOLUTION: A power supply control device (2) provided in a switching power supply device (1) that generates an output voltage (VOUT) from an input voltage (VIN), includes: an output stage (MM) having an output element (M1) provided between an application end of the input voltage and a switch terminal and having a rectification element (M2) provided between the switch terminal and a reference voltage end; a control circuit (10) for generating a control signal (CNT1) dependent on the output voltage; and an output element driving circuit (11, 13 to 15) which turns on or off the output element according to the control signal using a driving voltage (VDRV1) for turning on the output element. When switching the output element from off to on based on the control signal, the output element driving circuit switches the output element from off to on using a driving voltage having a first voltage (VBOOT-Vf), and then boosts the driving voltage to a second voltage (VBOOT).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a power supply control device and a switching power supply device. [Background technology]

[0002] In switching power supply devices, a so-called bootstrap circuit is often used to form a boost power supply for driving an output element (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-78023 A

[0004] [overview] In switching power supplies and their component parts, it is important to improve both power supply efficiency and noise characteristics.

[0005] A semiconductor device according to one embodiment of the present disclosure is a power supply control device configured to be provided in a switching power supply configured to generate an output voltage from an input voltage and configured to control the operation of the switching power supply, and includes an output stage having an output element provided between an application terminal of the input voltage and a switch terminal and a rectifier element provided between the switch terminal and a reference potential terminal, a control circuit configured to generate a control signal corresponding to the output voltage, and an output element drive circuit configured to use a drive voltage for turning on the output element and to turn the output element on or off in response to the control signal, wherein when switching the output element from off to on based on the control signal, the output element drive circuit switches the output element from off to on using the drive voltage having a first voltage, and then increases the drive voltage to a second voltage. [Brief description of the drawings]

[0006] [Figure 1]FIG. 1 is an overall configuration diagram of a switching power supply device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is an external perspective view of the power supply control device according to the embodiment of the present disclosure. [Diagram 3] FIG. 3 is a waveform diagram of a gate signal for an output transistor and a delayed signal based on the gate signal according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a timing chart of the switching power supply device according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram showing the overall configuration of a switching power supply device according to a reference example. [Figure 6] FIG. 6 is a waveform diagram relating to the switching power supply device of FIG. [Figure 7] FIG. 7 is a waveform diagram relating to the switching power supply device of FIG.

[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are generally omitted. In this specification, for the sake of simplicity, by writing a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, the name of the information, signal, physical quantity, functional part, circuit, element, or part corresponding to the symbol or code may be omitted or abbreviated.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference potential end (reference conductive part) having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage shown without a particular reference represents a potential seen from the ground. Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level. For any signal of interest, when the signal is at a high level, the inverted signal of the signal takes a low level, and when the signal is at a low level, the inverted signal of the signal takes a high level.

[0009] For any transistor configured as a FET (field effect transistor) such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." In addition, unless otherwise specified, the backgate of any MOSFET can be considered to be shorted to the source.

[0010] Hereinafter, the on and off states of any transistor may be expressed simply as on and off. For any transistor, the period during which the transistor is in the on state is referred to as the on period, and the period during which the transistor is in the off state is referred to as the off period. For any signal that has a high or low signal level, the period during which the signal level is high is referred to as the high level period, and the period during which the signal level is low is referred to as the low level period. The same applies to any voltage that has a high or low voltage level.

[0011] Unless otherwise specified, the connection between multiple parts that form a circuit, such as any circuit elements, wiring, nodes, etc., may be understood to refer to an electrical connection.

[0012] 1 is an overall configuration diagram of a switching power supply device 1 according to an embodiment of the present disclosure. The switching power supply device 1 includes a power supply control device 2 that controls the operation of the switching power supply device 1, and a plurality of discrete components provided outside the power supply control device 2. The plurality of discrete components include a capacitor C1 as an output capacitor, a capacitor C2 as a boot capacitor, resistors R1 and R2 as feedback resistors, and a coil L1. The switching power supply device 1 is connected to an input voltage V IN More desired output voltage V OUT The output terminal OUT has an output voltage V OUT That is, the output terminal OUT is the output voltage V OUT The application terminal (output voltage V OUT The output voltage V OUT is supplied to an arbitrary load (not shown) connected to the output terminal OUT.

[0013] Input voltage V IN and the output voltage V OUT is a positive DC voltage, and the output voltage V OUT is the input voltage V IN For example, the input voltage V IN is 12V, the resistance of resistors R1 and R2 can be adjusted to obtain a desired target voltage V TG (For example, 5V) at output voltage V OUT can be stabilized.

[0014] The switching power supply device 1 may be mounted on a vehicle such as an automobile. In this case, the input voltage V IN may be the output voltage of a battery mounted on a vehicle. Additionally, the switching power supply device 1 may be provided in any device (for example, a smartphone, a portable information terminal, a computer device, a game device, a television device, or an air conditioner).

[0015] FIG. 2 shows an external perspective view of the power supply control device 2. The power supply control device 2 is an electronic component (semiconductor device) including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) for accommodating the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the power supply control device 2. The power supply control device 2 is formed by sealing the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the power supply control device 2 and the type of housing of the power supply control device 2 shown in FIG. 2 are merely examples, and can be designed arbitrarily. The parts referenced by the reference numerals 11 to 17 shown in FIG. 1 are included in the semiconductor integrated circuit.

[0016] In Figure 1, only an input terminal IN, a switch terminal SW, a ground terminal GND, a boot terminal BOOT, and a feedback terminal FB are shown as the multiple external terminals provided in the power supply control device 2, but other external terminals (e.g., an enable terminal and a power good terminal) may also be provided in the power supply control device 2.

[0017] The external configuration of the power supply control device 2 will be described. IN is supplied to the input terminal IN. A coil L1 is interposed in series between the switch terminal SW and the output terminal OUT. That is, a first end of the coil L1 is connected to the switch terminal SW, and a second end of the coil L1 is connected to the output terminal OUT. In addition, the output terminal OUT is connected to ground via a capacitor C1. That is, a first end of the capacitor C1 is connected to the output terminal OUT, and a second end of the capacitor C1 is connected to ground. The current flowing through the coil L1 is referred to as a coil current IL.

[0018] The capacitor C2 is provided between the terminals BOOT and SW. That is, a first end of the capacitor C2 is connected to the boot terminal BOOT, and a second end of the capacitor C2 is connected to the switch terminal SW. The ground terminal GND is connected to ground.

[0019] The output terminal OUT is connected to the first end of the resistor R1, and the second end of the resistor R1 is connected to ground via the resistor R2. The connection node between the resistors R1 and R2 is connected to the feedback terminal FB. The output voltage V OUT Feedback voltage V according to FB The feedback voltage V FB is the output voltage V OUT Therefore, the output voltage V OUT The feedback voltage V FB The feedback terminal FB of the power supply control device 2 is connected to the connection node between the resistors R1 and R2, and a feedback voltage V FB The output voltage V OUT It is the feedback voltage V FB In any case, the feedback voltage V FB is the output voltage V OUT The voltage depends on

[0020] The following describes the internal configuration of the power supply control device 2. The power supply control device 2 includes an output stage MM, a control circuit 10, a high-side driver 11, a low-side driver 12, an insert transistor 13, a diode 14, a delay circuit 15, a boot rectifier element 16, and an internal power supply circuit 17. The high-side driver 11, the insert transistor 13, the diode 14, and the delay circuit 15 form an output transistor drive circuit 20 (output element drive circuit).

[0021] The internal power supply circuit 17 is connected to the input voltage V IN Based on the internal power supply voltage V REG Generates one or more internal supply voltages, including the internal supply voltage V REG has a predetermined positive DC voltage value (eg, 5V).

[0022] The output stage MM includes transistors M1 and M2. The transistors M1 and M2 are N-channel MOSFETs. The transistors M1 and M2 are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (in other words, ground). The transistors M1 and M2 are switched to drive the input voltage VIN is switched, and a square-wave switch voltage V SW (switching voltage) appears. Transistor M1 is a high-side transistor provided on the high side, and transistor M2 is a low-side transistor provided on the low side. Specifically, the drain of transistor M1 is connected to the input voltage V IN The input voltage V IN The source of the transistor M1 and the drain of the transistor M2 are commonly connected to a switch terminal SW. The source of the transistor M2 is connected to a ground terminal GND. Note that a resistor for detecting current (sense resistor) may be inserted between the source of the transistor M2 and ground.

[0023] The transistor M1 functions as an output element, and the transistor M2 functions as a synchronous rectifier element. The transistor M1 can be called an output transistor, and the transistor M2 can be called a synchronous rectifier transistor. The control circuit 10 controls the switching of the output stage MM. In the switching control of the output stage MM, the output element (M1) and the rectifier element (M2) are alternately turned on and off. The coil L1 and the capacitor C1 convert a square-wave-shaped switch voltage V appearing at the switch terminal SW into a square-wave-shaped switch voltage V SW The rectification and smoothing circuit rectifies and smooths the output voltage V OUT At least one of the output element (M1) and the rectifier element (M2) may be provided outside the power supply control device 2. The entire output stage MM may also be provided outside the power supply control device 2.

[0024] Gate signals G1 and G2 are supplied to the gates of the transistors M1 and M2, respectively. The transistors M1 and M2 are turned on and off according to the gate signals G1 and G2. When the gate signal G1 has a high level, the transistor M1 is in an on state, and when the gate signal G1 has a low level, the transistor M1 is in an off state. Similarly, when the gate signal G2 has a high level, the transistor M2 is in an on state, and when the gate signal G2 has a low level, the transistor M2 is in an off state. Basically, the transistors M1 and M2 are alternately turned on and off, but both the transistors M1 and M2 may be turned off. That is, the state of the output stage MM is one of an output high state, an output low state, and a Hi-Z state. In the output high state, the transistors M1 and M2 are in an on state and an off state, respectively. In the output low state, the transistors M1 and M2 are in an off state and an on state, respectively. In the Hi-Z state, both the transistors M1 and M2 are in an off state. Transistors M1 and M2 are never both turned on.

[0025] In the example of FIG. 1, the boot rectifier element 16 is a P-channel MOSFET. The internal power supply voltage V REG is supplied to the MOSFET as the boot rectifier element 16, and the source of the MOSFET is connected to a node ND1. The node ND1 is connected to a boot terminal BOOT. The boot rectifier element 16 and the capacitor C2 form a bootstrap circuit. The voltage at the boot terminal BOOT and the node ND1 is set to a boot voltage V BOOT FIG. 1 illustrates a parasitic diode associated with a MOSFET as the boot rectifier element 16, and the parasitic diode is connected to the internal power supply voltage V REG The forward direction is from the application end toward the node ND1.

[0026] When the output stage MM is in the output low state, the control circuit 10 controls the boot rectifier element 16 to be on, and the internal power supply voltage V REG The capacitor C2 is charged through the boot rectifier element 16 based on the boot voltage V BOOTis the voltage across the capacitor C2 only. SW When the output stage MM is in the high output state, the control circuit 10 controls the boot rectifier element 16 to be turned off. Even when the output stage MM is in the high output state, the boot voltage V BOOT is the voltage across the capacitor C2 only. SW is maintained at a higher level.

[0027] The node ND2 is an internal node provided in the power supply control device 2, similar to the node ND1. The insert transistor 13 is a switch provided between the nodes ND1 and ND2. The insert transistor 13 makes the node ND1 and ND2 conductive or cuts off the connection depending on a signal supplied to its gate. The insert transistor 13 is formed of a P-channel MOSFET. The drain of the insert transistor 13 is connected to the node ND1, and the source of the insert transistor 13 is connected to the node ND2. The diode 14 is added in parallel to the insert transistor 13. The diode 14 has a forward direction from the node ND1 to the node ND2. That is, the anode of the diode 14 is connected to the node ND1, and the cathode of the diode 14 is connected to the node ND2. Here, the diode 14 is a parasitic diode associated with the insert transistor 13. However, the diode 14 may be a diode provided separately from the insert transistor 13 (that is, it may be a diode different from the parasitic diode of the insert transistor 13). The voltage at the node ND2 is set to a driving voltage V DRV1 It is called.

[0028] The control circuit 10 controls the internal power supply voltage V REG The control circuit 10 is connected to a feedback terminal FB and is driven based on a feedback voltage V FB The control circuit 10 receives the feedback voltage V FB The control signals CNT1 and CNT2 are generated in response to the internal power supply voltage V REGThe low level of the control signals CNT1 and CNT2 has a potential of ground potential.

[0029] The high-level and low-level control signal CNT1 are signals that instruct the transistor M1 to be set to an on state and an off state, respectively. The high-level and low-level control signal CNT2 are signals that instruct the transistor M2 to be set to an on state and an off state, respectively. The control signals CNT1 and CNT2 are square wave signals having a predetermined PWM frequency. The PWM frequency corresponds to the switching period of the output stage MM. During the high-level period of the control signal CNT1, the control signal CNT2 is always at a low level, and during the high-level period of the control signal CNT2, the control signal CNT1 is always at a low level.

[0030] The control circuit 10 controls the feedback voltage V FB Based on the difference between the high-side driver 11 and a predetermined reference voltage, the control signals CNT1 and CNT2 are generated using pulse width modulation or the like so as to reduce the difference. The control circuit 10 may have a sense circuit that detects the coil current IL, and may generate the control signals CNT1 and CNT2 by referring to the detection result of the coil current IL (so-called current mode control may be performed). The control signal CNT1 is supplied to the high-side driver 11, and the control signal CNT2 is supplied to the low-side driver 12.

[0031] The control circuit 10 also sets the boot rectifier element 16 on or off by controlling the gate potential of the boot rectifier element 16. The control circuit 10 controls the gate potential of the boot rectifier element 16 so that the boot rectifier element 16 is on during a high-level period of the control signal CNT2 (in other words, the boot rectifier element 16 is on during a low-level period of the control signal CNT1) and is off during a low-level period of the control signal CNT2 (in other words, the boot rectifier element 16 is off during a high-level period of the control signal CNT1).

[0032] The high-side driver 11 is connected to the gate of the transistor M1. The high-side driver 11 turns the transistor M1 on or off by supplying a gate signal G1 to the gate of the transistor M1 in accordance with a control signal CNT1. The high-side driver 11 is connected to a node ND2 and a switch terminal SW, and supplies a drive voltage V DRV1 is the positive power supply voltage and the switch voltage V at the switch terminal SW SW is used as the negative power supply voltage. DRV1 serves as the voltage to turn on transistor M1.

[0033] The gate signal G1 has a high or low potential. The high-side driver 11 generates the gate signal G1 so that the gate signal G1 has a high level during a high-level period of the control signal CNT1 and has a low level during a low-level period of the control signal CNT1. The high-side driver 11 includes a level shifter that shifts the level of the control signal CNT1 to the level of the gate signal G1.

[0034] The high level of the gate signal G1 is the driving voltage V DRV1 and substantially corresponds to the driving voltage V DRV1 Strictly speaking, the high-level gate signal G1 is equal to the drive voltage V DRV1 In the following, the high-level gate signal G1 is driven by the driving voltage V DRV1 The potential of the high-level gate signal G1 is the driving voltage V DRV1 increases with increasing drive voltage V DRV1 The low level of the gate signal G1 is the switch voltage V SW , which corresponds substantially to the switch voltage V SW Strictly speaking, the low-level gate signal G1 is equal to the switch voltage V SW In the following, the low level gate signal G1 is set to the switch voltage V SW It is considered that the potential is

[0035] When switching control is performed, the differential voltage (V DRV1 -V SW ) is higher than the gate threshold voltage of transistor M1. REG is set. Therefore, the transistor M1 is on during the high-level period of the gate signal G1. During the low-level period of the gate signal G1, the gate-source voltage of the transistor M1 is substantially 0 V (because it is at least smaller than the gate threshold voltage of the transistor M1), so the transistor M1 is off.

[0036] The low-side driver 12 is connected to the gate of the transistor M2. The low-side driver 12 turns the transistor M2 on or off by supplying a gate signal G2 to the gate of the transistor M2 in accordance with a control signal CNT2. The low-side driver 12 supplies a driving voltage V DRV2 and ground, and the driving voltage V DRV2 The driving voltage V is used as the positive power supply voltage and the ground voltage is used as the negative power supply voltage. DRV2 is one of the internal power supply voltages generated by the internal power supply circuit 17, and has a positive DC voltage value. DRV2 is higher than the gate threshold voltage of transistor M2. Here, the driving voltage V DRV2 as the internal power supply voltage V REG is used, but the driving voltage V DRV2 is the internal power supply voltage V REG The driving voltage V may be a different DC voltage. DRV2 serves as the voltage to turn on transistor M2.

[0037] The gate signal G2 has a high or low potential. The low-side driver 12 generates the gate signal G2 such that the gate signal G2 has a high potential during a high-level period of the control signal CNT2 and has a low potential during a low-level period of the control signal CNT2.

[0038] The high level of the gate signal G2 is the driving voltage V DRV2 and substantially corresponds to the driving voltage V DRV2 Strictly speaking, the high-level gate signal G2 is equal to the drive voltage V DRV2 In the following, the high-level gate signal G2 is driven by the driving voltage V DRV2 The low level of the gate signal G2 is substantially equal to the ground potential. Strictly speaking, the low level of the gate signal G2 can be a small voltage higher than the ground potential, but in the following, the low level of the gate signal G2 is considered to have the ground potential.

[0039] Drive voltage V DRV2 is higher than the gate threshold voltage of the transistor M2, so that the transistor M2 is on during the high-level period of the gate signal G2. During the low-level period of the gate signal G2, the gate-source voltage of the transistor M2 is substantially 0 V (at least smaller than the gate threshold voltage of the transistor M2), so that the transistor M2 is off.

[0040] The delay circuit 15 is provided between the gate of the transistor M1 and the gate of the insert transistor 13. The delay circuit 15 is connected to the gate of the transistor M1 and the gate of the insert transistor 13. The delay circuit 15 supplies a delay signal dG1 based on the gate signal G1 to the gate of the insert transistor 13. The delay circuit 15 generates and outputs a signal obtained by delaying the gate signal G1 as the delay signal dG1. At this time, the delay circuit 15 generates and outputs an inverted signal of the gate signal G1 as the delay signal dG1. For this reason, the delay signal dG1 may be referred to as an inverted delay signal dG1.

[0041] FIG. 3 shows the relationship between the gate signal G1 and the delay signal dG1. In principle, the delay circuit 15 uses the delay signal dG1 as an inverted signal of the gate signal G1. However, when the gate signal G1 switches from low level to high level at time T1, the delay circuit 15 switches the delay signal dG1 from high level to low level at a point in time when a predetermined delay time Δtd1 has elapsed from time T1. Thereafter, when the gate signal G1 switches from high level to low level at time T2, the delay circuit 15 switches the delay signal dG1 from low level to high level at a point in time when a predetermined delay time Δtd2 has elapsed from time T2. The delay times Δtd1 and Δtd2 are sufficiently shorter than 1 / 2 the switching period of the output stage MM (i.e., 1 / 2 the reciprocal of the PWM frequency). The delay times Δtd1 and Δtd2 may be the same as each other or may be different from each other. It is not essential to provide the delay time Δtd2. In addition, during the high-level period of the gate signal G1, the driving voltage V DRV1 The level of the gate signal G1 also varies with the variation of the gate voltage Vcc, but this variation is not shown in FIG.

[0042] The insertion transistor 13 is turned on or off in response to the delay signal dG1. When the delay signal dG1 has a high level, the insertion transistor 13 is off, and when the delay signal dG1 has a low level, the insertion transistor 13 is on. Therefore, after the gate signal G1 of the transistor M1 switches from a low level to a high level, the transistor M1 switches from off to on, and then the insertion transistor 13 switches from off to on.

[0043] The delay circuit 15 delays the boot voltage V BOOT is the positive power supply voltage and the switch voltage V at the switch terminal SW SW is used as the negative power supply voltage. Therefore, the high-level delayed signal dG1 is driven by the boot voltage V BOOT The low-level delayed signal dG1 has a potential of SW As a variant, the negative power supply voltage in the delay circuit 15 is the switch voltage V SWIn this case, the low-level delayed signal dG1 is equal to the switch voltage V SW The delay circuit 15 has a lower potential (for example, a ground potential) and is composed of a single inverter circuit, or is composed of a plurality of delay elements connected in series including an inverter circuit.

[0044] 4 shows a timing chart of the switching power supply device 1. From top to bottom, the timing chart shows a control signal CNT1, a gate signal G1, a delay signal dG1, a control signal CNT2, a gate signal G2, a switch voltage V SW , boot voltage V BOOT , driving voltage V DRV1 4 shows the waveform of the coil current IL. The timing chart of FIG. 4 is a timing chart for a period in which switching control is performed in the current continuous mode. In the current continuous mode, the coil current IL always flows from the switch terminal SW to the output terminal OUT. It is assumed that the on-resistance of each of the transistors M1 and M2 is sufficiently small, and for the sake of simplicity, it is assumed that the drain-source voltage of the transistor M1 during the on-period of the transistor M1 and the drain-source voltage of the transistor M2 during the on-period of the transistor M2 are zero. In addition, when switching the output stage MM between the output high state and the output low state, a dead time period in which the transistors M1 and M2 are simultaneously turned off can be inserted to suppress shoot-through current, but the existence of the dead time period is ignored here.

[0045] During the execution period of the switching control, the level of the control signal CNT1 alternates between a low level and a high level. One of the times when the level of the control signal CNT1 switches from a low level to a high level is time T1, and time T2 is the time after time T1 when the level of the control signal CNT1 switches from a high level to a low level.

[0046] At time T1, the control circuit 10 switches the level of the control signal CNT1 from low to high and switches the level of the control signal CNT2 from high to low. As a result, at time T1, the state of the transistor M1 switches from off to on and the state of the transistor M2 switches from on to off through the transition of the gate signal G1 to high and the transition of the gate signal G2 to low. As a result, the switch voltage V SW The input voltage V IN The boot voltage V BOOT also rises.

[0047] Boot voltage V BOOT In conjunction with the rise in DRV1 However, from time T1 until the delay time Δtd1 has elapsed, the delay signal dG1 is at a high level, so the insertion transistor 13 is off. Therefore, from time T1 until the delay time Δtd1 has elapsed, the drive voltage V DRV1 is the boot voltage V BOOT is lower by the forward voltage Vf of the diode 14.

[0048] The time after the delay time Δtd1 from time T1 is before time T2. At the time after the delay time Δtd1 from time T1, the delay signal dG1 changes from high level to low level, so that the state of the insertion transistor 13 switches from off to on. As a result, the drive voltage V DRV1 The boot voltage V BOOT rises to a level of

[0049] After that, at time T2, the control circuit 10 switches the level of the control signal CNT1 from high to low and switches the level of the control signal CNT2 from low to high. As a result, the state of the transistor M1 switches from on to off and the state of the transistor M2 switches from off to on through the transition of the gate signal G1 to low and the transition of the gate signal G2 to high. As a result, the switch voltage V SW is the input voltage V INThe boot voltage V BOOT also decreases.

[0050] Boot voltage V BOOT In conjunction with the decrease in the drive voltage V DRV1 At time T2, the insertion transistor 13 is on based on the low-level delayed signal dG1, so that the boot voltage V BOOT In conjunction with the decrease in the boot voltage V BOOT The drive voltage V DRV1 After this, the same operation is repeated.

[0051] FIG. 5 shows a switching power supply device 1ref according to a reference example, which is provided for comparison with the switching power supply device 1. The switching power supply device 1ref includes a power supply control device 2ref instead of the power supply control device 2. The power supply control device 2ref does not include the insertion transistor 13, the diode 14, and the delay circuit 15. In the power supply control device 2ref, the voltage "V DRV1 =V BOOT "

[0052] FIG. 6 shows the gate signals G1 and G2 and the switch voltage V SW In the switching power supply device 1ref, the gate signal G1 is switched to the switch voltage V SW from the boot voltage V BOOT As a result, in the switching power supply device 1ref, the switching voltage V SW Ringing occurs at the switch voltage V SW The ringing of the boot voltage V BOOT If the voltage across the capacitor C2 is reduced, the switch voltage V SW The ringing of the boot voltage V BOOTA decrease in Vref decreases the efficiency of the power supply through an increase in the on-resistance of the transistor M1.

[0053] FIG. 7 shows the gate signals G1 and G2 and the switch voltage V SW In the switching power supply device 1, in response to the transition of the control signal CNT1 to a high level, the gate signal G1 first changes to the switch voltage V SW Voltage (V BOOT The rise of the gate signal G1 causes the voltage (V BOOT -Vf), the switching voltage V SW rises smoothly, and the switch voltage V SW In the switching power supply device 1, the insertion transistor 13 is then turned on, causing the gate signal G1 to reach the boot voltage V BOOT By increasing the gate signal G1, the on-resistance of the transistor M1 can be reduced, thereby suppressing a decrease in power supply efficiency. In other words, the switching power supply device 1 can improve noise characteristics while suppressing a decrease in power supply efficiency.

[0054] In this manner, in the switching power supply device 1, when switching the transistor M1 from off to on based on the control signal CNT1, the output transistor drive circuit 20 generates a drive voltage V DRV1 After switching the transistor M1 from off to on using DRV1 to a second voltage.

[0055] Here, the first voltage is the driving voltage V when the insert transistor 13 is turned off. DRV1 (=V BOOT -Vf), and the second voltage corresponds to the drive voltage V DRV1 (=V BOOT ) in the state where the insert transistor 13 is turned off, when the output transistor drive circuit 20 switches the transistor M1 from off to on based on the control signal CNT1.DRV1 (=V BOOT -Vf) is used to switch the transistor M1 from off to on, and then the drive voltage V DRV1 (=V BOOT ) is used to keep transistor M1 on.

[0056] It can be said that the output transistor drive circuit 20 includes an output element driver and a drive voltage generation circuit. The output element driver corresponds to the high-side driver 11. The output element driver is connected to a node ND2 and a switch terminal SW, and generates a drive voltage V DRV1 A high-level gate signal G1 or a switch voltage V SW The drive voltage generating circuit includes an insert transistor 13 (switch), a diode 14, and a delay circuit 15, and generates the second voltage (V BOOT ) to the driving voltage V DRV1 Generate.

[0057] <<Deformations, etc.>> Modifications, applications, and supplementary points regarding the above-described switching power supply device 1 will now be described.

[0058] A diode rectification method may be adopted in the output stage MM. When the diode rectification method is adopted, a synchronous rectification diode having an anode connected to the ground terminal GND and a cathode connected to the switch terminal SW is used as a rectification element instead of the transistor M2. When the diode rectification method is adopted, the low-side driver 12 is not required, and therefore the generation of the control signal CNT2 is also not required. When the diode rectification method is adopted, only the output element (M1) is turned on and off in the switching control of the output stage MM. When the diode rectification method is adopted, the control circuit 10 only needs to control the gate potential of the boot rectification element 16 so that the boot rectification element 16 is turned on during the low-level period of the control signal CNT1 and so that the boot rectification element 16 is turned off during the high-level period of the control signal CNT1.

[0059] 1, a switching element is used as the boot rectifier element 16, but the boot rectifier element 16 may be configured as a simple rectifier diode. In this case, the rectifier diode as the boot rectifier element 16 is REG and a cathode connected to a node ND1. When the boot rectifier element 16 is a rectifier diode, the control circuit 10 does not need to control the conduction of the boot rectifier element 16.

[0060] The boot rectifier element 16 may be provided outside the power supply control device 2 .

[0061] For any signal or voltage, the relationship between the high level and the low level thereof may be reversed to that described above without prejudice to the spirit of the above.

[0062] The channel types of FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel without departing from the spirit of the above.

[0063] Any of the transistors described above may be any type of transistor, provided that no disadvantage occurs. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage occurs. Any of the transistors has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

[0064] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and can be changed to various numerical values ​​as a matter of course.

[0065] <<Additional Notes>> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0066] A power supply control device according to one aspect of the present disclosure is a device for controlling an input voltage (V IN ) to output voltage (V OUT A power supply control device (2) is provided in a switching power supply device (1) configured to generate a drive voltage (V) for turning on the output element (M1) and configured to control the operation of the switching power supply device, the power supply control device (2) comprising an output stage (MM) having an output element (M1) provided between an application terminal (IN) of the input voltage and a switch terminal (SW) and a rectifier element (M2) provided between the switch terminal and a reference potential terminal, a control circuit (10) configured to generate a control signal (CNT1) corresponding to the output voltage, and a drive voltage (V) for turning on the output element (M1). DRV1 and an output element drive circuit (11, 13 to 15) configured to turn on or off the output element in response to the control signal using a first voltage (V BOOT After switching the output element from OFF to ON using the drive voltage having a second voltage (V BOOT ) (first configuration).

[0067] This makes it possible to improve noise characteristics while suppressing a decrease in power supply efficiency.

[0068] In the power supply control device according to the first configuration, the output element drive circuit may include a switch (13) provided between a first node (ND1) having the second voltage and a second node (ND2) having the drive voltage, and a diode (14) having a forward direction from the first node to the second node is added in parallel to the switch, and when switching the output element from off to on based on the control signal, the output element drive circuit switches the output element from off to on using the drive voltage when the switch is off, and then keeps the output element on using the drive voltage when the switch is on, and the first voltage corresponds to the drive voltage when the switch is off and is lower than the second voltage by the forward voltage of the diode, and the second voltage corresponds to the drive voltage when the switch is on (second configuration).

[0069] In the power supply control device according to the second configuration, a boot terminal (BOOT) configured to be connected to a first end of a boot capacitor (C2), and the switch terminal configured to be connected to a second end of the boot capacitor, the boot terminal is connected to the first node, the output element is an output transistor (13) formed by an N-channel type field effect transistor, the drain and source of the output transistor are connected to the input voltage application terminal and the switch terminal, respectively, and the output element drive circuit may be configured to turn on the output transistor by supplying a high-level gate signal corresponding to the drive voltage to the gate of the output transistor (third configuration).

[0070] In the power supply control device according to the third configuration, the output element drive circuit may be configured to turn off the output transistor by supplying a low-level gate signal that is lower than a high-level gate signal to the gate of the output transistor, and the output element drive circuit may have a delay circuit (15) provided between the gate of the output transistor and the switch, and may be configured to switch the switch from off to on using the delay circuit after the gate signal of the output transistor switches from low level to high level (fourth configuration).

[0071] In the power supply control device according to the fourth configuration, the switch may be a P-channel field effect transistor (13) configured to connect or disconnect the first node and the second node depending on a signal supplied to its gate, the diode may be a parasitic diode added to the insert transistor or a diode provided separately from the parasitic diode, and the delay circuit may be configured to supply an inverted signal of the gate signal of the output transistor to the gate of the insert transistor, thereby switching the insert transistor from off to on after the gate signal of the output transistor switches from low level to high level (fifth configuration).

[0072] In the power supply control device according to the fourth or fifth configuration, the output element drive circuit may be configured (sixth configuration) to include an output element driver (11) connected to the second node and the switch terminal and configured to supply, based on the control signal, a high-level gate signal corresponding to the drive voltage or a low-level gate signal corresponding to the voltage of the switch terminal to the gate of the output transistor, and a drive voltage generation circuit (13-15) having the switch, the diode and the delay circuit and configured to generate the drive voltage from the second voltage.

[0073] In the power supply control device according to any one of the first to sixth configurations, the output element is alternately turned on and off based on the control signal, thereby generating a switch voltage (VSW ) may be rectified and smoothed to generate the output voltage (seventh configuration).

[0074] A switching power supply device according to one aspect of the present disclosure includes a power supply control device according to any one of the first to sixth configurations described above, and a rectifying and smoothing circuit (L1, C1) connected to the switch terminal and an output terminal (OUT), and the rectifying and smoothing circuit controls a switching voltage (V SW ) may be rectified and smoothed to generate the output voltage at the output terminal (eighth configuration). [Explanation of symbols]

[0075] 1 Switching power supply 2 Power supply control device 10 Control circuit 11 High Side Driver 12 Low Side Driver 13 Insertion transistor 14 Diode 15 Delay Circuit 16 Boot rectifier 17 Internal power circuit MM output stage M1 Transistor (output element) M2 Transistor (synchronous rectifier) C1, C2 capacitors L1 coil R1, R2 resistance IN Input terminal SW Switch terminal GND Ground terminal BOOT Boot terminal FB Feedback pin OUT Output terminal V IN Input voltage V OUT Output Voltage V FB Feedback Voltage V SW Switch Voltage V BOOT Boot Voltage V DRV1 , V DRV2 Driving voltage V REG Internal Power Supply Voltage CNT1, CNT2 control signals G1, G2 gate signals IL Coil current ND1, ND2 nodes

Claims

1. A power supply control device provided in a switching power supply device configured to generate an output voltage from an input voltage, and configured to control an operation of the switching power supply device, an output stage having an output element provided between an application terminal of the input voltage and a switch terminal, and a rectifying element provided between the switch terminal and a reference potential terminal; a control circuit configured to generate a control signal responsive to the output voltage; an output element drive circuit configured to turn on or off the output element in response to the control signal by using a drive voltage for turning on the output element; When switching the output element from OFF to ON based on the control signal, the output element drive circuit switches the output element from OFF to ON using the drive voltage having a first voltage, and then increases the drive voltage to a second voltage. , power supply control device.

2. the output element drive circuit includes a switch provided between a first node having the second voltage and a second node having the drive voltage; a diode having a forward direction in a direction from the first node to the second node is added in parallel to the switch; when switching the output element from OFF to ON based on the control signal, the output element drive circuit switches the output element from OFF to ON using the drive voltage when the switch is OFF, and then keeps the output element ON using the drive voltage when the switch is ON; the first voltage corresponds to the drive voltage when the switch is turned off, and is lower than the second voltage by a forward voltage of the diode; The second voltage corresponds to the drive voltage when the switch is turned on. The power supply control device according to claim 1 .

3. a boot terminal configured to be connected to a first end of a boot capacitor, and the switch terminal configured to be connected to a second end of the boot capacitor, the boot terminal being connected to the first node; the output element is an output transistor formed of an N-channel type field effect transistor, a drain and a source of the output transistor are connected to the input voltage application terminal and the switch terminal, respectively; The output element drive circuit supplies a high-level gate signal corresponding to the drive voltage to the gate of the output transistor, thereby turning on the output transistor. The power supply control device according to claim 2 .

4. the output element drive circuit turns off the output transistor by supplying a low-level gate signal that is lower than a high-level gate signal to a gate of the output transistor; The output element drive circuit has a delay circuit provided between the gate of the output transistor and the switch, and switches the switch from off to on using the delay circuit after the gate signal of the output transistor switches from low level to high level. The power supply control device according to claim 3 .

5. the switch is a P-channel field effect transistor configured to connect or disconnect the first node and the second node in response to a signal supplied to a gate of the switch; The diode is a parasitic diode added to the insertion transistor, or a diode provided separately from the parasitic diode, The delay circuit supplies an inverted signal of the gate signal of the output transistor to the gate of the insert transistor, thereby switching the insert transistor from off to on after the gate signal of the output transistor switches from a low level to a high level. The power supply control device according to claim 4 .

6. The output element drive circuit includes: an output element driver connected to the second node and the switch terminal, and configured to supply a high-level gate signal corresponding to the drive voltage or a low-level gate signal corresponding to a voltage of the switch terminal to a gate of the output transistor based on the control signal; a drive voltage generating circuit having the switch, the diode, and the delay circuit, and configured to generate the drive voltage from the second voltage. The power supply control device according to claim 4 .

7. The output element is alternately turned on and off based on the control signal, and a switch voltage generated at the switch terminal is rectified and smoothed to generate the output voltage. A power supply control device according to any one of claims 1 to 6.

8. A power supply control device according to any one of claims 1 to 6, a rectifying and smoothing circuit connected to the switch terminal and an output terminal, The rectifying and smoothing circuit rectifies and smoothes a switch voltage generated at the switch terminal when the output element is alternately turned on and off based on the control signal, thereby generating the output voltage at the output terminal. , switching power supply.

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