Display device

Abstract

To provide a display device capable of having higher definition.SOLUTION: A gate driver 42 includes a shift register circuit 421 in which a plurality of register circuits SRA are cascade-connected in a descending or ascending order in a Dy direction, and output circuits 422_p provided in accordance with the respective register circuits SRA. The output circuits 422_p include Q AND circuits that generate AND operation values of enable signal ENBs and output signals TRN(r) of the register circuits SRA, as a logical value of a scanning signal GATE(m). In the register circuits SRA, shift clock signals CKV1, CKV2, and CKV3 that become a high potential in (Q+1) horizontal periods are input in the descending or ascending order while being displaced by the Q horizontal periods. In the AND circuits, the enable signals ENBs that become a high potential in two horizontal periods are input in the descending or ascending order while being displaced by one horizontal period.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] In recent years, there has been a demand for higher resolution display panels in configurations where images are enlarged using lenses, such as virtual reality (VR), augmented reality (AR), and mixed reality (MR). As the resolution of display panels increases, ensuring the charging time for pixels becomes an issue.

[0003] Conventionally, in a dot sequential driving active matrix liquid crystal display device, a configuration has been disclosed in which the write time of the pixels on the scanning end side is delayed by about 1 / 2H in order to secure the time to write a video signal to the pixels on the scanning end side (for example, Patent Document 1). Also, in a high-resolution active matrix liquid crystal display device, a configuration has been disclosed in which a logical sum signal of an output signal of a shift register and a signal obtained by delaying the output signal by 1H is supplied as a scanning signal in order to secure the charging time of the pixels, and a display data signal is supplied in the latter 1H period of the scanning signal (for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2002-023683 A [Patent Document 2] JP 2001-356738 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the above Patent Document 1, it is necessary to provide a vertical driving circuit on both the left and right sides of the pixel section. Also, in the above Patent Document 2, it is necessary to provide a delay circuit and an OR circuit for each scanning signal line. Thus, in the above conventional techniques, there is a possibility that the circuit scale for driving the scanning lines will increase.

[0006] An object of the present invention is to provide a display device capable of achieving high resolution. [Means for solving the problem]

[0007] A display device according to an embodiment of the present disclosure includes a substrate having a display area in which a plurality of pixels are aligned in a first direction and a second direction different from the first direction, a plurality of scanning lines connected to the pixels aligned in the first direction, a plurality of signal lines connected to the pixels aligned in the second direction, a gate driver that supplies scanning signals to the scanning lines, and a signal line selection circuit that supplies pixel signals to the signal lines, the gate driver including: a shift register circuit in which a plurality of register circuits are cascaded in descending or ascending order in the second direction, the shift register circuit outputting a binary signal in which a high potential of an input signal at the rising edge of a shift clock signal is maintained until the falling edge of the shift clock signal; and a plurality of output circuits provided corresponding to the plurality of register circuits, respectively, the output circuit including: The scanning signal includes Q AND circuits which generate a logical product value of an output signal of the register circuit and an enable signal as a logical value of the scanning signal, and the register circuits each receive a shift clock signal which is at a high potential for Q+1 horizontal periods, in descending or ascending order, with a delay of Q horizontal periods, and the AND circuits each receive an enable signal which is at a high potential for two horizontal periods, in descending or ascending order, with a delay of one horizontal period.

[0008] A display device according to one embodiment of the present disclosure includes a substrate having a display area in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction, a plurality of scanning lines connected to the pixels arranged in the first direction, a plurality of signal lines connected to the pixels arranged in the second direction, a gate driver that supplies scanning signals to the scanning lines, and a signal line selection circuit that supplies pixel signals to the signal lines. The gate driver includes a shift register circuit in which a plurality of register circuits are cascaded in descending or ascending order in the second direction, the shift register circuit outputting a binary signal in which a high potential of an input signal at the falling edge of a shift clock signal is maintained until the rising edge of the shift clock signal, and a plurality of output circuits provided corresponding to the plurality of register circuits, respectively. The output circuit includes Q AND circuits that generate a logical product of an output signal of the register circuit and an enable signal as a logical value of the scanning signal, and the register circuits each receive a shift clock signal that is at a low potential for Q+1 horizontal periods in descending or ascending order with a shift period of Q horizontal periods, and the AND circuits each receive an enable signal that is at a high potential for two horizontal periods in descending or ascending order with a shift period of one horizontal period. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a display device. [Diagram 2] FIG. 2 is a diagram showing an example of a pixel arrangement in a display region. [Diagram 3] FIG. 3 is a cross-sectional view showing a schematic cross-sectional structure of the display device. [Figure 4] FIG. 4 is a plan view showing an example of the configuration of a pixel. [Figure 5A] FIG. 5A is a diagram showing a first example of a cross section taken along line A1-A2 in FIG. [Figure 5B] FIG. 5B is a diagram showing a second example of a cross section taken along line A1-A2 in FIG. [Figure 6] FIG. 6 is a diagram showing an example of a drive circuit configuration. [Figure 7] FIG. 7 is a diagram showing an example of a gate driver configuration according to a conventional example. [Figure 8] FIG. 8 is a timing chart of each part in the conventional example. [Figure 9A] FIG. 9A is a diagram showing a first waveform example in a conventional example. [Figure 9B] FIG. 9B is a diagram showing a second waveform example in the conventional example. [Figure 9C] FIG. 9C is a diagram showing a third waveform example in the conventional example. [Figure 10] FIG. 10 is a diagram showing an example of a display defect in a conventional example. [Figure 11] FIG. 11 is a diagram showing an example of a gate driver configuration according to the embodiment. [Figure 12] FIG. 12 is a timing chart of each part in the configuration shown in FIG. [Figure 13A] FIG. 13A is a diagram showing a first waveform example in the embodiment. [Figure 13B] FIG. 13B is a diagram showing a second waveform example in the embodiment. [Figure 13C] FIG. 13C is a diagram showing a third waveform example in the embodiment. [Figure 14] FIG. 14 is a diagram showing an example of a gate driver configuration according to a first modified example of the embodiment. [Figure 15] FIG. 15 is a timing chart of each part in the configuration shown in FIG. [Figure 16] FIG. 16 is a diagram showing an example of a gate driver configuration according to a second modified example of the embodiment. [Figure 17] FIG. 17 is a timing chart of each part in the configuration shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The form (embodiment) for carrying out the invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiment. The components described below include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the components described below can be appropriately combined. Note that the disclosure is merely an example, and those that a person skilled in the art can easily imagine appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, in order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0011] Fig. 1 is a diagram showing an example of a schematic configuration of a display device, and Fig. 2 is a diagram showing an example of a pixel arrangement in a display region.

[0012] The display device 1 according to the present embodiment is, for example, a liquid crystal display device using a liquid crystal display element as a display element. In addition, in the present disclosure, the display device 1 may adopt, for example, a column inversion driving method or a frame inversion method as a driving method. The driving method in the display device 1 is not limited to the column inversion driving method or the frame inversion method.

[0013] The display device 1 has a display area AA provided on a display panel 11, and a drive circuit 40 provided in a peripheral area of ​​the display area AA. The display device 1 is supplied with power from a power supply device 12.

[0014] The drive circuit 40 includes a gate driver 42, a signal line selection circuit 43, and a display control circuit 44. The gate driver 42 and the signal line selection circuit 43 are thin film transistor (TFT) circuits formed in the peripheral region of the display area AA. The display control circuit 44 is included in a driver IC4 mounted in the peripheral region of the display area AA. The driver IC4 is connected to the control device 13 via a relay board constituted by, for example, a flexible printed circuit (FPC) board or the like.

[0015] The control device 13 controls the power supply from the power supply device 12 to the display device 1. The control device 13 also controls power on and power off of the display device 1. The power supply device 12 and the control device 13 are mounted, for example, in a device (not shown) in which the display device 1 is mounted.

[0016] The display area AA is provided with a plurality of pixels Pix arranged in the Dx direction (first direction) and the Dy direction (second direction). The display area AA is also provided with scanning lines (gate lines) SCL that supply scanning signals (gate signals) GATE to the pixels Pix, signal lines DTL that supply pixel signals SIG to the pixels Pix, and a common electrode COML that supplies a common potential VCOM to the pixels Pix. In this embodiment, the scanning lines SCL are provided extending in the Dx direction (first direction). In this embodiment, the signal lines DTL are provided extending in the Dy direction (second direction).

[0017] As shown in Fig. 2, each pixel Pix includes a pixel transistor Tr and a pixel electrode PX. The pixel transistor Tr is configured with a thin film transistor (TFT), for example, an n-channel MOS (Metal Oxide Semiconductor) type TFT (hereinafter also referred to as "n-type TFT"). The source of the pixel transistor Tr is connected to a signal line DTL, the gate is connected to a scanning line (gate line) SCL, and the drain is connected to the pixel electrode PX. A storage capacitance CS is formed between the pixel electrode PX and a common electrode COML.

[0018] A scanning signal (gate signal) GATE (1, 2, . . . , m, . . . , M) is supplied to the gates of the pixel transistors Tr of the pixels Pix arranged in the Dx direction (first direction) via the respective scanning lines (gate lines) SCL, and a pixel signal SIG (1, 2, . . . , n, . . . N) is supplied to the sources of the pixel transistors Tr of the pixels Pix arranged in the Dy direction (second direction) via the respective signal lines DTL. In FIG. 2, an example is shown in which N pixels Pix are arranged in the Dx direction (first direction) and M pixels Pix are arranged in the Dy direction (second direction), but this is not limiting. Hereinafter, a row in which the pixels Pix are arranged in the Dx direction (first direction) is also referred to as a pixel row. Also, a column in which the pixels Pix are arranged in the Dy direction (second direction) is also referred to as a pixel column.

[0019] In the present disclosure, the pixel Pix includes, for example, a red pixel for displaying red (R), a green pixel for displaying green (G), and a blue pixel for displaying blue (B). An example of the pixel arrangement is a stripe arrangement in which RGB pixels are arranged in the Dx direction (first direction), but the pixel arrangement is not limited to the RGB stripe arrangement. Specifically, for example, the pixel Pix may be a white pixel for displaying white (W), a diagonal stripe arrangement having a predetermined angle with respect to the Dx direction (first direction) or the Dy direction (second direction), or an arrangement in which a plurality of pixel groups displaying different colors are periodically arranged in both the Dx direction (first direction) and the Dy direction (second direction).

[0020] The power supply device 12 generates a first power supply voltage signal PSIG1 of a positive value and a second power supply voltage signal PSIG2 of a negative value to be supplied to the display device 1. The first power supply voltage signal PSIG1 is controlled to a first potential (VGH). The second power supply voltage signal PSIG2 is controlled to a second potential (VGL) that is lower than the first potential (VGH). The first potential (VGH) is set to, for example, 6V. The second potential (VGL) is set to, for example, -6V. The first potential (VGH) is not limited to 6V. Furthermore, the second potential (VGL) is not limited to -6V.

[0021] The control device 13 transmits a video signal, which is an original signal of a video to be displayed on the display device 1, to the display device 1. The control device 13 also transmits a control signal for controlling the display device 1 to the display device 1. The control device 13 also transmits a control signal for controlling the power supply from the power supply device 12 to the display device 1 to the power supply device 12.

[0022] The control device 13 includes, for example, a storage device such as a CPU (Central Processing Unit) and a memory. The control device 13 executes a program using these hardware resources such as the CPU and the storage device, thereby realizing the display function of the display device 1. The control device 13 controls the driver IC 4 to handle an image to be displayed on the display device 1 as image input gradation information according to the execution result of the program.

[0023] The display control circuit 44 controls the display operation in the display area AA by controlling the gate driver 42 and the signal line selection circuit 43. The display control circuit 44 receives video signals and various control signals from the control device 13. The display control circuit 44 also converts the video signals from the control device 13 into image signals Vsig and outputs them. The image signals Vsig are, for example, signals obtained by time-division multiplexing pixel signals SIG corresponding to the RGB pixel arrangement. The display control circuit 44 also supplies a common potential VCOM to the common electrode COML.

[0024] The display control circuit 44 also functions as an interface (I / F) between the signal line selection circuit 43 and the control device 13, and as a timing generator.

[0025] Next, a schematic structure of the display device 1 according to the embodiment will be described with reference to FIG. 3 to FIG. 5B. FIG. 3 is a cross-sectional view showing a schematic cross-sectional structure of the display device. FIG. 4 is a plan view showing a configuration example of a pixel. FIG. 5A is a diagram showing a first example of a cross section taken along line A1-A2 in FIG. 4. In the first example shown in FIG. 5A, a bottom-gate type transistor is used as the pixel transistor Tr. FIG. 5B is a diagram showing a second example of a cross section taken along line A1-A2 in FIG. 4. In the second example shown in FIG. 5B, a top-gate type transistor is used as the pixel transistor Tr.

[0026] The array substrate 2 includes a first substrate 21 made of glass or transparent resin, a plurality of pixel electrodes PX, a common electrode COML, and an insulating layer 24 that insulates the pixel electrodes PX and the common electrode COML. The plurality of pixel electrodes PX are arranged, for example, in a matrix above the first substrate 21. The common electrode COML is provided between the first substrate 21 and the pixel electrodes PX.

[0027] The pixel electrodes PX are provided corresponding to each pixel Pix. A pixel signal SIG for performing a display operation is supplied to the pixel electrodes PX from a signal line selection circuit 43 via a signal line DTL and a pixel transistor Tr. During a display operation, a common potential VCOM for display, which is a voltage signal, is supplied to the common electrode COML from a driver IC4. The common potential VCOM is preferably a potential different from the GND potential, and is set to, for example, about −0.7V. The set value of the common potential VCOM is set to an optimal value that does not cause flicker in a driving method such as a column inversion driving method or a frame inversion driving method. The common potential VCOM is preferably a fixed potential, but may be configured to have a waveform consisting of an AC rectangular wave.

[0028] The pixel electrodes PX and the common electrode COML are made of a conductive material having light-transmitting properties, such as ITO (Indium Tin Oxide), etc. A polarizing plate 35B is provided on the lower side of the first substrate 21 via an adhesive layer (not shown).

[0029] The counter substrate 3 includes a second substrate 31 made of glass or transparent resin, and a color filter 32 and a light-shielding layer (not shown) formed on one surface of the second substrate 31. In addition, a polarizing plate 35A is provided on the upper side of the second substrate 31 via an adhesive layer (not shown).

[0030] The array substrate 2 and the counter substrate 3 are disposed opposite to each other with a predetermined gap (cell gap) provided. A liquid crystal layer 6 is provided as a display function layer in the space between the first substrate 21 and the second substrate 31. The liquid crystal layer 6 modulates light passing through the liquid crystal layer 6 by changing the alignment state of the liquid crystal molecules for each pixel Pix according to the state of the electric field between each pixel electrode PX and the common electrode COML. In this embodiment, for example, a liquid crystal suitable for a lateral electric field mode such as IPS (in-plane switching) including FFS (fringe field switching) is used.

[0031] The array substrate 2 includes wiring such as pixel transistors Tr of each pixel Pix, signal lines DTL that supply pixel signals SIG to each pixel electrode PX, and scanning lines (gate lines) SCL that supply gate signals GATE that drive each pixel transistor Tr. The signal lines DTL and the scanning lines (gate lines) SCL extend in a plane parallel to the surface of the first substrate 21.

[0032] 4, a region surrounded by a scanning line (gate line) SCL and a signal line DTL is a pixel Pix. The pixel electrode PX has a plurality of strip-shaped electrodes 22a and a connecting portion 22b.

[0033] As shown in FIG. 4, the pixel transistor Tr includes a semiconductor 61, a source electrode 62, a drain electrode 63 and a gate electrode 64.

[0034] As shown in FIG. 5A, in a configuration using a bottom-gate type transistor as the pixel transistor Tr, a gate line layer 51 is provided on a first substrate 21. A gate electrode 64 (scanning line (gate line) SCL) is provided on the gate line layer 51. An insulating layer 58a (second insulating layer) is provided on the first substrate 21, covering the gate electrode 64. A semiconductor layer 52 is provided on the insulating layer 58a. A semiconductor 61 is provided on the semiconductor layer 52. A signal line layer 53 is provided on the upper side of the semiconductor layer 52 via an insulating layer 58c (first insulating layer).

[0035] As shown in FIG. 5B, in a configuration using a top-gate transistor as the pixel transistor Tr, a light shield LS is provided on the first substrate 21. A semiconductor layer 52 is provided on the light shield LS via an insulating layer 58f. A semiconductor 61 is provided on the semiconductor layer 52. A gate line layer 51 is provided on the upper side of the semiconductor layer 52 via an insulating layer 58c. A gate electrode 64 is provided on the gate line layer 51. An insulating layer 58a is provided on the insulating layer 58c, covering the gate electrode 64. A signal line layer 53 is provided on the upper side of the gate line layer 51 via the insulating layer 58a.

[0036] A drain electrode 63 and a source electrode 62 (signal line DTL) are provided on the signal line layer 53. An auxiliary wiring layer 54 is provided above the drain electrode 63 and the source electrode 62 (signal line DTL) via an insulating layer 58d (third insulating layer). A common electrode layer 55 is provided above the auxiliary wiring layer 54 via an insulating layer 58e. A common electrode COML is provided on the common electrode layer 55. Note that a configuration in which the auxiliary wiring layer and the common electrode layer overlap without an insulating layer can also be employed. A pixel electrode PX is provided above the common electrode layer 55 via an insulating layer 24.

[0037] As shown in FIG. 4 and FIG. 5A (or FIG. 5B), the pixel electrode PX is connected to a drain electrode 63 of the pixel transistor Tr through a contact hole H11. The drain electrode 63 is connected to a semiconductor 61 through a contact hole H12. The semiconductor 61 intersects with a gate electrode 64 in a plan view. The gate electrode 64 is connected to a scanning line (gate line) SCL and is provided so as to protrude from one side of the scanning line (gate line) SCL. The semiconductor 61 extends to a position where it overlaps with a source electrode 62 and is electrically connected to the source electrode 62 through a contact hole H13. The source electrode 62 is connected to a signal line DTL and protrudes from one side of the signal line DTL.

[0038] The semiconductor 61 may be made of known materials such as polysilicon or oxide semiconductor. For example, the use of TAOS (Transparent Amorphous Oxide Semiconductor) provides a good ability to hold the voltage for image display for a long time (holding rate), improving the display quality. In addition, oxide semiconductors containing TAOS have a small leakage current when the pixel transistor Tr is off.

[0039] The gate electrode 64 (scanning line (gate line) SCL) is made of, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy thereof. The drain electrode 63 and the source electrode 62 (signal line DTL) are made of, for example, titanium aluminum (TiAl), which is an alloy of titanium and aluminum.

[0040] Known insulating materials can be used as the material of the insulating layers 24, 58a, 58c, 58d, 58e, and 58f. For example, TEOS (Tetra Ethyl Ortho Silicate) can be used as the material of the insulating layer 58b. For example, silicon oxide film (SiO2) can be used as the material of the insulating layer 58c. An organic insulating film such as acrylic is used as the material of the insulating layer 58d. This allows the surface on which the common electrode COML is provided to be flattened.

[0041] The auxiliary wiring layer 54 is made of a material similar to that of the gate electrode 64 (scanning line (gate line) SCL), such as aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy thereof.

[0042] Fig. 6 is a diagram showing an example of a drive circuit configuration. Fig. 6 shows an example of a circuit configuration corresponding to pixels Pix(n,m) and Pix(n+1,m). Pixel Pix(n,m) indicates the n-th pixel Pix from the left in the figure of pixels Pix arranged in the Dx direction (first direction) and the m-th pixel Pix from the top in the figure of pixels Pix arranged in the Dy direction (second direction) in the pixel array shown in Fig. 2. Also, pixel Pix(n+1,m) indicates the n+1-th pixel Pix from the left in the figure of pixels Pix arranged in the Dx direction (first direction) and the m-th pixel Pix from the top in the figure of pixels Pix arranged in the Dy direction (second direction) in the pixel array shown in Fig. 2.

[0043] Each circuit element constituting the drive circuit 40 operates by receiving a first power supply voltage signal PSIG1 and a second power supply voltage signal PSIG2 from the power supply device 12. The potential of the first power supply voltage signal PSIG1 (first potential VGH) is set to the high potential of the scanning signal (gate signal) GATE(m) supplied to the gate of the pixel transistor Tr. Also, the potential of the second power supply voltage signal PSIG2 (second potential VGL) is set to the low potential of the scanning signal GATE(m) supplied to the gate of the pixel transistor Tr.

[0044] The display control circuit 44 (driver IC4) controls the gate driver 42 and the signal line selection circuit 43. Specifically, the display control circuit 44 (driver IC4) supplies synchronization signals such as a start pulse signal STV and a shift clock signal CKV, and a scanning line drive signal ENB to the gate driver 42. The display control circuit 44 (driver IC4) also supplies a selection control signal MUX to the signal line selection circuit 43. The potential of the first power supply voltage signal PSIG1 (first potential VGH) is set to, for example, the high potential of the selection control signal MUX. The potential of the second power supply voltage signal PSIG2 (second potential VGL) is set to, for example, the low potential of the selection control signal MUX. The present disclosure is not limited by the potential of the selection control signal MUX.

[0045] The gate driver 42 is a circuit that generates a scanning signal GATE(m) to be supplied to the gate of the pixel transistor Tr based on a start pulse signal STV, a shift clock signal CKV, and a scanning line driving signal ENB output from a display control circuit 44 (driver IC4).

[0046] Specifically, during a selection period of the scanning line SCL to which the m-th pixel row is connected, the scanning signal GATE(m) is set to a high potential (first potential VGH), thereby turning on the pixel transistors Tr of the pixels Pix(n,m) and Pix(n+1,m).

[0047] In addition, during a non-selection period of the scanning line SCL to which the m-th pixel row is connected, the scanning signal GATE(m) is set to a low potential (second potential VGL), thereby turning off the pixel transistors Tr of the pixels Pix(n,m) and Pix(n+1,m).

[0048] The signal line selection circuit 43 includes a switch circuit ASW that time-divides a selection period of the scanning line SCL to which the m-th pixel row is connected, and supplies a pixel signal SIG(n) to the pixel Pix(n,m) and a pixel signal SIG(n+1) to the pixel Pix(n+1,m). In the example shown in Fig. 6, the switch circuit ASW includes switch transistors Trn1 and Trn2 formed of n-type TFTs, and switch transistors Trp1 and Trp2 formed of p-type TFTs.

[0049] The signal line selection circuit 43 has a plurality of switch circuits ASW arranged side by side in the Dx direction (first direction) on the array substrate 2. Fig. 6 illustrates an example in which the selection period of the scanning line SCL to which the m-th pixel row is connected is divided into two, and the corresponding pixel signals SIG(n) and SIG(n+1) are selectively output during each selection period of the pixel Pix(n,m) and the pixel Pix(n+1,m). In this configuration, the total number of switch circuits ASW arranged side by side in the Dx direction (first direction) is N / 2.

[0050] Specifically, during a selection period of the signal line DTL to which the pixel Pix(n,m) is connected, the selection control signal MUX1 is set to a high potential (first potential VGH) and the selection control signal xMUX1 is set to a low potential (second potential VGL), whereby the switch transistors Trn1 and Trp1 are controlled to be on, and the image signal Vsig output from the display control circuit 44 (driver IC4) is selectively output as the pixel signal SIG(n).

[0051] During a selection period of the signal line DTL to which the pixel Pix(n+1,m) is connected, the selection control signal MUX2 is set to a high potential (first potential VGH) and the selection control signal xMUX2 is set to a low potential (second potential VGL), thereby turning on the switch transistors Trn2 and Trp2, and the image signal Vsig output from the display control circuit 44 (driver IC4) is selectively output as the pixel signal SIG(n+1).

[0052] 6 shows a switch circuit ASW having a CMOS configuration, but is not limited thereto. The switch circuit ASW may be configured, for example, only with n-type TFTs, or only with p-type TFTs.

[0053] 6 illustrates an example in which the selection period of the scanning line SCL to which the m-th pixel row is connected is divided into two, and the pixel signals SIG(n) and SIG(n+1) corresponding to the pixels Pix(n,m) and Pix(n+1,m) are selectively output during each selection period, but the present invention is not limited to this. For example, any embodiment may be used as long as the selection period of the scanning line SCL to which the m-th pixel row is connected is divided into three or more periods, and the pixel signals SIG corresponding to the pixels Pix are selectively output during each selection period. When the number of divisions of the selection period of the scanning line SCL to which the m-th pixel row is connected, in other words, the number of pixels sequentially selected by the switch circuit ASW during the selection period of the scanning line SCL to which the m-th pixel row is connected, is T, the total number of switch circuits ASW arranged side by side in the Dx direction (first direction) is N / T.

[0054] Fig. 7 is a diagram showing an example of a gate driver configuration according to a conventional example. Fig. 8 is a timing chart of each part in the conventional example. In the present disclosure, the interval between the dashed dotted lines in the timing charts of each part shown in Figs. 8, 11, 15, and 17 is defined as one horizontal period (1H).

[0055] In the conventional configuration shown in FIG. 7, the gate driver 42 includes a shift register circuit 421 and a plurality of output circuits 422_p (p is an integer equal to or greater than 1).

[0056] The shift register circuit 421 is configured by alternately cascading in descending (or ascending) order a register circuit SRA that outputs a binary signal in which the high potential of the input signal at the rising edge of the shift clock signal CKV is maintained until the falling edge of the shift clock signal CKV, and a register circuit SRB that outputs a binary signal in which the high potential of the input signal at the falling edge of the shift clock signal CKV is maintained until the rising edge of the shift clock signal CKV.

[0057] The output circuits 422_p are provided corresponding to the register circuits SRA and SRB, respectively. Each of the output circuits 422_p includes Q (four in this case) two-input, one-output AND circuits that generate the logical value of the scanning signal GATE(m) to be supplied to Q (four in this case) scanning lines SCL arranged in the Dy direction (second direction). The output circuit 422_p may be configured to include a driving circuit in the subsequent stage of each AND circuit.

[0058] A start pulse signal STV and a shift clock signal CKV that is at a high potential for Q horizontal periods (here, four horizontal periods) and at a low potential for the following Q horizontal periods (here, four horizontal periods) are input to the shift register circuit 421. The shift clock signal CKV is input to each of the register circuits SRA and SRB constituting the shift register circuit 421. The start pulse signal STV is input to the first-stage register circuit SRA arranged in descending order (or ascending order) in the shift register circuit 421. Thereafter, an output signal TRN(odd) of the register circuit SRA in the previous stage (or an output signal TRN(even) of the register circuit SRB) is input to the register circuit SRB in the subsequent stage (or the register circuit SRA).

[0059] The AND circuit generates the logical product value of the output signal TRN(odd) of the register circuit SRA (or the output signal TRN(even) of the register circuit SRB) and the enable signal ENBq (q is an integer from 1 to Q (here, 4)) as the logical value of the scanning signal GATE(m). The enable signals ENBq that become high potential during one horizontal period are input to each AND circuit in descending order (or ascending order) with a shift of one horizontal period.

[0060] With the gate driver configuration according to the conventional example described above, the scanning signal GATE(m) that becomes a high potential during one horizontal period is supplied to the scanning lines SCL arranged in the Dy direction (second direction) in descending (or ascending) order, shifted by one horizontal period.

[0061] Fig. 9A is a diagram showing a first waveform example in a conventional example, Fig. 9B is a diagram showing a second waveform example in a conventional example, Fig. 9C is a diagram showing a third waveform example in a conventional example, and Fig. 10 is a diagram showing an example of a display defect in a conventional example.

[0062] 9A, 9B, and 9C show an example in which the selection control signals MUX1, xMUX1, MUX2, and xMUX2 are controlled by the display control circuit 44 (driver IC4) to sequentially supply a pixel signal SIG(n) for pixel Pix(n,m) and a pixel signal SIG(n+1) for pixel Pix(n+1,m) during one horizontal period (1H) during which the scanning signal GATE(m) is output. 9A, 9B, and 9C show an example in which the potential of the pixel signal SIG(n) is the same as the potential of the pixel signal SIG(n+1).

[0063] 9A, 9B, and 9C show an example in which in a region where the selection control signal MUX1 is equal to or higher than the potential indicated by the dashed line, the switch transistor Trn1 is turned on to supply the pixel signal SIG(n), and in a region where the selection control signal MUX2 is equal to or higher than the potential indicated by the dashed line, the switch transistor Trn2 is turned on to supply the pixel signal SIG(n+1). The potential at which the switch transistors Trn1 and Trn2 are turned on varies according to the potentials of the pixel signals SIG(n) and SIG(n+1).

[0064] In a period t1 during which the ON period of the switch transistor Trn1 (the supply period of the pixel signal SIG(n)) and the ON period of the pixel transistor Tr overlap, the pixel electrode PX of the pixel Pix(n,m) is charged according to the potential of the pixel signal SIG(n). In addition, in a period t2 during which the ON period of the switch transistor Trn2 (the supply period of the pixel signal SIG(n+1)) and the ON period of the pixel transistor Tr overlap, the pixel electrode PX of the pixel Pix(n+1,m) is charged according to the potential of the pixel signal SIG(n+1).

[0065] The on-timing of the pixel transistor Tr is delayed due to the time constant of the scanning line SCL. Specifically, the pixel transistor Tr is turned on when the potential of the scanning signal GATE(m) exceeds the threshold voltage VTH of the pixel transistor Tr. For this reason, there is a possibility that the pixel transistor Tr is turned on with a delay from the timing at which the switch transistor Trn1 is turned on. As a result, as shown in FIG. 9A, the charging period t1 of the pixel electrode PX of the pixel Pix(n,m) is shorter than the charging period t2 of the pixel electrode PX of the pixel Pix(n+1,m).

[0066] In the example shown in Figure 9B, the length of one horizontal period (1H) is set to the same length as in Figure 9A in a display panel with higher resolution than that in Figure 9A. In this case, the time constant of the scanning line SCL becomes larger than that in Figure 9A, the on-timing of the pixel transistor Tr is further delayed, and the charging period t1 of the pixel electrode PX of the pixel Pix(n,m) becomes shorter than the charging period t2 of the pixel electrode PX of the pixel Pix(n+1,m).

[0067] The example shown in Figure 9C shows an example in which the length of one horizontal period (1H) is shorter than that of Figure 9A in the same display panel as in Figure 9A. In this case, the on-timing of the pixel transistor Tr is delayed relatively to one horizontal period, and the charging period t1 of the pixel electrode PX of the pixel Pix(n,m) is shorter than the charging period t2 of the pixel electrode PX of the pixel Pix(n+1,m).

[0068] 9B and 9C, as the resolution of display panels increases and display speeds increase, the charging period t1 of the pixel electrode PX of pixel Pix(n,m) becomes shorter than the charging period t2 of the pixel electrode PX of pixel Pix(n+1,m), which may result in a decrease in the charging potential of the pixel electrode PX of pixel Pix(n,m) relative to the charging potential of the pixel electrode PX of pixel Pix(n+1,m). In this case, the pixel row including pixel Pix(n+1,m) will be displayed darker than the pixel row including pixel Pix(n+1,m) as shown in FIG.

[0069] Fig. 11 is a diagram showing an example of a gate driver configuration according to the embodiment. Fig. 12 is a timing chart of each part in the configuration shown in Fig. 11. Note that, here, components different from the configuration according to the conventional example shown in Fig. 7 will be described in detail, and descriptions of components similar to the configuration according to the conventional example shown in Fig. 7 may be omitted.

[0070] In the configuration according to the embodiment shown in FIG. 11, the shift register circuit 421 is configured by cascading a plurality of register circuits SRA in descending (or ascending) order, each of which outputs a binary signal that maintains the high potential of an input signal at the rising edge of the shift clock signal CKV until the falling edge of the shift clock signal CKV.

[0071] Shift clock signals CKV1, CKV2, and CKV3, each of which is at a high potential for Q+1 horizontal periods, are input to the register circuit SRA in descending (or ascending) order, shifted by Q horizontal periods. The start pulse signal STV is input to the first-stage register circuit SRA arranged in descending (or ascending) order in the shift register circuit 421. Thereafter, the output signal TRN(r) of the previous-stage register circuit SRA is input to the subsequent-stage register circuit SRA.

[0072] The AND circuit generates the logical product value of the output signal TRN(r) of the register circuit SRA and the enable signal ENBs (s is an integer from 1 to S (=Q+1, here 5)) as the logical value of the scanning signal GATE(m). The enable signals ENBs that are at a high potential for two horizontal periods are input to each AND circuit in descending (or ascending) order, shifted by one horizontal period.

[0073] With the gate driver configuration according to the embodiment described above, a scanning signal GATE(m) that is at a high potential for two horizontal periods is supplied to the scanning lines SCL arranged in the Dy direction (second direction) in descending (or ascending) order, with a shift of one horizontal period between each.

[0074] Fig. 13A is a diagram showing a first waveform example in the embodiment, Fig. 13B is a diagram showing a second waveform example in the embodiment, and Fig. 13C is a diagram showing a third waveform example in the embodiment.

[0075] 13A, 13B, and 13C show an example in which the selection control signals MUX1, xMUX1, MUX2, and xMUX2 are controlled by the display control circuit 44 (driver IC4) in the latter half of the horizontal period (1H) in which the scanning signal GATE(m) is output, so that the pixel signal SIG(n) for the pixel Pix(n,m) and the pixel signal SIG(n+1) for the pixel Pix(n+1,m) are sequentially supplied. Similarly to FIGS. 9A, 9B, and 9C, FIGS. 13A, 13B, and 13C also show an example in which the potential of the pixel signal SIG(n) is the same as the potential of the pixel signal SIG(n+1).

[0076] 13A, 13B, and 13C show an example in which in a region where the selection control signal MUX1 is equal to or higher than the potential indicated by the dashed line, the switch transistor Trn1 is turned on to supply the pixel signal SIG(n), and in a region where the selection control signal MUX2 is equal to or higher than the potential indicated by the dashed line, the switch transistor Trn2 is turned on to supply the pixel signal SIG(n+1). In Figures 13A, 13B, and 13C, as in Figures 9A, 9B, and 9C, the potentials at which the switch transistors Trn1 and Trn2 are turned on vary according to the potentials of the pixel signals SIG(n) and SIG(n+1).

[0077] As described above, the on-timing of the pixel transistor Tr is delayed due to the time constant of the scanning line SCL. Specifically, the pixel transistor Tr is turned on when the potential of the scanning signal GATE(m) exceeds the threshold voltage VTH of the pixel transistor Tr.

[0078] In the example shown in FIG. 13B, similarly to FIG. 9B in the conventional example, an example is shown in which the length of one horizontal period (1H) is set to the same length as in FIG. 13A in a display panel with higher resolution than that in FIG. 13A.

[0079] In the example shown in FIG. 13C, similarly to the conventional example shown in FIG. 9C, an example is shown in which the length of one horizontal period (1H) is made shorter than that in FIG. 13A in the same display panel as in FIG. 13A.

[0080] In the configuration according to the embodiment, the scanning signal GATE(m) is set to a high potential over two horizontal periods (2H), and after the potential of the scanning signal GATE(m) exceeds the threshold voltage VTH of the pixel transistor Tr to turn on the pixel transistor Tr, the switch transistor Trn1 can be turned on. This makes it possible to make the charging period t1 of the pixel electrode PX of the pixel Pix(n,m) approximately equivalent to the charging period t2 of the pixel electrode PX of the pixel Pix(n+1,m), as shown in FIG.

[0081] In addition, in the example shown in Fig. 13B in which the length of one horizontal period (1H) is the same as that of Fig. 13A in a display panel with higher resolution than that of Fig. 13A, the switch transistor Trn1 can be turned on after the pixel transistor Tr is turned on. This makes it possible to make the charging period t1 of the pixel electrode PX of the pixel Pix(n,m) approximately equivalent to the charging period t2 of the pixel electrode PX of the pixel Pix(n+1,m), as in Fig. 13A.

[0082] 13C, in which the length of one horizontal period (1H) is shorter than that of FIG. 13A in the same display panel as FIG. 13A, the switch transistor Trn1 can be turned on after the pixel transistor Tr is turned on. This makes it possible to make the charging period t1 of the pixel electrode PX of the pixel Pix(n,m) approximately equivalent to the charging period t2 of the pixel electrode PX of the pixel Pix(n+1,m), as in FIG. 13A.

[0083] In this manner, in the configuration according to the embodiment, a pixel signal SIG(n) for pixel Pix(n,m) and a pixel signal SIG(n+1) for pixel Pix(n+1,m) are sequentially supplied in the latter half of two horizontal periods (2H) for outputting a scanning signal GATE(m) without adding any circuit to the configuration according to the conventional example shown in Fig. 7 and Fig. 8, thereby making it possible to avoid a delay in the on-timing of the pixel transistor Tr caused by the time constant of the scanning line SCL. This makes it possible to suppress a reduction in the charging period t1 of the pixel electrode PX of pixel Pix(n,m) and a decrease in the charging potential of the pixel electrode PX of pixel Pix(n,m) that accompanies higher resolution and faster display of display panels.

[0084] (First Modification) Fig. 14 is a diagram showing an example of a gate driver configuration according to a first modified example of an embodiment. Fig. 15 is a timing chart of each part in the configuration shown in Fig. 14. Note that, here, components different from the configuration according to the embodiment shown in Fig. 11 will be described in detail, and descriptions of components similar to those in the configuration according to the embodiment shown in Fig. 11 may be omitted.

[0085] In the configuration of the first modified example of the embodiment shown in FIG. 14, the shift register circuit 421 is configured by cascading a plurality of register circuits SRB in descending (or ascending) order to output a binary signal in which the high potential of the input signal at the falling edge of the shift clock signal CKV is maintained until the rising edge of the shift clock signal CKV.

[0086] Shift clock signals CKV1, CKV2, and CKV3, each of which is at a low potential for Q+1 horizontal periods, are input to the register circuit SRB in descending (or ascending) order, shifted by Q horizontal periods. The start pulse signal STV is input to the first-stage register circuit SRB arranged in descending (or ascending) order in the shift register circuit 421. Thereafter, the output signal TRN(r) of the previous-stage register circuit SRB is input to the subsequent-stage register circuit SRB.

[0087] The configuration according to the first modified example of the embodiment differs from the configuration according to the embodiment shown in Figures 11 and 12 only in that the logical values ​​of the shift clock signals CKV1, CKV2, and CKV3 are inverted, and like the configuration according to the embodiment, it is possible to avoid a delay in the on-timing of the pixel transistor Tr caused by the time constant of the scanning line SCL without adding any circuit to the configuration according to the conventional example shown in Figures 7 and 8. This makes it possible to suppress a reduction in the charging period t1 of the pixel electrode PX of the pixel Pix(n,m) and a decrease in the charging potential of the pixel electrode PX of the pixel Pix(n,m) that accompanies higher resolution and faster display of the display panel.

[0088] (Second Modification) Fig. 16 is a diagram showing an example of a gate driver configuration according to a second modified example of the embodiment. Fig. 17 is a timing chart of each part in the configuration shown in Fig. 16. Note that, here, components different from the configuration according to the embodiment shown in Fig. 11 will be described in detail, and descriptions of components similar to those in the configuration according to the embodiment shown in Fig. 11 may be omitted.

[0089] In the configuration of the second variant of the embodiment shown in FIG. 16, the output circuit 422_p includes two 2-input 1-output AND circuits that generate the logical values ​​of the scanning signal GATE(m) to be supplied to two scanning lines SCL arranged in the Dy direction (second direction).

[0090] The AND circuit generates the logical product value of the output signal TRN(r) of the register circuit SRA and the enable signal ENBs (s is an integer from 1 to 3) as the logical value of the scanning signal GATE(m). The enable signals ENBs that are at a high potential for two horizontal periods are input to each AND circuit in descending (or ascending) order, shifted by one horizontal period.

[0091] In the configuration according to the second modification of the embodiment, the number of AND circuits included in the output circuit 422_p is different from that in the configuration according to the embodiment shown in Figures 11 and 12. As with the configuration according to the embodiment, the configuration according to the second modification of the embodiment can also avoid a delay in the on-timing of the pixel transistor Tr caused by the time constant of the scanning line SCL without adding any circuits to the configuration according to the conventional example. This makes it possible to suppress a reduction in the charging period t1 of the pixel electrode PX of the pixel Pix(n,m) and a decrease in the charging potential of the pixel electrode PX of the pixel Pix(n,m) that accompanies higher resolution and faster display of the display panel.

[0092] In addition, in the configuration of the second modified example, similar to the first modified example, the logical values ​​of the shift clock signals CKV1, CKV2, and CKV3 may be inverted compared to the configuration of the second modified example of the embodiment shown in Figures 16 and 17.

[0093] The display device 1 is not limited to a liquid crystal display device, and may be, for example, an organic EL display using organic light emitting diodes (OLEDs) as display elements. The display device 1 may be an inorganic EL display using inorganic light emitting diodes (micro LEDs) as display elements. The display device 1 may be an electrophoretic display (EPD), or may be a transparent display that displays an image on a transparent display surface.

[0094] Although the preferred embodiment of the present disclosure has been described above, the present disclosure is not limited to such an embodiment. The contents disclosed in the embodiment are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure also naturally belong to the technical scope of the present disclosure. [Explanation of symbols]

[0095] 1 Display device 4 Driver IC 11 Display Panel 12 Power supply 13 Control device 40 Drive circuit 42 Gate Driver 43 Signal line selection circuit 44 Display control circuit 51 Gate Line Layer 53 Signal Line Layer 421 Shift Register Circuit 422_p Output circuit AA display area ASW Switch circuit CKV, CKV1, CKV2, CKV3 Shift clock signal COML Common electrode CS retention capacity DTL signal line ENB, ENBq, ENBs Enable signals GATE Scan signal (gate signal) MUX, MUX1, MUX2, xMUX1, xMUX2 selection control signal Pix, Pix(n,m), Pix(n+1,m) pixels PSIG1 First power supply voltage signal PSIG2 Second power supply voltage signal PX pixel electrode SCL Scan line (gate line) SIG Pixel signal SRA,SRB register circuit STV Start pulse signal TRN(odd),TRN(even),TRN(r) Output signal Tr Pixel transistor Trn1, Trn2, Trp1, Trp2 switch transistors VCOM common potential VGH First potential VGL 2nd potential Vsig Image signal

Claims

1. a substrate having a display area in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction; A plurality of scanning lines connected to pixels aligned in the first direction; A plurality of signal lines connected to pixels arranged in the second direction; A gate driver that supplies a scanning signal to the scanning line; a signal line selection circuit for supplying pixel signals to the signal lines; Equipped with The gate driver includes: a shift register circuit in which a plurality of register circuits are cascaded in the second direction in descending or ascending order to output a binary signal in which a high potential of an input signal at a rising edge of a shift clock signal is maintained until a falling edge of the shift clock signal; a plurality of output circuits provided corresponding to the plurality of register circuits, respectively; Equipped with The output circuit includes: Q AND circuits for generating a logical product of an output signal of the register circuit and an enable signal as a logical value of the scanning signal, The register circuit includes: Shift clock signals that are at a high potential for Q+1 horizontal periods are input in descending or ascending order with a shift of Q horizontal periods, The AND circuit is The enable signals that are at a high potential for two horizontal periods are input in descending or ascending order, shifted by one horizontal period each. Display device.

2. a substrate having a display area in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction; A plurality of scanning lines connected to pixels aligned in the first direction; A plurality of signal lines connected to pixels arranged in the second direction; A gate driver that supplies a scanning signal to the scanning line; a signal line selection circuit for supplying pixel signals to the signal lines; Equipped with The gate driver includes: a shift register circuit in which a plurality of register circuits are cascaded in the second direction in descending or ascending order to output a binary signal in which a high potential of an input signal at a falling edge of a shift clock signal is maintained until a rising edge of the shift clock signal; a plurality of output circuits provided corresponding to the plurality of register circuits, respectively; Equipped with The output circuit includes: Q AND circuits for generating a logical product of an output signal of the register circuit and an enable signal as a logical value of the scanning signal, The register circuit includes: Shift clock signals that are at a low potential for Q+1 horizontal periods are input in descending or ascending order with a shift of Q horizontal periods, The AND circuit is The enable signals that are at a high potential for two horizontal periods are input in descending or ascending order, shifted by one horizontal period each. Display device.

3. A scanning signal that is at a high potential for two horizontal periods is supplied to the scanning lines arranged in the second direction in a descending or ascending order, the scanning signals being shifted by one horizontal period, The signal line selection circuit includes: a second half horizontal period during which the scanning signal is at a high potential is divided into a time division period, and pixel signals are sequentially supplied to a plurality of pixels connected to the selected scanning line; The display device according to claim 1 .

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