Photoelectric conversion device, photoelectric conversion system, mobile entity, and apparatus

Abstract

To solve the problem that the examination regarding control for changing an exposure period in a pixel that includes an avalanche photodiode is insufficient.SOLUTION: Provided is a photoelectric conversion device comprising: a pixel unit in which are arranged over a plurality of rows a plurality of pixels, each of which includes a quench circuit to which a signal for regulating the start and end of an exposure period is inputted, and an avalanche photodiode which is connected to the quench circuit; a selection unit, to which a plurality of clock signals differing in cycle are inputted in parallel, and which selects a clock signal to be outputted, from among the plurality of clock signals; and a generation unit that generates said signal using the clock signal outputted from the selection unit.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a photoelectric conversion device, a photoelectric conversion system, a mobile object, and an instrument. [Background technology]

[0002] There is known a photoelectric conversion device including a pixel array in which a plurality of pixels, each of which includes an avalanche photodiode (APD), are arranged. In the PN junction region of the APD, avalanche multiplication occurs due to charges generated by incident light.

[0003] Patent Document 1 discloses a device including an APD, a quench circuit connected to the APD, a quench circuit having a gate to which a pulse signal is input, and a pulse generating circuit that generates the pulse signal. The pulse generating circuit controls the on / off of the quench circuit. The exposure period of the APD is controlled by this pulse signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-123847 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the technique described in Patent Document 1, no consideration is given to control of the exposure period.

[0006] For example, no consideration has been given to a suitable configuration of a photoelectric conversion device when the length of the exposure period is changed. [Means for solving the problem]

[0007] One aspect of the present disclosure is a photoelectric conversion device comprising: a pixel section in which a plurality of pixels are arranged across a plurality of rows, each pixel having a quench element having a gate to which a pulse signal that specifies the start and end of an exposure period is input, and an avalanche photodiode connected to the quench element; a scanning section that scans the pixel section by performing a readout process to read out signals from the pixels, a start process for the exposure period, and an end process for the exposure period in row sequence for the plurality of rows, with one or more rows as a unit; and a control section that outputs a synchronization signal to the scanning section to control timing of the readout process, wherein the timing of at least one of the start process and the end process is controlled by a control signal that is different from the synchronization signal. Effect of the Invention

[0008] According to the present disclosure, it is possible to provide a photoelectric conversion device capable of suitably changing the length of an exposure period. [Brief description of the drawings]

[0009] [Figure 1] Photoelectric conversion device configuration diagram [Diagram 2] Pixel configuration diagram [Diagram 3] Control unit configuration diagram [Figure 4] Vertical scanning control unit configuration diagram [Diagram 5] Vertical scanning section configuration diagram [Figure 6] Pixel drive timing diagram [Figure 7] Pixel configuration diagram [Figure 8] Pixel configuration diagram [Figure 9] Vertical scanning control unit configuration diagram [Figure 10] Vertical scanning section configuration diagram [Figure 11] Pixel drive timing diagram [Figure 12] A diagram showing the configuration of a photoelectric conversion system. [Figure 13] A diagram showing the configuration and operation of a moving object [Figure 14] Equipment configuration diagram DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Each embodiment will be described below with reference to the drawings.

[0011] In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to an image pickup device, and can be applied to other examples of photoelectric conversion devices. For example, a distance measuring device (a device for measuring distance using focus detection or TOF (Time Of Flight)) or a photometric device (a device for measuring the amount of incident light) can be used.

[0012] The conductivity types of the transistors described in the following embodiments are merely examples and are not limited to those described in the examples. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistors are changed as appropriate.

[0013] For example, in the case of a transistor operated as a switch, the low level and high level of the potential supplied to the gate may be reversed with respect to the description in the embodiment in accordance with the change in the conductivity type. The conductivity type of the semiconductor region described in the following embodiment is also an example, and is not limited to the conductivity type described in the embodiment. The conductivity type may be changed as appropriate from the conductivity type described in the embodiment, and the potential of the semiconductor region may be changed as appropriate with this change. For example, in the following embodiment, an example will be described in which the quench element 12 connected to the avalanche diode is a PMOS transistor, but it may be changed to an NMOS transistor. In this case, the high level and low level of the signal supplied to the gate may be changed.

[0014] First Embodiment [Overall Description of Photoelectric Conversion Device 100] Fig. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to the present embodiment. As shown in Fig. 1, the photoelectric conversion device 100 according to the present embodiment includes a pixel section 10, a control section 20, a vertical scanning section 30 (scanning section), a signal processing section 40, a horizontal scanning section 50 (second scanning section), and an output section 60.

[0015] The pixel section 10 is provided with a plurality of pixels P arranged across a plurality of rows and a plurality of columns. In Fig. 1, the pixels P arranged in N rows from the 1st row to the Nth row and M columns from the 1st column to the Mth column are shown with reference characters indicating the row number and the column number. For example, the pixel P arranged in the 1st row and the 1st column is given the reference character P(1,1).

[0016] It is not necessary for the pixels P to be arranged in a plurality of columns in the pixel section 10. For example, the pixels P may be arranged in one column and a plurality of rows.

[0017] A control line group 150 is arranged in each row of the pixel array of the pixel unit 10, extending in a first direction (horizontal direction in FIG. 1). The control line group 150 is connected to each of the pixels P arranged in the first direction, and is commonly connected to the pixels P in a plurality of columns arranged in one row. The control line group 150 includes a plurality of control lines for controlling the pixels P in one row. Each of the plurality of control lines transmits a signal pCLK, a signal pRES, and a signal pVSEL, which will be described later, from the vertical scanning unit 30 to the pixels P in the corresponding row. The vertical scanning unit 30 selects the pixels P in each row of the pixel unit 10 one row at a time, or in units of two or more rows, in row sequence. In this way, row scanning (vertical scanning) of the pixel unit 10 is performed by the vertical scanning unit 30. The "unit" here refers to one or two or more pixel rows in which the periods selected by the vertical scanning unit 30 overlap, collectively referred to as one group.

[0018] The first direction in which the control line group 150 extends may be referred to as the row direction or the horizontal direction. In Fig. 1, the control line group 150 is shown with a reference number indicating the row number. For example, the control line group in the first row is given the reference number 150[1].

[0019] The control line group 150 of each row is connected to the vertical scanning section 30. The vertical scanning section 30 supplies control signals for driving the pixels P to the pixels P via the control lines.

[0020] An output line 152 is arranged in each column of the pixel array of the pixel unit 10, extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. The output line 152 is connected to each of the pixels P arranged in the second direction, and serves as a signal line common to these pixels P.

[0021] The second direction in which the output lines 152 extend may be referred to as the column direction or vertical direction. 1, the output lines 152 are shown with reference characters indicating the column numbers. For example, the output line of the first column is referenced pOUT[1]. Each of the output lines 152 outputs a pixel signal, which is a digital signal, from a pixel P of a row selected by the vertical scanning unit 30. Typically, the pixel signal is a multi-bit digital signal. The output line 152 can be in the form of a bus including a plurality of signal lines for transmitting a corresponding 1-bit signal among the multi-bit digital signals. This allows the signals of each bit of the digital signal to be transmitted in parallel. In addition, a plurality of such buses may be provided for one column of pixels P. Some of the plurality of buses are connected to pixels P in some rows of the plurality of rows, and another portion of the buses are connected to pixels P in another portion of rows. This allows the digital signals of the pixels P in the plurality of rows to be read out in parallel. Note that the present disclosure is not limited to this form, and the output line 152 corresponding to one column of pixels P may be only one, and the multi-bit digital signal may be transmitted serially.

[0022] The output line 152 is connected to the signal processing unit 40. The signal processing units 40 are provided corresponding to the respective columns of the pixel unit 10, and are connected to the output line 152 of the corresponding column. The signal processing unit 40 includes a holding unit that holds the pixel signal output from the pixel P via the output line 152 of the corresponding column.

[0023] The horizontal scanning unit 50 is a circuit unit that supplies the signal processing unit 40 with a control signal for reading out a signal from the signal processing unit 40. The horizontal scanning unit 50 supplies a control signal to the signal processing unit 40 of each column via a control line 154. The signal processing unit 40 that receives the control signal from the horizontal scanning unit 50 outputs the signal held in the holding unit to the output unit 60. The horizontal scanning unit 50 selects the signal processing units 40 of multiple columns one column at a time or two or more columns at a time to perform column scanning (horizontal scanning). A horizontal synchronization signal HD is input to the horizontal scanning unit 50 from the control unit 20. When the level of the horizontal synchronization signal HD changes, the horizontal scanning unit 50 starts horizontal scanning (second scanning) of the signal processing units 40 of each column. Typically, the horizontal synchronization signal HD transitions from a low level to a high level, causing the horizontal scanning unit 50 to start horizontal scanning of the signal processing units 40 of each column. The horizontal synchronization signal HD is a signal that controls the cycle at which horizontal scanning is performed.

[0024] 1, the control lines 154 are indicated with a reference number indicating the column number. For example, the control line in the first column is indicated with the reference number 154[1].

[0025] The output unit 60 is a circuit unit for outputting the signal output from the signal processing unit 40 to the outside of the photoelectric conversion device 100. Note that the output unit 60 may output the signal to the outside of the photoelectric conversion device 100 after performing various processes such as noise reduction processing and correction processing.

[0026] The control unit 20 is a circuit unit for supplying control signals that control the operations of the vertical scanning unit 30, the signal processing unit 40, the horizontal scanning unit 50, and the output unit 60 and the timing thereof.

[0027] The CPU 70 is a circuit section for controlling the photoelectric conversion device via the control section 20 by executing a program.

[0028] At least some of the control signals that control the operations and timings of the control unit 20, vertical scanning unit 30, signal processing unit 40, horizontal scanning unit 50, output unit 60, and CPU 70 may be supplied from outside the photoelectric conversion device 100.

[0029] [Pixel P(m,n)] FIG. 2 is a diagram showing the configuration of a pixel P(m,n) of the photoelectric conversion device of this embodiment.

[0030] The pixel P(m,n) has an APD 11, a quench circuit unit 19, a waveform shaping unit 13, a counter 14, and a pixel output circuit 15. The quench circuit unit 19 is configured by a quench element 12 in the example of FIG.

[0031] The APD 11 generates charge pairs through photoelectric conversion in response to incident light (in response to incidence of photons). A voltage VL (first voltage) is supplied to the anode of the APD 11. A voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the APD 11. A reverse bias voltage is supplied to the anode and cathode such that the APD 11 performs avalanche multiplication. With such a voltage supplied, the charge (seed charge) generated by the incident light undergoes avalanche multiplication, generating an avalanche current.

[0032] When a reverse bias voltage is supplied, there are two modes: a Geiger mode in which the potential difference between the anode and cathode is greater than the breakdown voltage, and a linear mode in which the potential difference between the anode and cathode is close to or less than the breakdown voltage.

[0033] An APD operated in the Geiger mode is called a SPAD (single photon avalanche diode). For example, the voltage VL (first voltage) is −30 V, and the voltage VH (second voltage) is 3 V. The APD 11 may be operated in either the linear mode or the Geiger mode.

[0034] The quench element 12 is connected to a power supply line that supplies a voltage VH and the APD 11. The quench element 12 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication.

[0035] The quench element 12 may be configured with a transistor. For example, the quench element 12 may be configured with a MOS transistor, and FIG 2 shows the case where the quench element 12 is a PMOS transistor.

[0036] The quench element 12 receives a signal pCLK at its gate, which is a control node. When the signal pCLK is inactive, the quench element 12 is in a non-conductive state (off state). On the other hand, when the signal pCLK is active, the quench element 12 is in a conductive state (on state). When the quench element 12 is in a non-conductive state, it suppresses the voltage supplied to the APD 11 and suppresses avalanche multiplication (quench operation). When the quench element 12 is in a conductive state, it returns the voltage supplied to the APD 11 to the voltage VH by flowing a current equivalent to the voltage drop caused by the quench operation (recharge operation). Note that the off state of the quench element 12 does not need to completely non-conduct (cut off) the electrical path between the power supply line supplying the voltage VH and the APD 11, and it is sufficient that the resistance is controlled to be a value required for the quench operation. Therefore, the OFF state of the quench element 12 should be a state in which the resistance value of the electrical path between the power supply line and the APD 11 is larger than that in the ON state of the quench element 12.

[0037] A signal pCLK[n] is supplied to the gate of the quench element 12 via a control line (not shown in FIG. 1) to switch between a conductive state and a non-conductive state of the quench element 12. This signal pCLK is a pulse signal input to the gate of the quench element 12 as a control signal that specifies the start and end of the exposure period of the pixel P.

[0038] The waveform shaping unit 13 shapes the potential change of the cathode of the APD 11 obtained when a photon is detected, and outputs a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 13. Although an example in which one inverter is used as the waveform shaping unit 13 is shown in FIG. 2, a circuit in which a plurality of inverters are connected in series may be used. Also, other circuits having a waveform shaping effect may be used as the waveform shaping unit 13.

[0039] The counter 14 counts the number of pulse signals output from the waveform shaping unit 13 and holds the count value. In addition, a signal pRES[n] is supplied from the vertical scanning unit 30 via a control line (not shown in FIG. 1). When this signal pRES[n] is active, the count value held in the counter 14 is reset to an initial value. Typically, this initial value is a value in which all bits are 0, but it may also be reset to another initial value.

[0040] A signal pVSEL[n] is supplied to the pixel output circuit 15 from the vertical scanning unit 30 via a control line. This signal vSEL[n] switches between electrical connection and disconnection between the counter 14 and the signal line pOUT[m]. The pixel output circuit 15 includes, for example, a buffer circuit for outputting a signal.

[0041] A switch such as a transistor may be further provided between the APD 11 and the quench element 12 to switch between electrical connection and non-connection. Similarly, a switch such as a transistor for switching between supply and non-supply of the voltage VH supplied to the quench element 12 may be further provided in the configuration of FIG. 2. This switch may be provided for each pixel or for each row of pixels. Also, one switch may be shared by all the pixels. Similarly, a switch such as a transistor for switching between supply and non-supply of the voltage VL supplied to the APD 11 may be further provided in the configuration of FIG. 2. This switch may be provided for each pixel or for each row of pixels. Also, one switch may be shared by all the pixels.

[0042] In this embodiment, the configuration using the counter 14 has been described. However, instead of the counter 14, the photoelectric conversion device 100 may be configured to acquire the pulse detection timing using a time-to-digital converter (hereinafter, referred to as TDC) and a memory. In this case, the generation timing of the pulse signal output from the waveform shaping unit 13 is converted into a digital signal by the TDC. To measure the timing of the pulse signal, the signal pREF[n] is supplied to the TDC from the vertical scanning unit 30 in FIG. 1 via a control line (not shown in FIG. 1). The TDC acquires, as a digital signal, a signal obtained by converting the input timing of the signal output from each pixel via the waveform shaping unit 13 into a relative time based on the signal pREF[n].

[0043] [Control unit 20] 3 is a configuration diagram of the control unit 20. A control signal is input to the control unit 20 from a CPU 70 provided outside the control unit 20. The control unit 20 includes a synchronization signal generation unit 21, a vertical scanning control unit 22, a signal processing control unit 23, and a horizontal scanning control unit 24.

[0044] The synchronization signal generating unit 21 generates a vertical synchronization signal VD, a horizontal synchronization signal HD, and a clock MCLK (reference clock signal) under the control of the CPU 70. The vertical synchronization signal VD is a signal that controls the period of one frame. Typically, the start of vertical scanning by the vertical scanning unit 30 is controlled based on the vertical synchronization signal VD. The horizontal synchronization signal HD is a signal that switches the selection of pixel rows in vertical scanning and horizontal scanning. The horizontal synchronization signal HD is a signal that controls a readout process that reads out signals from pixels P in each row. In addition, the vertical synchronization signal VD is a signal that controls a readout process that reads out signals from the entire pixel unit.

[0045] The vertical scanning control unit 22 generates a signal for controlling the drive timing of the vertical scanning unit 30 and outputs the signal to the vertical scanning unit 30 .

[0046] The signal processing control unit 23 generates a signal for controlling the drive timing of the signal processing unit 40 and outputs the signal to the signal processing unit 40 .

[0047] The horizontal scanning control unit 24 generates a signal for controlling the drive timing of the horizontal scanning unit 50 and outputs the signal to the horizontal scanning unit 50 .

[0048] [Vertical scanning control unit 22] 4 is a configuration diagram of the vertical scanning control unit 22. The vertical scanning control unit 22 includes a pulse signal generating unit 221, a horizontal synchronization signal counting unit 222, a pulse counting unit 223, a read signal generating unit 224, a reset signal generating unit 225, and a start trigger generating unit 226. The vertical scanning control unit 22 further includes a selection generating unit 228.

[0049] The pulse signal generating unit 221 has a frequency dividing circuit (not shown) and divides the frequency of the clock MCLK to generate the signals P_CLK1 and P_CLK2. By using the clock MCLK as the original signal, it becomes possible to control the periods of the signals P_CLK1 and P_CLK2 in units of one cycle of the clock MCLK. Each of the signals P_CLK1 and P_CLK2 is input to the vertical scanning unit 30.

[0050] The horizontal synchronizing signal counting unit 222 receives the vertical synchronizing signal VD and the horizontal synchronizing signal HD, counts the number of horizontal synchronizing signals HD in one period of the vertical synchronizing signal VD, and outputs a count value cnt_HD.

[0051] The pulse count unit 223 receives the vertical synchronization signal VD and the signal P_CLK, counts the signal P_CLK for one period of the vertical synchronization signal VD, and outputs a count value cnt_P_CLK.

[0052] The read signal generating unit 224 receives the count value cnt_HD and generates a signal P_VSEL according to the count value cnt_HD.

[0053] The reset signal generating unit 225 receives the count value cnt_HD and generates a signal P_RES according to the count value cnt_HD.

[0054] The start trigger generation unit 226 receives the count value cnt_P_CLK and generates a signal P_EXP_STR according to the count value cnt_P_CLK. Here, the signal P_EXP_STR is a control signal that controls the exposure start timing of the pixel P.

[0055] The selection generation unit 228 receives the signal P_EXP_STR and generates signals P_SH1 and P_SH2 indicating the shutter number. Note that the number of input signals P_EXP_STR may be two or more, and the number of output signals P_SH may be three or more.

[0056] Furthermore, the pulse signal generating unit 221 outputs a signal P_CLK1 and a signal P_CLK2 each having a different frequency. Note that the signal P_CLK output by the pulse signal generating unit 221 may be three or more clock signals each having a different period.

[0057] [Vertical scanning unit 30] 5 is a configuration diagram of the vertical scanning unit 30. The vertical scanning unit 30 includes a first decoder unit 31, a second decoder unit 32, a third decoder unit 33, and N row driver units 35 arranged for each row of pixels in the pixel unit 10. Each row driver unit 35 is configured to drive one row of pixels in the pixel unit 10, but may be configured to drive multiple rows.

[0058] The first decoder section 31 decodes the signal P_VSEL generated by the vertical scanning control section 22 to generate read row selection signals vp_vsel(1) to (N), and outputs them to the row driving sections .

[0059] Similarly, the second decoder section 32 decodes the signal P_RES generated by the vertical scanning control section 22 to generate reset row selection signals vp_res(1) to (N) and outputs them to the row driving sections .

[0060] Similarly, the third decoder section 33 decodes the signal P_EXP_STR generated by the vertical scanning control section 22 to generate exposure start row selection signals vp_exp_str(1) to (N) and outputs them to the row driving sections .

[0061] The row driver 35 includes a readout control unit 351, an exposure start control unit 352, an exposure end control unit 353, and a pixel drive signal generation unit 354. The row driver 35 further includes a selection holding unit 356 and a pulse signal selection unit 357.

[0062] The selection holding unit 356 receives the signals P_SH1, P_SH2, and vp_exp_str(1) and generates a signal p_sh[1] indicating the shutter number of the target row.

[0063] The pulse signal selection unit 357 (selection unit) inputs the signals P_CLK1, P_CLK2, and p_sh[1], selects the signal P_CLK to be used in the target row from either the signal P_CLK1 or the signal P_CLK2, and outputs it as the signal p_clk[1]. In other words, the pulse signal selection unit 357 is a selection unit that selects the clock signal to be output from among multiple input clock signals with different cycles.

[0064] In the following description, the configuration of the row driver 35 for the first row will be mainly described, but it is assumed that the row driver 35 for the other rows also has a similar configuration.

[0065] The read row selection signal vp_vsel(1) output from the first decoder unit 31 and the reset row selection signal vp_res(1) output from the second decoder unit 32 are input to the read control unit 351. The read control unit 351 is controlled by a read control signal, and stores the levels of the read row selection signal vp_vsel(1) and the reset row selection signal vp_res(1). The output signal of the read control unit 351 is a signal for resetting the counter 14 of the pixel P in the corresponding row and connecting it to the signal line pOUT.

[0066] The exposure start row selection signal vp_exp_str(1) output from the third decoder unit 33 is input to the exposure start control unit 352. The exposure start control unit 352 stores the level of the exposure start row selection signal vp_exp_str(1). The output signal of the exposure start control unit 352 is a signal (start signal) for starting exposure of the pixels P in the corresponding row.

[0067] The pixel drive signal generation unit 354 receives the read row selection signal vp_vsel(1) and the reset row selection signal vp_res(1) stored in the read control unit 351. The pixel drive signal generation unit 354 also receives the exposure start row selection signal vp_exp_str(1) stored in the exposure start control unit 352 and the exposure end row selection signal vp_exp_stop(1) stored in the exposure end control unit 353. These signals are used to perform readout, reset processing, exposure start processing, and exposure end processing for the corresponding pixel rows. The timing of performing these processes is controlled by the signals input to the pixel drive signal generation unit 354. The pixel drive signal generation unit 354 outputs each pixel drive signal required for these processes to the corresponding pixel rows. The pixel drive signals output from the pixel drive signal generation unit 354 are the signal pCLK[1], the signal pVSEL[1], and the signal pRES[1]. Here, the pixel drive signal generation section 354 is configured to drive one row of the pixel section 10 by itself, but may be configured to drive two or more rows.

[0068] [Pixel drive signal operation] The operation of the photoelectric conversion device according to the first embodiment shown in FIG. 1 will be described.

[0069] 6 is a timing chart showing an example of the operations of the vertical scanning control section 22, the vertical scanning section 30, and the pixel section 10. The operations will be described below with reference to FIG.

[0070] <Input of vertical scanning control unit 22> First, a program is executed by the CPU 70 , and a signal for controlling the photoelectric conversion device 100 is supplied to the control unit 20 .

[0071] In response to this, a synchronization signal generating section 21 in the control section 20 generates a vertical synchronization signal VD, a horizontal synchronization signal HD, and a clock MCLK. These signals are supplied to a vertical scanning control section 22, a signal processing control section 23, and a horizontal scanning control section 24.

[0072] 《cnt_HD》 At time t100, when the vertical synchronization signal VD transitions to a high level, the counter value cnt_HD is initialized to the value 0 based on this.

[0073] At time t101, when the horizontal synchronization signal HD transitions to a high level, the counter value cnt_HD counts up based on this and transitions to a value of 1. The counter value cnt_HD counts up every time the horizontal synchronization signal HD transitions to a high level.

[0074] 《cnt_P_CLK》 At time t100, when the vertical synchronization signal VD transitions to a high level, the pulse count unit 223 starts counting the signal P_CLK.

[0075] At time t101, when the signal P_CLK transitions to a high level, the counter value cnt_P_CLK is initialized to the value zero.

[0076] At time t103, when the signal P_CLK transitions to a high level, the counter value cnt_P_CLK counts up based on this and transitions to a value of 1. The counter value cnt_P_CLK counts up every time the signal P_CLK transitions to a high level.

[0077] <Reset process> At time t101, the signal P_RES transitions to the value 0 based on cnt_HD=1. The value 0 is a preset value and may be configured to be controllable by a register, etc. Also, the timing at which the signal P_RES transitions to the value 0 does not necessarily have to be when the counter value cnt_HD is 1, and may be configured to be controllable by a register, etc.

[0078] At time t102, when the horizontal synchronization signal HD transitions to a high level, the signal P_RES transitions (counts up) to a value of 1 based on this. The width of the transition does not necessarily have to be +1, and the signal P_RES may transition to a specific value. The settings of these transitions may be configured to be controllable using setting information held in a register. After that, the signal P_RES counts up (+1) every time the horizontal synchronization signal HD transitions to a high level.

[0079] Furthermore, at time t101, when the value of the signal P_RES transitions to value 0, the signal pRES[1] transitions to high level, and the first row of the pixel unit 10 becomes the target row for the reset process. The signal pRES[1] controls the counter 14 of the pixel P, and resets the count value held in the counter 14 when at high level.

[0080] When the signal P_RES value transitions to the value 1 at time t104, the first row of the pixel unit 10 is no longer the target row for the reset process, and the signal pRES[1] transitions to a low level.

[0081] 《cnt_P_CLK》 At time t103, when the value of the signal P_EXP_STR transitions to the value 0, the pulse count unit 355 starts counting the signal P_CLK.

[0082] At time t104, when the signal P_CLK transitions to a high level, the counter value cnt_P_CLK is initialized to the value zero.

[0083] At time t105, when the signal P_CLK transitions to a high level, the counter value cnt_P_CLK counts up based on this and transitions to a value of 1. The counter value cnt_P_CLK counts up every time the signal P_CLK transitions to a high level.

[0084] <<Exposure start processing and exposure end processing>> At time t103, the value of the signal P_EXP_STR transitions to a value of 0. This causes the signal P_SH1 to transition to a high level, and the signal P_SH2 to transition to a low level. At time t112, when the value of the signal P_EXP_STR transitions to a value of 0, based on this, the signal P_SH1 transitions to a low level, and the signal P_SH2 transitions to a high level. After that, the signals P_SH1 and P_SH2 toggle every time the value of the signal P_EXP_STR transitions to a value of 0.

[0085] The timing at which the signals P_SH1 and P_SH2 toggle is not necessarily limited to when the signal P_EXP_STR has a value of 0. It may be configured to be controllable by a set value held in a register or the like.

[0086] Furthermore, at time t103, when the value of the signal P_EXP_STR transitions to the value 0, the first row of the pixel unit 10 becomes the target row for the exposure start process, and the supply of the signal pCLK[1] starts. The signal pCLK[1] is generated using the signal P_CLK.

[0087] At time t107, the signal p_exp_stop[1] transitions to a high level based on cnt_P_CLK[1] = 4. Note that the timing at which the signal p_exp_stop[1] transitions to a high level is not necessarily limited to when the counter value cnt_P_CLK[1] is 4. It may be configured to be controllable by another set value held in a register or the like.

[0088] When the signal p_exp_stop[1] transitions to a high level at time t107, the first row of the pixel unit 10 becomes the target row for the exposure end process, and the supply of the signal pCLK[1] is terminated.

[0089] The period from time t104 to time t107 is the exposure time for the first row of the pixel section 10. During the exposure time, the signal pCLK[1] controls the resistance value of the quench element 12 of the pixel P in the first row of the pixel section 10. This controls the voltage supplied to the APD 11. Since the quench element 12 is a PMOS transistor, it is in an off state when the signal pCLK is at a high level, and in an on state when the signal pCLK is at a low level.

[0090] Furthermore, at time t103, when the value of the signal P_EXP_STR transitions to a value of 0, the first row of the pixel section 10 becomes the target row for the exposure start process. As a result, the vertical scanning section 30 starts supplying the signal pCLK[1]. The signal pCLK[1] is generated using the signal P_CLK. The signal pCLK[1] controls the quench element 12 of the pixel P in the first row of the pixel section 10, and controls the voltage supplied to the APD 11. Since the quench element 12 is a PMOS transistor, it is in an off state when the signal pCLK is at a high level, and in an on state when the signal pCLK is at a low level.

[0091] At time t107, the signal p_exp_stop[1] transitions to a high level based on cnt_P_CLK[1] = 4. Note that the timing at which the signal p_exp_stop[1] transitions to a high level is not necessarily limited to when the counter value cnt_P_CLK[1] is 4. It may be configured so that it can be controlled by another set value held in a register or the like.

[0092] At time t107, when the signal p_exp_stop[1] transitions to high level, the exposure end process is performed on the first row of the pixel section 10. The vertical scanning section 30 stops supplying the signal pCLK[1].

[0093] The period from time t104 to time t107 is the exposure period for the first row of the pixel section 10. During the exposure period, the signal pCLK[1] controls the operation state (resistance value) of the quench element 12 of the pixel P in the first row of the pixel section 10. This controls the voltage supplied to the APD 11.

[0094] <<Pixel drive signal operation>> At time t103, the value of the signal P_EXP_STR transitions to the value 0. At this timing, the signal P_SH1 is at a high level, and the signal P_SH2 is at a low level. This causes the signal p_sh[1] to transition to a high level.

[0095] At time t112, the value of the signal P_EXP_STR transitions to the value 0. At this timing, the signal P_SH1 is at a low level, and the signal P_SH2 is at a high level. This causes the signal p_sh[1] to transition to a low level.

[0096] The pulse signal selection unit 357 selects the signal P_CLK1 during the period from time t100 to time t102 when the signal p_sh[1] indicates a high level, and therefore the signal P_CLK1 is output as the signal p_clk[1].

[0097] During the period in which the signal p_sh[1] indicates a low level, the pulse signal selection unit 357 selects the signal P_CLK2 and outputs it as the signal p_clk[1].

[0098] At time t103, the value of the signal P_EXP_STR transitions to 0. As a result, the first row of the pixel unit 10 becomes the target row for the exposure start process, and the vertical scanning unit 30 starts supplying the signal pCLK[1]. The signal pCLK[1] is generated using the signal p_clk[1].

[0099] At time t106, the value of the signal P_EXP_STR transitions to the value 1. At this timing, the signal P_SH1 is at a high level, and the signal P_SH2 is at a low level. This causes the signal p_sh[2] to transition to a high level.

[0100] At time t113, the value of the signal P_EXP_STR transitions to the value 1. At this timing, the signal P_SH1 is at a low level, and the signal P_SH2 is at a high level. At this time, the signal p_sh[2] transitions to a low level.

[0101] The pulse signal selection unit 357 selects the signal P_CLK1 during the period from time t106 when the signal p_sh[2] indicates a high level to time t113. As a result, the signal P_CLK1 is output as the signal p_clk[2].

[0102] In addition, the pulse signal selection unit 357 selects the signal P_CLK2 during the period in which the signal p_sh[2] indicates a low level, so that the signal P_CLK2 is output as the signal p_clk[2].

[0103] Furthermore, at time t106, when the value of the signal P_EXP_STR transitions to the value 1, the second row of the pixel unit 10 becomes the target row for the exposure start process, and the supply of the signal pCLK[2] starts. The signal pCLK[2] is generated using the signal p_clk[2].

[0104] <Reading process> At time t110, the signal P_VSEL transitions to value 0 based on cnt_HD=0. The value 0 is a preset setting value, but is not limited to this example. It may be configured to be controllable by another setting value held in a register or the like. Furthermore, the timing at which the signal P_VSEL transitions to value 0 does not necessarily have to be when the counter value cnt_HD is 0. For example, the timing at which the signal P_VSEL transitions may be adjusted based on setting information held in a register so that it is the timing at which the counter value cnt_HD is a predetermined value.

[0105] At time t111, when the horizontal synchronization signal HD transitions to a high level, the signal P_VSEL transitions to a value of 1 based on this. The width of the transition does not necessarily have to be +1, and the signal P_VSEL may transition to a specific value. These may be configured to be controllable by another set value held in a register or the like. After that, the signal P_VSEL is counted up (+1) every time the horizontal synchronization signal HD transitions to a high level.

[0106] Furthermore, at time t110, when the value of the signal P_VSEL transitions to value 0, the signal pVSEL[1] transitions to high level. This causes the first row of the pixel unit 10 to become the target row for the readout process. The signal pVSEL[1] controls the pixel output circuit 15 of the pixel P, and when it is at high level, the counter 14 and the signal line pOUT are connected to read out the count value.

[0107] When the value of the signal P_VSEL transitions to the value 1 at time t111, the first row of the pixel unit 10 is no longer the target row for the readout process, and the signal pVSEL[1] transitions to a low level.

[0108] <<Transition of target rows for each process>> When the value of the signal P_RES transitions to the value 1 at time t102, the second row of the pixel section 10 becomes the target row for the reset process.

[0109] When the value of the signal P_EXP_STR transitions to the value 1 at time t103, the second row of the pixel section 10 becomes the target row for the exposure start process.

[0110] At time t109, when the value of the signal P_EXP_STOP transitions to the value 1, the exposure end process is performed on the second row of the pixel section 10. As a result, the vertical scanning section 30 stops supplying the signal pCLK[2].

[0111] When the value of the signal P_VSEL transitions to value 1 at time t111, the second row of the pixel section 10 becomes the target row for the readout process.

[0112] The operation of the second row of the pixel section 10 is similar to the operation of the first row of the pixel section 10.

[0113] According to this embodiment, the vertical scanning timing control section 22 includes a pulse signal generating section 221 that generates a plurality of signals P_CLK1 and P_CLK2 having different cycles.

[0114] Consider, for example, a case where the period of the signal MCLK is changed instead of the configuration in which the signals P_CLK1 and P_CLK2 are generated as in this embodiment. In this case, the signal MCLK is a signal that is used commonly for all pixel rows. If the period of the signal MCLK is changed before the exposure periods of all pixel rows end, the exposure periods of the pixel rows before the exposure ends will change. As a result, the obtained images will have exposure periods of different lengths, and brightness steps will occur in the image. For this reason, the period of the signal MCLK is changed after the exposure periods of all pixel rows end.

[0115] On the other hand, in this embodiment, as described above, a plurality of signals P_CLK1 and P_CLK2 with different cycles are generated, which makes it possible to change the length of the exposure period for pixel rows from which signals have already been read out before the end of the exposure period for all pixel rows.

[0116] Furthermore, in this embodiment, the selection of the clock signal by the selection unit can be changed during a period in which readout scanning is performed to read out signals from pixels P in multiple rows. In other words, during a period in which signals are read out from pixels P in some rows, the selection unit corresponding to pixels P in another portion of rows can change the clock signal to be output from among multiple clock signals. This allows the length of the exposure period to be changed even during a readout scanning period.

[0117] In this manner, in this embodiment, the length of the exposure period can be suitably changed.

[0118] Furthermore, in this embodiment, the selection holding unit 356 is provided corresponding to each row of pixels P, but the present invention is not limited to this example. For example, one selection holding unit 356 may be shared by a plurality of row driving units 35 corresponding to two or more pixel rows. Even in this case, the length of the exposure period can be changed in units of pixel rows in which the selection holding unit 356 is provided.

[0119] In this embodiment, the signals P_CLK1 and 2 are generated inside the photoelectric conversion device, but the present invention is not limited to this example. For example, the signals P_CLK1 and 2 may be supplied to the photoelectric conversion device from a generation circuit provided outside the photoelectric conversion device. In this case, the photoelectric conversion device is provided with an external input pad (external connection terminal) to which the signal P_CLK1 is input, and an external input pad (external connection terminal) to which the signal P_CLK2 is input.

[0120] In addition, in this embodiment, the quench circuit unit 19 is configured only by the quench element 12, but the present invention is not limited to this example. As shown in Fig. 7(a), the quench circuit unit 19 may include a switch 17 and a resistive element 18. In this case, the signal pCLK described in this embodiment is input to the switch 17. The switch 17 is configured by a PMOS transistor, but the present invention is not limited to this example and may be any element that functions as a switch.

[0121] Also, as shown in FIG. 7(b), the switch 17 may include a plurality of transistors. In this case, a voltage VH is input to one transistor, and a voltage V0 is input to the other transistor. The voltage V0 is closer to the voltage VL than the voltage VH. Even if the voltage V0 is input to the APD 11, the avalanche multiplication operation is not performed. In a state in which the voltage VH is input to the resistive element 18, the quench operation of the APD 11 is performed. On the other hand, in a state in which the voltage V0 is input to the resistive element 18, the quench operation of the APD 11 is not performed. A signal pCLK is input to the gates of the plurality of transistors. In this configuration, the conductivity types of the plurality of transistors to whose gates the signal pCLK is input are different. However, this is not limited to this example. For example, the signal pCLK is input to the gate of one of the transistors. And, a signal obtained by inverting the signal pCLK by an inverter circuit may be input to the gate of the other transistor.

[0122] <Second embodiment> Next, a photoelectric conversion device according to a second embodiment of the present disclosure will be described with a focus on differences from the first embodiment, with reference to Figures 8 to 11. This embodiment has different configurations of the pixel P, the vertical scanning timing control unit 22, and the vertical scanning unit 30 from those of the first embodiment.

[0123] [Pixel P(m,n)] FIG. 8 is a diagram showing the configuration of a pixel P(m,n) according to the second embodiment.

[0124] In this embodiment, the pixel P(m,n) has a memory unit 16. A signal pMEM[n] is supplied to the memory unit 16 from the vertical scanning unit 30 via a drive line. This signal pMEM switches the operation of the memory unit 16 between an operation of updating the signal value held by the memory unit 16 to the signal value output from the counting unit 14 and an operation of holding the signal value. In addition, the output value of the memory unit 16 is input to the selection circuit 15.

[0125] [Vertical scanning timing control section 22] FIG. 9 is a diagram showing the configuration of the vertical scanning timing control section 22 according to the second embodiment.

[0126] In this embodiment, the start trigger generating unit 226 generates a signal TRG_STR as an exposure start trigger signal and outputs it to the vertical scanning unit 30. The signal TRG_STR is a trigger signal indicating the start of exposure, and can be used commonly for all pixel rows of the pixel unit 10. The signal TRG_STR may be generated by the CPU 70. Furthermore, the pulse signal generating unit 221 in the vertical scanning timing control unit 22 generates signals P_CLK1, P_CLK2, P_CLK3, and P_CLK4. The period of each signal can be controlled based on one cycle unit of the signal MCLK. Furthermore, each signal can be set to a different period.

[0127] Also, the selection generation unit 228 generates 2N pulse signal selection information signals, P_SH_L(1) to (N) and P_SH_R(1) to (N), in accordance with the timing of the signal TRG_STR. Here, the suffixes "L" and "R" of the pulse signal selection information signals correspond to the first and second regions when the pixel unit 10 is divided in half in the horizontal direction. The first region is the left region from the 1st column to the M / 2th column. The second region is the right region from the (M / 2)+1th column to the Mth column. However, the number of divided regions is not limited to two, and may be three or more. In that case, the pulse signal selection information signals may be increased appropriately.

[0128] Alternatively, the pulse signal generating unit 221 may output the signals P_CLK_L[1]-[N] and P_CLK_R[1]-[N] corresponding to each pixel region. In this case, the selection generating unit 228, the signals P_SH_L, the signals P_SH_R, and the signals P_CLK1-4 can be omitted. In this case, the signal TRG_STR is input to the pulse signal generating unit 221. The period of each pulse signal is changed according to the timing of this signal TRG_STR. In this case, the signals P_CLK_L[1]-[N] and P_CLK_R[1]-[N], which are pulse signals, can be driven in the same manner as the pulse signals p_clk_L[1]-[N] and p_clk_R[1]-[N] in FIG. 10, which will be described later.

[0129] [Vertical scanning unit 30] FIG. 10 is a configuration diagram of the vertical scanning unit 30 according to the second embodiment. In this embodiment, the vertical scanning unit 30 is configured to omit the second decoder unit 32, the third decoder unit 33, and the exposure start control unit 352. Moreover, instead of the signal P_CLK being input to the vertical scanning unit 30, the signals P_CLK1, P_CLK2, P_CLK3, and P_CLK4 are input, and are input in common to the row driving units 35 of all rows. Note that the configuration may be appropriately changed so that the number of signals P_CLK is five or more. Moreover, instead of the signals P_SH1 and P_SH2 being input to the selection holding unit 356, the corresponding signals among the signals P_SH_L(1)-(N) and P_SH_R(1)-(N) are input. Moreover, the signal P_EXP_STR is input to the pulse count unit 355, not to the selection holding unit 356.

[0130] Furthermore, the signals P_MEM and P_RES are commonly input to the pixel drive signal generation units 354 of all rows.

[0131] The pixel unit 10 is divided horizontally into a first region (here, the left region from the 1st column to the M / 2th column) and a second region (here, the right region from the (M / 2)+1th column to the Mth column). Signals pCLK_L and pCLK_R are supplied to the first region and the second region, respectively. Note that the number of regions may be three or more, in which case signals pCLK are added as appropriate.

[0132] In this embodiment as well, the pulse signal selection unit 357 is a selection unit that selects a clock signal to be output from a plurality of input clock signals having different cycles.

[0133] [Pixel drive signal operation] 11 is a timing chart showing an example of the operation of the vertical scanning timing control section 22, the vertical scanning section 30, and the pixel section 10 according to the second embodiment. Hereinafter, the operation will be described with reference to FIG.

[0134] At time t100, the vertical synchronization signal VD transitions to a high level. In accordance with this transition, the signal p_MEM transitions to a high level. As a result, the signals pMEM for each pixel row transition to a high level simultaneously for all pixel rows.

[0135] At time t101, when the signal p_MEM transitions to a low level, the signal pMEM also transitions to a low level. Then, the signal p_RES transitions to a high level, and based on this, the signals pRES for each pixel row simultaneously transition to a high level.

[0136] At time t102, when the signal TRG_STR transitions to a high level, the supply of the signals pCLK_L and pCLK_R of each row is started. In addition, the levels of the signals P_SH_L(1), P_SH_R(1) to P_SH_L(N), P_SH_R(N) transition. Here, P_SH_L(1) is value 0, P_SH_R(1) is value 1, P_SH_L(2) is value 0, P_SH_R(2) is value 1, P_SH_L(N) is value 2, and P_SH_R(N) is value 3. Note that the above values ​​may be different from each other. Here, the pulse signal selection unit 357 selects P_CLK1 when the pulse signal selection information signal is value 0, selects P_CLK2 when the pulse signal selection information signal is value 1, selects P_CLK3 when the pulse signal selection information signal is value 2, and selects P_CLK4 when the pulse signal selection information signal is value 3. Note that this selection may be assigned differently.

[0137] Furthermore, at time t102, when the signal TRG_STR transitions to a high level, the pulse count unit 355 starts counting the signals p_clk_L and p_clk_R.

[0138] At time t103, when the counter value cnt_P_CLK_L[N] transitions to the value 11, the signal p_exp_stop_L[N] transitions to the high level. Note that the timing at which the signal p_exp_stop_L[N] transitions to the high level is not necessarily limited to when the counter value cnt_P_CLK_L[N] is the value 11. It may be configured so that it can be controlled by another set value held in a register or the like.

[0139] At time t103, when the signal p_exp_stop_L[N] transitions to high level, the supply of the signal pCLK_L[N] corresponding to the 1st column to the M / 2th column in the Nth row of the pixel section 10 is terminated.

[0140] At time t104, when the counter values ​​cnt_P_CLK_L[1] and cnt_P_CLK_L[2] transition to the value 10, the signals p_exp_stop_L[1] and p_exp_stop_L[2] transition to the high level. Note that the timing at which the signals p_exp_stop_L[1] and p_exp_stop_L[2] transition to the high level is not necessarily limited to when the counter values ​​cnt_P_CLK_L[1] and cnt_P_CLK_L[2] are 10. A configuration in which they can be controlled by another setting value held in a register or the like is also possible.

[0141] At time t104, the signals p_exp_stop_L[1] and p_exp_stop_L[2] transition to a high level, thereby terminating the supply of the signals pCLK_L[1] and pCLK_L[2] corresponding to the 1st to M / 2nd columns of the 1st and 2nd rows of the pixel unit 10.

[0142] At time t105, the counter values ​​cnt_P_CLK_R[1] and cnt_P_CLK_R[2] transition to a value of 9. This causes the signals p_exp_stop_R[1] and p_exp_stop_R[2] to transition to a high level. Note that the timing at which the signals p_exp_stop_R[1] and p_exp_stop_R[2] transition to a high level is not necessarily limited to when the counter values ​​cnt_P_CLK_R[1] and cnt_P_CLK_R[2] are 9. A configuration in which they can be controlled by another setting value held in a register or the like is also possible.

[0143] At time t105, the signals p_exp_stop_R[1] and p_exp_stop_R[2] transition to a high level, thereby terminating the supply of the signals pCLK_R[1] and pCLK_R[2] corresponding to the (M / 2)+1 to M columns of the first and second rows of the pixel unit 10.

[0144] At time t106, when the counter value cnt_P_CLK_R[N] transitions to the value 8, the signal p_exp_stop_R[N] transitions to the high level. Note that the timing at which the signal p_exp_stop_R[N] transitions to the high level is not necessarily limited to when the counter value cnt_P_CLK_R[N] is the value 8. It may be configured so that it can be controlled by another setting value held in a register or the like.

[0145] At time t106, when the signal p_exp_stop_R[N] transitions to high level, the supply of the signal pCLK_R[N] corresponding to the (M / 2)+1 to M-th columns in the N-th row of the pixel section 10 is terminated.

[0146] By selecting the period of pCLK supplied to pixel P and the exposure time settings according to each pixel area, it is possible to individually control the exposure time of each area controlled by each pCLK in units of one cycle of signal P_CLK.

[0147] At time t107, p_MEM transitions to a high level, and based on this, the signal pMEM for each pixel row simultaneously transitions to a high level, causing the memory unit 16 to hold the count value of each pixel due to the exposure that began at time t102.

[0148] At time t108, the signal p_MEM transitions to a low level. This also causes the signal pMEM to transition to a low level. Then the signal p_RES transitions to a high level, and based on this, the signals pRES for each pixel row simultaneously transition to a high level. This resets the count value of each pixel due to the exposure that began at t102. In addition, p_VSEL transitions to 0, and based on this, pVSEL[1] transitions to a high level. This causes the count value held in the pixels in the first row to be read out. Thereafter, the count values ​​of each row are read out in sequence according to the value of p_VSEL.

[0149] At time t109, when the signal TRG_STR transitions to a high level, the pulse count unit 355 starts counting the signals p_clk_L and p_clk_R. Note that the values ​​of the signals P_SH_L and P_SH_R may be changed from the values ​​at time t102. In that case, the exposure period of the exposure started at t109 will be different in length from the exposure period of the exposure started at t102.

[0150] According to this embodiment, it is possible to realize a pixel driving method (so-called global shutter) in which the timing of exposure start and end is simultaneous for all rows. In addition, the selection unit selects a clock signal to be used for each pixel region from a plurality of clock signals with different cycles. This makes it possible to change the exposure period for each pixel region while obtaining the effect of the first embodiment. This makes it possible to capture an image with an exposure period of a length suitable for each region, even if there is a difference in brightness between the regions of the subject.

[0151] <Third embodiment> The photoelectric conversion system according to this embodiment will be described with reference to Fig. 12. Fig. 12 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0152] The imaging devices described in the first and second embodiments are applicable to various photoelectric conversion systems. Examples of the applicable photoelectric conversion systems include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion systems. FIG. 12 illustrates a block diagram of a digital still camera as an example of these.

[0153] 12 includes an image capturing device 1004, a lens 1002 that forms an optical image of a subject on the image capturing device 1004, an aperture 1003 that varies the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and the aperture 1003 form an optical system that focuses light on the image capturing device 1004. The image capturing device 1004 is a photoelectric conversion device (image capturing device) according to any one of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0154] The photoelectric conversion system also has a signal processing unit 1007 which is an image generating unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compression as necessary to output image data. The signal processing unit 1007 may be formed on a semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004. Moreover, the imaging device 1004 and the signal processing unit 1007 may be formed on the same semiconductor substrate.

[0155] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data on the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system, or may be removable.

[0156] The photoelectric conversion system further includes an overall control / calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, the timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0157] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004, and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0158] In this way, according to this embodiment, it is possible to realize a photoelectric conversion system to which the photoelectric conversion device (imaging device) according to any one of the above embodiments is applied.

[0159] <Fourth embodiment> The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 13. Fig. 13 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0160] FIG. 13(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0161] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0162] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 300. Fig. 13(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0163] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0164] [Modified embodiment] The present disclosure is not limited to the above-described embodiment, and various modifications are possible.

[0165] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted for the other embodiment, is also included in the embodiments of the present disclosure.

[0166] Furthermore, the photoelectric conversion systems shown in the above third and fourth embodiments are examples of photoelectric conversion systems to which the photoelectric conversion device can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present disclosure can be applied are not limited to the configurations shown in Figures 12 and 13.

[0167] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present disclosure, and the technical scope of the present disclosure should not be interpreted as being limited by these embodiments. In other words, the present disclosure can be implemented in various forms without departing from its technical concept or main features.

[0168] <Fifth embodiment> This embodiment is applicable to any of the first and second embodiments. FIG. 14(a) is a schematic diagram for explaining a device 9191 including a photoelectric conversion device 930 of this embodiment. The photoelectric conversion device 930 can be any of the photoelectric conversion devices explained in the first to seventh embodiments, or a photoelectric conversion device combining a plurality of the embodiments. The device 9191 including the photoelectric conversion device 930 will be explained in detail. As described above, the photoelectric conversion device 930 can include a package 920 that houses the semiconductor device 910 in addition to the semiconductor device 910 having the semiconductor layer 10. The package 920 can include a base to which the semiconductor device 910 is fixed, and a cover such as glass that faces the semiconductor device 910. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the base and a terminal provided on the semiconductor device 910.

[0169] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the photoelectric conversion device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the photoelectric conversion device 930. The control device 950 is, for example, a photoelectric conversion device such as an ASIC.

[0170] The processing device 960 processes the signal output from the photoelectric conversion device 930. The processing device 960 is a photoelectric conversion device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (image) obtained by the photoelectric conversion device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (image) obtained by the photoelectric conversion device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0171] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the photoelectric conversion device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) included in the device 9191. For this purpose, the device 9191 preferably further includes a storage device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit included in the photoelectric conversion device 930. The mechanical device 990 may be controlled based on the signal output from the photoelectric conversion device 930.

[0172] The device 9191 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the photoelectric conversion device 930 for vibration isolation operation.

[0173] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as a transportation equipment is suitable for transporting the photoelectric conversion device 930 or for assisting and / or automating driving (piloting) by using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the photoelectric conversion device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0174] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the photoelectric conversion device can be increased. Increasing the value here means at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, making the device smaller, and reducing weight.

[0175] Therefore, if the photoelectric conversion device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can be improved. For example, by mounting the photoelectric conversion device 930 on a transport equipment, excellent performance can be obtained when photographing the outside of the transport equipment and measuring the external environment. Therefore, in manufacturing and selling the transport equipment, it is advantageous to decide to mount the photoelectric conversion device according to this embodiment on the transport equipment in order to improve the performance of the transport equipment itself. In particular, the photoelectric conversion device 930 is suitable for the transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the photoelectric conversion device. [Explanation of symbols]

[0176] 10 Pixel section 11 Avalanche photodiode 12 Quench element 13 Waveform shaping circuit 14 Counter 15 Pixel output circuit 20 Control section 22 Vertical scanning control section 30 Vertical scanning section 40 Signal holding section 50 Horizontal scanning unit (second scanning unit) 60 Output section 70 CPU (calculation section) 100 Photoelectric conversion device

Claims

1. a quench circuit unit to which a signal that specifies the start and end of an exposure period is input, and a pixel unit in which a plurality of pixels each having an avalanche photodiode connected to the quench circuit unit are arranged across a plurality of rows; a selection unit that receives a plurality of clock signals having different cycles in parallel and selects a clock signal to be output from the plurality of clock signals; a generating unit that generates the signal using the clock signal output from the selecting unit; A photoelectric conversion device comprising:

2. A reference clock signal is input to the photoelectric conversion device; The photoelectric conversion device according to claim 1 , further comprising a generation unit that generates the plurality of clock signals in parallel using the reference clock signal.

3. 2. The photoelectric conversion device according to claim 1, further comprising a plurality of pads to which the plurality of clock signals are input in parallel from outside the photoelectric conversion device.

4. The clock signal selected by a selection unit corresponding to pixels in some rows among the plurality of rows; The photoelectric conversion device according to any one of claims 1 to 3, characterized in that the period of the clock signal selected by a selection section corresponding to pixels of another part of rows among the plurality of rows is different from that of the clock signal selected by the selection section corresponding to pixels of another part of rows.

5. 5. The photoelectric conversion device according to claim 1, wherein the selection section performs the selection in accordance with a trigger signal that controls the start of the exposure period.

6. 6. The photoelectric conversion device according to claim 1, wherein the length of the exposure period is controlled using the clock signal selected by the selection section.

7. a pulse counting unit that generates a count value by counting the clock signal selected by the selection unit; 7. The photoelectric conversion device according to claim 1, further comprising an exposure end control unit that controls the end of the exposure period based on the count value.

8. Each of the plurality of pixels comprises a transistor having a gate; a pixel drive signal generating unit that supplies a control signal to the gate; 8. The photoelectric conversion device according to claim 7, wherein the exposure end control unit outputs a signal to the pixel drive signal generation unit to control the end of the exposure period.

9. a scanning unit that scans the plurality of rows in units of one row or two or more rows; the scanning unit includes a plurality of row driving units each corresponding to a portion of the plurality of rows, 9. The photoelectric conversion device according to claim 8, wherein each of the plurality of row driving sections includes the pixel driving signal generating section and the exposure end control section.

10. The photoelectric conversion device according to claim 9 , wherein each of the plurality of row driving sections includes the pulse count section.

11. During the exposure period of pixels of a portion of the plurality of rows, A photoelectric conversion device according to any one of claims 1 to 10, characterized in that the selection unit corresponding to pixels in another part of the plurality of rows changes the clock signal output from among the plurality of clock signals to another clock signal.

12. During a period in which signals are read out from pixels in some of the plurality of rows, A photoelectric conversion device according to any one of claims 1 to 10, characterized in that the selection unit corresponding to pixels in another part of the plurality of rows changes the clock signal output from among the plurality of clock signals to another clock signal.

13. 13. The photoelectric conversion device according to claim 1, wherein the exposure period starts simultaneously for the plurality of rows.

14. 14. The photoelectric conversion device according to claim 13, wherein the exposure period is ended simultaneously for the plurality of rows.

15. 15. The photoelectric conversion device according to claim 1, wherein the quench circuit section includes a quench element which is a transistor having a gate to which the signal is input.

16. 15. The photoelectric conversion device according to claim 1, wherein the quench circuit section includes a switch controlled by the signal, and a resistive element connected to the switch.

17. The photoelectric conversion device according to any one of claims 1 to 16, and a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

18. A moving object including the photoelectric conversion device according to any one of claims 1 to 16, A moving body comprising: a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

19. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 16, an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

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