system

Abstract

To provide a system capable of increasing the speed of a communication interface.SOLUTION: A memory card comprises a terminal group PA1 arranged in a row R1 and including a power supply terminal VDD and a ground terminal VSS, and a terminal group PA2 arranged in a row R2 extending parallel to the row R1 and including a plurality of differential data terminals for communicating differential data signals and a plurality of ground terminals GND. The differential data terminals include a pair of differential data terminals RX0N, RX0P, TX0N, TX0P arranged adjacent to one another. The pair of differential data terminals are arranged between a plurality of ground terminals, and in communication compliant with the SD standard, use a terminal included in the terminal group PA1 to receive a single-ended signal, and in communication compliant with the PCIe standard, use a terminal included in the terminal group PA1 to receive a differential clock signal and a reset signal compliant with the PCIe standard, and use a terminal included in the terminal group PA2 to receive the differential data signal compliant with the PCIe standard.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present embodiments generally relate to a system. [Background technology]

[0002] In memory cards, the amount of data transferred is increasing as the storage capacity increases. To prevent the data transfer time from increasing as the amount of data transferred increases, there is a demand for faster communication interfaces mounted on memory cards. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-29556 A Summary of the Invention [Means for solving the problem]

[0004] According to one embodiment, a system including a memory card and a host device is provided. The memory card has a first main surface, a first terminal group, and a second terminal group. The first main surface includes a first side and a second side parallel to the first side. The first terminal group is arranged in a first row of the first main surface and includes three or more terminals. The second terminal group is arranged in a second row of the first main surface, parallel to the first row, and includes three or more terminals. The first row is closer to the first side than the second side. The second row is closer to the second side than the first side. The second terminal group includes a plurality of differential data terminals for communicating differential data signals and a plurality of ground terminals connected to a ground potential. In a first mode of communication compatible with the SD standard, the memory card receives a single-ended signal compatible with the SD standard using a terminal included in the first terminal group. In a second mode of communication conforming to the PCIe (Peripheral Component Interconnect express) standard, the memory card receives a differential clock signal and a reset signal conforming to the PCIe standard using a terminal included in the first terminal group, and receives a differential data signal conforming to the PCIe standard using a terminal included in the second terminal group. The host device is capable of supplying a first power source to a first power source terminal of the memory card. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a plan view showing a schematic configuration of a memory card according to a first embodiment. [Diagram 2] FIG. 2 is a plan view showing a schematic configuration of a memory card according to the second embodiment. [Diagram 3] FIG. 3 is a plan view showing another schematic configuration of the memory card according to the second embodiment. [Figure 4A] FIG. 4A is a plan view showing a schematic configuration of a memory card according to a third embodiment. [Figure 4B] FIG. 4B is a plan view showing a schematic configuration of a memory card according to the fifth embodiment. [Figure 4C] FIG. 4C is a plan view showing a schematic configuration of a memory card according to the fourth embodiment. [Diagram 5] FIG. 5 is a block diagram showing a schematic configuration of a memory card according to the sixth embodiment. [Figure 6] FIG. 6 is a block diagram showing a schematic configuration of a host device in which a memory card according to the seventh embodiment is inserted. [Figure 7] FIG. 7 is a block diagram showing a schematic configuration of an interface card to which a memory card according to the eighth embodiment is attached. [Figure 8] FIG. 8 is a flowchart showing the operation of the host device when setting the bus mode of the memory card according to the ninth embodiment. [Figure 9] FIG. 9 is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission path connected to a memory card according to the tenth embodiment. [Figure 10A] FIG. 10A is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to an eleventh embodiment. [Figure 10B] FIG. 10B is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission path connected to a memory card according to the twelfth embodiment. [Figure 11A] FIG. 11A is a perspective view showing an example of a schematic configuration of a connector used in a memory card according to a thirteenth embodiment. [Figure 11B] FIG. 11B is a cross-sectional view showing an example of a schematic configuration of a connector used in a memory card according to the thirteenth embodiment. [Figure 12A] FIG. 12A is a cross-sectional view showing an example of a schematic configuration of a connector according to a fourteenth embodiment before a memory card is mounted. [Figure 12B] FIG. 12B is a plan view showing an example of a schematic configuration of the connector according to the fourteenth embodiment before a memory card is inserted. [Figure 12C] FIG. 12C is a cross-sectional view showing an example of a schematic configuration of the connector after a memory card is mounted according to the fourteenth embodiment. [Figure 12D]FIG. 12D is a plan view showing an example of a schematic configuration of the connector after a memory card is mounted according to the fourteenth embodiment. [Figure 13A] FIG. 13A is a cross-sectional view showing an example of a schematic configuration of an adapter before a memory card is attached according to a fifteenth embodiment. [Figure 13B] FIG. 13B is a plan view showing an example of a schematic configuration of the adapter before a memory card is inserted according to the fifteenth embodiment. [Figure 13C] FIG. 13C is a cross-sectional view showing an example of a schematic configuration of the adapter after a memory card is attached according to the fifteenth embodiment. [Figure 13D] FIG. 13D is a plan view showing an example of a schematic configuration of the adapter after a memory card is attached according to the fifteenth embodiment. [Figure 14A] FIG. 14A is a cross-sectional view showing an example of a schematic configuration of an adapter before a memory card is inserted according to the sixteenth embodiment. [Figure 14B] FIG. 14B is a plan view showing an example of a schematic configuration of the adapter before a memory card is inserted according to the sixteenth embodiment. [Figure 14C] FIG. 14C is a cross-sectional view showing an example of a schematic configuration of the adapter after a memory card is attached according to the sixteenth embodiment. [Figure 14D] FIG. 14D is a plan view showing an example of a schematic configuration of the adapter after a memory card is attached according to the sixteenth embodiment. [Figure 15A] FIG. 15A is a cross-sectional view showing an example of a schematic configuration of an adapter before a memory card is inserted according to the seventeenth embodiment. [Figure 15B] FIG. 15B is a plan view showing an example of a schematic configuration of the adapter before a memory card is inserted according to the seventeenth embodiment. [Figure 15C] FIG. 15C is a cross-sectional view showing an example of a schematic configuration of the adapter after a memory card is attached according to the seventeenth embodiment. [Figure 15D] FIG. 15D is a plan view showing an example of a schematic configuration of the adapter after a memory card is attached according to the seventeenth embodiment. [Figure 16A]FIG. 16A is a perspective view showing a schematic configuration of a memory card according to an eighteenth embodiment. [Figure 16B] FIG. 16B is a cross-sectional view showing an example of a schematic configuration of the adapter before a memory card is attached according to the 19th embodiment. [Figure 16C] FIG. 16C is a perspective view showing a schematic configuration of a memory card according to the twentieth embodiment. [Figure 16D] FIG. 16D is a cross-sectional view showing the state of the adapter after the memory card of FIG. 16C has been inserted. [Figure 17] FIG. 17 is a plan view showing an example of a schematic configuration of an adapter after a memory card according to the twenty-first embodiment is mounted. [Figure 18] FIG. 18 is a plan view showing a schematic configuration of a memory card according to the twenty-second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] A memory card, a host device, a memory card connector, and a memory card adapter according to the embodiments will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. In the following embodiments, an SD card is used as an example of a memory card, but other cards such as a multimedia card may also be used.

[0007] (First embodiment) FIG. 1 is a plan view showing a schematic configuration of a memory card according to a first embodiment. In Fig. 1, rows R1 and R2 are provided on the card surface of memory card SD1. Terminal groups PA1 and PA2 are provided in rows R1 and R2, respectively. Row R1 can specify an area in which the terminals of terminal group PA1 are arranged side by side. Row R2 can specify an area in which the terminals of terminal group PA2 are arranged side by side.

[0008] The terminals of the terminal groups PA1 and PA2 may have different dimensions, and the intervals between the terminals of the terminal groups PA1 and PA2 may be different. In row R1, the positions of the terminals of the terminal group PA1 may be shifted vertically. In row R2, the positions of the terminals of the terminal group PA2 may be shifted vertically.

[0009] The form factor of this memory card SD1 can be made compatible with a microSD card. In this case, the vertical dimension A1 of the memory card SD1 can be set to 15 mm, the horizontal dimension B1 to 11 mm, and the thickness to 1.0 mm.

[0010] A signal used for communication conforming to one interface standard is assigned to each of the rows R1 and R2. At this time, it is possible to prevent signals used for communication conforming to multiple interface standards from being assigned to one row. However, a signal used for communication conforming to one interface standard may be assigned to multiple rows.

[0011] A signal used for communication in a first mode corresponding to the SD standard is assigned to row R1. A single-ended signal can be used for communication in the first mode corresponding to the SD standard. That is, the single-ended signal corresponds to the SD standard. In the first mode corresponding to the SD standard, a power supply VDD, a ground potential VSS, a command CMD, a clock CLK, and data DAT[3:0] are assigned to terminal group PA1.

[0012] In the first mode, which is compatible with the SD standard, communication is possible in accordance with DS (Default Speed), HS (High Speed), or UHS (Ultra High Speed)-I. The maximum transfer speed of DS is 12.5 MB / s, that of HS is 25 MB / s, and that of UHS-I is 104 MB / s.

[0013] Signals used for communication in a second mode compliant with the PCIe (Peripheral Component Interconnect express) standard are assigned to row R2. In the second mode compliant with the PCIe standard, differential signals can be used for data communication. In the second mode compliant with the PCIe standard, transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N are assigned to terminal group PA2. Bidirectional communication can be performed by using the transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N. At this time, GND terminals at ground potential are assigned to row R2 so as to sandwich the terminals to which the differential signals are assigned.

[0014] Furthermore, in row R2, one terminal of the terminal group PA2 is assigned to the power supply terminal VDD2 or the power supply terminal VDD3, and another terminal of the terminal group PA2 is assigned to the power supply terminal VDD2. Furthermore, yet another terminal of the terminal group PA2 is assigned to SWIO. SWIO can be used for NFC (Near Field Communication).

[0015] In the first mode that complies with the SD standard, the clock CLK and the data DAT[3:0] are assigned to separate terminals, and therefore the clock CLK and the data DAT[3:0] are transmitted via separate transmission paths.

[0016] In the second mode, which is compatible with the PCIe standard, data is transmitted serially, but the data is coded in units so that the same voltage level does not continue for long periods of time, allowing the receiving circuit to generate a clock. Methods such as 8B10B or 128b / 130b are used for coding. The receiving side can receive data even if the voltage level fluctuates slightly by generating a clock from the point where the data changes. Even if there are multiple lanes (pairs of up and down differential data signals), the skew between lanes can be canceled by configuring independent receiving circuits for each lane and aligning the start position of the received data.

[0017] For example, in the second mode compatible with the PCIe 3.0 standard, the maximum transfer speed is 2 GB / s per lane (total of uplink and downlink). In the second mode compatible with the PCIe standard, one lane can be configured with a pair of transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N. The pair of transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N can be arranged in one row of the memory card SD1.

[0018] Therefore, by increasing the number of rows of the memory card SD1, the number of lanes in the second mode compatible with the PCIe standard can be increased, and the transfer speed in the second mode compatible with the PCIe standard can be improved. In the second mode compatible with the PCIe standard, a multiple lane configuration is recognized at the time of initialization, and one piece of data can be transferred over multiple lanes.

[0019] When communication is performed in the second mode corresponding to the PCIe standard, control signals used to control communication in the second mode corresponding to the PCIe standard are assigned to row R1. The control signals may include the reference differential clock signal REFCLKp / n, the reset signal PERST, and the power management control signal CLKREQ. The control signals may further include the wake-up signal PEWAKE. These control signals are assigned instead of the command CMD and data DAT[3:0] of row R1.

[0020] The reference differential clock signal REFCLKp / n is a differential clock made up of two lines, and by sending the clock from the host device, the memory card SD1 can easily synchronize with the host device in which the memory card SD1 is inserted. However, the reference differential clock signal REFCLKp / n is assigned to row R1, and the transmit differential signals TX0P, TX0N and the receive differential signals RX0P, RX0N are assigned to row R2 and onwards. For this reason, the reference differential clock signal REFCLKp / n is transmitted on a transmission path separate from the transmit differential signals TX0P, TX0N and the receive differential signals RX0P, RX0N.

[0021] The host device may be, for example, an information processing device such as a personal computer, a mobile phone, a digital camera, an imaging device, a mobile terminal such as a tablet computer or a smartphone, a game device, or an in-vehicle terminal such as a car navigation system.

[0022] The memory card SD1 generates a bit clock by multiplying the received reference differential clock. Data is output from the transmit differential signals TX0P, TX0N in synchronization with the bit clock, and the data read from the receive differential signals RX0P, RX0N is aligned in synchronization with the bit clock. Even in the case of multiple lanes, the data can be aligned as one piece of data by synchronizing with the bit clock.

[0023] The reset signal PERST can be used by the host device to reset the bus used for communication in the second mode conforming to the PCIe standard. This reset signal PERST can be used by the host device to reinitialize the card when an error occurs, for example.

[0024] The power management control signal CLKREQ can be used as a clock to return from the power saving mode, in which the high frequency bit clock used for data transfer is stopped, thereby reducing power consumption.

[0025] If the wake-up signal PEWAKE is implemented in the memory card SD1, the wake-up signal PEWAKE can be used by the memory card SD1 to notify the host device of various events in power saving mode. When the host device receives the wake-up signal PEWAKE from the memory card SD1, it can cancel the power saving mode and process the event. Some memory cards implement I / O functions, and can also be used as a means of notifying I / O interrupts.

[0026] In row R2, one terminal of the terminal group PA2 is assigned to a power supply terminal VDD2 or a power supply terminal VDD3. The host device can supply a power supply voltage VDD1 to the power supply VDD of row R1. The power supply voltage VDD1 can be set to 3.3V. The power supply terminal VDD2 of row R2 can be supplied with a power supply voltage VDD2. The power supply voltage VDD2 can be set to 1.8V. Alternatively, the power supply terminal VDD3 of row R2 can be supplied with a power supply voltage VDD3. The power supply voltage VDD3 can be set to 1.2V. The power supply voltage notation indicates the median value, and a certain voltage fluctuation range is allowed. For example, the allowable range for 3.3V is 2.7V to 3.6V, for 1.8V is 1.70 to 1.95V, and for 1.2V is 1.1V to 1.3V.

[0027] The following explanation assumes the presence of the power supply terminal VDD3, but if the memory card SD1 that supports the power supply voltage VDD3 does not have the power supply terminal VDD3, the power supply voltage VDD2 or the power supply voltage VDD3 can be supplied using the power supply terminal VDD2 of row R2. Specifically, the power supply voltage VDD2 is applied at 1.8 V or 1.2 V. In other words, there are cases where the memory card SD1 does not have the power supply terminal VDD3, but the explanation is the same except that the supply destination of the power supply voltage VDD3 is changed to the power supply terminal VDD2. In the above description, the signals used for communication in the second mode conforming to the PCIe standard are assigned to row R2, but the signals used for communication in UHS-II may be assigned to row R2. The maximum transfer speed of UHS-II is 312 MB / s.

[0028] Here, in order to determine whether the memory card SD1 communicates in the second mode corresponding to the UHS-II standard or the second mode corresponding to the PCIe standard, the power supply voltage VDD2 or the power supply voltage VDD3 can be used. When a power supply voltage is applied to the power supply terminal VDD2 or the power supply terminal VDD3 of the terminal group PA2, the memory card SD1 can communicate in the PCIe bus mode if it supports the PCIe standard.

[0029] Alternatively, there is a method to detect the change point of the power supply voltage VDD2 or VDD3 and switch. When VDD2 or VDD3 changes from off to on, the PCIe bus mode is entered, and when it changes from on to off, the PCIe bus mode is exited. This allows operation in SD mode whether VDD2 or VDD3 is on or off.

[0030] A host device using the UHS-II standard applies the power supply voltage VDD2 to the power supply terminal VDD2, and a host device using the PCIe standard applies the power supply voltage VDD2 to the power supply terminal VDD2 or applies the power supply voltage VDD3 to the power supply terminal VDD3. The memory card SD1 can easily determine the bus mode expected by the host device based on the combination of the presence or absence of the VDD2 / VDD3 voltages. Therefore, the memory card SD1 does not need to determine the bus mode based on the symbol sent in the data.

[0031] Here, in order to enable the host device to recognize whether the memory card SD1 supports the PCIe standard or the UHS-II standard, the host device that supports the PCIe standard can transmit a predetermined PCIe symbol to the terminal group PA2 of row R2 to recognize that the memory card SD1 supports the PCIe standard. If there is a response from the memory card SD1 to that symbol, the host device can recognize that the memory card SD1 supports the PCIe standard. The host device that supports UHS-II can transmit a UHS-II initialization symbol to the terminal group PA2 of row R2. If there is a response from the memory card SD1 to that symbol, the host device can recognize that the memory card SD1 supports UHS-II.

[0032] Here, by allocating signals used for communication in the second mode conforming to the PCIe standard to row R2 and enabling the memory card SD1 to support communication according to the PCIe standard, the data transfer speed can be increased. As the storage capacity of the memory card SD1 increases, the time required to access the entire memory area increases, but this time can be reduced by further increasing the bus speed using a method such as a multi-lane configuration.

[0033] In addition, the memory card SD1 supports communication based on the PCIe standard, which allows the use of a standard physical layer (PHY) of the PCIe standard, making it possible to simplify the design and reduce development costs in order to increase the data transfer speed of the memory card SD1.

[0034] Furthermore, because the memory card SD1 supports communication based on the PCIe standard, it is possible to adopt NVMe (Non Volatile Memory express) for the data link layer of the PCIe standard, which reduces the overhead during data transfer and improves data transfer efficiency.

[0035] Second embodiment FIG. 2 is a plan view showing a schematic configuration of a memory card according to the second embodiment.

[0036] In Fig. 2, rows R1 to R4 are provided on the card surface of the memory card SD2. Terminal groups PA1 and PA2 are provided in rows R1 and R2, respectively. Rows R1 and R2 can be used in the same way as memory card SD1 in Fig. 1. For example, row R2 can support UHS-II, and rows R3 and R4 can support the PCIe standard.

[0037] Rows R3 and R4 are provided with terminal groups PA3 and PA4, respectively. Row R3 can specify an area in which the terminals of terminal group PA3 are arranged horizontally. Row R4 can specify an area in which the terminals of terminal group PA4 are arranged horizontally. The form factor of this memory card SD2 can be made compatible with a microSD card. Note that if memory card SD2 is provided with rows R3 and R4, row R2 can be optional (not required).

[0038] In Figure 2, rows R3 and R4 are configured in two rows, but each row indicates a set of terminals required to configure one lane, and does not limit the terminal arrangement on the memory card. For example, the pads in the two rows may be arranged in a zigzag pattern, or rows R3 and R4 may be arranged in a single row to form a U-shape.

[0039] The area of ​​each terminal of the terminal groups PA3 and PA4 can be smaller than the area of ​​each terminal of the terminal groups PA1 and PA2. Depending on the contact method of the connector, the shapes of each terminal of the terminal groups PA3 and PA4 can be made equal to each other. Here, by making the area of ​​each terminal of the terminal groups PA3 and PA4 smaller, it is possible to reduce the parasitic capacitance, and the stub when contacting the terminal can be made smaller, thereby improving the frequency characteristics. Note that the stub here refers to the end of the terminal that is formed in the part that does not contact the connector pin when contacting the terminal of the memory card SD2. Also, by making the shapes of each terminal of the terminal groups PA3 and PA4 equal to each other, it is possible to improve the symmetry of the electrical characteristics of the differential signals that make up the lanes.

[0040] Signals used for communication according to the PCIe standard are assigned to each of the rows R3 and R4. The terminal group PA3 of row R3 is assigned the transmit differential signals TX0P and TX0N and the receive differential signals RX0P and RX0N. The terminal group PA4 of row R4 is assigned the transmit differential signals TX1P and TX1N and the receive differential signals RX1P and RX1N.

[0041] Here, one row can constitute one lane of the PCIe standard. Therefore, by allocating signals used for communication according to the PCIe standard to rows R3 and R4, two lanes of the PCIe standard can be constituted, and the data transfer speed can be doubled compared to a method in which signals used for communication according to the PCIe standard are allocated to one row.

[0042] Even when communication is performed according to the PCIe standard using the two rows R3 and R4, the control signal used to control communication according to the PCIe standard is assigned to row R1. In this case, the control signal assigned to row R1 can be shared by the two rows R3 and R4.

[0043] In row R3, a power supply terminal VDD3 is assigned to one terminal of the terminal group PA3. A power supply voltage VDD3 can be supplied to the power supply terminal VDD3 of row R3. The power supply terminal VDD3 of the terminal group PA3 can be shared by rows R3 and R4. The power supply voltage VDD3 can be used to determine whether the memory card SD2 communicates in a first mode conforming to the SD standard or in a second mode conforming to the PCIe standard.

[0044] In addition, in each of rows R3 and R4, GND terminals of ground potential are assigned so that the terminals to which the differential signals are assigned are sandwiched between them. For example, in row R3, the receive differential signals RX0N, RX0P, TX0N, and TX0P are assigned to the second, third, sixth, and seventh terminals from the right. At this time, the ground potential GND is assigned to the first, fourth, fifth, and eighth terminals from the right of row R3.

[0045] However, the memory card may have a configuration as shown in Fig. 3, in which a power supply terminal is arranged in place of one of the two GND terminals surrounding the differential signal terminals as compared to the configuration shown in Fig. 2. The power supply terminal may be a power supply terminal corresponding to a stable power supply. Fig. 3 is a plan view showing another schematic configuration of the memory card according to the second embodiment.

[0046] Here, by assigning the ground potential GND to terminals sandwiching a terminal to which a differential signal is assigned, a return path can be secured for each differential signal, and mutual interference between the differential signals can be reduced.

[0047] In the example of Fig. 2 or 3, the method of assigning the ground potential GND independently to each differential signal has been described, but if there is a sufficient noise margin against mutual interference between differential signals, adjacent terminals to which the ground potential GND has been assigned may be common. For example, in row R3, either of the fourth and fifth terminals from the right to which the ground potential GND has been assigned may be omitted. This makes it possible to reduce the number of terminals provided in each row R3 and R4, and even if there is a limit to the number of terminals that can be arranged in one row of the memory card SD2, the limit can be easily accommodated.

[0048] Also, in the examples of FIG. 2 and FIG. 3, a method of providing rows R3 and R4 in the memory card SD2 has been described, but row R4 may be omitted.

[0049] 2 or 3, a method of providing two rows R3 and R4 in addition to rows R1 and R2 has been described, but three or more rows may be provided in addition to rows R1 and R2. For example, rows R5 and R6 may be added. Here, by supporting communication in accordance with the PCIe standard, the memory card SD2 can increase the number of lanes by increasing the number of rows, and can easily accommodate an increase in data transfer speed.

[0050] That is, N (N is an integer equal to or greater than 2) rows can be provided on the card surface of the memory card. In the first row, data communication is performed in a first mode corresponding to the SD standard, and in the second row to the Nth row, data communication is performed according to the PCIe standard. The second row may be assigned as a PCIe lane, but since the shape of the pads is different from the third row and onwards, it does not have to be used. If the number of PCIe lanes is X, the PCIe standard allows data communication using X lanes; for example, the maximum transfer speed of the PCIe 3.0 standard can achieve X x 2 Gbytes / sec (bidirectional).

[0051] Third embodiment FIG. 4A is a plan view showing a schematic configuration of a memory card according to a third embodiment.

[0052] There are three possible combinations for the microSD form factor: with or without row R2, and with or without rows R3 and R4.

[0053] (1) With row R2, but without rows R3 and R4 (case in Figure 1) Row R2 is assigned one lane of UHS-II differential signals or PCIe standard differential signals. Which one is supported is identified during initialization (both may be supported). Furthermore, there are combinations where Row R2 has or does not have a power supply terminal VDD3, and if there is a power supply terminal VDD3, 1.2V is applied. If there is no power supply terminal VDD3, the power supply terminal VDD2 is used, and 1.8V or 1.2V is applied to the power supply terminal VDD2.

[0054] (2) Without row R2, with rows R3 and R4 (case in Figure 4A) Rows R3 and R4 are assigned two lanes of differential signals according to the PCIe standard. The power supply voltage VDD3 is in row R3. UHS-II is not supported.

[0055] (3) When row R2 is present and rows R3 and R4 are present (case in Figure 2) Row R2 is assigned a UHS-II differential signal, while rows R3 and R4 are assigned two lanes of differential signals conforming to the PCIe standard. Furthermore, there are combinations in which Row R2 either has or does not have a power supply terminal VDD3; if the power supply terminal VDD3 is present, 1.2V is applied to it. If the power supply terminal VDD3 is not present, the power supply terminal VDD2 is used, or the power supply terminal VDD3 of Row R3 may be used. If the power supply terminal VDD2 is used, 1.8V or 1.2V is applied. Furthermore, in the second mode conforming to the PCIe standard, Row R2 can be used as an interface for a different purpose.

[0056] The rows R1, R3, R4 of the memory card SD3 can be used in the same way as the rows R1, R3, R4 of the memory card SD2 in FIG.

[0057] Here, by removing row R2 of memory card SD2, the free space on the card surface of memory card SD3 can be increased, which can be used, for example, as a contact area for heat dissipation.

[0058] (Fourth embodiment) FIG. 4C is a plan view showing a schematic configuration of a memory card according to the fourth embodiment.

[0059] In Fig. 4C, rows R1, R3, and R4 are provided on the card surface of memory card SD5. A terminal group PC1 is provided in row R1. Signals used for communication in a first mode conforming to the SD standard are assigned to row R1. At this time, in row R1, a power supply VDD is assigned to terminal 4, a ground potential VSS is assigned to terminals 3 and 6, a command CMD is assigned to terminal 2, a clock CLK is assigned to terminal 5, and data DAT[3:0] is assigned to terminals 1, 9, 8, and 7.

[0060] Rows R3 and R4 are provided with terminal groups PC3 and PC4, respectively, allowing for a two-lane configuration. The form factor of this memory card SD5 can be made compatible with a standard-sized SD card. In this case, the vertical dimension A2 of the memory card SD5 can be set to 32 mm, the horizontal dimension B2 to 24 mm, and the thickness to 2.1 mm.

[0061] Rows R1, R3 / R4 of the memory card SD5 can be used in the same way as rows R1, R3, R4 of the memory card SD2. This allows the memory card SD5 to support communication in the second mode that complies with the PCIe standard, even if the form factor of the memory card SD5 supports standard-sized SD cards, thereby increasing the data transfer speed.

[0062] Fifth embodiment FIG. 4B is a plan view showing a schematic configuration of a memory card according to the fifth embodiment.

[0063] In FIG. 4B, rows R1, R3, and R4 are provided on the card surface of memory card SD4. Row R1 is provided with terminal group PB1. Row R1 is assigned with signals used for communication in the first mode that complies with the SD standard. Although the terminal group PB1 in FIG. 4B shows an example in which the terminal group PB1 has the same shape as the terminal group PA1 in FIG. 4A, the shape of the terminal group PB1 may be a small pad shape that is the same as or similar to the terminal shapes of rows R3 and R4. By using an adapter, it can be made to maintain compatibility by converting to the form factor of FIG. 4C.

[0064] Terminal groups PB3 and PB4 are provided in rows R3 and R4, respectively. The form factor of this memory card SD4 can be volumetrically included in the form factor corresponding to a microSD card, and can be volumetrically included in the form factor corresponding to a standard size SD card. In this case, the vertical dimension A3 of the memory card SD4 can be set in the range of 16 mm to 20 mm, the horizontal dimension B3 can be set in the range of 12 mm to 16 mm, and the thickness can be set in the range of 1.4 mm to 1.6 mm.

[0065] Here, the form factor of the memory card SD4 volumetrically encompasses a form factor corresponding to a microSD card, so that even if the chip size of the NAND flash memory increases, the NAND flash memory can be stored in the memory card SD4, and it can accommodate increases in the storage capacity of the NAND flash memory.

[0066] In addition, the form factor of the memory card SD4 is volumetrically contained within the form factor corresponding to a standard size SD card, which makes it possible to suppress an increase in the size of the memory card SD4. This ensures the compactness of the memory card SD4, and it can be used in mobile terminals such as smartphones and mobile devices such as digital cameras.

[0067] Rows R1, R3, and R4 of memory card SD4 can be used in the same way as rows R1, R3, and R4 of memory card SD5, and rows R1, R3, and R4 of memory card SD3. This allows communication under the PCIe standard to be supported even if the form factor of memory card SD4 is different from that of a microSD card and a standard size SD card, and allows access to memory areas regardless of the difference in form factor.

[0068] The memory cards SD2 to SD5 can have the same dimensions, shapes, and spacing of the terminals arranged in rows R3 and R4, and therefore the connectors that make contact with the terminals arranged in rows R3 and R4 can be standardized among the memory cards SD2 to SD5.

[0069] Sixth embodiment Fig. 5 is a block diagram showing a schematic configuration of a memory card according to a sixth embodiment. The configuration in Fig. 5 can be used for any of the memory cards SD1 to SD5 in Figs. 1, 2, and 4A to 4C. In the following description, the configuration in Fig. 5 is applied to the memory card SD2 in Fig. 2 as an example.

[0070] In FIG. 5, the memory card SD2 is provided with regulators 11 and 12, a comparator 13, a card controller 14, a memory interface circuit 15, and a memory 16. The memory 16 can be a NAND flash memory. The card controller 14 can perform read / write control for the memory 16 and communication control with the outside. This communication control can include protocol control corresponding to a first mode corresponding to the SD standard and protocol control corresponding to the PCIe standard. The card controller 14 is provided with an IO cell 17, a physical layer interface 18, and a card interface circuit 19.

[0071] The IO cell 17 can accommodate a single-ended signal. The IO cell 17 can accommodate a signal assigned to row R1. The IO cell 17 is provided with input buffers V1 and V3 and an output buffer V2. A clock CLK can be input to the input buffer V1. A command CMD and data DAT[3:0] can be input to the input buffer V3. The output buffer V2 can output a response to the command CMD and data DAT[3:0]. The input buffer V3 and the output buffer V2 can be provided for each command CMD and data DAT[3:0].

[0072] The physical layer interface 18 can accommodate differential signals. The physical layer interface 18 can accommodate signals assigned to the rows R2, R3, and R4. The physical layer interface 18 is provided with a receiver RE and a transmitter TR. The receiver RE can receive differential signals RX0P and RX0N of the rows R2 and R3 and receive differential signals RX1P and RX1N of the row R4. The transmitter TR can output differential signals TX0P and TX0N of the rows R2 and R3 and transmit differential signals TX1P and TX1N of the row R4. The receiver RE and the transmitter TR can be provided for each of the rows R2, R3, and R4. In the row R2, the physical layer interface 18 can have the same configuration whether in the second mode corresponding to the UHS-II standard or the second mode corresponding to the PCIe standard.

[0073] The IO cell 17 and the physical layer interface 18 are connected to the card interface circuit 19. The card controller 14 is connected to the memory 16 via the memory interface circuit 15. In order to make the memory card SD2 support the PCIe standard, the card controller 14 can be provided with a data link layer and a transaction layer of the PCIe standard in addition to the physical layer interface 18 of the PCIe standard. The physical layer interface 18 can perform serial / parallel conversion, parallel / serial conversion, and data symbolization. This symbolization is a process of suppressing the number of consecutive occurrences of the same value below a predetermined value when data has consecutive 0s or 1s. This symbolization can suppress bias in voltage levels during data transmission. In addition, EMI (ElectroMagnetic Interference) can be suppressed by using symbols that do not increase harmonics of a specific frequency.

[0074] In addition, the transaction layer of the PCIe standard can packetize data and add commands to the packet headers. The data link layer of the PCIe standard can add sequence numbers and CRC (Cyclic Redundancy Check) codes to packets received from the transaction layer. The sequence number can be used to confirm the delivery of packets, etc.

[0075] A power supply voltage VDD1 is supplied to the regulator 11, the card controller 14, the memory interface circuit 15, and the memory 16. The power supply voltage VDD1 supplied to the regulator 11 is converted to a power supply voltage VDDL and supplied to the card controller 14 and the memory interface circuit 15. The power supply voltage VDDL is determined according to the technology of the card controller. The memory interface circuit 15 is a level shifter circuit when the interface voltage of the card controller 14 and the interface voltage of the memory 16 are different.

[0076] In the first mode (DS, HS, or UHS-I) corresponding to the SD standard, the device is configured to be operable with only the power supply voltage VDD1. In the UHS-7 mode, the card controller 14 and memory interface circuit 15 can use the power supply voltage VDDL as 1.8V. At this time, the IO cell 17 can switch the output signal voltage and input threshold according to the power supply voltages VDD1 and VDDL. The voltage VDD2 can be supplied as an option.

[0077] The power supply voltage VDD3 is supplied to the regulator 12 and the comparator 13. The power supply voltage VDD3 supplied to the regulator 12 is converted to a power supply voltage VDDPHY required for operating the physical layer interface 18, and is supplied to the physical layer interface 18.

[0078] The power supply voltage VDD3 supplied to the comparator 13 is compared with a reference voltage. Then, based on the result of this comparison, the application of the power supply voltage VDD3 is detected, and a detection signal VDD3SP is output to the card controller 14. Although not shown in the figure, when the power supply voltage VDD2 is used, the power supply voltage VDD2 is similarly supplied to the regulator 12 and the comparator 13, converted into the power supply voltage VDDPHY required to operate the physical layer interface 18, supplied to the physical layer interface 18, and the detection signal VDD3SP is output to the card controller 14.

[0079] When the application of the power supply voltage VDD3 is not detected by the comparator 13, the memory card SD2 communicates in the first mode corresponding to the SD standard. At this time, the clock CLK transmitted from the host device to the memory card SD2 is transmitted to the card interface circuit 19 via the input buffer V1. The command CMD and data DAT[3:0] transmitted from the host device to the memory card SD2 are transmitted to the card interface circuit 19 via the input buffer V3. The response to the command CMD and the data DAT[3:0] transmitted from the card interface circuit 19 are transmitted to the host device via the output buffer V2.

[0080] When the comparator 13 detects application of the power supply voltage VDD2 or VDD3, the memory card SD2 communicates in a second mode conforming to the PCIe standard. At this time, the memory card SD2 can communicate data via rows R3 and R4, and communicate control signals via row R1. As control signals, the reference differential clock signal REFCLKp / n, the reset signal PERST, the power management control signal CLKREQ, and the wake-up signal PEWAKE are assigned in place of the command CMD and data DAT[3:0] of row R1. However, the implementation of the wake-up signal PEWAKE is not essential.

[0081] When serial reception differential signals RX0P, RX0N, RX1P, and RX1N are transmitted from the host device to the memory card SD2, they are converted into parallel data reception signals Rx by the receiver RE and transmitted to the card interface circuit 19. When parallel data transmission signals Tx are transmitted from the card interface circuit 19 to the transmitter TR, the transmission signals Tx are converted into serial transmission differential signals TX0P, TX0N, TX1P, and TX1N and transmitted to the host device.

[0082] Seventh embodiment FIG. 6 is a block diagram showing a schematic configuration of a host device in which a memory card according to the seventh embodiment is inserted.

[0083] 6, the host device includes a system controller 21 and a system memory 27. The system controller 21 includes a route complex 22, an SD host controller 23, a first row switch 24, a connector 25, and a memory controller 26. The memory controller 26 is connected to the system memory 27.

[0084] The root complex 22 can control access to the system memory by arbitrating multiple PCIe lanes. It can also arbitrate data transfer between the system memory and devices connected to the PCIe lanes. When the root complex 22 has multiple PCIe lanes, it can be connected to multiple PCIe devices (including memory cards) in a star-star configuration. Multiple lanes can also be assigned to one device. The SD host controller 23 can be used when controlling the memory card SD2 in a first mode compatible with the SD standard. The first row switch 24 can switch whether the row R1 is used for communication in the first mode compatible with the SD standard or for communication in the second mode compatible with the PCIe standard based on the selection signal R1SEL.

[0085] The connector 25 can make contact with the memory card SD2. At this time, the form factor of the connector 25 can be made to correspond to a microSD card. The connector 25 can be provided with a connector contact terminal group corresponding to the card terminal group of the memory card SD2 in order to make contact with the memory card SD2. The card terminal group of the memory card SD2 is the terminal group PA1 to PA4 in FIG. 2. The connector 25 also has a connector terminal group for connecting to a host controller. In the following description, in order to distinguish between the terminal group provided on the memory card and the terminal group provided on the connector, the terminal group provided on the memory card may be referred to as the card terminal group, and the terminal group provided on the connector may be referred to as the connector terminal group.

[0086] A power supply voltage VDD3 is applied to the connector 25, and when the power supply voltage VDD3 is not applied, a power supply voltage VDD2 is applied to the connector 25. The memory controller 26 can control the operation of the system memory 27.

[0087] The root complex 22 is provided with physical layer interfaces 22A, 22C, and 22E and IO cells 22B, 22D, and 22F. Each of the physical layer interfaces 22A, 22C, and 22E is a differential signal interface of the PCIe standard, and each of the IO cells 22B, 22D, and 22F is an interface for a single-ended signal and a differential reference clock of the PCIe standard.

[0088] The physical layer interface 22A and the IO cell 22B are connected to the SD host controller 23. At this time, the root complex 22 can communicate with the SD host controller 23 using a differential signal DS1 and a control signal CS1. The physical layer interface 22C is connected to a connector 25. The IO cell 22D is connected to a first row switch 24. The physical layer interface 22E and the IO cell 22F are connected to an M.2 slot. The M.2 supports the SATA (Serial Advanced Technology Attachment) and PCIe standards, and can connect various PCIe devices. The SD host controller 23 is connected to the connector 25 via the first row switch 24.

[0089] When communication in the first mode conforming to the SD standard is selected by the selection signal R1SEL, the row R1 of the memory card SD2 is switched to the SD host controller 23 side by the first row switch 24. Then, the SD bus signal BS output from the SD host controller 23 is assigned to the row R1, and communication is performed between the SD host controller 23 and the memory card SD2 in the first mode conforming to the SD standard. The SD bus signal BS can include a command CMD, a clock CLK, and data DAT[3:0].

[0090] When the selection signal R1SEL selects communication in the second mode corresponding to the PCIe standard, the row R1 of the memory card SD2 is switched to the IO cell 22D side by the first row switch 24. Then, the control signal CS2 is assigned to the row R1. This control signal CS2 may include the reference differential clock signal REFCLKp / n, the reset signal PERST, and the power management control signal CLKREQ. In addition, this control signal CS2 may further include a wake-up signal PEWAKE.

[0091] Furthermore, a differential signal DS2 is transmitted and received between the physical layer interface 22C and rows R3 and R4 of the memory card SD2. This differential signal DS2 can include receive differential signals RX0P, RX0N, RX1P, and RX1N and transmit differential signals TX0P, TX0N, TX1P, and TX1N. This allows communication between the root complex 22 and the memory card SD2 in a second mode compatible with the PCIe standard.

[0092] The selection signal R1SEL can be set depending on whether the power supply voltage VDD2 or VDD3 is applied. The state during initialization can be controlled by detecting the change point (from off to on, from on to off) of the power supply voltage VDD2 or VDD3. Alternatively, a register may be provided in the system controller 21 or the like, and the selection signal R1SEL may be set based on a value stored in the register. By setting the selection signal R1SEL based on a value stored in the register, it is possible to switch between communication in a first mode conforming to the SD standard and communication in a second mode conforming to the PCIe standard, regardless of whether the power supply voltage VDD3 is used.

[0093] In the embodiment of FIG. 6, a configuration is shown in which the connector 25 into which the memory card SD2 can be attached is mounted on the host device, but connectors into which the memory cards SD1, SD3 to SD5 can be attached may also be mounted on the host device. The form factor of the connector into which the memory cards SD1 and SD3 can be attached can be made to correspond to a microSD card. The form factor of the connector into which the memory card SD4 can be attached can include a form factor corresponding to a microSD card, and can be included in a form factor corresponding to a standard-sized SD card. The form factor of the connector into which the memory card SD5 can be attached can be made to correspond to a standard-sized SD card, and includes a form factor corresponding to a microSD card and the form factor of the card SD4.

[0094] Eighth embodiment FIG. 7 is a block diagram showing a schematic configuration of an interface card to which a memory card according to the eighth embodiment is attached.

[0095] In FIG. 7, an interface card 31 is provided with a bridge 32, an SD host controller 33, a first row switch 34, and a connector 35.

[0096] The bridge 32 can transition to communication in the second mode compatible with the PCIe standard by installing the interface card 31 in the PCIe slot or M.2 slot. The SD host controller 33, the first row switch 34, and the connector 35 can be configured in the same manner as the SD host controller 23, the first row switch 24, and the connector 25 in FIG.

[0097] The bridge 32 includes physical layer interfaces 32A and 32C and IO cells 32B and 32D. Each of the physical layer interfaces 32A and 32C can interface a differential signal of the PCIe standard. The IO cells 32B and 32D can interface a single-ended signal and a differential reference clock of the PCIe standard.

[0098] The physical layer interface 32A and the IO cell 32B are connected to the SD host controller 33. At this time, the bridge 32 can communicate with the SD host controller 33 using the differential signal DS1 and the control signal CS1. The physical layer interface 32C is connected to the connector 35. The IO cell 32D is connected to the first row switch 34.

[0099] When communication in the first mode compatible with the SD standard is selected by the selection signal R1SEL, the row R1 of the memory card SD2 is switched to the SD host controller 33 side by the first row switch 34. Then, the SD bus signal BS output from the SD host controller 33 is assigned to the row R1, and communication is performed between the SD host controller 33 and the memory card SD2 in the first mode compatible with the SD standard.

[0100] When communication in the second mode compatible with the PCIe standard is selected by the selection signal R1SEL, the row R1 of the memory card SD2 is switched to the IO cell 32D side by the first row switch 34. Then, a control signal CS2 is assigned to the row R1. Also, a differential signal DS2 is transmitted and received between the physical layer interface 32C and rows R3 and R4 of the memory card SD2. Then, communication in the second mode compatible with the PCIe standard is performed between the bridge 32 and the memory card SD2.

[0101] Ninth embodiment Fig. 8 is a flowchart showing the operation of the host device when setting the bus mode of the memory card according to the 9th embodiment. This method of setting the bus mode of the memory card can be used for any of the memory cards SD1 to SD5 in Figs. 1, 2, and 4A to 4C.

[0102] In FIG. 8, the host device supplies power supply voltages VDD1 and VDD3 to the memory card (S1). The power supply voltage VDD1 can be supplied to the power supply terminal VDD of row R1 of the memory card. As shown in FIG. 1, if the memory card has only rows R1 and R2, the power supply voltage VDD3 can be supplied to the power supply terminal VDD3 of row R2 of the memory card, or to the power supply terminal VDD2 if there is no power supply terminal VDD3. As shown in FIG. 2 or FIG. 4A to FIG. 4C, if the memory card has row R3, the power supply voltage VDD3 can be supplied to the power supply terminal VDD3 of row R3 of the memory card.

[0103] Although not shown, if the power supply voltage VDD3 is not supported, the power supply voltage VDD2 is supplied to the power supply terminal VDD2 instead.

[0104] At this time, the host device can detect whether a card is inserted by monitoring the rise time of the voltage at the terminals of rows R3 and R4 to which the transmit differential signals TX0P, TX0N, TX1P, and TX1N are assigned. The host device and the card are connected by an AC coupling capacitor, and a charging current flows to the capacitor only when a card is inserted. Therefore, when a memory card is inserted in the host device, the rise time is longer than when a memory card is not inserted in the host device. Therefore, it is possible to determine whether a memory card is inserted in the host device based on this rise time. When the host device is configured with multiple lanes, it is also possible to determine how many lanes are available for communication. Then, when a memory card is inserted in the host device, the host device can start communication with the memory card.

[0105] Next, the host device selects row R1 as the third bus mode (S2). The third bus mode is communication in the second mode compliant with the PCIe standard.

[0106] Next, the host device transmits a symbol to row R2, R3, or R4 that identifies whether the memory card supports the PCIe standard (S3).

[0107] If a response to the symbol in S3 is sent from the memory card within a specified time (Yes in S4), the host device executes a training sequence (S5). In this training sequence, the maximum operating frequency that both the memory card and the host device can support can be determined.

[0108] Next, the host device sets the communication method with the memory card to the third bus mode (S6).

[0109] On the other hand, if a response to the symbol in S3 is not sent from the memory card within the specified time (No in S4), the host device stops the supply of power supply voltage VDD3 (S7) and supplies power supply voltage VDD2 to the memory card (S8). The power supply voltage VDD2 can be supplied to the power supply terminal VDD2 of row R2 of the memory card.

[0110] Next, the host device selects row R1 as a control terminal for the UHS-II mode (S9). Specifically, a differential reference clock is assigned to the two terminals.

[0111] Next, the host device transmits a symbol to row R2 that identifies whether the memory card supports UHS-II (S10).

[0112] If a response to the symbol in S10 is sent from the memory card within a specified time (Yes in S11), the host device executes initialization in UHS-II mode (S12). In this initialization in UHS-II mode, the operating frequency with the maximum performance supported by both the memory card and the host device can be determined.

[0113] Next, the host device sets the communication method with the memory card to the second bus mode (S13). The second bus mode is communication according to UHS-II.

[0114] On the other hand, if a response to the symbol in S10 is not transmitted from the memory card within the specified time (No in S11), the host device stops the supply of the power supply voltage VDD2 (S14). Note that it is optional whether or not to stop the supply of the power supply voltage VDD2.

[0115] Next, the host device selects row R1 as a signal terminal for the first mode compatible with the SD standard (S15).

[0116] Next, the host device transmits a command to row R1 to execute initialization in the first mode compatible with the SD standard (S16).

[0117] If a response to the command in S16 is sent from the memory card within the specified time (Yes in S17), the host device executes initialization in the first mode that complies with the SD standard (S18). In this initialization in the first mode that complies with the SD standard, it is possible to determine the SD bus mode and operating frequency that provide the maximum performance supported by both the memory card and the host device.

[0118] Next, the host device sets the communication method with the memory card to the first bus mode (S19). The first bus mode is a first mode of communication that complies with the SD standard.

[0119] On the other hand, if a response to the command in S16 is not sent from the memory card within the specified time (No in S17), the host device determines that there is an error and stops the initialization in the first mode that complies with the SD standard (S20). S20 also includes the case where a card other than an SD card is connected.

[0120] For example, assume that the process of Fig. 8 is applied to the memory card SD1 of Fig. 1. At this time, a power supply voltage VDD3 is supplied to the power supply terminal VDD3 of row R2 of the memory card SD1 (S1). If the memory card SD1 supports the PCIe standard, when a symbol is transmitted to row R2 of the memory card SD1 (S3), there is a response from the memory card SD1 (Yes in S4). Therefore, the host device sets the communication method with the memory card SD1 to a second mode compatible with the PCIe standard (S6).

[0121] On the other hand, if the memory card SD1 supports UHS-II, when a symbol is transmitted to row R2 of memory card SD1 (S3), there is no response from memory card SD1 (No in S4). Therefore, the power supply voltage VDD3 of the power supply terminal VDD3 of row R2 of memory card SD1 is stopped (S7), and the power supply voltage VDD2 is supplied to the power supply terminal VDD2 of row R2 of memory card SD1 (S8). Then, when a symbol is transmitted to row R2 of memory card SD1 (S10), there is a response from memory card SD1 (Yes in S11). Therefore, the host device sets the communication method with memory card SD1 to UHS-II (S13).

[0122] On the other hand, if the memory card SD1 does not support UHS-II either, when a symbol is sent to row R2 of the memory card SD1 (S10), there is no response from the memory card SD1 (No in S11). Then, when a command is sent to row R1 of the memory card SD1 (S16), if there is a response from the memory card SD1, the host device sets the communication method with the memory card SD1 to the first mode compatible with the SD standard (S19).

[0123] As another example, assume that the process of Fig. 8 is applied to the memory card SD3 of Fig. 4A. At this time, a power supply voltage VDD3 is supplied to the power supply terminal VDD3 of row R3 of memory card SD3 (S1). Since memory card SD3 supports the PCIe standard, when a symbol is transmitted to row R3 of memory card SD3 (S3), there is a response from memory card SD3 (Yes in S4). Therefore, the host device sets the communication method with memory card SD1 to a second mode compatible with the PCIe standard (S6).

[0124] On the other hand, when the memory card SD3 is operated in the first mode corresponding to the SD standard, the power supply voltage VDD3 is not supplied to the power supply terminal VDD3 of row R3 of the memory card SD3 in S1. At this time, when a symbol is transmitted to row R3 of the memory card SD3 (S3), there is no response from the memory card SD3 (No in S4). Also, since the memory card SD3 does not have row R2, there is no response from the memory card SD3 when a symbol is transmitted to row R2 of the memory card SD3 (S10) (No in S11). Since the memory card SD3 supports the SD standard, there is a response from the memory card SD3 when a command is transmitted to row R1 of the memory card SD3 (S16) (Yes in S17). Therefore, the host device sets the communication method with the memory card SD3 to the first mode corresponding to the SD standard (S19).

[0125] Tenth embodiment FIG. 9 is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission path connected to a memory card according to the tenth embodiment.

[0126] 9, the host device is provided with a system board 81 and a system controller 83. The system board 81 is provided with a connector 82 and a physical layer interface 84. The physical layer interface 84 is provided with a receiver RE1 and a transmitter TR1. The receiver RE1 can input transmission differential signals TX0P, TX0N transmitted from row R2 of the memory card SD1. The transmitter TR1 can output reception differential signals RX0P, RX0N received in row R2 of the memory card SD1.

[0127] The transmitter TR1 and the connector 82 are connected via a differential transmission line TP1. At this time, the differential transmission line TP1 can connect the transmitter TR1 and the connector 82 via AC coupling capacitors C1 and C2. A switch WT is connected to the AC coupling capacitors C1 and C2. The switch WT can short-circuit the AC coupling capacitors C1 and C2. Implementation of the switch WT can be optional.

[0128] The receiver RE1 and the connector 82 are connected via a differential transmission line TP2. At this time, the differential transmission line TP2 can connect the receiver RE1 and the connector 82 via AC coupling capacitors C3 and C4. A switch WR is connected to the AC coupling capacitors C3 and C4. The switch WR can short-circuit the AC coupling capacitors C3 and C4. The implementation of the switch WR can be optional.

[0129] The memory card SD1 is provided with a physical layer interface 85. The physical layer interface 85 can support only either the UHS-II standard or the PCIe standard. The physical layer interface 85 is provided with a receiver RE2 and a transmitter TR2. The receiver RE2 can input reception differential signals RX0P, RX0N received at row R2 of the memory card SD1. The transmitter TR2 can output transmission differential signals TX0P, TX0N transmitted from row R2 of the memory card SD1.

[0130] The receiver RE2 is connected to the differential transmission path TP3. The transmitter TR2 is connected to the differential transmission path TP4. By mounting the memory card SD1 to the connector 82, the differential transmission paths TP1 and TP3 can be connected to each other, and the differential transmission paths TP2 and TP4 can be connected to each other.

[0131] If the memory card SD1 supports the UHS-II standard, the system controller 83 can turn on the switches WT and WR to short-circuit the AC coupling capacitors C1 to C4.

[0132] On the other hand, if the memory card SD1 supports the PCIe standard, the system controller 83 can turn off the switches WT and WR to DC-isolate the physical layer interfaces 84 and 85.

[0133] This allows the memory card SD1 to be compatible with both the case where it supports the UHS-II standard and the case where it supports the PCIe standard without having to replace the system board 81 depending on whether the memory card SD1 supports the UHS-II standard or the PCIe standard.

[0134] In the second mode compatible with the PCIe standard, by connecting the physical layer interfaces 84, 85 via AC coupling capacitors C1 to C4, DC separation can be achieved between the transmitting side and the receiving side of the differential signal, and the common voltage levels of the physical layer interfaces 84, 85 can be designed independently for the transmitting side and the receiving side (not influenced by each other). On the other hand, in the case of DC coupling without AC coupling capacitors, fluctuations in the ground level affect the signal voltages of both sides, so a design that suppresses fluctuations in the ground level is required.

[0135] In addition, the AC coupling capacitor needs to have a capacitance of about 200 nF, and its size makes it difficult to mount it in the microSD form factor. Therefore, by providing the AC coupling capacitors C1 to C4 on the system board 81, it becomes unnecessary to provide the AC coupling capacitors C3 and C4 on the memory card SD1, and it becomes possible to easily manufacture the thin memory card SD1.

[0136] Eleventh embodiment FIG. 10A is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to an eleventh embodiment.

[0137] 10A, the host device is provided with a system board 81'. The system board 81' is provided with a connector 82 and a physical layer interface 84. The physical layer interface 84 is provided with a receiver RE1 and a transmitter TR1.

[0138] The transmitter TR1 and a differential transmission line TP1 from the connector 82 are connected via AC coupling capacitors C1 and C2.

[0139] The receiver RE1 and the connector 82 are connected via a differential transmission line TP2. At this time, the differential transmission line TP2 can directly connect the receiver RE1 and the connector 82.

[0140] The memory card SD5 is provided with a physical layer interface 85'. The physical layer interface 85' can support the PCIe standard. The physical layer interface 85' is provided with a receiver RE2' and a transmitter TR2'. The receiver RE2' can input reception differential signals RX0P, RX0N received in row R3 of the memory card SD5. The transmitter TR2' can output transmission differential signals TX0P, TX0N transmitted from row R3 of the memory card SD5.

[0141] The receiver RE2' is connected to the differential transmission path TP3. The transmitter TR2' and the differential transmission path TP4 are connected via AC coupling capacitors C3 and C4. This is a common mounting method for PCIe devices.

[0142] However, the capacitance range of the AC coupling capacitor is limited, and it is too large to be implemented in the microSD form factor, which means that the configuration of Figure 10A is not suitable for application to small removable cards with a thin form factor.

[0143] Twelfth embodiment FIG. 10B is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission path connected to a memory card according to the twelfth embodiment.

[0144] In FIG. 10B, the host device is provided with a system board 81". The system board 81" is provided with a connector 82' and a physical layer interface 84. The physical layer interface 84 is provided with a receiver RE1 and a transmitter TR1. The connector 82' is provided with AC coupling capacitors C3 and C4. The AC coupling capacitors C3 and C4 can be electrically inserted between a connector terminal of the connector 82' to which the memory card SD1 side can be connected and a connection terminal connected to the physical layer interface 84 of the host device.

[0145] The transmitter TR1 and the differential transmission path TP1 from the connector 82' are connected via AC coupling capacitors C1 and C2. The AC coupling capacitors C1 and C2 may be disposed inside the connector 82', and in that case, there is no need to secure an area on the PCB for disposing C1 and C2.

[0146] The receiver RE1 and the connector 82' are connected via a differential transmission path TP2. At this time, the differential transmission path TP2 can directly connect the receiver RE1 and the connector 82'. The differential transmission path TP2 on the host device side and the differential transmission path TP4 on the card side are connected via AC coupling capacitors C3 and C4 in the connector 82'.

[0147] 10B shows a case where AC coupling capacitors C3 and C4 are arranged inside the connector, but instead of arranging the AC coupling capacitors C3 and C4 inside the connector, they may be inserted between the receiver RE1 and the differential transmission path TP2 from the connector 82'. In this case, it is necessary to secure an area on the PCB (Printed Circuit Board) for arranging the AC coupling capacitors C3 and C4.

[0148] By attaching the memory card SD1 to the connector 82', the differential transmission path (differential transmission path on the transmitting side of the host device) TP1 and the differential transmission path (differential transmission path on the receiving side of the memory card SD1) TP3 can be connected to each other, and the differential transmission path (differential transmission path on the receiving side of the host device) TP2 and the differential transmission path (differential transmission path on the transmitting side of the memory card SD1) TP4 can be connected to each other via AC coupling capacitors C3 and C4.

[0149] Here, by providing the AC coupling capacitors C3 and C4 in the connector 82', it becomes unnecessary to provide the AC coupling capacitors C3 and C4 in the memory card SD1, and it becomes possible to support a small removable card with a thin form factor such as a microSD memory card. Naturally, it can also be applied to larger form factors.

[0150] Thirteenth embodiment Fig. 11A is a perspective view showing an example of a schematic configuration of a connector used in a memory card according to a thirteenth embodiment, and Fig. 11B is a cross-sectional view showing an example of a schematic configuration of a connector used in a memory card according to a thirteenth embodiment. Note that Fig. 11B shows two pogo pins as in Fig. 11A.

[0151] 11A, this connector can be used to make contact with terminal groups PA3-PC3 and PA4-PC4 of rows R3 and R4 of memory cards SD2-SD5. This connector is provided with pogo pins 40. The pogo pins 40 can be arranged in accordance with the arrangement of terminals in rows R3 and R4.

[0152] 11B, the pogo pin 40 is provided with a pin 44. The pin 44 is housed in a cylinder 43. Inside the cylinder 43, a spring 45 is provided at the bottom of the pin 44, and the pin 44 is supported in a state in which it can move up and down via the spring 45. The pogo pin 40 is supported by a housing 42 in an upright state. The housing 42 can be installed on a base 41.

[0153] For example, when making contact with row R3 of memory card SD2, each terminal of terminal group PA3 of memory card SD2 is pressed against the tip of pin 44. At this time, pin 44 is pressed down, and is pushed upward by spring 45. This allows pin 44 to be firmly crimped to the terminal, improving impact resistance. As a result, even when memory card SD2 is used in an environment where it is subject to severe vibrations and impacts, such as in an automobile or drone, it is possible to prevent the operation of memory card SD2 from becoming unstable.

[0154] Fourteenth embodiment Figure 12A is a cross-sectional view showing an example of the schematic configuration of a connector before a memory card is inserted in the 14th embodiment, Figure 12B is a plan view showing an example of the schematic configuration of a connector before a memory card is inserted in the 14th embodiment, Figure 12C is a cross-sectional view showing an example of the schematic configuration of a connector after a memory card is inserted in the 14th embodiment, and Figure 12D is a plan view showing an example of the schematic configuration of a connector after a memory card is inserted in the 14th embodiment.

[0155] 12B and 12D show a state where the cover of the connector is removed. In addition, in this embodiment, a connector that makes contact with the memory card SD4 in FIG. 4B is taken as an example.

[0156] 12A and 12B, connector CN1 is provided with a base 51 and a cover 52. An end of base 51 and an end of cover 52 are connected via pin 53. At this time, cover 52 can be opened and closed by rotating cover 52 about pin 53 as a rotation axis.

[0157] A recess 54 is provided in the center of the base 51 so as to cross the base in the horizontal direction. A heat dissipation sheet 55 is provided in the recess 54. The heat dissipation sheet 55 can be made of a flexible material with high thermal conductivity. The material of the heat dissipation sheet 55 can be, for example, an acrylic resin. In this case, the dimensions of the heat dissipation sheet 55 can be set so that the sheet is pulled out laterally from the base 51. The heat dissipation sheet 55 pulled out laterally from the base 51 can be brought into contact with the installation surface of the connector CN1. The installation surface of the connector CN1 is, for example, the housing of the host device.

[0158] The base 51 has a connector row R1 terminal group 58 and a connector row R3 / R4 terminal group 59 for connection with the host side, a connector row R1 contact group and a connector row R3 / R4 contact group for connection with the card side while protruding above the surface of the base 51, and has lead pins 56 and pogo pins 57 embedded therein. The lead pins 56 can be arranged in correspondence with the terminal arrangement of row R1 of the memory card SD4. The pogo pins 57 can be arranged in correspondence with the terminal arrangement of rows R3 and R4 of the memory card SD4. The connector row R1 contact group of the lead pins 56 is wired to the connector row R1 terminal group 58 and can be connected to a host device. The connector row R3 / R4 contact group of the pogo pins 57 is wired to the connector row R3 / R4 terminal group 59 and can be connected to a host device.

[0159] When the memory card SD4 is inserted into the connector CN1, the memory card SD4 is placed on the base 51 with the cover 52 open. Then, the cover 52 is closed to fix the memory card SD4 to the connector CN1.

[0160] 12C and 12D, the terminal group PB1 of row R1 of the memory card SD4 can be pressed onto the lead pin 56, and the terminal groups PB3, PB4 of rows R3, R4 of the memory card SD4 can be pressed onto the pogo pin 57. In addition, the empty spaces between the row R1 and the rows R3, R4 on the card surface of the memory card SD4 can be pressed onto the heat dissipation sheet 55.

[0161] Here, by using the pogo pins 57 to make contact with the terminal groups PB3, PB4 of rows R3, R4 of the memory card SD4, it is possible to reduce lateral deviation when the terminal groups PB3, PB4 make contact with the pogo pins 57. Therefore, it is possible to reliably make contact between the terminal groups PB3, PB4 and the pogo pins 57 while also dealing with the miniaturization of each terminal of the terminal groups PB3, PB4.

[0162] Furthermore, by providing the connector CN1 with the heat dissipation sheet 55, the heat generated in the memory card SD4 can be efficiently dissipated to the host device via the heat dissipation sheet 55, thereby improving the heat dissipation performance of the memory card SD4.

[0163] In the above embodiment, the method of installing the heat dissipation sheet 55 in the recess 54 of the base 51 has been described, but a Peltier element may be installed in the recess 54 of the base 51 instead of the heat dissipation sheet 55. By using a Peltier element, it becomes possible to forcibly cool the memory card SD4.

[0164] Fifteenth embodiment Figure 13A is a cross-sectional view showing an example of the general configuration of an adapter before a memory card in the 15th embodiment is installed, Figure 13B is a plan view showing an example of the general configuration of an adapter before a memory card in the 15th embodiment is installed, Figure 13C is a cross-sectional view showing an example of the general configuration of an adapter after a memory card in the 15th embodiment is installed, and Figure 13D is a plan view showing an example of the general configuration of an adapter after a memory card in the 15th embodiment is installed.

[0165] In this embodiment, an adapter that converts the form factor of the memory card SD1 in FIG. 1 into the form factor of the memory card SD4 in FIG. 4B is shown.

[0166] 13A and 13B, an adapter AP1 is provided with an insertion portion IE1 into which a memory card SD1 is inserted. An entrance to the insertion portion IE1 can be provided at the rear end of the adapter AP1.

[0167] The surface of the adapter AP1 is provided with a terminal group DA1, which is a group of adapter row R1 terminals to be connected to the connector, and terminal groups DA3 and DA4, which are a group of adapter row R3 / R4 terminals. The terminals of the terminal groups DA1, DA3, and DA4 can be arranged to correspond to the terminal arrangements of rows R1, R3, and R4 of the memory card SD4, respectively.

[0168] The inner surface of the insertion part IE1 of the adapter AP1 is provided with lead pins IA1, which are a group of adapter row R1 contacts that connect to the memory card, and lead pins IA2, which are a group of adapter row R2 contacts. The lead pins IA1 can be arranged in correspondence with the terminal arrangement of row R1 of the memory card SD1. The lead pins IA2 can be arranged in correspondence with the terminal positions of the terminals to which the transmit differential signals TX0P, TX0N, the receive differential signals RX0P, RX0N, and the power supply VDD are assigned in row R2 of the memory card SD1.

[0169] The adapter row R1 contact group of lead pin IA1 is wired to the adapter row R1 terminal group of terminal group DA1, and can be connected to a connector. The adapter row R2 contact group of lead pin IA2 is wired to the connector row R4 terminal group of terminal group DA4 (or the connector row R3 terminal group of terminal group DA3), and can be connected to a connector. Figure 5 shows an example of connection to row R4. The wiring between the power supply terminal VDD3 and the data line is shown with dashed lines, but the wiring to the GND terminal has been omitted for ease of viewing.

[0170] The terminal groups DA1, DA3, and DA4 can be used as adapter terminal groups of the adapter AP1. The lead pins IA1 and IA2 can be used as adapter contact groups of the adapter AP1. The adapter terminal groups can come into contact with the connector contact groups when the adapter AP1 is attached to a connector. The adapter contact groups can come into contact with the card terminal groups when the memory card SD1 is inserted into the adapter AP1.

[0171] Lead pin IA1 is connected one-to-one to each terminal in terminal group DA1 via wiring HA1. Lead pin IA2 is connected one-to-one to each terminal in terminal group DA4 (or DA3) via wiring HA2. The host device can recognize whether the card is connected to terminal group DA3 or terminal group DA4 during the initialization sequence, so it does not matter which one you connect to. Connecting to terminal group DA4 results in shorter wiring, so this example is shown in the figure.

[0172] When the memory card SD1 is attached to the adapter AP1, the memory card SD1 is inserted into the insertion portion IE1 from the rear end of the adapter AP1.

[0173] At this time, as shown in Figures 13C and 13D, each terminal of the terminal group PA1 in row R1 of the memory card SD1 can be brought into contact with the lead pin IA1, and each terminal of the terminal group PA2 in row R2 of the memory card SD1 can be brought into contact with the lead pin IA2. This makes it possible to convert the form factor of the memory card SD1 into the form factor of the memory card SD4.

[0174] Sixteenth embodiment Figure 14A is a cross-sectional view showing an example of the general configuration of an adapter before a memory card in accordance with the 16th embodiment is installed, Figure 14B is a plan view showing an example of the general configuration of an adapter before a memory card in accordance with the 16th embodiment is installed, Figure 14C is a cross-sectional view showing an example of the general configuration of an adapter after a memory card in accordance with the 16th embodiment is installed, and Figure 14D is a plan view showing an example of the general configuration of an adapter after a memory card in accordance with the 16th embodiment is installed.

[0175] In this embodiment, an adapter that converts the form factor of the memory card SD3 in FIG. 4A into the form factor of the memory card SD4 in FIG. 4B is shown.

[0176] 14A and 14B, the adapter AP3 is provided with an insertion portion IE2 into which a memory card SD3 is inserted. An entrance to the insertion portion IE2 can be provided at the rear end of the adapter AP3. The insertion portion IE2 is provided with a notch IK2 that exposes the terminal groups PA3, PA4 of rows R3, R4 of the memory card SD3 on the surface of the adapter AP3 when the memory card SD3 is inserted into the insertion portion IE2.

[0177] The position of the insertion portion IE2 can be set so that when the memory card SD3 is inserted into the insertion portion IE2, the positions of each terminal of the terminal groups PA3, PA4 of rows R3, R4 of the memory card SD3 correspond to the positions of each terminal of the terminal groups PB3, PB4 of rows R3, R4 of the memory card SD4.

[0178] A terminal group DA1 is provided on the surface of the adapter AP3. The terminals of the terminal group DA1 can be arranged to correspond to the terminal arrangement of row R1 of the memory card SD4.

[0179] Lead pins IA1 are provided on the inner surface of the insertion part IE2 of the adapter AP3. The lead pins IA1 can be arranged in accordance with the terminal arrangement of row R1 of the memory card SD3. The lead pins IA1 are connected in a one-to-one relationship to the respective terminals of the terminal group DA1 via wiring HA1.

[0180] When the memory card SD3 is attached to the adapter AP3, the memory card SD3 is inserted into the insertion portion IE2 from the rear end of the adapter AP3.

[0181] At this time, as shown in Figures 14C and 14D, each terminal of the terminal group PA1 in row R1 of the memory card SD3 can be brought into contact with the lead pin IA1. Furthermore, when each terminal of the terminal group PA1 in row R1 of the memory card SD3 is brought into contact with the lead pin IA1, the arrangement of the terminal group DA1 of the adapter AP3 and the terminal groups PA3 and PA4 of the memory card SD3 can be made to match the arrangement of the terminal groups PB1, PB3 and PB4 of the memory card SD4. This makes it possible to convert the form factor of the memory card SD3 into the form factor of the memory card SD4.

[0182] Here, when the memory card SD3 is inserted into the adapter AP3, the terminals PA3, PA4 of the memory card SD3 are exposed on the surface of the adapter AP3, so that they can be in contact with the terminals PA3, PA4 of the memory card SD3 without the need for the terminals of the adapter AP3. Therefore, even if the form factor of the memory card SD3 is converted to the form factor of the memory card SD4, it is no longer necessary to bring the terminals PA3, PA4 of the memory card SD3 into contact with the terminals of the adapter AP3. As a result, when the memory card SD3 is inserted into the adapter AP3, deterioration of the electrical characteristics of the terminals PA3, PA4 of the memory card SD3 can be prevented.

[0183] Seventeenth embodiment Figure 15A is a cross-sectional view showing an example of the general configuration of an adapter before a memory card in accordance with the 17th embodiment is installed, Figure 15B is a plan view showing an example of the general configuration of an adapter before a memory card in accordance with the 17th embodiment is installed, Figure 15C is a cross-sectional view showing an example of the general configuration of an adapter after a memory card in accordance with the 17th embodiment is installed, and Figure 15D is a plan view showing an example of the general configuration of an adapter after a memory card in accordance with the 17th embodiment is installed.

[0184] In this embodiment, an adapter that converts the form factor of the memory card SD4 in FIG. 4B into the form factor of the memory card SD5 in FIG. 4C is shown.

[0185] 15A and 15B, the adapter AP4 is provided with an insertion portion IE3 into which a memory card SD4 is inserted. An entrance to the insertion portion IE3 can be provided on the surface of the adapter AP4. The entrance to the insertion portion IE3 can expose terminal groups PB3 and PB4 of rows R3 and R4 of the memory card SD4 on the surface of the adapter AP4 when the memory card SD4 is inserted into the insertion portion IE3.

[0186] The position of the insertion portion IE3 can be set so that when the memory card SD4 is inserted into the insertion portion IE3, the positions of each terminal of the terminal groups PB3, PB4 in rows R3, R4 of the memory card SD4 correspond to the positions of each terminal of the terminal groups PC3, PC4 in rows R3, R4 of the memory card SD5.

[0187] A terminal group DB1 is provided on the surface of the adapter AP4. The terminals of the terminal group DB1 can be arranged to correspond to the terminal arrangement of row R1 of the memory card SD5.

[0188] Lead pins IB1 are provided on the inner surface of the insertion part IE3 of the adapter AP4. The lead pins IB1 can be arranged in accordance with the terminal arrangement of row R1 of the memory card SD4. The lead pins IB1 are connected one-to-one to the terminals of the terminal group DB1 via wiring HB1.

[0189] When the memory card SD4 is attached to the adapter AP4, the memory card SD4 is inserted into the insertion portion IE3 from the front side of the adapter AP4.

[0190] At this time, as shown in Figures 15C and 15D, each terminal of the terminal group PB1 of row R1 of memory card SD4 can be brought into contact with the lead pin IB1. Also, when each terminal of the terminal group PB1 of row R1 of memory card SD4 is brought into contact with the lead pin IB1, the arrangement of the terminal group DB1 of adapter AP4 and the terminal groups PB3 and PB4 of memory card SD4 can be made to match the arrangement of the terminal groups PC1, PC3, and PC4 of memory card SD5. This makes it possible to convert the form factor of memory card SD4 into the form factor of memory card SD5.

[0191] Here, when the memory card SD4 is inserted into the adapter AP4, the terminals PB3 and PB4 of the memory card SD4 are exposed on the surface of the adapter AP4, so that they can be in contact with the terminals PB3 and PB4 of the memory card SD4 without the need for the terminals of the adapter AP4. Therefore, even if the form factor of the memory card SD4 is converted to the form factor of the memory card SD5, it is no longer necessary to bring the terminals PB3 and PB4 of the memory card SD4 into contact with the terminals of the adapter AP4. As a result, when the memory card SD4 is inserted into the adapter AP4, deterioration of the electrical characteristics of the terminals PB3 and PB4 of the memory card SD4 can be prevented.

[0192] (18th embodiment) Fig. 16A is a perspective view showing a schematic configuration of a memory card according to an eighteenth embodiment, which is a modified example of the memory card SD4 in Fig. 4B.

[0193] 16A, this memory card SD4' has a terminal group PB1' instead of the terminal group PB1 of the memory card SD4. The terminals of the terminal group PB1' are arranged from the front surface to the front end face of the memory card SD4'. This allows contact to be made from the tip of the memory card SD4' to the terminals of row R1 of the memory card SD4'.

[0194] Nineteenth embodiment Fig. 16B is a cross-sectional view showing an example of a schematic configuration of the adapter before a memory card is inserted according to the nineteenth embodiment. Fig. 16B shows a modified example of the adapter AP4 in Figs. 15A to 15D.

[0195] 16B, an adapter AP4' is provided with an insertion part IE3', a pogo pin 62, and a wire HB2 instead of the insertion part IE3, lead pin IB1, and wire HB1 of the adapter AP4. The pogo pin 62 is embedded in the side surface of the tip of the insertion part IE3'. The pogo pin 62 is connected one-to-one to each terminal of the terminal group DB1 via the wire HB2.

[0196] When the memory card SD4' is attached to the adapter AP4', the memory card SD4' is inserted into the insertion portion IE3' from the front side of the adapter AP4'. At this time, the tip of each terminal of the terminal group PB1' of row R1 of the memory card SD4' is pressed against the pogo pin 62 to obtain a stable contact.

[0197] 15C, when the memory card SD4 is attached to the adapter AP4, a step occurs between the terminal group DB1 of the adapter AP4 and the terminal groups PB3 and PB4 of the memory card SD4. When making contact with these terminal groups DB1, PB3, and PB4, the step needs to be absorbed by the connector.

[0198] On the other hand, when the memory card SD4' is attached to the adapter AP4', the step between the terminal group DB1 of the adapter AP4' and the terminal group PB3, PB4 of the memory card SD4' can be almost completely eliminated. Therefore, it is not necessary to absorb the step with a connector that makes contact with the terminal groups DB1, PB3, PB4, and it is possible to prevent the connector structure from becoming complicated.

[0199] (Twentieth embodiment) Fig. 16C is a perspective view showing a schematic configuration of a memory card according to a twentieth embodiment, and Fig. 16D is a cross-sectional view showing a state of an adapter after the memory card of Fig. 16C is inserted. Fig. 16C shows a modified example of the memory card SD4 of Fig. 4B.

[0200] 16C, a step 61 is provided at the leading end of the memory card SD4". ​​In this case, the terminal group PB1 can be disposed at a position lower by the height of the step 61.

[0201] When the memory card SD4" is attached to the adapter AP4, the memory card SD4" is inserted into the insertion portion IE3 from the front side of the adapter AP4. At this time, each terminal of the terminal group PB1 of row R1 of the memory card SD4" can be brought into contact with the lead pin IB1.

[0202] Here, as shown in FIG. 15C, when the memory card SD4 is attached to the adapter AP4, a step occurs between the terminal group DB1 of the adapter AP4 and the terminal group PB3, PB4 of the memory card SD4.

[0203] On the other hand, when the memory card SD4" is attached to the adapter AP4, the step between the terminal group DB1 of the adapter AP4 and the terminal group PB3, PB4 of the memory card SD4" can be almost completely eliminated. This eliminates the need to absorb the step with a connector that makes contact with the terminal groups DB1, PB3, PB4, and prevents the connector structure from becoming complicated.

[0204] (21st embodiment) Fig. 17 is a plan view showing an example of a schematic configuration of an adapter according to the twenty-first embodiment after a memory card is inserted therein. Fig. 17 shows a modified example of the adapter AP1 shown in Figs. 13A to 13D.

[0205] In Fig. 17, the adapter AP1' is provided with a semiconductor chip 71. The mounting position of the semiconductor chip 71 is arbitrary other than the location shown in the figure, and the semiconductor chip 71 can be embedded in an empty space of the adapter AP1'. The semiconductor chip 71 is connected to the lead pin IA2 in Figs. 13A and 13B.

[0206] The semiconductor chip 71 can be provided with functions such as a wireless module, a close-proximity wireless module, a secure module, and a sensor for smells, illuminance, and the like.

[0207] The wireless module can be compatible with standards such as 11a, 11b, 11g, 11n, 11ad, WiGig, etc. The proximity wireless module can be compatible with standards such as NFC, Zwave, ZigBee, Transfer Jet, etc. The secure module can be compatible with standards such as TEE (Trusted Execution Environment), TCG (Trusted Computing Group), OPAL, etc.

[0208] When the memory card SD2 is attached to the adapter AP1', the host device is connected via rows R3 and R4 of the memory card SD2, and the semiconductor chip 71 can connect to the memory card using the terminal group of row R2 of the memory card SD2. As a result, by attaching the adapter AP1' with the memory card SD2 attached to the host device, the host device can be provided with functions such as a wireless module, a secure module, or a sensor.

[0209] (Twenty-second embodiment) Fig. 18 is a plan view showing a schematic configuration of a memory card according to a 22nd embodiment of the present invention, which is a modified example of the memory card SD4 shown in Fig. 4B.

[0210] In FIG. 18, in the memory card SD6, the terminal group PB1 in row R1 of the memory card SD4 is removed. Rows R3 and R4 are provided in the position of row R1 of the memory card SD4. In rows R3 and R4 of the memory card SD6, terminal groups PB3' and PB4' are added to the differential signal terminal groups PB3 and PB4 of the memory card SD4, respectively, as replacements for the control signal terminals that used row R1. The terminal groups PB3' and PB4' may have different shapes and numbers of terminals, but compatibility can be maintained by inheriting the functions of row R1. In other words, the memory card SD6 can be converted into the memory card SD5 by using an adapter.

[0211] The memory card SD6 can have a second mode communication function compatible with the PCIe standard. At this time, the terminal groups PB3' and PB4' are assigned with control signals used to control communication in the second mode compatible with the PCIe standard. The control signals can be the reference differential clock signals REFCLKp / n, the reset signal PERST, and the power management control signal CLKREQ. The control signal can also be the wake-up signal PEWAKE.

[0212] Here, by removing the terminal group PB1 in row R1 of the memory card SD4 and providing the terminal groups PB3, PB3', PB4, PB4' in rows R3 and R4 of the memory card SD6, it is possible to increase the free space on the card surface of the memory card SD6 while providing the memory card SD6 with a second mode communication function compatible with the PCIe standard. This makes it possible to easily increase the number of rows of the memory card SD6 and easily increase the number of lanes of the PCIe standard, thereby easily improving the data transfer speed of the memory card SD6.

[0213] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0214] SD1 to SD5 memory cards, PA1 to PA4 terminal group, R1 to R4 rows, 11, 12 regulator, 13 comparator, 14 card controller, 15 memory interface circuit, 16 memory, 17 IO cell, 18 physical layer, 19 card interface circuit

Claims

1. a first terminal group arranged in a first row and including a first power supply terminal and a first ground terminal; a second terminal group including a plurality of differential data terminals for communicating differential data signals and a plurality of ground terminals, the second terminal group being arranged in a second row extending parallel to the first row; Equipped with the plurality of differential data terminals include a pair of differential data terminals arranged adjacent to each other, the pair of differential data terminals are disposed between the plurality of ground terminals, In a first mode of communication conforming to the SD standard, a single-ended signal conforming to the SD standard is received using a terminal included in the first terminal group; In communication in a second mode conforming to the PCIe standard, a terminal included in the first terminal group is used to receive a differential clock signal and a reset signal conforming to the PCIe standard, and a terminal included in the second terminal group is used to receive a differential data signal conforming to the PCIe standard. A memory card; a host device capable of supplying a first power source to the first power source terminal of the memory card; A system comprising:

2. the first terminal group includes a first terminal, a plurality of second terminals, and a third terminal; In the first mode of communication, the memory card receives a data signal corresponding to the SD standard using the second terminals included in the first terminal group, and receives a clock signal corresponding to the SD standard using the third terminal included in the first terminal group; In the communication in the second mode, the memory card receives a differential clock signal and a reset signal corresponding to the PCIe standard using the first terminal and the plurality of second terminals included in the first terminal group, and receives a differential data signal corresponding to the PCIe standard using the plurality of differential data terminals included in the second terminal group. The system of claim 1 .

3. the second terminal group of the memory card further includes a second power supply terminal; when a power supply voltage is not applied to the second power supply terminal, the memory card performs communication in the first mode; When a power supply voltage is applied to the second power supply terminal, the memory card performs communication in the second mode. The system of claim 1 .

4. The host device is capable of supplying a second power supply voltage lower than the first power supply voltage to the second power supply terminal of the memory card. The system of claim 3.

5. The pair of differential data terminals of the memory card are a pair of differential data terminals for transmitting differential data signals; a pair of differential data terminals for receiving differential data signals; Including, the plurality of ground terminals of the memory card include a second ground terminal, a third ground terminal, and a fourth ground terminal; the pair of differential data terminals for transmitting of the memory card are disposed between the second ground terminal and the third ground terminal; the pair of differential data receiving terminals of the memory card are disposed between the third ground terminal and the fourth ground terminal; The third ground terminal of the memory card is adjacent to the pair of differential data terminals for transmitting and the pair of differential data terminals for receiving on both sides. The system of claim 1 .

6. The memory card includes: A NAND flash memory; A memory interface circuit; a card interface circuit connected to the NAND flash memory via the memory interface circuit; Further equipped The system of claim 1 .

7. The thickness of the memory card is in the range of 1.4 mm to 1.6 mm. The system of claim 1 .

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