Nitride semiconductor light-emitting element

Abstract

To provide a nitride semiconductor light-emitting element capable of extending the service life.SOLUTION: A nitride semiconductor light-emitting element 1 includes: an n-type semiconductor layer 4; an active layer 6 being formed on the n-type semiconductor layer 4 and emitting ultraviolet light; an electron blocking layer 7 formed on the active layer 6; and a p-type semiconductor layer 8 formed on the electron blocking layer 7. Multiple pits 10 are formed at least in the active layer 6. A ratio of a second density D2 to a first density D1, i.e., the ratio R=D2 / D1, is less than 30%, where the first density D1 is a density of the pits 10 on an upper surface 60 of the active layer 6, and the second density D2 is a density of the pits 10 on an upper surface 70 of the electron blocking layer 7.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a nitride semiconductor light emitting device. [Background technology]

[0002] Patent Document 1 discloses a nitride semiconductor light-emitting device in which a V pit, which is a type of crystal defect, is formed in the light-emitting layer. Patent Document 1 describes that the formation of the V pit in the light-emitting layer suppresses the occurrence of non-radiative recombination, thereby improving the light-emitting efficiency. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-050247 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the nitride semiconductor light emitting device described in Patent Document 1 has room for improvement in terms of suppressing the decrease in light emission output over time and extending the life span.

[0005] The present invention has been made in view of the above circumstances, and has an object to provide a nitride semiconductor light-emitting device that can achieve a long life. [Means for solving the problem]

[0006] In order to achieve the above-mentioned object, the present invention provides a nitride semiconductor light-emitting element comprising: an n-type semiconductor layer, an active layer formed on the n-type semiconductor layer and emitting ultraviolet light, an electron blocking layer formed on the active layer, and a p-type semiconductor layer formed on the electron blocking layer, wherein a plurality of pits are formed in at least the active layer, and when a density of the pits on an upper surface of the active layer is a first density D1 and a density of the pits on an upper surface of the electron blocking layer is a second density D2, a ratio R=D2 / D1 of the second density D2 to the first density D1 is less than 30%. Effect of the Invention

[0007] According to the present invention, it is possible to provide a nitride semiconductor light emitting device that can achieve a longer life. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic diagram illustrating a configuration of a nitride semiconductor light emitting device according to an embodiment. [Diagram 2] 2 is a schematic diagram showing an example of a pit formed in the nitride semiconductor light emitting element in the embodiment. FIG. [Diagram 3] 4 is a graph showing silicon concentration distribution and magnesium concentration distribution for each of the nitride semiconductor light emitting devices of the example and the comparative example. [Figure 4] 1 shows examples of AFM images of the upper surface of an active layer in an example and a comparative example. [Diagram 5] 1 is an example of an AFM image of the upper surface of an electron blocking layer in an embodiment. [Figure 6] 13 is an example of an AFM image of the upper surface of an electron blocking layer in a comparative example. [Figure 7] FIG. 11 is a schematic diagram showing an example of a pit formed in a nitride semiconductor light emitting device in a comparative example. [Figure 8] FIG. 13 is a diagram showing the relationship between current application time and light emission output in Examples B1 and B2 and Comparative Examples B1 and B2. [Figure 9]FIG. 13 is a graph showing the relationship between the power-on time and the luminous output maintenance rate in Examples B1 and B2 and Comparative Examples B1 and B2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Embodiment Mode] An embodiment of the present invention will be described with reference to Figures 1 and 2. Note that the embodiment described below is shown as a preferred specific example for carrying out the present invention, and while there are some parts that specifically exemplify various technical matters that are technically preferable, the technical scope of the present invention is not limited to this specific embodiment.

[0010] (Nitride semiconductor light emitting device 1) FIG. 1 is a schematic diagram showing the configuration of a nitride semiconductor light-emitting element 1. In FIG. 1, the dimensional ratio of the stacking direction of each semiconductor layer of the nitride semiconductor light-emitting element 1 (hereinafter also simply referred to as "light-emitting element 1") does not necessarily match the actual one. Hereinafter, the stacking direction of each semiconductor layer of the light-emitting element 1 is referred to as the up-down direction. Also, one side in the up-down direction, that is, the side on which each semiconductor layer of the substrate 2 is grown (e.g., the upper side in FIG. 1) is referred to as the upper side, and the opposite side (e.g., the lower side in FIG. 1) is referred to as the lower side. Note that the expressions up and down are for convenience, and do not limit the attitude of the light-emitting element 1 with respect to the vertical direction, for example, when the light-emitting element 1 is used.

[0011] The light-emitting element 1 constitutes, for example, a light-emitting diode (LED) or a semiconductor laser (LD: Laser Diode). In this embodiment, the light-emitting element 1 constitutes a light-emitting diode that emits light with a wavelength in the ultraviolet region. In particular, the light-emitting element 1 in this embodiment emits ultraviolet light with a central wavelength of 240 nm or more and 365 nm or less. The light-emitting element 1 can be used in the fields of, for example, sterilization (e.g., air purification, water purification, etc.), medicine (e.g., phototherapy, measurement and analysis, etc.), UV curing, etc.

[0012] The light-emitting element 1 includes a buffer layer 3, an n-type semiconductor layer 4, a compositionally graded layer 5, an active layer 6, an electron blocking layer 7, and a p-type semiconductor layer 8, which are arranged in this order on a substrate 2. The light-emitting element 1 also includes an n-side electrode 11 provided on the n-type semiconductor layer 4, and a p-side electrode 12 provided on the p-type semiconductor layer 8.

[0013] The semiconductor constituting the light emitting element 1 is, for example, Al. a Ga b In 1-a-b In this embodiment, the semiconductor constituting the light emitting element 1 can be Al. c Ga 1-c The semiconductor material uses a binary or ternary group III nitride semiconductor represented by N (0≦c≦1). Some of these group III elements may be replaced with boron (B), thallium (Tl), etc. Also, some of the nitrogen may be replaced with phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), etc.

[0014] The substrate 2 is made of a material that transmits the light emitted by the active layer 6. The substrate 2 is made of, for example, sapphire (Al 2 O 3 ) substrate. The upper surface of the substrate 2 is a c-plane. This c-plane may have an off-axis angle. Furthermore, as the substrate 2, for example, an aluminum nitride (AlN) substrate or an aluminum gallium nitride (AlGaN) substrate may be used.

[0015] The buffer layer 3 is formed on the substrate 2. In this embodiment, the buffer layer 3 is made of aluminum nitride. When the substrate 2 is an aluminum nitride substrate or an aluminum gallium nitride substrate, the buffer layer 3 is not necessarily provided. The buffer layer 3 may be an undoped Al gallium nitride layer formed on a layer made of aluminum nitride. p Ga 1-p N layers, where 0≦p≦1.

[0016] The n-type semiconductor layer 4 is formed on the buffer layer 3. The n-type semiconductor layer 4 is, for example, Al doped with n-type impurities. q Ga 1-q N (0≦q≦1). In this embodiment, silicon (Si) is used as the n-type impurity. The same applies to semiconductor layers containing n-type impurities other than the n-type semiconductor layer 4. Note that germanium (Ge), selenium (Se), tellurium (Te), or the like may also be used as the n-type impurity. The n-type semiconductor layer 4 may have a single-layer structure or a multi-layer structure.

[0017] The compositionally graded layer 5 is formed on the n-type semiconductor layer 4. The compositionally graded layer 5 is made of Al r Ga 1-r N (0≦r≦1). The Al composition ratio at each position in the vertical direction of the composition gradient layer 5 increases toward the upper side. Note that the composition gradient layer 5 may include a region in which the Al composition ratio does not increase toward the upper side, for example, in a very small region in the vertical direction (for example, a region of 5% or less of the entire vertical direction of the composition gradient layer 5).

[0018] The Al composition ratio of the lower end of the composition gradient layer 5 is preferably approximately the same (for example, within a difference of 5%) as the Al composition ratio of the upper end of the n-type semiconductor layer 4 adjacent to the lower side of the composition gradient layer 5. In addition, the Al composition ratio of the upper end of the composition gradient layer 5 is preferably approximately the same (for example, within a difference of 5%) as the Al composition ratio of the lower end of the barrier layer 61 adjacent to the upper side of the composition gradient layer 5.

[0019] The compositionally graded layer 5 also serves as a trigger layer which is the starting point of pits (see reference numeral 10 in FIG. 2). Details of the pits will be described later. The trigger layer is, for example, a layer containing a high concentration of silicon. The silicon concentration of the trigger layer can be adjusted based on the density of dislocations 9 present in the n-type semiconductor layer 4, the target density of pits in the active layer 6, and the like. In this embodiment, the silicon concentration of the trigger layer is 5.0×10 18 atoms / cm 3 That's it, 5.0 x 10 19 atoms / cm 3 The following is the result.

[0020] The active layer 6 is formed on the composition gradient layer 5 as a trigger layer. The active layer 6 of this embodiment has a multiple quantum well structure having a plurality of well layers 621 and 622. The bandgap of the active layer 6 is adjusted so that it can emit ultraviolet light with a central wavelength of 240 nm or more and 365 nm or less. When the active layer 6 has a multiple quantum well structure as in this embodiment, from the viewpoint of improving the emission output, the central wavelength of the ultraviolet light emitted by the active layer 6 is preferably 250 nm or more and 300 nm or less, and more preferably 260 nm or more and 290 nm or less. In this embodiment, the active layer 6 has three barrier layers 61 and three well layers 621 and 622, and the barrier layers 61 and the well layers 621 and 622 are alternately laminated. In the active layer 6, the barrier layer 61 is located at the lower end and the well layer 622 is located at the upper end.

[0021] Each barrier layer 61 is formed of Al s Ga 1-s N (0 < s ≦ 1). The Al composition ratio of each barrier layer 61 is, for example, 75% or more and 95% or less. Also, the film thickness of each barrier layer 61 is, for example, 2 nm or more and 50 nm or less.

[0022] The well layers 621 and 622 are formed of Al t Ga 1-t N (0 < t < 1). The Al composition ratio t of each well layer 621 and 622 is smaller than the Al composition ratio s of the barrier layer 61 (that is, t < s).

[0023] The three well layers 621, 622 have different configurations between the bottom well layer 621, which is the well layer disposed at the bottom, and the upper well layer 622, which is the two well layers other than the bottom well layer 621. For example, the film thickness of the bottom well layer 621 is 1 nm or more larger than the film thickness of each of the two upper well layers 622, and the Al composition ratio of the bottom well layer 621 is 2% or more larger than the Al composition ratio of each of the two upper well layers 622. In this embodiment, the upper well layer 622 has a film thickness of 2 nm to 4 nm and an Al composition ratio of 25% to 45%, and the bottom well layer 621 has a film thickness of 4 nm to 6 nm and an Al composition ratio of 35% to 55%. The difference in film thickness between the bottom well layer 621 and each upper well layer 622 can be 2 nm to 4 nm.

[0024] By making the Al composition ratio of the bottom well layer 621 larger than that of the upper well layer 622, the crystallinity of the bottom well layer 621 is improved. This is because the difference in Al composition ratio between the bottom well layer 621 and the n-type semiconductor layer 4 is reduced. By improving the crystallinity of the bottom well layer 621, the crystallinity of each semiconductor layer of the active layer 6 formed above the bottom well layer 621 is also improved. This improves the mobility of carriers in the active layer 6 and improves the light emission output. This effect becomes more pronounced as the thickness of the bottom well layer 621 increases, but from the viewpoint of suppressing an increase in the electrical resistance value of the entire light emitting device 1, the thickness of the bottom well layer 621 is designed to be equal to or less than a predetermined value.

[0025] The bottom well layer 621 also contains silicon. This can also induce the formation of pits in the active layer 6. In this embodiment, the silicon concentration of the bottom well layer 621 is 1.0×10 19 atoms / cm 3 Above 6.0×10 19 atoms / cm 3 The upper well layer 622 may also contain n-type impurities such as silicon, but among the multiple well layers 621, 622, it is preferable that the bottom well layer 621 has the highest silicon concentration.

[0026] In addition, in this embodiment, the active layer 6 has been described by taking the example in which the well layers 621 and 622 have a three - multiple - quantum - well structure. However, the present invention is not limited to this, and the well layers may have a multiple - quantum - well structure with two or four or more well layers. Further, the active layer 6 may have a single - quantum - well structure having only one well layer.

[0027] The electron - blocking layer 7 is formed on the active layer 6. The electron - blocking layer 7 has a role of improving the electron injection efficiency into the active layer 6 by suppressing the occurrence of an overflow phenomenon in which electrons leak from the active layer 6 to the p - type semiconductor layer 8 side (hereinafter, also referred to as an electron - blocking effect). The electron - blocking layer 7 has a laminated structure in which a first layer 71 and a second layer 72 are laminated in order from the lower side.

[0028] The first layer 71 is provided on the active layer 6. The first layer 71 is made of, for example, Al u Ga 1-u N (0 < u ≦ 1). The Al composition ratio u of the first layer 71 is, for example, 90% or more, and in this embodiment, it is made of aluminum nitride. The film thickness of the first layer 71 is, for example, 0.5 nm or more and 5.0 nm or less.

[0029] The second layer 72 is made of, for example, Al v Ga 1-v N (0 < v < 1). The Al composition ratio v of the second layer 72 is smaller than the Al composition ratio t of the first layer 71 (that is, v < t), and is, for example, 70% or more and 90% or less. The film thickness of the second layer 72 is larger than the film thickness of the first layer 71, and is, for example, 15 nm or more and 100 nm or less.

[0030] Since a semiconductor layer with a larger Al composition ratio has a larger electrical resistance value, if the film thickness of the first layer 71 with a relatively high Al composition ratio is made too large, an excessive increase in the overall electrical resistance value of the light - emitting element 1 will occur. Therefore, it is preferable to make the film thickness of the first layer 71 somewhat small. On the other hand, if the film thickness of the first layer 71 is made small, the probability that electrons pass through the first layer 71 from the lower side to the upper side due to the tunnel effect may increase. Therefore, in the light - emitting element 1 of this embodiment, by forming the second layer 72 on the first layer 71, the electrons passing through the entire electron - blocking layer 7 are suppressed.

[0031] Each of the first layer 71 and the second layer 72 is made of an undoped semiconductor layer or a semiconductor layer doped with impurities at a low concentration. In this embodiment, the electron blocking layer 7 is made of an undoped semiconductor layer. Although details will be described later, the ratio of the density of pits on the upper surface 70 of the electron blocking layer 7 (i.e., the upper surface 70 of the second layer 72) to the density of pits (see reference numeral 10 in FIG. 2) on the upper surface 60 of the active layer 6 is preferably less than 30%, and from the viewpoint of reducing the density of pits on the upper surface 70 of the electron blocking layer 7, it is preferable that the impurity concentration in the electron blocking layer 7 is low, and it is more preferable that the electron blocking layer 7 is an undoped semiconductor layer. The electron blocking layer 7 may be formed as a single layer or as three or more layers.

[0032] Silicon is included between the electron blocking layer 7 and the p-type semiconductor layer 8. Silicon and magnesium are easily attracted to each other, and by including silicon between the electron blocking layer 7 and the p-type semiconductor layer 8, magnesium that attempts to diffuse from the p-type semiconductor layer 8 to the active layer 6 is blocked by silicon between the electron blocking layer 7 and the p-type semiconductor layer 8. Hydrogen also easily bonds with magnesium, and as the diffusion of magnesium from the p-type semiconductor layer 8 to the active layer 6 is suppressed as described above, the diffusion of hydrogen from the p-type semiconductor layer 8 to the active layer 6 is also suppressed. The diffusion of magnesium and hydrogen into the active layer 6 may cause deterioration of the active layer 6 and shorten the life of the light-emitting element 1, and therefore, by including silicon between the electron blocking layer 7 and the p-type semiconductor layer 8, the life of the light-emitting element 1 is extended.

[0033] Between the electron block layer 7 and the p-type semiconductor layer 8, silicon may be present in at least one of the following states: a state in which silicon is dissolved in a crystal, a state in which clusters are formed, and a state in which a compound containing silicon is precipitated. The state in which silicon is dissolved in a crystal means that silicon is doped in the aluminum gallium nitride constituting the boundary between the electron block layer 7 and the p-type semiconductor layer 8, that is, silicon is present at the lattice positions of the aluminum gallium nitride. The state in which silicon forms clusters means that silicon is excessively doped in the aluminum gallium nitride constituting the boundary between the electron block layer 7 and the p-type semiconductor layer 8, and silicon is present at the lattice positions of the aluminum gallium nitride and also exists in interstitial positions by agglomeration or the like. The state in which a compound containing silicon is precipitated means, for example, a state in which silicon nitride or the like is formed. At the boundary between the electron block layer 7 and the p-type semiconductor layer 8, a layer containing silicon may be formed, or portions containing silicon may be scattered in a plane direction perpendicular to the stacking direction.

[0034] The p-type semiconductor layer 8 is formed on the electron blocking layer 7. The p-type semiconductor layer 8 has a smaller Al composition ratio than the electron blocking layer 7 and is doped with p-type impurities. w Ga 1-w N (0≦w≦1). Magnesium (Mg) can be used as the p-type impurity, but zinc (Zn), beryllium (Be), calcium (Ca), strontium (Sr), barium (Ba), carbon (C), etc. may also be used. In this embodiment, the p-type semiconductor layer 8 has, from the bottom, a p-type cladding layer 81 and a p-type contact layer 82.

[0035] The p-type cladding layer 81 is provided so as to be in contact with the upper surface 70 of the electron blocking layer 7. The Al composition ratio of the p-type cladding layer 81 can be smaller than the Al composition ratio of the semiconductor layer (i.e., the second layer 72) adjacent to the p-type cladding layer 81 in the electron blocking layer 7, and larger than the Al composition ratio of the p-type contact layer 82. The thickness of the p-type cladding layer 81 is, for example, not less than 9 nm and not more than 105 nm.

[0036] The p-type contact layer 82 is a layer to which the p-side electrode 12 described later is connected, and is doped with a high concentration of p-type impurities. The p-type contact layer 82 is configured to have a low Al composition ratio (for example, 10% or less) to achieve ohmic contact with the p-side electrode 12, and from this perspective is preferably formed of p-type gallium nitride (GaN). Since the p-type contact layer 82 with a low Al composition ratio can absorb ultraviolet light emitted from the active layer 6, the thickness of the p-type contact layer 82 is preferably 50 nm or less.

[0037] The n-side electrode 11 is formed on an exposed surface 41 of the n-type semiconductor layer 4 that is exposed above the active layer 6. The n-side electrode 11 may be, for example, a multilayer film in which titanium (Ti), aluminum, titanium, and gold (Au) are laminated in this order on the n-type semiconductor layer 4. In addition, when the light-emitting element 1 is flip-chip mounted as described later, the n-side electrode 11 may be made of a material capable of reflecting ultraviolet light emitted by the active layer 6.

[0038] The p-side electrode 12 is formed on the upper surface of the p-type semiconductor layer 8. The p-side electrode 12 may be, for example, a multilayer film in which nickel (Ni) and gold are laminated in this order on the p-type semiconductor layer 8. In addition, when the light-emitting element 1 is flip-chip mounted as described later, the p-side electrode 12 may be made of a material capable of reflecting ultraviolet light emitted by the active layer 6.

[0039] The light emitting element 1 can be used by being flip-chip mounted on a package substrate (not shown). That is, the side of the light emitting element 1 on which the n-side electrode 11 and the p-side electrode 12 are provided in the up-down direction faces the package substrate, and each of the n-side electrode 11 and the p-side electrode 12 is mounted on the package substrate via a gold bump or the like. The flip-chip mounted light emitting element 1 extracts light from the substrate 2 side (i.e., the lower side). However, the light emitting element 1 may be mounted on the package substrate by wire bonding or the like. In this embodiment, the light emitting element 1 is a so-called horizontal type light emitting element in which both the n-side electrode 11 and the p-side electrode 12 are provided on the upper side of the light emitting element 1, but the light emitting element 1 may be a vertical type light emitting element. The vertical type light emitting element is a light emitting element in which an active layer is sandwiched between an n-side electrode and a p-side electrode. When the light emitting element is a vertical type, it is preferable to remove the substrate and the buffer layer by laser lift-off or the like.

[0040] Next, a description will be given of the pits 10 formed in the light-emitting element 1 of the present embodiment. Fig. 2 is a schematic diagram showing an example of the pits 10 formed in the light-emitting element 1 of the present embodiment.

[0041] 2, pits 10 are a type of crystal defect that originates from dislocations 9 propagated from the n-type semiconductor layer 4. It is believed that during the growth of the compositionally graded layer 5 serving as a trigger layer, a silicon source having a predetermined concentration or higher is supplied to a location where dislocations 9 propagated from the n-type semiconductor layer 4 exist, changing the growth mode of the parent phase of the compositionally graded layer 5 and forming the pits 10. The pits 10 are formed in multiple layers as a result of a recess in a part of the upper surface of the compositionally graded layer 5 and then each semiconductor layer of the active layer 6 above the recess being recessed along the recess in the upper surface of the compositionally graded layer 5.

[0042] The light-emitting device 1 of this embodiment is formed so that the density of pits 10 confirmed on the upper surface 70 of the electron blocking layer 7 is lower than the density of pits 10 confirmed on the upper surface 60 of the active layer 6. In other words, the light-emitting device 1 of this embodiment is formed with a large number of pits 10 as shown in Fig. 2, that is, pits 10 that are formed at least from the composition gradient layer 5 serving as a trigger layer to the upper surface 60 of the active layer 6 but not to the upper surface 70 of the electron blocking layer 7.

[0043] When the density of the pits 10 on the upper surface 60 of the active layer 6 is a first density D1 and the density of the pits 10 on the upper surface 70 of the electron blocking layer 7 is a second density D2, the ratio R=D2 / D1, which is the ratio of the second density D2 to the first density D1, is less than 30%, and more preferably less than 15%. As will be described in detail later, reducing the ratio R improves the maintenance rate of the light emission output of the light-emitting element 1 and extends the lifespan. The maintenance rate of the light emission output of the light-emitting element 1 is the ratio of the current light emission output to the initial light emission output.

[0044] It is known that when pits 10 are formed in the active layer 6, the occurrence of non-radiative recombination is suppressed and the light emission output is improved (see, for example, JP 2019-054247 A). For this reason, it is preferable that pits 10 are formed in the active layer 6. From the viewpoint of improving the light emission output, the density of the pits 10 that can be confirmed on the upper surface 60 of the active layer 6 is 1.0×10 9 pieces / cm 2 Above 5.0×10 9 pieces / cm 2 The following is preferable: The density of the pits 10 in the upper surface 60 of the active layer 6 can be controlled by adjusting, for example, the density of dislocations present in the n-type semiconductor layer 4 and the silicon concentration in the compositionally graded layer 5 serving as a trigger layer.

[0045] As described above, while there are advantages to forming the pits 10 in the active layer 6, when many pits 10 are formed up to the upper surface 70 of the electron blocking layer 7, the light emitting output of the light emitting element 1 is likely to decrease over time, shortening the life of the light emitting element 1. This is presumably because, when the pits 10 are formed up to the upper surface 70 of the electron blocking layer 7, magnesium and hydrogen that easily binds to magnesium contained in the p-type semiconductor layer 8 are likely to diffuse into the active layer 6 through the pits 10.

[0046] Therefore, as described above, by making the ratio R smaller than 30%, it is possible to obtain the advantage of improving the light emission output by forming the pits 10 in the active layer 6, and the advantage of extending the lifespan by reducing the number of pits 10 formed up to the upper surface 70 of the electron blocking layer 7. From this viewpoint, it is more preferable that the ratio R is less than 15%.

[0047] The second density D2 can be reduced by, for example, reducing the impurity concentration of the electron blocking layer 7. Impurities such as magnesium and silicon tend to gather near the pits 10, and when the electron blocking layer 7 is doped with an impurity such as magnesium, the impurities in the electron blocking layer 7 are attracted to the pits 10, and when the electron blocking layer 7 is formed, oblique growth along the pits 10 is promoted in the areas where the pits 10 exist, and it is presumed that the pits 10 formed in the active layer 6 are also inherited in the electron blocking layer 7.

[0048] Therefore, from the viewpoint of reducing the ratio R, it is preferable that the impurity concentration of the electron blocking layer 7 is low, and it is more preferable that the electron blocking layer 7 is undoped. From the viewpoint of reducing the ratio R by lowering the impurity concentration of the electron blocking layer 7, it is preferable that the Al composition ratio of the electron blocking layer 7 is high. Note that the second density D2 may be reduced by a method other than adjusting the impurity concentration of the electron blocking layer 7. For example, it is considered that the second density D2 can be reduced by increasing the overall film thickness of the electron blocking layer 7.

[0049] FIG. 2 shows an example in which the pits 10 are formed up to the upper surface of the first layer 71 of the electron blocking layer 7, but are buried in the second layer 72, and are not formed up to the upper surface 70 of the second layer 72. In this embodiment, since the film thickness of the first layer 71 is very thin, 0.5 nm or more and 5.0 nm or less, as described above, the first layer 71 cannot completely fill the pits 10. However, since the second layer 72 has a low impurity concentration and a film thickness that exceeds the film thickness of each semiconductor layer of the active layer 6, it is presumed that the pits 10 are easily filled. Therefore, in order to reduce the ratio R, it is preferable that the electron blocking layer 7 includes at least one semiconductor layer that is thicker than each semiconductor layer of the active layer 6 and has a low impurity concentration (preferably undoped). In addition, the total film thickness of the electron blocking layer 7 is preferably at least twice the film thickness of the semiconductor layer with the largest film thickness among the semiconductor layers constituting the active layer 6.

[0050] 2 also shows a schematic example of a micro-dent 700 appearing in a portion of the upper surface 70 of the electron blocking layer 7 that is located above the pit 10. The micro-dent 700 can appear on the upper surface 70 of the second layer 72 of the electron blocking layer 7 as evidence that the pit 10 has been filled in by the second layer 72 of the electron blocking layer 7. The micro-dent 700 is a minute dent with a depth D of less than 1 nm, and such a dent is not considered to be a pit. In other words, the second density D2 is the density of dents on the upper surface 70 of the electron blocking layer 7 that have a depth D of 1 nm or more. The density of relatively large pits 10 with a depth D of 2 nm or more on the upper surface 70 of the electron blocking layer 7 is 1.0×10 8 pieces / cm 2 It is preferable that:

[0051] The concave surface 101 at the top of the pit 10 is recessed so that the cross section parallel to the vertical direction is approximately V-shaped. The entire concave surface 101 has an approximately pyramidal shape (for example, an approximately conical shape, an approximately polygonal pyramid shape, or an elliptical cone shape) or an approximately frustum shape, with the area inside the concave surface 101 becoming smaller toward the lower position. The pit 10 having the concave surface 101 with a V-shaped cross section is called a V-pit. The shape of the concave surface 101 may be a V-shaped cross section, a cylindrical shape, or a polygonal column shape. The diameter φ of the uppermost edge of the concave surface 101 of the pit 10 is, for example, 100 nm or less, more specifically, 20 nm or more and 60 nm or less. In addition, when the concave surface 101 of the pit 10 has a shape other than a cone, such as a polygonal pyramid, the diameter φ can be the diameter when the uppermost edge of the concave surface 101 is approximated to a circle by a circumscribing circle or the like. The total length L of the pit 10 in the vertical direction is, for example, 1 nm or more and 60 nm or less.

[0052] (Method of Manufacturing Nitride Semiconductor Light Emitting Device 1) Next, an example of a method for manufacturing the light emitting device 1 of this embodiment will be described. In this embodiment, a buffer layer 3, an n-type semiconductor layer 4, a compositionally graded layer 5, an active layer 6, an electron blocking layer 7, and a p-type semiconductor layer 8 are epitaxially grown in this order on a disk-shaped substrate 2 by metal organic chemical vapor deposition (MOCVD). That is, in this embodiment, the disk-shaped substrate 2 is placed in a chamber, and the source gases for each semiconductor layer to be formed on the substrate 2 are introduced into the chamber, thereby forming each semiconductor layer on the substrate 2. The source gases for epitaxially growing each semiconductor layer include trimethylaluminum (TMA) as an aluminum source, trimethylgallium (TMG) as a gallium source, ammonia (NH 3 ), tetramethylsilane (TMSi) as a silicon source, and biscyclopentadienylmagnesium (Cp 2 Mg) can be used.

[0053] When forming the compositionally graded layer 5, the supply amount of silicon source to the chamber is adjusted based on the density of dislocations 9 present in the n-type semiconductor layer 4, the target density of pits 10 in the active layer 6, and the like.

[0054] The MOCVD method is also called Metal Organic Vapor Phase Epitaxy (MOVPE). When epitaxially growing each semiconductor layer on the substrate 2, other epitaxial growth methods such as Molecular Beam Epitaxy (MBE) and Hydride Vapor Phase Epitaxy (HVPE) can also be used.

[0055] After each semiconductor layer is formed on the disk-shaped substrate 2, a mask is formed on a portion of the p-type semiconductor layer 8, i.e., on a portion other than the portion that will become the exposed surface 41 of the n-type semiconductor layer 4. Then, the region where the mask is not formed is removed by etching from the top surface of the p-type semiconductor layer 8 to the middle of the n-type semiconductor layer 4 in the vertical direction. As a result, the exposed surface 41 that is exposed toward the upper side is formed in the n-type semiconductor layer 4. After the exposed surface 41 is formed, the mask is removed.

[0056] Next, an n-side electrode 11 is formed on the exposed surface 41 of the n-type semiconductor layer 4, and a p-side electrode 12 is formed on the p-type semiconductor layer 8. The n-side electrode 11 and the p-side electrode 12 may be formed by a well-known method such as an electron beam deposition method or a sputtering method. The above-completed product is cut into pieces of desired dimensions, and a plurality of light-emitting elements 1 as shown in FIG. 1 are manufactured from one wafer.

[0057] (Functions and Effects of the Embodiments) When the density of the pits 10 on the upper surface 60 of the active layer 6 is a first density D1 and the density of the pits 10 on the upper surface 70 of the electron blocking layer 7 is a second density D2, the ratio R=D2 / D1, which is the ratio of the second density D2 to the first density D1, is less than 30%. Therefore, the maintenance rate of the light emitting output of the light emitting element 1 is improved, and the life of the light emitting element 1 is extended.

[0058] Moreover, the electron blocking layer 7 is made of an undoped semiconductor layer, which makes it easier to reduce the second density D2 as described above.

[0059] Moreover, the ratio R further satisfies the requirement of less than 15%, so that the life of the light-emitting element 1 is further extended.

[0060] In addition, the density of the pits 10 having a depth of 2 nm or more on the upper surface 70 of the electron blocking layer 7 is 1.0×10 8 pieces / cm 2 In this manner, the number of deep pits 10 on the upper surface 70 of the electron blocking layer 7 is reduced, which suppresses the diffusion of magnesium and hydrogen that easily bonds with magnesium contained in the p-type semiconductor layer 8 into the active layer 6 through the pits 10, thereby further extending the life of the light-emitting element 1.

[0061] Moreover, the thickness of the p-type contact layer 82 made of p-type GaN is 50 nm or less. In such a case, the lifetime of the light-emitting element 1 tends to be shortened, but as described above, the lifetime of the light-emitting element 1 can be extended by setting the ratio R to less than 30%.

[0062] Furthermore, the thickness of the electron blocking layer 7 is greater than the thickness of each semiconductor layer of the active layer 6. This increases the probability that the pits 10 are filled when the electron blocking layer 7 is formed, and reduces the second density D2.

[0063] As described above, according to this embodiment, it is possible to provide a nitride semiconductor light emitting device that can achieve a longer life.

[0064] [Experimental Example] This experimental example is an example in which the relationship between the ratio R and the maintenance rate of the light emission output was confirmed. In the experimental examples and subsequent examples, the names of the components that are the same as those used in the previously described embodiments represent the same components as those in the previously described embodiments, unless otherwise specified.

[0065] In this experimental example, first, wafers according to Examples A1 to A6 and wafers according to Comparative Examples A1 to A6 were manufactured. Examples A1 to A6 are wafers having a laminated structure similar to that of the light-emitting device shown in the embodiment, and the first layer 71 and the second layer 72 of the electron blocking layer 7 are both undoped. Comparative Examples A1 to A6 are wafers having the second layer 72 doped with magnesium, and other structures similar to those of Examples A1 to A6. Examples A1 to A6 were manufactured by the same manufacturing method, but multiple wafers were manufactured in consideration of manufacturing variations. Similarly, Comparative Examples A1 to A6 were manufactured by the same manufacturing method, but multiple wafers were manufactured in consideration of manufacturing variations. The structures of Examples A1 to A6 and Comparative Examples A1 to A6 are shown in Table 1.

[0066] [Table 1]

[0067] The thickness of each semiconductor layer listed in Table 1 was measured by a transmission electron microscope. The Al composition ratio of each semiconductor layer listed in Table 1 is a value estimated from the secondary ion intensity of Al measured by secondary ion mass spectrometry (SIMS). The "compositional gradient layer" column in Table 1 indicates that the Al composition ratio at each position in the vertical direction of the compositional gradient layer 5 varies from 55% to 85% from the bottom to the top.

[0068] Moreover, the "Si concentration" and "Mg concentration" in Table 1 are silicon concentration and magnesium concentration obtained by secondary ion mass spectrometry. In Table 1, the silicon concentration of the bottom well layer 621 indicates the peak concentration among the silicon concentrations at each position in the vertical direction of the bottom well layer 621. In Table 1, the points marked with * in the "Si concentration" and "Mg concentration" columns indicate that the semiconductor layer is thin and therefore it is difficult to accurately measure the silicon concentration and magnesium concentration. In the "Si concentration" and "Mg concentration" columns in Table 1, the notation "BG" means the background level. The background level is the concentration of silicon or magnesium detected when silicon or magnesium is not doped.

[0069] 3 is a graph showing the silicon concentration distribution and magnesium concentration distribution in the vertical direction (hereinafter, simply referred to as "silicon concentration distribution" and "magnesium concentration distribution") obtained by secondary ion mass spectrometry for each of the light emitting elements of the example and the comparative example. The depth on the horizontal axis in FIG. 3 represents the depth in the vertical direction from the upper surface of the p-type semiconductor layer 8. In FIG. 3, the measurement result of the silicon concentration distribution of the example is represented by a thick solid line, the measurement result of the magnesium concentration distribution of the example is represented by a thick dashed line, the measurement result of the silicon concentration distribution of the comparative example is represented by a thin solid line, and the measurement result of the magnesium concentration distribution of the comparative example is represented by a thin dashed line. Also, in FIG. 3, the depth range of each semiconductor layer is assigned the symbol of each semiconductor layer used in the embodiment.

[0070] First, from FIG. 3, it can be seen that both the first layer 71 and the second layer 72 of the electron block layer 7 are undoped in the example. Here, when looking at the magnesium concentration distribution obtained using secondary ion mass spectrometry, even if the electron block layer 7 is undoped (i.e., even if a magnesium source is not supplied during the deposition of the electron block layer 7), if the semiconductor layer adjacent to the upper side of the electron block layer 7 is a p-type semiconductor layer 8 containing magnesium, magnesium appears to be contained at the end of the electron block layer 7 on the p-type semiconductor layer 8 side, but this is a problem in SIMS measurement. Therefore, when magnesium is contained at a position adjacent to the electron block layer 7, if the magnesium concentration of a region other than the region on the adjacent position side in the electron block layer 7 (for example, within a range of 10 nm from the position) is at the background level in the magnesium concentration distribution obtained using secondary ion mass spectrometry, it can be said that the electron block layer 7 does not contain magnesium. Therefore, the Mg concentration of the second layer 72 in the example in Table 1 is expressed as background.

[0071] 3 shows that in the comparative example, magnesium is contained in the second layer 72 of the electron blocking layer 7. Furthermore, FIG. 3 shows that the magnesium in the second layer 72 diffuses into the active layer 6 in the comparative example.

[0072] 3, silicon is contained between the electron blocking layer 7 and the p-type semiconductor layer 8. When silicon is contained between the electron blocking layer 7 and the p-type semiconductor layer 8, a silicon concentration peak P appears between the electron blocking layer 7 and the p-type semiconductor layer 8 in the silicon concentration distribution. The value of the peak P is 1.0×10 18 atoms / cm 3 Above 1.0×10 20 atoms / cm 3 It is preferable to satisfy the following: 1.0×10 18 atoms / cm 3 By setting the concentration to 1.0×10 or more, it is easy to suppress the diffusion of magnesium from the p-type semiconductor layer 8 side to the active layer 6. 20 atoms / cm 3By setting the value of the peak P in the silicon concentration distribution in the stacking direction of the light-emitting element to 3.0×10 or less, it is possible to suppress a decrease in the crystallinity of the electron blocking layer 7 and the p-type semiconductor layer 8 adjacent to both sides of the silicon position. 18 atoms / cm 3 Above 5.0×10 19 atoms / cm 3 It is more preferable to satisfy the following:

[0073] Here, when the silicon concentration distribution obtained by using secondary ion mass spectrometry is examined, even if the electron block layer 7 is undoped (i.e., even if a silicon source is not supplied during the formation of the electron block layer 7), the bottom portion of the peak P and the like appear at the end of the electron block layer 7 on the p-type semiconductor layer 8 side, and silicon appears to be contained at the end of the electron block layer 7 on the p-type semiconductor layer 8 side, but this is a problem in SIMS measurement. Therefore, when silicon is contained at a position adjacent to the electron block layer 7, if the silicon concentration in a region other than the region on the adjacent position side in the electron block layer 7 (for example, within a range of 10 nm from the position) is at the background level in the silicon concentration distribution obtained by using secondary ion mass spectrometry, it can be said that the electron block layer 7 does not contain silicon.

[0074] Next, for each of Examples A1 to A6 and Comparative Examples A1 to A6, a first density D1 which is the density of pits 10 on the upper surface 60 of the active layer 6 and a second density D2 which is the density of pits 10 on the upper surface 70 of the electron blocking layer 7 were obtained, and the ratio R = D2 / D1 was calculated.

[0075] The first density D1 was obtained by first growing each of Examples A1 to A6 and Comparative Examples A1 to A6 up to the active layer 6, removing them from the chamber, imaging the top surface 60 of the active layer 6 with an atomic force microscope, and counting the number of pits 10 in the captured AFM image. FIG. 4 shows an example of an AFM image of the top surface 60 of the active layer 6. As shown in FIG. 4, an image of a 1 μm square area of ​​the top surface 60 of the active layer 6 is taken with an atomic force microscope, and if n pits 10 are identified in the captured AFM image, the first density D1 of the pits 10 identified in the captured image is n [pits / μm 2 ]=n×10 8 [pcs / cm 2 As shown in Table 2 below, there is no significant difference in the first density D1 between the example and the comparative example. That is, in both the example and the comparative example, the state of the upper surface 60 of the active layer 6 is similar to the state shown in FIG.

[0076] The second density D2 was obtained by forming the electron block layer 7 on another wafer under the same conditions as those on the wafer up to the active layer 6 formed to observe the first density D1, imaging the top surface 70 of the electron block layer 7 with an atomic force microscope, and counting the number of pits 10 in the captured image. In each of the Examples A1 to A6, the wafer formation up to the active layer 6 for observing the first density D1 and the wafer formation up to the electron block layer 7 for observing the second density D2 were performed at a short interval so that the formation could be said to be performed almost simultaneously (i.e., so that the film formation conditions were almost the same). The same is true for each of the Comparative Examples A1 to A6. FIG. 5 shows an example of an AFM image of the top surface 70 of the electron block layer 7 in the Example, and FIG. 6 shows an example of an AFM image of the top surface 70 of the electron block layer 7 in the Comparative Example. Table 2 shows the first density D1, the second density D2, and the ratio R for the Examples A1 to A6 and the Comparative Examples A1 to A6.

[0077] [Table 2]

[0078] From Table 2 and Figs. 4 to 6, it can be seen that, although there is no significant difference in the first density D1 between the examples and the comparative examples, the second density D2 is smaller in the examples than in the comparative examples. From Table 2, it can be seen that in the examples A1 to A6 in which the electron blocking layer 7 is undoped, the ratio R is less than 30%, and in the comparative examples A1 to A6 in which the second layer 72 of the electron blocking layer 7 is magnesium-doped, the ratio R exceeds 30%. That is, in the examples A1 to A6, as shown in Fig. 2, the active layer 6 is formed at least up to the upper surface 60, but relatively many pits 10 are formed that are filled up to the upper surface 70 of the electron blocking layer 7. On the other hand, in the comparative examples A1 to A6, as shown in the schematic diagram of Fig. 7, relatively many pits 10 are formed up to the upper surface 70 of the electron blocking layer 7.

[0079] Here, in Examples A1 to A6 and Comparative Examples A1 to A6, the wafer is removed from the chamber both after the active layer 6 is grown and after the electron blocking layer 7 is regrown in order to count the first density D1 and the second density D2, but this action may affect the life of the completed light-emitting device. Therefore, apart from Examples A1 to A6 and Comparative Examples A1 to A6, light-emitting devices according to Examples B1 and B2 and Comparative Examples B1 and B2 were fabricated using wafers that were not removed from the chamber during film formation, and the transition of the light-emitting output was observed using these.

[0080] Examples B1 and B2 are light-emitting devices manufactured using wafers obtained under the same conditions as Examples A1 to A6, and Comparative Examples B1 and B2 are light-emitting devices manufactured using wafers obtained under the same conditions as Comparative Examples A1 to A6. Since Examples B1 and B2 are manufactured under the same conditions as Examples A1 to A6, the ratio R is estimated to be similar to Examples A1 to A6, i.e., less than 30%. Similarly, Comparative Examples B1 and B2 are manufactured under the same conditions as Comparative Examples A1 to A6, so the ratio R is estimated to be similar to Comparative Examples A1 to A6, i.e., 30% or more.

[0081] For each of Examples B1 and B2 and Comparative Examples B1 and B2, a current of 500 mA was continuously applied for 1000 hours to evaluate the transition of the light emission output. The results of the transition of the light emission output for each of Examples B1 and B2 and Comparative Examples B1 and B2 are shown in Figures 8 and 9. Figure 8 is a diagram showing the relationship between the current application time and the light emission output in Examples B1 and B2 and Comparative Examples B1 and B2. Figure 9 is a diagram in which the light emission output in Figure 8 is converted into a light emission output maintenance rate.

[0082] As can be seen from FIGS. 8 and 9, in Examples B1 and B2 in which the ratio R is less than 30%, the rate of decrease in the light emission output is slower than in Comparative Examples B1 and B2 in which the ratio R exceeds 30%, and thus a longer life can be achieved.

[0083] (Summary of the embodiment) Next, the technical ideas grasped from the above-described embodiment will be described by using the reference numerals and the like in the embodiment. However, the reference numerals and the like in the following description do not limit the components in the claims to the members and the like specifically shown in the embodiment.

[0084] [1] A first embodiment of the present invention is a nitride semiconductor light-emitting element 1 comprising an n-type semiconductor layer 4, an active layer 6 formed on the n-type semiconductor layer 4 and emitting ultraviolet light, an electron blocking layer 7 formed on the active layer 6, and a p-type semiconductor layer 8 formed on the electron blocking layer 7, wherein a plurality of pits 10 are formed in at least the active layer 6, and when a density of the pits 10 on an upper surface 60 of the active layer 6 is a first density D1 and a density of the pits 10 on an upper surface 70 of the electron blocking layer 7 is a second density D2, a ratio R=D2 / D1 of the second density D2 to the first density D1 is less than 30%. This improves the rate at which the light emission output of the nitride semiconductor light emitting element 1 can be maintained, and the life of the nitride semiconductor light emitting element 1 can be extended.

[0085] [2] A second embodiment of the present invention is the first embodiment, in which the electron blocking layer 7 is made of an undoped semiconductor layer. This makes it easier to reduce the second density D2.

[0086] [3] A third embodiment of the present invention is the first or second embodiment, wherein the ratio R further satisfies less than 15%. This makes it possible to further extend the life of the nitride semiconductor light emitting element 1.

[0087] [4] A fourth embodiment of the present invention is any one of the first to third embodiments, wherein the density of the pits 10 having a depth of 2 nm or more on the upper surface 70 of the electron blocking layer 7 is 1.0×10 8 pieces / cm 2 The following is true: This makes it possible to further extend the life of the nitride semiconductor light emitting element 1.

[0088] [5] A fifth embodiment of the present invention is any one of the first to fourth embodiments, in which the p-type semiconductor layer 8 has a p-type contact layer 82 formed of p-type GaN, and the thickness of the p-type semiconductor layer 8 is 50 nm or less. When the thickness of the p-type contact layer 82 having a small Al composition ratio is small, the lifetime of the nitride semiconductor light-emitting element 1 tends to be short unless special measures are taken. However, even with such a basic configuration, the lifetime of the nitride semiconductor light-emitting element 1 can be extended by setting the ratio R to less than 30% as described above.

[0089] [6] A sixth embodiment of the present invention is any one of the first to fifth embodiments, in which the electron blocking layer 7 has a thickness greater than the thickness of each semiconductor layer of the active layer 6. This makes it easier to reduce the second density D2.

[0090] (Additional Note) Although the embodiment of the present invention has been described above, the invention according to the claims is not limited to the above embodiment. It should be noted that not all of the combinations of features described in the embodiment are essential to the means for solving the problems of the invention. The present invention can be modified appropriately without departing from the spirit of the invention. [Explanation of symbols]

[0091] 1...Nitride semiconductor light emitting device 10. Pit 4...n-type semiconductor layer 6…Active layer 60...Top surface of active layer 7...Electron blocking layer 70...Top surface of electron blocking layer 8...p-type semiconductor layer 82...p-type contact layer

Claims

1. An n-type semiconductor layer; an active layer formed on the n-type semiconductor layer and emitting ultraviolet light; an electron blocking layer formed on the active layer; a p-type semiconductor layer formed on the electron blocking layer, At least the active layer has a plurality of pits formed therein; a density of the pits on the upper surface of the active layer is a first density D1, and a density of the pits on the upper surface of the electron blocking layer is a second density D2, a ratio R=D2 / D1 of the second density D2 to the first density D1 is less than 30%. Nitride semiconductor light emitting element.

2. The electron blocking layer is made of an undoped semiconductor layer. The nitride semiconductor light emitting device according to claim 1 .

3. The ratio R further satisfies less than 15%; The nitride semiconductor light emitting device according to claim 1 .

4. The density of the pits having a depth of 2 nm or more on the upper surface of the electron blocking layer is 1.0×10 ８ pieces / cm ２ Below is the The nitride semiconductor light emitting device according to claim 1 .

5. the p-type semiconductor layer has a p-type contact layer formed of p-type GaN, The thickness of the p-type semiconductor layer is 50 nm or less. The nitride semiconductor light emitting device according to claim 1 .

6. The thickness of the electron blocking layer is greater than the thickness of each semiconductor layer of the active layer. The nitride semiconductor light emitting device according to claim 1 .

Images