Square circuit
The square circuit design addresses base current errors in NPN bipolar transistors by using NMOS transistors in a current mirror and Wilson current mirror configuration, achieving accurate squared output currents on high voltage CMOS processes.
Patent Information
- Application Number
- JP2023121360
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-07-26
- Publication Date
- 2025-02-06
AI Technical Summary
Conventional square circuits using NPN bipolar transistors on high voltage CMOS processes suffer from reduced base current amplification factors, leading to significant base current errors and inaccurate output currents.
A square circuit design incorporating NPN bipolar transistors and NMOS transistors, utilizing a first current mirror circuit and a Wilson current mirror circuit to compensate for base current errors, ensuring accurate squared output currents.
The design effectively reduces and suppresses base current errors, enabling highly accurate squared output currents, even when formed on high voltage CMOS processes.
Smart Images
Figure 2025017998000001_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates to a squaring circuit, and more particularly to a squaring circuit for use in an analog circuit within an integrated circuit, which has an output current with high accuracy. [Background technology]
[0002] A squaring circuit is one of the so-called functional circuits used in analog circuits, and for example, those disclosed in Non-Patent Documents 1 and 2 and the like are known. FIG. 2 shows an example of a conventional squaring circuit, and hereinafter, this conventional circuit will be described with reference to the same figure. The conventional squaring circuit is a so-called translinear circuit that is configured using first to fourth transistors Q1p to Q4p, which are NPN bipolar transistors.
[0003] The operating principle of this conventional circuit will now be described. First, the characteristics of an NPN bipolar transistor are as follows: collector current is IC, normalized emitter area ratio is χ, saturation current is Is, base-emitter voltage is VBE, elementary charge is q, Boltzmann constant is k, absolute temperature is T, thermal voltage is VT=k×T÷q, base current is IB, base current amplification is β, and emitter current is IE. The relationships between the collector current and base-emitter voltage, and between the collector current and the base current and emitter current are expressed by the following Equations 1A to 1C.
[0004] IC=χ×Is×exp(VBE / VT)...Formula 1A
[0005] IC=βIB...Formula 1B
[0006] IC+IB=IE···Formula 1C
[0007] In Fig. 2, "IINP" refers to the first current input terminal and is also the name of the current flowing into this first current input terminal. Similarly, "IBIASP" refers to the second current input terminal and is also the name of the current flowing into this second current input terminal. Similarly, "IOP" refers to the first current output terminal and is also the name of the current flowing into this first current output terminal. Also, "VCCp" refers to the power supply voltage terminal and is also the name of the voltage applied to this power supply voltage terminal.
[0008] In the conventional circuit shown in FIG. 2, it is assumed that the base current amplification factors of the first to fourth transistors Q1p to Q4p are sufficiently large, that is, the base currents are zero. Under these conditions, the collector current IC1p of the first transistor Q1p is equal to the current flowing into the first current input terminal IINP, and flows as the emitter current IE1p of the transistor Q1p. Furthermore, this emitter current IE1p flows as the collector current IC2p of the second transistor Q2p.
[0009] Moreover, the emitter current IE3p of the third transistor Q3p becomes the current IBIASP flowing through the second current output terminal IBIASP, and becomes equal to the collector current IC3p of the third transistor Q3p. Furthermore, the collector current IC4p of the fourth transistor Q4p becomes a current flowing to the first current output terminal IOP.
[0010] Here, among the base-emitter voltages of the first to fourth transistors Q1p to Q4p, if the base-emitter voltage of the first transistor Q1p is VBE1p, the base-emitter voltage of the second transistor Q2p is VBE2p, the base-emitter voltage of the third transistor Q3p is VBE3p, and the base-emitter voltage of the fourth transistor Q4p is VBE4p, then the relationship shown in Equation 2 below holds according to Kirchhoff's voltage law.
[0011] VBE2p+VBE1p-VBE3p-VBE4p=0...Equation 2
[0012] Here, by transforming the above formulas 1A to 1C, the following formula 3 can be obtained.
[0013] VBE=VT×ln(IC / Is / χ)...Equation 3
[0014] By applying this formula 3 to the above formula 2, the relational expression shown in formula 4 below can be obtained.
[0015] IC4p=(IC1p) 2 / IC3p...Formula 4
[0016] Therefore, it can be confirmed that a current proportional to the square of the collector current IC1p of the first transistor Q1p is generated as the collector current IC4p, which is the output current. [Prior art documents] [Non-patent literature]
[0017] [Non-Patent Document 1] Kunihiro Asada and Yuzuru Nagata, supervising translation, PR Gray, SH Levis, and RG Mayer, "Analog Integrated Circuit Design Techniques for System LSI (Basics) (Applications)", Baifukan Publishing, 2004. [Non-Patent Document 2] Willy Sansen, Rudy J.Van De Plassche, Johan H.Huijing, "Analog Circuit Design, MOST RF Circuit, Sigma-DeltaConverters and Translinear Circuits", 1996 Summary of the Invention [Problem to be solved by the invention]
[0018] However, as mentioned above, the above-mentioned conventional squaring circuit is a circuit that is established under the premise that the base current amplification factor is sufficiently large, whereas in recent years, the base current amplification factor of NPN bipolar transistors formed on high-voltage CMOS processes has decreased to single digits compared to the conventional base current amplification factor of about 100 to 200, and the base current error has become non-negligible. That is, the above formula 4 becomes the following formula 5 with the base current amplification factor βnp.
[0019] IC4p≒{βnp / (1+βnp)}×(IC1p) 2 / IC3p...Formula 5
[0020] Therefore, in the case of the conventional circuit shown in FIG. 2, in a configuration using an NPN bipolar transistor formed on a high-voltage CMOS process, it is not possible to obtain an output current that is proportional to the square.
[0021] The present invention has been made in consideration of the above circumstances, and provides a squaring circuit that can reduce or suppress the influence of errors in the base current of an NPN bipolar transistor and obtain a highly accurate squared output current. [Means for solving the problem]
[0022] In order to achieve the above object of the present invention, the squaring circuit according to the present invention comprises: a first current mirror circuit including first and third bipolar transistors which are NPN bipolar transistors and a first MOS transistor which is an NMOS transistor; a Wilson current mirror circuit including second to fourth MOS transistors, each of which is an NMOS transistor, and an output stage of which is connected to an output stage of the first current mirror circuit; a fourth bipolar transistor, the fourth bipolar transistor being an NPN bipolar transistor as an output transistor, the base of which is connected to the first current mirror circuit and an output stage of the Wilson current mirror circuit; In the first current mirror circuit, the bases of the first and third bipolar transistors are connected to each other and to the source of the first MOS transistor, a power supply voltage can be applied to the drain of the first MOS transistor together with the drain of the third MOS transistor, the collector of the first bipolar transistor and the gate of the first MOS transistor are connected to each other, and a current can be input from the outside to the connection point, the emitter of the first bipolar transistor is connected to the collector and base of the second bipolar transistor, and the emitter of the second bipolar transistor is connected to ground, while In the Wilson current mirror circuit, the gates of the second and fourth MOS transistors are connected to each other and to the source of the third MOS transistor and the drain of the fourth MOS transistor. The drain of the second MOS transistor is connected to the base of the fourth bipolar transistor together with the emitter of the third bipolar transistor. The sources of the second and fourth MOS transistors and the emitter of the fourth bipolar transistor are all connected to ground. The gate of the third MOS transistor is connected to the collector of the third bipolar transistor. A bias current can be input to the connection point from the outside, and a squared output current can be output to the collector of the fourth bipolar transistor. Effect of the Invention
[0023] According to the present invention, in a squaring circuit based on a translinear circuit using NPN bipolar transistors, the base current error of the NPN bipolar transistors can be reduced and suppressed by MOS transistors, so that it is possible to obtain a more accurate squaring current than in the past. [Brief description of the drawings]
[0024] [Figure 1]FIG. 2 is a circuit diagram showing an example of a circuit configuration of a squaring circuit according to an embodiment of the present invention. [Diagram 2] FIG. 1 is a circuit diagram showing an example of a circuit configuration of a conventional squaring circuit. [Diagram 3] 4 is a characteristic diagram showing an example of an output current characteristic with respect to an input current of a squaring circuit according to an embodiment of the present invention, together with a similar characteristic example of a conventional circuit. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0025] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. It should be noted that the components, arrangements, etc. described below do not limit the present invention, and various modifications can be made within the scope of the present invention. First, the circuit configuration of a squaring circuit in the embodiment of the present invention will be described with reference to FIG. The squaring circuit in the embodiment of the present invention is roughly divided into a first current mirror circuit 51 which is the input stage of the circuit, a Wilson current mirror circuit 52 provided in the subsequent stage, and a fourth bipolar transistor 4 which serves as an output transistor.
[0026] The squaring circuit in the embodiment of the present invention has as its main components first to fourth bipolar transistors (in FIG. 1, these are indicated as “Q1”, “Q2”, “Q3”, and “Q4”, respectively) 1 to 4 which are NPN bipolar transistors, and first to fourth MOS transistors (in FIG. 1, these are indicated as “Mn1”, “Mn2”, “Mn3”, and “Mn4”, respectively) 11 to 14 which are NMOS transistors, and is configured so as to enable reduction and suppression of base current errors as described later in a circuit configuration based on a so-called translinear circuit.
[0027] First, the first and third bipolar transistors 1, 3 are connected in a so-called current mirror manner to configure a first current mirror circuit 51 via a first MOS transistor 11 for base current compensation. That is, the bases of the first and third bipolar transistors 1, 3 are connected to each other, and the connection point is connected to the source of the first MOS transistor 11. The gate of the first MOS transistor 11 is connected to the first current input terminal 21 together with the collector of the first bipolar transistor 1. The drain of the first MOS transistor 11 is connected to a power supply voltage terminal 23, and a voltage Vcc is applied to the drain of the first MOS transistor 11 from the outside via the power supply voltage terminal 23. In FIG. 1, “IIN” refers to the current flowing through the first current input terminal 21.
[0028] The collector of the third bipolar transistor 3, together with the gate of the third MOS transistor 13, is connected to the second current input terminal 22. In addition, in FIG. 1, "IBIAS" means a bias current flowing through the second current input terminal 22. On the other hand, the emitter of the first bipolar transistor 1 is connected to ground via a second bipolar transistor 2 that is provided in a diode-connected state.
[0029] That is, the emitter of the first bipolar transistor 1 is connected to the collector and base of the second bipolar transistor 2, while the emitter of the second bipolar transistor 2 is connected to ground. In addition, the emitter of the third bipolar transistor 3 is connected to the drain of the second MOS transistor 12 and the base of the fourth bipolar transistor 4 .
[0030] The second to fourth MOS transistors 12 to 14 are provided to configure a Wilson current mirror circuit 52 as described below. That is, the second and fourth MOS transistors 12 and 14 have their respective gates and the drain of the fourth MOS transistor 14 connected to each other, while their respective sources are both connected to ground.
[0031] The source of the third MOS transistor 13 and the drain of the fourth MOS transistor 14 are connected together, while the drain of the third MOS transistor 13 is connected to a power supply voltage terminal 23 . The collector of the fourth bipolar transistor 4 is connected to the current output terminal 24, while the emitter is connected to the ground. In addition, in FIG.
[0032] Next, the circuit operation in the above configuration will be described. First, the input current IIN flowing to the first current input terminal 21 does not flow to the gate of the first MOS transistor 11 because the gate of the first MOS transistor 11 is made of an insulator. Therefore, the input current IIN flowing through the first current input terminal 21 is equal to the collector current IC1 of the first bipolar transistor 1. In addition, the base currents of the first and third bipolar transistors 1 and 3 are supplied from the source of the first MOS transistor 11.
[0033] The first and second bipolar transistors 1 and 2 are made of elements having the same characteristics. Therefore, the emitter current IE1 of the first bipolar transistor 1 is divided into the collector and base of the second bipolar transistor 2, and the current values of these currents are equal to the collector current and base current of the first bipolar transistor 1, respectively. That is, IC1=IC2 holds. Here, "IC2" is the collector current of the second bipolar transistor 2.
[0034] Moreover, the current flowing through the drain of the second MOS transistor 12 becomes equal to the emitter current of the third bipolar transistor 3 due to the Wilson current mirror circuit 52 formed by the second to fourth MOS transistors 12 to 14 . These facts prove that the currents flowing through the first and second current input terminals 21, 22, respectively, are supplied to the collectors of the first bipolar transistor 1 and the third bipolar transistor 3, respectively, without being branched.
[0035] As in the conventional circuit, the base-emitter voltages of the first to fourth bipolar transistors 1 to 4 satisfy the relationship in Equation 5 below according to Kirchhoff's voltage law, assuming that the base-emitter voltage of the first bipolar transistor 1 is VBE1, the base-emitter voltage of the second bipolar transistor 2 is VBE2, the base-emitter voltage of the third bipolar transistor 3 is VBE3, and the base-emitter voltage of the fourth bipolar transistor 4 is VBE4.
[0036] VBE2+VBE1-VBE3-VBE4=0...Equation 5
[0037] Here, as in the conventional circuit, the base-emitter voltage VBE of the bipolar transistor satisfies the relationship of Equation 3 shown in the explanation of the conventional circuit above. Therefore, by applying Equation 3 to Equation 5, the following relational expression Equation 6 can be obtained.
[0038] IC4=(IC1) 2 / IC3...Formula 6
[0039] Therefore, it can be seen from equation 6 that the output current IO at the current output terminal 24 is the collector current IC4 of the fourth bipolar transistor 4 itself, and is proportional to the square of the collector current IC1 of the first bipolar transistor 1. The squaring circuit in the above-described embodiment of the present invention is preferably applied to cases where a circuit is formed using a so-called BCD (bipolar CMOS DMOS) process, for example.
[0040] FIG. 3 shows the results of a simulation of the change characteristics of the output current with respect to the change in the input current of the squaring circuit in the embodiment of the present invention, together with an example of similar change characteristics of a conventional circuit. The figure will be described below. In Fig. 3, the horizontal axis indicates the input current IIN and the vertical axis indicates the output current IO, both in units of μA. The figure is also expressed logarithmically.
[0041] In FIG. 3, the solid characteristic line represents the simulation result of the change characteristic of the output current with respect to the change in the input current of the squaring circuit in the embodiment of the present invention. Moreover, the multiple black circles on this solid characteristic line indicate theoretical values. Furthermore, in FIG. 3, the dotted characteristic line represents the similar simulation results for the conventional circuit (see FIG. 2).
[0042] This simulation was performed under the assumption that the current flowing through the second current input terminal 22 is 1 μA and the base current amplification factor is 5. According to FIG. 3, it can be seen that the squaring circuit in the embodiment of the present invention has characteristics that are almost identical to the theoretical values, whereas in the case of the conventional circuit, deviation from the theoretical values is unavoidable. [Industrial Applicability]
[0043] The effect of errors in the base current of an NPN bipolar transistor can be reduced or suppressed, and the present invention can be applied to a squaring circuit in which a highly accurate squared output current is desired. [Explanation of symbols]
[0044] 1 to 4: First to fourth bipolar transistors 11 to 14: first to fourth MOS transistors 51...First current mirror circuit 52…Wilson current mirror circuit
Claims
[Claim 1] a first current mirror circuit including first and third bipolar transistors which are NPN bipolar transistors and a first MOS transistor which is an NMOS transistor; a Wilson current mirror circuit including second to fourth MOS transistors each being an NMOS transistor, the output stage of which is connected to the output stage of the first current mirror circuit; a fourth bipolar transistor, the fourth bipolar transistor being an NPN bipolar transistor as an output transistor, the base of which is connected to the first current mirror circuit and to an output stage of the Wilson current mirror circuit; In the first current mirror circuit, the bases of the first and third bipolar transistors are connected to each other and to the source of the first MOS transistor, a power supply voltage can be applied to the drain of the first MOS transistor together with the drain of the third MOS transistor, a collector of the first bipolar transistor and a gate of the first MOS transistor are connected to each other, and a current can be input from the outside to the connection point, an emitter of the first bipolar transistor is connected to the collector and base of a second bipolar transistor, and an emitter of the second bipolar transistor is connected to ground, In the Wilson current mirror circuit, the gates of the second and fourth MOS transistors are connected to each other and to the source of the third MOS transistor and the drain of the fourth MOS transistor, the drain of the second MOS transistor is connected to the base of the fourth bipolar transistor together with the emitter of the third bipolar transistor, the sources of the second and fourth MOS transistors and the emitter of the fourth bipolar transistor are both connected to ground, and the gate of the third MOS transistor is connected to the collector of the third bipolar transistor, and the connection point is configured to allow an external bias current to be input and to allow a squared output current to be output to the collector of the fourth bipolar transistor.