Laminate and thermoelectric conversion material including the same

Abstract

To provide a laminate in which a p-type semiconductor and an n-type semiconductor are laminated, each of which is made of a silicon alloy of silver, barium, and silicon, and at least one of a thermoelectric conversion material and a thermoelectric conversion module including the laminate.SOLUTION: A silicon alloy laminate made of silver, barium, and silicon, has a structure in which a p-type semiconductor layer, a mixed semiconductor layer containing a p-type semiconductor and an n-type semiconductor, and an n-type semiconductor layer are laminated in this order, and the mixed semiconductor layer has a structure in which two or more unit layers are laminated.SELECTED DRAWING: None

Description

[Technical field]

[0001] The present disclosure relates to a laminate and a thermoelectric conversion material using the same. [Background technology]

[0002] Thermoelectric conversion materials are incorporated into thermoelectric conversion elements and used as thermoelectric conversion modules. In recent years, there has been an increasing demand for miniaturization of thermoelectric conversion modules for the purpose of application to wearable devices, etc. Conventionally, bismuth-tellurium alloys consisting of bismuth (Bi) and tellurium (Te) have been used as thermoelectric conversion materials. However, from the viewpoints of low environmental load and low cost, silicon alloys containing silicon (Si) and elements other than silicon are being considered as thermoelectric conversion materials. As a silicon alloy that functions as a thermoelectric conversion material, the present inventors have reported a silicon alloy (silicide-based alloy material) containing silver, barium, and silicon as main components (Patent Document 1).

[0003] However, thermoelectric conversion elements have the problem that power generation stops when the temperature difference becomes small, so their use is limited to places where high-temperature parts and low-temperature parts are close to each other. In response to this problem, Patent Document 2 proposes a thermoelectric conversion element structure that is capable of generating large amounts of power even under conditions where the temperature difference between the semiconductor parts is 1°C or less by forming a sintered body in which a specific p-type semiconductor part and an n-type semiconductor part are joined, and has demonstrated its performance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2021-181397 A [Patent Document 2] JP 2020-088028 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present disclosure is to provide at least one of a laminate in which a p-type semiconductor and an n-type semiconductor are stacked, the p-type semiconductor being made of a silicon alloy of silver, barium, and silicon, and a thermoelectric conversion material and a thermoelectric conversion module including the laminate. [Means for solving the problem]

[0006] In this disclosure, the stacking of a p-type semiconductor and an n-type semiconductor made of a silicon alloy of silver, barium, and silicon was investigated. As a result, it was confirmed that when a p-type semiconductor and an n-type semiconductor made of a silicon alloy of silver, barium, and silicon are stacked by the method disclosed in Patent Document 2, cracks occur at the stacking interface, and an integrated stack cannot be obtained. Furthermore, it was found that by interposing a specific intermediate layer between the p-type semiconductor and the n-type semiconductor, the occurrence of defects at the junction interface is suppressed, and a stack in which a p-type semiconductor and an n-type semiconductor made of a silicon alloy of silver, barium, and silicon are integrated can be obtained.

[0007] That is, the present invention is as described in the claims, and the gist of the present disclosure is as follows. [1] A structure in which a p-type semiconductor layer, a mixed semiconductor layer containing a p-type semiconductor and an n-type semiconductor, and an n-type semiconductor layer are laminated in this order, and The mixed semiconductor layer has a structure in which two or more unit layers are stacked, and is a silicon alloy laminate made of silver, barium, and silicon. [2] The laminate according to the above [1], wherein the mass ratio of the n-type semiconductor to the total mass of the n-type semiconductor and the p-type semiconductor of a unit layer directly laminated on the n-type semiconductor layer is smaller than the mass ratio of the n-type semiconductor to the total mass of the n-type semiconductor and the p-type semiconductor of a unit layer directly laminated on the p-type semiconductor layer. [3] The laminate according to the above [1] or [2], wherein the mass ratio of the n-type semiconductor to the total mass of the n-type semiconductor and p-type semiconductor of the unit layer directly laminated on the n-type semiconductor layer is 0.45 or more. [4] The laminate according to any one of [1] to [3] above, wherein the silicon alloys constituting the p-type semiconductor layer, the unit layer and the n-type semiconductor layer each have a composition in which the atomic ratio when the total atomic weight of silver, barium and silicon is taken as 100 at %, satisfies the following: Silver: 9 at% or more or 15 at% or more, and 27at% or less Barium: 20 at% or more or 30 at% or more, and 53at% or less or 45at% or less Silicon: 29 at% or more or 32 at% or more, and 64at% or less or 52at% or less

[0008] [5] A thermoelectric conversion material comprising the laminate according to any one of [1] to [4] above. [6] A thermoelectric conversion module comprising the laminate described in any one of [1] to [4] above. Effect of the Invention

[0009] The present disclosure can provide at least one of a laminate in which a p-type semiconductor and an n-type semiconductor are stacked, each made of a silicon alloy of silver, barium, and silicon, and a thermoelectric conversion material and a thermoelectric conversion module including the same. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The present disclosure will be described in detail below. However, the following description of the configuration elements is an example of an embodiment of the present disclosure, and the present disclosure is not limited to these contents. In addition, the configurations and parameters disclosed in this specification can be combined in any combination, and the upper and lower limits of the values ​​disclosed in this specification can be combined in any combination.

[0011] [Laminate] In this embodiment, a p-type semiconductor layer, a mixed semiconductor layer containing a p-type semiconductor and an n-type semiconductor, and an n-type semiconductor layer are laminated in this order, and The mixed semiconductor layer has a structure in which two or more unit layers are stacked, and is a laminate of a silicon alloy made of silver, barium, and silicon. The laminate of this embodiment is a laminate of a silicon alloy (hereinafter, also referred to as "Ag-Ba-Si alloy") consisting of silver, barium, and silicon. In this embodiment, the "silicon alloy" is a metal consisting of silicon (Si) and one or more metal elements other than silicon, and the silicon alloy of this embodiment is a silicon alloy containing silver and barium.

[0012] The crystal phase of the silicon alloy contained in the laminate of this embodiment is preferably AgBa2Si3, and more preferably AgBa2Si3 having a space group of 70.

[0013] The laminate of this embodiment, and the Ag-Ba-Si alloy constituting the p-type semiconductor layer, unit layer, and n-type semiconductor layer each have a composition in which the atomic ratio when the total atomic weight of silver, barium, and silicon is 100 at %, satisfies the following: Silver: 9 at% or more or 15 at% or more, and 27at% or less Barium: 20 at% or more or 30 at% or more, and 53at% or less or 45at% or less Silicon: 29 at% or more or 32 at% or more, and 64at% or less or 52at% or less

[0014] The laminate of the present embodiment has a structure in which a p-type semiconductor layer, a mixed semiconductor layer containing a p-type semiconductor and an n-type semiconductor, and an n-type semiconductor layer are laminated in this order, whereby the laminate of the present embodiment exhibits thermoelectric conversion ability.

[0015] The p-type semiconductor layer may be made of a p-type semiconductor made of an Ag-Ba-Si alloy, while the n-type semiconductor layer may be made of an n-type semiconductor made of an Ag-Ba-Si alloy. The Ag-Ba-Si alloy can be either a p-type semiconductor or an n-type semiconductor depending on the composition of silicon to silver. A p-type semiconductor is obtained by lowering the atomic ratio of silicon to silver (hereinafter also referred to as the "Si / Ag ratio"), while an n-type semiconductor is obtained by increasing the Si / Ag ratio. Therefore, compared to a p-type semiconductor made of an Ag-Ba-Si alloy, an n-type semiconductor made of an Ag-Ba-Si alloy has a high Si / Ag ratio.

[0016] The n-type and p-type semiconductor layers preferably have approximately the same thickness, and the ratio of the thickness [mm] of the p-type semiconductor layer to the thickness [mm] of the n-type semiconductor layer is preferably 0.8 to 1.2.

[0017] The laminate of this embodiment has a mixed semiconductor layer (hereinafter, simply referred to as "mixed semiconductor layer") containing a p-type semiconductor and an n-type semiconductor, and is a laminate in which the p-type semiconductor layer and the n-type semiconductor layer are integrated via the mixed semiconductor layer. By interposing the mixed semiconductor layer, a quasi-continuous composition gradient can be provided between the p-type semiconductor layer and the n-type semiconductor layer. This improves the strength of the laminate.

[0018] The mixed semiconductor layer has a structure in which two or more unit layers are laminated. Each unit layer may contain a p-type semiconductor and an n-type semiconductor, but it is preferable that the mass ratio of the n-type semiconductor to the total mass of the n-type semiconductor and the p-type semiconductor in the unit layer directly laminated on the n-type semiconductor layer (hereinafter also referred to as "n / (p+n) ratio") [mass %] is smaller than the n / (p+n) ratio of the unit layer directly laminated on the p-type semiconductor layer.

[0019] The unit layer directly laminated on the n-type semiconductor layer preferably has a mass ratio of the n-type semiconductor to the total mass of the n-type semiconductor and the p-type semiconductor (hereinafter also referred to as "n / (p+n) ratio") [mass %] of 0.45 or more, and more preferably 0.5 or more. On the other hand, the unit layer directly laminated on the p-type semiconductor layer preferably has an n / (p+n) ratio less than 0.45, and more preferably 0.4 or less.

[0020] The unit layers may be stacked in two or more layers, or even three or more layers. On the other hand, it is not necessary to have a multi-layer structure more than necessary, and for example, the unit layers may be seven or less layers, or six or less layers. When the mixed semiconductor layer is composed of three or more unit layers, it is preferable that the unit layers are stacked so that the n / (p+n) ratio decreases in the direction from the n-type semiconductor layer toward the p-type semiconductor layer (hereinafter, simply referred to as the "stacking direction").

[0021] In order to achieve a more continuous change in physical properties in the stacking direction, it is preferable that the n-type semiconductor and the p-type semiconductor contained in each unit layer have the same composition as the n-type semiconductor constituting the n-type semiconductor layer and the p-type semiconductor constituting the p-type semiconductor layer, respectively.

[0022] The thickness of the mixed semiconductor layer is arbitrary, but the ratio of the thickness [mm] of the mixed semiconductor layer to the thickness [mm] of the n-type semiconductor layer is, for example, 0.7 to 1.5, or more than 1.0 to 1.2.

[0023] Although the thickness of each unit layer is arbitrary, it is preferable that the thickness satisfies the following relationship. 0.3T mix ≦ T unit ≦ 0.7T mix Preferably, 0.4T mix ≦ T unit ≦ 0.6T mix

[0024] In addition, T unit is the thickness of each unit layer [mm] and T mixis the thickness [mm] of the mixed semiconductor layer. The thicknesses of the unit layers may be different from each other, and for example, the ratio of the thickness of the unit layer to the thickness of the n-type semiconductor layer may be 0.25 to 0.60, or further 0.25 to 0.45.

[0025] Each layer included in the laminate of this embodiment may contain inevitable impurities or a metal phase containing one or more selected from the group consisting of iron, barium, and silicon, as long as the effect is not impaired. Examples of inevitable impurities include one or more metal elements selected from the group consisting of tungsten (W), copper (Cu), iron (Fe), and aluminum (Al), or compounds thereof, and one or more oxides selected from the group consisting of tungsten, copper, iron, and aluminum. Examples of metal phases include one or more selected from the group consisting of iron, barium, silicon, iron-barium alloy, iron-silicon alloy, and barium-silicon alloy.

[0026] The shape of the laminate of this embodiment may be any shape depending on the application, and may be, for example, one or more shapes selected from the group consisting of a disk shape, a cylindrical shape, a cone shape, a roughly spherical shape, and a polygonal shape.

[0027] The relative density of the laminate of this embodiment can be 95% or more, or 96% or more, and can be 99.5% or less, or 99% or less, and is preferably 95% or more and 99.5% or less, or 96% or more and 99% or less.

[0028] In this embodiment, the relative density is expressed as true density [g / cm 3 ] vs. measured density [g / cm 3 The true density of AgBa2Si3 is 4.777 [g / cm 3 The actual density is a value measured according to a method in accordance with JIS R 1634.

[0029] True density [g / cm 3 ] = 4.777 × {M / M AgBa2Si3} (1) In the above formula, M is the amount of substance [g / mol] of the laminate whose density was measured, and M AgBa2Si3 is the amount of substance of AgBa2Si3 (=466.8[g / mol]). In calculating M, the composition of the laminate can be obtained by ICP-MS mass spectrometry, and the amount of substance of each element can be Ag: 107.9[g / mol], Ba: 137.3[g / mol], and Si: 28.1[g / mol].

[0030] The electromotive force of the laminate of this embodiment at 150° C. is 100 μV / K or more, or 300 μV / K or more, and may be 500 μV / K or less, or 400 μV / K or less, and is preferably 100 μV / K or more and 500 μV / K or less, or 300 μV / K or more and 400 μV / K or less. Such an electromotive force is an electromotive force generated by so-called isothermal thermoelectric conversion even when the temperature difference between the n-type semiconductor layer and the p-type semiconductor layer is extremely small, and is an electromotive force when the temperature difference between the p-type semiconductor and the n-type semiconductor in this case is 0° C. or more and 0.5° C. or less, or further 0° C. or more and 0.2° C. or less.

[0031] In this embodiment, the temperature difference between the p-type semiconductor and the n-type semiconductor is an absolute value.

[0032] The electrical resistivity of the laminate of this embodiment at 150° C. is 1.00×10 -3 Ω cm or more or 3.00×10 -3 Ω cm or more, 1.00×10 -1 Ω cm or less or 1.00×10 -2 For example, it is 1.00×10 -3 Ω cm or more 1.00×10 -1 Ω cm or less or 3.00×10 -3 Ω cm or more 1.00×10 -2 It is preferable that the resistivity is Ω·cm or less.

[0033] In this embodiment, the electromotive force and the electrical resistivity can be measured under the following conditions by connecting probes to the p-type semiconductor layer and the n-type semiconductor layer, respectively. Sample shape: Flat plate with dimensions of 6 mm length x 10 mm width x 1 mm thickness Electrode: Platinum electrode Measurement atmosphere: Vacuum atmosphere Measurement temperature: 150℃

[0034] [Method of manufacturing laminate] The laminate of this embodiment may be produced by any method as long as it has the above-mentioned characteristics. A preferred method for producing the laminate of this embodiment includes a step of firing a laminated powder in which a p-type semiconductor powder made of a silicon alloy of silver, barium, and silicon, a mixed powder of a p-type semiconductor and an n-type semiconductor made of a silicon alloy of silver, barium, and silicon, a mixed powder of a p-type semiconductor and an n-type semiconductor made of a silicon alloy of silver, barium, and silicon, which is a mixed powder of a p-type semiconductor and an n-type semiconductor made of a silicon alloy of silver, barium, and silicon and has a different composition from the mixed powder, and a powder of a silicon alloy n-type semiconductor made of silver, barium, and silicon are laminated in this order at 650°C to 950°C (hereinafter also referred to as a "firing step").

[0035] The firing step is performed using a laminated powder (hereinafter simply referred to as "laminated powder") in which a p-type semiconductor powder made of a silicon alloy of silver, barium, and silicon (hereinafter also referred to as "p-type powder"), a mixed powder of a p-type semiconductor and an n-type semiconductor made of a silicon alloy of silver, barium, and silicon (hereinafter also referred to as "mixed powder A"), a mixed powder of a p-type semiconductor and an n-type semiconductor made of a silicon alloy of silver, barium, and silicon but having a different composition from the mixed powder (mixed powder A) (hereinafter also referred to as "mixed powder B"), and a powder of a silicon alloy n-type semiconductor made of silver, barium, and silicon (hereinafter also referred to as "n-type powder") are sequentially laminated.

[0036] The p-type powder and the n-type powder may have the same composition as the Ag-Ba-Si alloy that will be the target p-type and n-type semiconductors, respectively. Also, the mixed powders A and B may have the same composition as the Ag-Ba-Si alloy that will form the target unit layer, respectively, and the p-type powder and the n-type powder may be mixed.

[0037] The p-type powder and n-type powder can be produced by any method, but an example of such a method includes a production method including a step of melting a composition containing a silver source, a barium source, and a silicon source (hereinafter also referred to as a "melting step").

[0038] The shape of the raw metal to be subjected to the melting step may be any shape, including at least one of amorphous and powder. A specific example of the shape of the raw metal is a powder having a particle size of 200 μm or less or 150 μm or less. In order to improve operability (handling), the particle size of the raw metal may be 10 μm or more or 50 μm or more.

[0039] The silver source may be at least one of silver and a silver-containing compound. The silver source preferably has a silver purity of 3N or more or 4N or more. A preferred silver source is metallic silver (pure silver).

[0040] The barium source may be at least one of barium and a barium-containing compound. The barium source preferably has a barium purity of 3N or more or 4N or more. A preferred barium source is metallic barium (pure barium).

[0041] The silicon source may be at least one of silicon and a silicon-containing compound. The silicon source preferably has a silicon purity of 3N or more or 4N or more. Preferred silicon sources include metal silicon (pure silicon) and amorphous silicon.

[0042] The composition to be subjected to the melting step only needs to contain the starting materials so as to obtain the atomic ratios of silver, barium, and silicon of the desired Ag-Ba-Si alloy, and the starting materials may be mixed by any method as necessary.

[0043] The mixing method may be any method, and examples thereof include at least one of wet mixing and dry mixing.

[0044] In the melting step, the composition is melted. This produces a raw material melt. The melting method may be one or more methods selected from the group consisting of arc melting, air melting, high frequency melting, plasma melting, skull melting, zone melting, and electron beam melting. The melting method is preferably arc melting, since it allows melting in a short time, allows atmosphere control, and causes less contamination from the crucible (copper mold).

[0045] In the arc melting, the current value per unit mass of the composition to be treated (hereinafter, simply referred to as "current value") is preferably 30 A / g or more or 50 A / g or more. This allows the melting process to be completed in a short time. In order to suppress the compositional fluctuation of the composition during the arc melting, the current value is preferably 150 A / g or less or 120 A / g or less.

[0046] The holding time at the above-mentioned current value may be appropriately adjusted according to the amount of composition to be treated and the performance of the arc melting furnace to be used, and may be, for example, 0.5 minutes or more or 1 minute or more and 5 minutes or less or 3 minutes or less.

[0047] In order to efficiently melt the composition, the treatment with the above-mentioned current value and holding time may be carried out multiple times, and the treatment may be carried out two or more times, or three or more times. The treatment does not need to be carried out more than necessary, and may be carried out five or four times or less.

[0048] The molten raw material after arc melting may be cooled by any method and recovered, or may be cooled by quenching. Quenching is a process for instantaneously solidifying the molten raw material in a fluid state (so-called molten state). This results in a molten mixture being obtained as a quenched ribbon. A known method may be used for the quenching method, and for example, a method in which a cooling rate of 1×10 5 K / s or more 1×10 6 A specific example of the cooling method is to bring the raw material melt in a fluid state into contact with water-cooled rollers.

[0049] If necessary, the molten raw material may be pulverized or granulated, so that the shape and size of the molten raw material can be made arbitrary.

[0050] The laminated powder can be obtained by laminating p-type powder, mixed powder A, mixed powder B, and n-type powder by any method. For example, the n-type powder is filled into a mold to be subjected to heat treatment, the surface is smoothed, and then mixed powder A is filled on the n-type powder and the surface is smoothed. The same operation is repeated to laminate mixed powder B and n-type powder in order.

[0051] The mass ratio of each powder contained in the laminated powder is arbitrary, but when the total mass of the laminated powder is 100 mass%, for example, n-type powder: mixed powder A: mixed powder B: p-type powder = 30-40: 10-20: 10-20: 30-40.

[0052] In the firing step, the laminated powder is heat-treated at 650°C or more and 950°C or less. If the temperature is less than 650°C, the densification of the laminated powder does not progress. On the other hand, if the heat treatment temperature exceeds 950°C, the laminated powder will fuse with the members of the firing device used for the treatment (e.g., a hot press mold), and the laminated body of this embodiment cannot be obtained. The temperature is preferably 700°C or more or 750°C or more and 920°C or less, and more preferably 700°C or more and 920°C or less.

[0053] The sintering may be any treatment that sinters the laminated powder, and is preferably pressure sintering, more preferably at least one of hot pressing, hot isostatic pressing, and discharge plasma sintering, and even more preferably discharge plasma sintering.

[0054] Hereinafter, firing will be described by taking a discharge plasma firing (hereinafter also referred to as "SPS") treatment as an example.

[0055] SPS is a process in which laminated powder is sintered by applying pressure to it and passing electricity directly through it. By sintering while applying pressure, it is possible to heat to high temperatures in a short time. This allows for a dense laminated body to be obtained without the grain size becoming coarse.

[0056] The pressure applied to the laminated powder in the SPS treatment may be 10 MPa or more, or 25 MPa or more, and may be 100 MPa or less, or 80 MPa or less, and is preferably 25 MPa or more and 80 MPa or less.

[0057] The atmosphere in the SPS process can be a vacuum, with a vacuum level of 5.0×10 -3 Vacuum atmosphere of less than 1.0×10 Pa, and even vacuum of less than 1.0×10 -3 Pa or more 5.0×10 -3 It is preferable that the atmosphere be a vacuum of 10 Pa or less.

[0058] The treatment temperature in the SPS treatment is 650° C. or higher, preferably 700° C. or higher or 750° C. or higher, and preferably 950° C. or lower or 900° C. or lower.

[0059] The rate of temperature rise to the treatment temperature is arbitrary, but may be, for example, 50° C. / min or more and 300° C. / min or less.

[0060] The holding time at the above-mentioned treatment temperature may be appropriately adjusted depending on the amount of the laminated powder to be treated and the performance of the SPS furnace to be used, and may be, for example, 15 minutes or less or 12 minutes or less. In order to heat the inside of the laminated powder uniformly, the holding time may be 1 minute or more or 5 minutes or more. The manufacturing method of this embodiment may include a step of processing the obtained laminate (hereinafter, also referred to as a "processing step"). In the processing step, the thermoelectric conversion material is processed into a shape according to the purpose, such as a thermoelectric conversion element. The processing method may be a known method applied to alloy processing, and examples thereof include one or more grinding methods selected from the group consisting of a surface grinding method, a rotary grinding method, and a cylindrical grinding method.

[0061] [Thermoelectric materials and thermoelectric elements] The laminate of this embodiment can be used as a thermoelectric conversion material including the laminate, and can also be used as a thermoelectric conversion element including the thermoelectric conversion material of this embodiment. In this embodiment, the "thermoelectric conversion material" is a material that enables direct conversion of thermal energy into electrical energy, and the "thermoelectric conversion element" is an element that includes a p-type thermoelectric conversion material and an n-type thermoelectric conversion material, and generates an electromotive force when a high-temperature substance is brought into contact with one thermoelectric conversion material and a low-temperature substance is brought into contact with the other thermoelectric conversion material, and includes a so-called isothermal thermoelectric element in which the temperature difference between the two thermoelectric conversion materials is very small. Since the laminate of this embodiment includes a p-type thermoelectric conversion material (p-type semiconductor layer) and an n-type thermoelectric conversion material (n-type semiconductor layer), it may be considered as a thermoelectric conversion material itself.

[0062] In addition, the laminate of this embodiment generates an electromotive force even when the temperature difference between the p-type thermoelectric conversion material (p-type semiconductor layer) and the n-type thermoelectric conversion material (n-type semiconductor layer) is very small, and is therefore suitable as a thermoelectric conversion material that generates an electromotive force even when the temperature difference between the thermoelectric conversion materials is 0°C or higher and 0.5°C or lower, or even 0°C or higher and 0.2°C or lower, i.e., a so-called isothermal thermoelectric conversion material.

[0063] The thermoelectric conversion element including the laminate of this embodiment may have a structure in which a p-type semiconductor layer and an n-type semiconductor layer are connected by electrodes.

[0064] The thermoelectric conversion element including the laminate of this embodiment can be used as a thermoelectric conversion module in which the thermoelectric conversion element is integrated. The thermoelectric conversion module may be any type of module depending on the purpose, and may be, for example, one or more selected from the group consisting of a single-stage thermoelectric conversion module, a cascade module, and a segment module, or may be a single-stage thermoelectric conversion module. The term "thermoelectric conversion module" refers to a module in which two or more thermoelectric conversion elements are integrated. EXAMPLES

[0065] The present disclosure will be described below with reference to examples. However, the present disclosure is not limited thereto.

[0066] (crystalline phase) The alloy samples were subjected to XRD measurement using a general powder X-ray diffraction device (device name: RINT UltimaIII, manufactured by RIGAKU Corporation). The measurement conditions were as follows: Acceleration current / voltage: 40mA / 40kV Radiation source: CuKα radiation (λ=1.5405Å) Measurement mode: Continuous scan Scan condition: 5° / min Measurement range: 2θ=20° to 50° Divergence vertical limit slit: 10mm Divergence / entrance slit: 1° Receiving slit: open Detector: D / teX Ultra Ni filter used

[0067] The obtained X-ray diffraction pattern was smoothed and background removed using an analysis program (software name: PDLX2, manufactured by RIGAKU) attached to the X-ray diffractometer, and the X-ray diffraction pattern after these processes was profile-fitted using a split pseudo-Voigt function. The crystalline phase of the alloy sample was identified by comparing the X-ray diffraction pattern after the fitting with the X-ray diffraction pattern on the PDF card (01-086-0810).

[0068] (composition) The composition of the samples was measured by ICP-MS mass spectrometry using a general ICP-MS device (Device name: Vista-PRO, manufactured by Seiko Instruments). As a pretreatment, the alloy samples were dissolved in hydrofluoric acid and sulfuric acid, and the resulting acid solution was used for the measurement.

[0069] (Relative Density) True density [g / cm 3 ] vs. measured density [g / cm 3The relative density of the laminate was calculated from the ratio [%] of [1] to [2]. The true density was calculated from the composition measured by the above method using the above formula (1). The measured density was the bulk density measured by a method conforming to JIS R 1634. Prior to measuring the density, the laminate was pretreated by a vacuum method using kerosene as a solvent.

[0070] (Electric resistance and electromotive force) Using a resistivity / Hall measurement system (device name: ResiTest8400, manufactured by Toyo Corporation) equipped with a Seebeck coefficient measurement option, probes were connected to the p-type semiconductor layer and the n-type semiconductor layer to measure the electrical resistance under the following conditions, and the electromotive force was measured by measuring the voltage between the probes. The measurement samples used were the laminates obtained in the examples and comparative examples, each processed into a flat plate of length 6 mm x width 10 mm x thickness 1 mm.

[0071] Electrode: Platinum electrode Measurement atmosphere: Vacuum atmosphere Measurement temperature: 150℃ Example 1 Metallic silicon (irregular silicon; purity 4N, average size 1cm, product name: SIE01GB, manufactured by Kojundo Chemical Co., Ltd.), metallic silver (pure silver; purity 3N, average particle size 1mm, product name: AGE08PB, manufactured by Kojundo Chemical Co., Ltd.), and metallic barium (barium; purity 99%, average size 2cm x 1mm, product name: BAE01GB, manufactured by Kojundo Chemical Co., Ltd.) were weighed out so that the atomic ratio was Ag:Ba:Si = 18:36:46. The weighed raw materials were filled into a water-cooled mold, and then arc-melted using an arc melting furnace (equipment name: ACM-S01, manufactured by Daia Vacuum Co., Ltd.) under the following conditions to obtain a p-type silicon alloy. Arc melting time: 1 minute x 3 times Output: 60A / g

[0072] The obtained p-type silicon alloy was pulverized in a mortar to obtain a p-type powder.

[0073] Next, n-type powder was obtained in the same manner as for the p-type powder, except that each raw material was weighed so that the atomic ratio of Ag:Ba:Si was 17:33:50. The p-type powder and the n-type powder were dry-mixed so that the mass ratio was 1:1 to obtain a mixed powder (mixed powder 1) with an n / (n+p) ratio of 0.50. Next, the p-type powder and the n-type powder were mixed in a mortar so that the mass ratio was 2:1 to obtain a mixed powder (mixed powder 2) with an n / (n+p) ratio of 0.33.

[0074] A circular carbon mold with a diameter of 10 mm was filled with n-type powder and the surface was smoothed. Then, mixed powder 1 was filled on top of the n-type powder and the surface was smoothed. The same operation was repeated to layer the n-type powder, mixed powder 1, mixed powder 2, and p-type powder in that order. The mass ratio of each powder used for layering was n-type powder:mixed powder 1:mixed powder 2:p-type powder=37:15:11:37.

[0075] The laminated powder was then subjected to discharge plasma sintering under the following conditions: Temperature was measured using a radiation thermometer (product name: IR-AHS, manufactured by Chino Corporation). Heating rate: 200℃ / min (up to 600℃) 100℃ / min (600℃~holding temperature) Vacuum degree: 5.0×10 -3 Pa Holding temperature: 900℃ Holding time: 10 minutes Holding pressure: 75MPa

[0076] After plasma firing, the laminate was cooled under the following conditions to obtain a four-layer laminate having an n-type semiconductor layer, a mixed layer, a mixed layer, and a p-type semiconductor layer stacked in order, which was used as the laminate of this embodiment. After holding, the pressure was reduced at a constant depressurization rate to 37.5 MPa by 600°C. Cooling rate: 15℃ / min (600℃~900℃) Cool (up to 600℃) Holding pressure: 37.5MPa Depressurization speed: 1.875MPa / min

[0077] Each layer constituting the laminate of this embodiment has a thickness corresponding to the mass ratio, and the relative density is 96.2%. In addition, as a result of observing each layer by EBSD measurement, it was confirmed that all layers are composed of AgBa2Si3 crystal phase (space group 70) containing barium phase with an area ratio of 0.0005 to 0.0015.

[0078] Example 2 The laminate of this example was obtained in the same manner as in Example 1, except that the p-type powder was obtained by weighing out the materials so that the atomic weight ratio was Ag:Ba:Si = 17:37:46, the n-type powder was obtained by weighing out the materials so that the atomic weight ratio was Ag:Ba:Si = 18:33:49, the p-type powder and the n-type powder obtained in place of mixed powder 1 were mixed in a mass ratio of 1:1 to obtain a mixed powder (mixed powder 3) having an n / (n + p) ratio of 0.50, the p-type powder and the n-type powder obtained in place of mixed powder 2 were mixed in a mass ratio of 2:1 to obtain a mixed powder (mixed powder 4) having an n / (n + p) ratio of 0.33, and the n-type powder, mixed powder 1, mixed powder 3, and p-type powder were stacked in a mass ratio of 33:15:19:33 to obtain a laminate consisting of four layers.

[0079] [Table 1]

[0080] From Table 1, it was confirmed that the laminate of this example functions as a thermoelectric conversion material that generates an electromotive force with a temperature difference of 0.5° C. or less.

[0081] Comparative Example 1 The laminate of this comparative example was produced in the same manner as in Example 1, except that a two-layer laminate was obtained by stacking n-type powder and p-type powder obtained in the same manner as in Example 2 in a mass ratio of 50:50.

[0082] In this comparative example, cracks occurred at the junction interface between the p-type semiconductor and the n-type semiconductor, and a laminate capable of measuring electromotive force and the like could not be obtained.

[0083] Comparative Example 2 The laminate of this comparative example was produced in the same manner as in Example 1, except that a three-layer laminate was obtained by stacking the p-type powder obtained in the same manner as in Example 1, the mixed powder 1, and the n-type powder in a mass ratio of 45:10:45.

[0084] In this comparative example, cracks occurred at the junction interface between the p-type semiconductor and the n-type semiconductor, and a laminate capable of measuring electromotive force and the like could not be obtained.

Claims

1. A p-type semiconductor layer, a mixed semiconductor layer containing a p-type semiconductor and an n-type semiconductor, and an n-type semiconductor layer are laminated in this order, and The mixed semiconductor layer has a structure in which two or more unit layers are stacked, and is a silicon alloy layer made of silver, barium, and silicon.

2. 2. The laminate according to claim 1, wherein the mass ratio of the n-type semiconductor to the total mass of the n-type semiconductor and the p-type semiconductor of the unit layer directly stacked on the n-type semiconductor layer is smaller than the mass ratio of the n-type semiconductor to the total mass of the n-type semiconductor and the p-type semiconductor directly stacked on the p-type semiconductor layer.

3. 3. The laminate according to claim 1, wherein the mass ratio of the n-type semiconductor to the total mass of the n-type semiconductor and p-type semiconductor of the unit layer directly stacked on the n-type semiconductor layer is 0.45 or more.

4. 3. The laminate according to claim 1, wherein the silicon alloys constituting the p-type semiconductor layer, the unit layer, and the n-type semiconductor layer each have a composition in which the atomic ratios thereof satisfy the following when the total atomic weight of silver, barium, and silicon is 100 at %: Silver: 9 at% or more or 15 at% or more, and 27at% or less Barium: 20 at% or more or 30 at% or more, and 53 at% or less or 45 at% or less Silicon: 29 at% or more or 32 at% or more, and 64 at% or less or 52 at% or less

5. A thermoelectric conversion material comprising the laminate according to claim 1 or 2.

6. A thermoelectric conversion module comprising the laminate according to claim 1 or 2.

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