Driving method for display device

Abstract

To provide a display device that can display a plurality of images in an overlapping manner using a plurality of memory circuits included in a pixel.SOLUTION: A plurality of memory circuits are provided in a pixel, and signals according to images to be overlapped for the respective memory circuits are kept. To the pixel, the images according to images to be overlapped for the respective memory circuits are applied. The signal is applied to the signal held in the memory circuit by capacitive coupling. A display element can display an image according to the signals resulting from the addition of the signals written in the pixel through the wire to the signals held in the memory circuits. The amount of arithmetic processes for displaying the images in the overlapping manner can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device, a driving method of the display device, and an electronic device. [Background technology]

[0002] The pixels each have a built-in memory circuit, arithmetic processing circuit, and display processing circuit, and can synthesize multiple image data. A display device capable of performing this is known (see, for example, Patent Document 1).

[0003] It is desirable for a display device to have high image quality. For example, in Patent Document 2, a gradation number consisting of multiple bits is increased. A driving unit is provided that drives pixels using a driving interval according to the modulation code and the weight of each bit number. The present invention relates to a display device that can correct the brightness of pixels to change smoothly. It is disclosed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2003 / 0098875 [Patent Document 2] US Patent Application Publication No. 2013 / 0076801 Summary of the Invention [Problem to be solved by the invention]

[0005] In a configuration where image synthesis is performed using an in-pixel arithmetic processing circuit, the amount of calculations required increases with the increase in image data. In addition, the voltage amplitude of the signal that can be input to the pixel is increased. However, due to limitations in the display, it is difficult to display a high dynamic range. .

[0006] In addition, in a configuration in which a signal such as a gray scale code is combined with a drive interval, the drive of the display device On the other hand, the number of gradations that can be displayed by a pixel depends on the number of bits that the source driver can output. Therefore, the source driver can output the signal that it can output. It has been difficult to display more gradations than the number of bits possible with pixels.

[0007] In one embodiment of the present invention, a display is performed with a number of gradations equal to or greater than the number of bits that a source driver can output. Another object of the present invention is to provide a display device that can achieve the above object. Display device capable of synthesizing images within a pixel without increasing the amount of computational processing Another object of the present invention is to provide a method for detecting a signal that can be input to a pixel. By enabling the display of images beyond the voltage swing, a high dynamic range is achieved. It is an object of the present invention to provide a display device which can

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor memory device including a first memory circuit, a second memory circuit, a first transistor, and The pixel includes a first wiring, a second wiring, and a third wiring. The first wiring is electrically connected to the line, and has a function of providing a first signal and a second signal to the pixel. The second wiring has a function of supplying a third signal and a fourth signal to the pixel, and the third wiring The line has a function of providing a fifth signal to the pixel, and the first memory circuit has a function of holding the first signal. the second memory circuit has a function of holding a third signal, and the first transistor The gate of the display element is applied with a voltage obtained by adding the first to fourth signals. This is a display device that has a function of controlling the flow of electric current.

[0010] In one embodiment of the present invention, the first memory circuit includes a second transistor, a third transistor, the second memory circuit has a second transistor, a fourth transistor, and a first capacitance element; A second transistor and a second capacitor are provided. The metal oxide is composed of In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf) and a display device having Positioning is preferred.

[0011] In one embodiment of the present invention, one electrode of the first capacitor is connected to a second transistor. The other electrode of the first capacitor is electrically connected to the first wiring. The second capacitor element is electrically connected to the second wiring via the second transistor. The other electrode of the second capacitor is electrically connected to the first wiring through a fourth transistor. A display device in which the third wiring is electrically connected to the display device through a transistor is preferable.

[0012] In one embodiment of the present invention, a pixel includes a third capacitor element. The electrode of the third capacitance element is electrically connected to the gate of the first transistor, and the other electrode of the third capacitance element is In the display device, the first transistor is preferably electrically connected to one of the source and the drain of the first transistor. It is.

[0013] In one embodiment of the present invention, the pixel is electrically connected to a fourth wiring for supplying a current to the light-emitting element. The other of the source and the drain of the first transistor is electrically connected to a fourth wiring. A display device connected to the

[0014] In one embodiment of the present invention, the pixel is electrically connected to a fifth wiring having a function of applying a constant potential. The pixel has a fifth transistor, and the source or drain of the fifth transistor One of the inputs is electrically connected to one of the source and drain of the first transistor, The other of the source and drain of the fifth transistor is electrically connected to the fifth wiring. A display device is preferred.

[0015] In one embodiment of the present invention, the pixel has a sixth transistor. Either the source or the drain is electrically connected to either the source or the drain of the first transistor. The other of the source and drain of the sixth transistor is connected to one of the display elements. A display device electrically connected to the electrodes is preferred.

[0016] In one embodiment of the present invention, the display element is preferably an EL element.

[0017] One embodiment of the present invention is an electronic device including the above-described display device and a camera.

[0018] One embodiment of the present invention is a display device including a first memory circuit, a second memory circuit, and a first transistor. A method for driving a display device having a pixel provided with a transistor, the method comprising: The first memory circuit stores a first signal corresponding to the first image, and the second memory circuit stores a second signal corresponding to the second image. The second signal is stored in the first memory circuit, and the third image is stored in the first memory circuit in which the first signal is stored. adding the third signal to the first signal and generating a second signal A fourth signal corresponding to the fourth image is supplied to the second memory circuit in which the fourth image is stored. A fourth signal is added to the second signal, and a display element displays the first to fourth signals. The present invention relates to a method for driving a display device that displays an image in which the first image, the second image, the third image, and the fourth image are superimposed on each other. .

[0019] One embodiment of the present invention is a semiconductor memory device including a first memory circuit, a second memory circuit, a first transistor, and a pixel having a first pixel for providing a first signal or a second signal; The pixel is electrically connected to a third wiring that provides a reference voltage or a third signal. The pixel is electrically connected to a fourth wiring that provides a reference voltage or a fourth signal. The first memory circuit has a function of storing a first signal, and the second memory circuit has a function of storing a second signal. The first transistor has a function of storing the first to fourth signals. The display device has a function of controlling the current flowing through the display element by applying a voltage to the gate. be.

[0020] One embodiment of the present invention is a display device including a first memory circuit, a second memory circuit, and a first transistor. A method for driving a display device having a pixel provided with a transistor, the method comprising: a first memory circuit for storing a first signal, a second memory circuit for storing a second signal, and supplying a third signal to the first memory circuit in which the second signal is held; providing a fourth signal to the second memory circuit; and By controlling the on / off of the switches of the respective transistor circuits, the first signal, the second signal, and the third signal are output. A signal obtained by adding the first signal and the second signal, a signal obtained by adding the first signal to the third signal, The image is displayed by combining the signal obtained by adding the first signal to the fourth signal and the signal obtained by adding the first signal to the fourth signal. The present invention relates to a method for driving a display device.

[0021] Other aspects of the present invention will be described in the following embodiments. As shown in the drawings. Effect of the Invention

[0022] In one embodiment of the present invention, a display is performed with a number of gradations equal to or greater than the number of bits that a source driver can output. According to another embodiment of the present invention, a display device capable of reducing the amount of calculation processing can be provided. To provide a display device capable of synthesizing images within a pixel without enlarging the display area. Alternatively, one embodiment of the present invention is a method for increasing the voltage amplitude of an image by a voltage exceeding the voltage amplitude of a signal that can be input to a pixel. A display device capable of displaying images with a high dynamic range by enabling the display of One of the aims is to provide

[0023] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0024] [Figure 1] 1A and 1B are a block diagram and a circuit diagram illustrating a configuration example of a display device. [Diagram 2] 1 is a timing chart illustrating an example of the configuration of a display device. [Diagram 3] FIG. 1 is a circuit diagram illustrating a configuration example of a display device. [Figure 4] 1A to 1C are diagrams illustrating an example of the operation of a display device. [Diagram 5] 1A to 1C are diagrams illustrating an example of the operation of a display device. [Figure 6] 1A to 1C are diagrams illustrating an example of the operation of a display device. [Figure 7] FIG. 1 is a circuit diagram illustrating a configuration example of a display device. [Figure 8] FIG. 1 is a circuit diagram illustrating a configuration example of a display device. [Figure 9] FIG. 1 is a block diagram illustrating a configuration example of a display device. [Figure 10] FIG. 1 is a circuit diagram illustrating a configuration example of a display device. [Figure 11] 1 is a timing chart illustrating an example of the configuration of a display device. [Figure 12] FIG. 1 is a circuit diagram illustrating a configuration example of a display device. [Figure 13] 1A to 1C are diagrams illustrating an example of the operation of a display device. [Figure 14] 1A and 1B illustrate a configuration example of a display device. [Figure 15] 1A and 1B illustrate a configuration example of a display device. [Figure 16] FIG. 2 is a diagram illustrating an example of the configuration of a touch panel. [Figure 17] 1A and 1B illustrate a configuration example of a display device. [Figure 18] 1A to 1C illustrate examples of the structure of a transistor. [Figure 19] 1A to 1C illustrate examples of the structure of a transistor. [Figure 20] FIG. 2 is a cross-sectional view showing an example of the configuration of a DOSRAM. [Figure 21] 1A to 1C are diagrams illustrating examples of electronic devices. [Figure 22] 1A to 1C are diagrams illustrating an example of the operation of a display device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, the embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms without departing from the spirit and scope of the invention. It will be readily understood by those skilled in the art that various modifications may be made to the mode and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiment.

[0026] In this specification, the ordinal numbers "first," "second," and "third" refer to the components of the The above is added to avoid confusion, and does not limit the number of components. In addition, the order of the components is not limited. The element referred to as "first" in one embodiment may be used in another embodiment or in the claims. In addition, for example, the second component may be the component referred to in the present specification. A component referred to as "first" in one embodiment may be used in another embodiment, or It may be omitted in the claims.

[0027] In the drawings, elements that are the same or have similar functions, elements that are made of the same material, or In some cases, the same reference numerals may be used to denote elements that are formed simultaneously, and repeated explanations of such elements will be omitted. It may be omitted.

[0028] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings. .

[0029] FIG. 1A shows a block diagram of a display device 100. The display device 100 has a plurality of pixels. The display unit 110 has a gate driver 130 and a data driver 140. do.

[0030] The pixel 111 includes a memory circuit 112 and a memory circuit 113. Although not shown, the pixel 111 includes a display element and a transistor for driving the display element. The pixels 111 are connected to a gate driver 130 via a plurality of wirings GL. The pixel 111 is supplied with a signal to control the driving. Signals are given via a number of wirings DL to control the driving.

[0031] The wirings GL function as scanning lines. The signals transmitted by the wirings GL are scanning signals. The scanning signal is also called a control signal. The transistor that functions as a switch is controlled to be in a conductive or non-conductive state (on or off). The signal transmitted through the wiring GL is output from the gate driver 130. do.

[0032] The multiple wirings DL function as data lines. The signals transmitted by the wirings DL are data The data signal is also called image data or image signal. The data signal is a signal for displaying an image. In addition to the signal held in the memory circuit 113, the signal is also stored in the memory circuit 112 and the memory circuit 113. In the state where the signal is held, a signal is applied later. It functions as a wiring for providing a necessary voltage, for example a reference voltage. The signal is output from the data driver 140.

[0033] The memory circuit 112 and the memory circuit 113 each include a capacitor and a transistor. The memory circuit 112 and the memory circuit 113 convert a signal given via the wiring DL into a charge ( The memory circuit 112 and the memory circuit 113 is a circuit that applies a different signal via the wiring DL to the potential held later. It has the function of holding the voltage obtained by adding up the potentials of the written signals. The signals can be summed by utilizing the capacitive coupling in the memory elements. The line 112 and the memory circuit 113 convert a signal given through the wiring DL into a charge and Holding a signal to a child is also called holding a signal.

[0034] In this specification, a pixel refers to, for example, one element whose brightness can be controlled. Therefore, as an example, one pixel refers to one color element, and one of the color elements Therefore, the brightness is expressed by the color components R (red), G (green), and B (blue). In the case of a color display device, the smallest unit of an image is a triplet of an R pixel, a G pixel, and a B pixel. In this case, each of the RGB pixels is a sub-pixel. ) and the RGB pixels together are called a pixel.

[0035] Next, FIG. 1B illustrates a configuration example of the pixel 111. Transistor 114, transistor 117, transistor 118, transistor 120, A resistor 121, a transistor 122, a capacitor 115, a capacitor 116, and a capacitor 119. 1B, the gate of the transistor 120 is The connected node is shown as node NM. Although the transistors shown are all n-channel, p-channel transistors are also used. It is also possible.

[0036] The transistor 120 has a function of controlling the amount of current flowing to the light-emitting element 123. The transistors other than the transistor 120 function as switches. The memory circuit includes a capacitor 115, a transistor 114, and a transistor 117. The path 113 includes a capacitive element 116 , a transistor 114 , and a transistor 118 . The memory circuits 112 and 113 each hold a charge in one electrode of a capacitance element. In order to add up the signals, the transistors 117 and 118 are There are cases where the circuit 112 and the memory circuit 113 are not included.

[0037] In FIG. 1B, the wiring GL shown in FIG. 1A is represented by wiring GL_1, wiring GL The wiring GL_1, wiring GL_2, and wiring GL_3 are illustrated. L_3 is a signal to control the on / off of a transistor that acts as a switch. to the pixel 111.

[0038] In FIG. 1B, the wiring DL shown in FIG. 1A includes wiring DL_1, wiring DL The wiring DL_1 and the wiring DL_2 are used for displaying images. The wiring DL_R has a function of transmitting a signal for driving the pixel 111. It also functions as wiring to provide the reference voltage required for operation.

[0039] The capacitance element 115 or the capacitance element 116 is connected to the memory circuit 112 or the memory circuit 113. The capacitor 115 or the capacitor 11 has a function of holding a signal to be written as a charge. A transistor 114 is electrically connected to one electrode or the other electrode of the transistor 16. When the capacitor 115 or the capacitor 116 is turned on, the capacitor 117 and the transistor 118 are turned on. The electrode of the capacitance element 116 has a function of holding a charge according to a signal. 4, the transistor 117 and the transistor 118 are turned off, so that the capacitance element 1 The transistor 11 has a function of storing charge in the electrode of the transistor 15 or the capacitor 116. 4, the transistor 117 and the transistor 118 are turned off, so that the capacitance element 1 15 or the node of one electrode of the capacitor element 116 is in an electrically floating state (floating). It has the function of

[0040] As shown in FIG. 1B, one electrode of the capacitor 115 is connected to the transistor 114. The other electrode of the capacitor 115 is connected to the wiring DL_R through the transistor 117. One electrode of the capacitor 116 is connected to the wiring DL_1 through the transistor 11. The other electrode of the capacitor 116 is connected to the wiring DL_R via the transistor 1 18 and is connected to the wiring DL_2.

[0041] Transistors 114, 117, and 118 conduct current when turned off. It is preferable that the current (off-state current) that flows through the transistor is low. This allows the potential of the node NM to be held for a long time. For example, a transistor using a metal oxide for the channel formation region (hereafter referred to as an OS transistor) ) can be used. As the metal oxide, In, Zn, and M (M is Al, Ti, The composition has the following elements: Ga, Sn, Y, Zr, La, Ce, Nd or Hf. The transistor will be described in detail in a later embodiment.

[0042] The capacitance element 119 has a function of holding the voltage between the gate and source of the transistor 120. One electrode of the capacitor 119 is connected to the gate of the transistor 120. The other electrode of the capacitor 119 is connected to one of the source and drain electrodes of the transistor 120. The other of the source and drain of the transistor 120 (the drain side) is connected to the The wiring AL is connected to a voltage supply for supplying a current to the light emitting element 123. The wiring AL functions as a current supply line or an anode line.

[0043] The transistor 121 is connected to the wiring VL and one of the source and drain of the transistor 120. It functions as a switch that controls the conduction state between the source side and the drain side. The source or drain of the transistor 121 is connected to the source or drain of the transistor 120. The other of the source and the drain of the transistor 121 is connected to the wiring VL. The wiring VL is a wiring for applying a constant potential (V0). The transistor 120 may have a function for outputting the current flowing through the transistor 120 to the outside. By using this configuration, it is possible to periodically monitor the current flowing through the transistor 120. Therefore, correction according to the variation of the transistor 120 can be performed.

[0044] The transistor 122 is connected to either the source or drain of the transistor 120 (the source side ) and one electrode of the light-emitting element 123. The source or drain of the transistor 122 is connected to the The source or drain of the transistor 122 is connected to The other electrode of the light emitting element 123 is connected to one of the electrodes of the light emitting element 123. The transistor is connected to the line 124. The line 124 functions as a cathode line. 122 indicates that the potential of the node NM is equal to the threshold voltage (V th ) or more This element is used to prevent problems such as unintended current flow when In other words, the transistor 122 is turned on during a period other than the period during which a current flows through the light emitting element 123 (light emitting period). The switch functions as a switch for preventing a current from flowing. To hold a charge on the gate of the transistor 120 and superimpose the signals, The potential of the node NM is likely to rise. Therefore, a structure is provided to prevent the light emitting element 123 from emitting light. The light emitting element 123 is a display device whose luminance can be controlled according to the amount of current flowing therethrough. For example, an organic EL element can be used.

[0045] One embodiment of the present invention provides a method for supplying signals for displaying an image to pixels and storing the signals in a plurality of memory circuits. The pixel is then supplied with multiple signals to display different images. ) holds the signals for displaying an image in two memory circuits, and wires D A structure in which a plurality of signals for displaying a different image are supplied to the pixels from the wiring L_1 and the wiring DL_2 It is completed.

[0046] With this configuration, two other signals are stored in a memory circuit. The current flowing through the light-emitting element is controlled based on a signal corresponding to the four image-based signals. Therefore, in a display unit having such pixels, four signals can be controlled. This allows the display of images based on the above-mentioned two types of pixels, which can be integrated into a single pixel. This is a simpler configuration than the configuration in which the image is captured by the pixel without increasing the amount of calculation processing. In addition, it is possible to synthesize a potential higher than the potential that the source driver etc. can generate. Since an image corresponding to the image signal can be displayed on a display device, the dynamics of the display device can be improved. It can improve cleanliness.

[0047] The timing charts shown in FIGS. 2A and 2B and the circuits shown in FIGS. 3A to 3C An example of a method for driving the pixel 111 will be described with reference to the drawings. 2 and the write operation of a signal to be held in the memory circuit 113. An image is generated by adding another signal to the signals held in the memory circuits 112 and 113. The figure shows the operation when superimposing the two images. In the timing chart, the wiring GL_1 to GL_3, DL_1, DL_2 and DL_R are The signal waveform to be applied is shown.

[0048] In addition, the signal supplied to the wiring DL_1 is W 1 and stored in the memory circuit 112 by a signal. The voltage held by the line DL_2 is Vw1. 2 Then, at the signal Therefore, the voltage held in the memory circuit 113 is Vw2. The signal dat is written to the pixel 111 through the wiring DL_1 while the voltage Vw1 is maintained. a_1, and the voltage applied to the memory circuit 112 by the signal is Vdata1. In addition, when the voltage Vw2 is held in the memory circuit 113, the pixel 111 is supplied with the voltage Vw2 through the wiring DL_2. The signal to be written is data_2, and the voltage applied to the memory circuit 113 by the signal is Let Vdata2.

[0049] First, the signals to be held in the memory circuit 112 and the memory circuit 113 will be described with reference to FIG. W 1 , W 2 The write operation of FIG. 2(A) and FIG. 2(B) will be described. For the sake of simplicity, the following description will be given with reference to the circuit diagrams in FIGS. 3(A) to 3(C). 1(B) to (C) show the main parts of the circuit diagram of FIG. The transistors functioning as switches are switches SW1 to SW4, and the capacitance elements 115 and 11 The capacitances of 6 and 119 are shown as C1, C2, and C3. SW1 to SW4 correspond to the transistors 117, 118, and 119 in FIG. The transistors 114 and 121 correspond to each other.

[0050] A signal W is input to the memory circuit 112 and the memory circuit 113. 1 , W 2 Based on voltage Vw1, Vw When writing 2, the wiring DL_1 is set to a voltage Vw1, the wiring DL_2 is set to a voltage Vw2, and The line DL_R is set to Vref (reference voltage), and the line VL is set to voltage V0. The Vref applied to the line DL_R is determined so that Vref-Vw1 is a positive value. In addition, in the case of image data, it is preferable to supply inverted data to the voltage Vw1. With the potential of each wiring set to the expected voltage, The signal applied to the line GL_1 and the wiring GL_2 is set to H level. Then, the switches SW1 to SW4 are turned on as shown in FIG. At this time, the voltages Vref and Vw1 are applied to the electrode of the capacitance element 115 on the node NM side. If the amount of accumulated charge is Q1, then it is expressed as follows:

[0051] Q1 = C1 (Vref - Vw1) (1)

[0052] Similarly, at this time, the capacitance elements 115 and 119 are stored in the electrodes on the node NM side. If the amounts of charge are Q2 and Q3, then we have equations (2) and (3).

[0053] Q2 = C2 (Vref - Vw2) (2)

[0054] Q3 = C3 (Vref - V0) (3)

[0055] Next, the signal W is input to the memory circuit 112 and the memory circuit 113 using FIG. 1 , W 2 While maintaining the voltages Vw1 and Vw2 based on The operation of adding signals data_1 and data_2 to 111 will be described.

[0056] The signals data_1 and data_2 are written to the memory circuit 112 and the memory circuit 113. In this case, the wiring DL_1 is set to Vdata1, the wiring DL_2 is set to Vdata2, and the wiring DL When _R is set to an L level such as VSS and the wiring VL is set to voltage V0, The signal to be supplied to the wiring GL_1 is set to H level, and the signal to be supplied to the wiring GL_2 is set to L level. During the period when the voltages Vdata1 and Vdata2 are written to the memory circuit 113, The signal given to L_3 is set to L level. In other words, as shown in FIG. 3(C), the switch SW 1, SW2 and SW4 are turned on, and switch SW3 is turned off. Then, the capacitance element 115 In this case, one electrode is electrically floating and the voltage of the other electrode changes from Vw1 to vdata1. The voltage of the node NM of the capacitance element 115 is Vg. If the amount of charge stored in the electrode is Q1', then it is expressed as in equation (4). Vg is the capacitance coupling It is a voltage that changes depending on the

[0057] Q1' = C1 (Vg - Vdata1) (4)

[0058] Similarly, at this time, the capacitance elements 116 and 119 are stored in the electrodes on the node NM side. If the charge amounts are Q2' and Q3', then we have equations (5) and (6).

[0059] Q2' = C2 (Vg - Vdata2) (5)

[0060] Q3' = C3 (Vg - V0) (6)

[0061] Between the operations of FIG. 2(A) and FIG. 2(B), the switches SW1 to SW3 are turned on and off at the node NM. Since the charge current is extremely low, the law of conservation of charge holds true, i.e., equation (7) holds true.

[0062] Q1+Q2+Q3=Q1'+Q2'+Q3'(7)

[0063] When equation (7) is solved for Vg, equation (8) holds.

[0064] [Number 1]

[0065] From equation (8), the voltage Vg is calculated by dividing the voltage Vg by the voltage -Vw1, the voltage -Vw2, the voltage Vdata1, and the voltage Vd Since the signal is obtained by adding up the ata2, the signal stored in the memory circuit and the signal to be used later are used. This allows images to be overlaid.

[0066] The display device according to one embodiment of the present invention includes a signal W 1 , W 2 And then write By using the signals data_1 and data_2, up to four images can be superimposed. It can be displayed.

[0067] Specifically, as shown in FIG. 1 After storing the pixel, other signals are written. In the configuration where the signal W 1 is variable, and other signals are fixed. By writing or not writing (=0), the signal W 1 You can view images based on Alternatively, the signal W 1 , W 2 is variable and other signals are fixed. Or, by not writing (=0), the signal W 1 , W 2 Based on the image, i.e. two Alternatively, the image of the signal W can be displayed superimposed. 1 , W 2 , data_ Set 1 as variable and other signals as fixed or not written (=0 ) to signal W 1 , W 2 , the image based on data_1, i.e. three images are overlaid Alternatively, the signal W 1 , W 2 , data_1, data By making _2 variable, the signal W 1 , W 2 , data_1, da It is possible to display an image based on ta_2, i.e., four images superimposed. Signal W 1 , W 2 Since these signals are stored in the memory circuits 112 and 113, It is preferable that the signal be based on image data with a low update frequency.

[0068] A more specific configuration example will be described with reference to Figs. 5 and 6. In Figs. 5 and 6, The present invention is based on the image displayed on the display device by the computer and the object displayed in the image. A display device according to one embodiment of the present invention will be described. In FIG. 5 and FIG. 6, the overlapping of signals in the above description is performed. The registration is described as a superposition of images.

[0069] FIG. 5A shows an image 160. The image 160 includes a display object 161, a display object 5B to 5E, the display object 162, the display object 163, and the display object 164 are also shown. ) shows images 160A to 160D. As shown in FIG. 5A, the objects 161 to 164 are images displayed separately. The display device according to one embodiment of the present invention is configured such that the signal W 1 , W 2 And then By using the signals data_1 and data_2, up to four images can be superimposed. For example, images 160A and 160B shown in FIG. 60B is stored in the memory circuit 112 and the memory circuit 113. 1 and W 2 By 5(D) and (E) are stored as signals data_1 and data_2. 5A ) to write the images 160C and 160D shown in FIG. The image 160 can be displayed superimposed on the image.

[0070] As another image, image 170 is shown in FIG. 5(F). Image 170 has a table The figures show display items 161, 162, 171, and 172. 5(G) and (H) show images 170A and 170B. As shown, 170A and 170B are the display objects 171 and 172 shown in FIG. The display device according to one embodiment of the present invention has an image in which the pixels stored in the memory circuit are displayed separately. Signal W 1 , W 2 Then, by using the signals data_1 and data_2 to be written, Up to four images can be displayed in a superimposed manner. For example, the images shown in Fig. 5(B) and (C) can be displayed in a superimposed manner. The images 160A and 160B to be displayed are stored in the memory circuit 112 and the memory circuit 113. Signal W 1 and W 2 The signals data_1 and data 5(G) and (H) are written as the images 170A and 170B shown in FIG. The desired image, image 170 in FIG. 5(F), can be displayed by superimposing it on the image. The signal W held in the circuit 112 and the memory circuit 113 1 and W 2 By using This is effective in reducing power consumption since it reduces the writing of return images.

[0071] In the examples described with reference to FIGS. 5(A) to 5(H), different objects are superimposed to form a single image. However, one embodiment of the present invention is also effective in other configurations. For example, as shown in FIG. 6, the image 160C is displayed as a signal W stored in a memory circuit. A configuration that retains the signal of a high-luminance image (e.g., an image of the sun) such as 163 is effective. Then, as the signal data to be written later, the display objects 161 to 164 are displayed as in the image 160. The image obtained by writing in a signal containing the above and displaying it overlaid (data+W) is The brightness of the display 163 of the 160HD can be increased (the increased brightness is indicated by the bold line). As described above, one aspect of the present invention is to provide a high-dynamic range (HDR Image processing such as HDR (High Dynamic Range) processing can also be achieved with a simple configuration. It is also possible to include text or other information in the combined display.

[0072] Next, a modified example of the pixel 111 will be described. The pixel 111 is the same as the pixel 1 shown in FIG. The pixel 111A may be configured as a pixel 111 having a transistor 122. This is a configuration that omits the above.

[0073] As described above, the transistor 122 is turned on when the signal written to the node NM is turned on. 0 threshold voltage (V th ) or more. However, if the signal written to node NM is V th If it is limited to a lower value, The resistor 122 can be omitted.

[0074] The pixel 111 may also have the configuration of a pixel 111B shown in FIG. 111B has a configuration in which a back gate is provided for each transistor. The gate is electrically connected to the front gate, which has the effect of increasing the on-current. In addition, a constant potential different from that of the front gate may be supplied to the back gate. By using this structure, the threshold voltage of the transistor can be controlled. In B), a configuration in which all transistors are provided with back gates is shown. Alternatively, the transistor may have no back gate. The configuration having a gate is also effective for other pixel circuits in this embodiment.

[0075] The pixel 111 may also have the configuration of a pixel 111C shown in FIG. The circuit 111C includes a transistor 125 and a capacitor 126 that function as a memory circuit. The memory circuit added to the pixel 111 is connected to the pixel 111 via the wiring DL_3. By adding a memory circuit as shown in Figure 8(A), three or more memories can be The display device may have pixels each equipped with a relay circuit.

[0076] The pixel 111 may also have the configuration of a pixel 111D shown in FIG. In 111D, the function of wiring GL_1 is divided into wiring GL_1A and wiring GL_1B. Transistor 117 and transistor 118, transistor 121 and an additional transistor In this configuration, the memory 127 is controlled by a separate signal. The signals held in the circuit can be selected and used to overlay images.

[0077] FIG. 9A shows a signal conversion circuit 15 in addition to the configuration of the block diagram shown in FIG. 0 and memory circuit 151 are shown.

[0078] When a plurality of images are displayed in a superimposed manner on the display device 100, the memory circuit 1 Signal W to hold at 12, 113 1 , W2 The signal conversion circuit 150 converts the signal into the memory circuit 15 1, converts the image data, and outputs the converted image data to the display device 100.

[0079] In the above description, the pixel 111 has been described. However, in the case of color display, the pixel 11 As shown in FIG. 9B, the pixel 111 has sub-pixels 111R, 111C, and 11D of the three primary colors RGB (red, green, and blue). Each corresponds to 1G and 111B, and multiple sub-pixels are combined to form one pixel. The number of sub-pixels is not limited to three, RGB, as shown in FIG. 9(B), but may be any number as shown in FIG. As shown in the figure, RGBW (red, green, blue, white) sub-pixels 111R, 111G, 111B, and 11 It is also effective to combine 1W to form one pixel.

[0080] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0081] (Embodiment 2) In this embodiment, a configuration example of a display device different from the configuration described in the above-mentioned embodiment 1 will be described. The present embodiment will be described with reference to the drawings. The present embodiment differs from the above-mentioned first embodiment in the following points. The following will provide a detailed explanation, and duplicate descriptions may be omitted.

[0082] FIG. 10 illustrates an example of the configuration of a pixel 111E that can be applied to the pixel 111 in FIG. The pixel 111E includes a transistor M1, a transistor M2, a transistor M4, A transistor M5, a capacitance element C1, a capacitance element C2, a capacitance element C3, and a light-emitting element OLED are In FIG. 10, the node to which the gate of the transistor M2 is connected is referred to as node NM The transistors shown in FIG. 10 are all n-channel transistors. Although a transistor is shown, a p-channel type can also be used.

[0083] The transistor M2 has a function of controlling the amount of current flowing to the light emitting element OLED. The transistors other than the transistor M2 function as switches. The memory circuit ME has a capacitance element C1, a transistor M1, and a transistor M4. M2 includes a capacitive element C2, a transistor M4, and a transistor M5.

[0084] In addition, in FIG. 10, the wiring GL shown in FIG. 1(A) includes wiring GL_1, wiring GL_2, , and wiring GL_3 are illustrated. 3 shows the signal that controls the on or off of the transistor that acts as a switch. It has the function of transmitting the information to the element 111E.

[0085] In FIG. 10, the wiring DL shown in FIG. 1A includes wiring DL_1, wiring DL_2, The wiring DL_1 and the wiring DL_2 are used to display images. The wiring DL_W has a function of transmitting a signal and a reference voltage for the pixel 111E. It has a function of transmitting a signal for displaying an image to the pixel 111E.

[0086] The capacitance element C1 or the capacitance element C2 is connected to the memory circuit MEM1 or the memory circuit MEM2. It has the function of holding the written signal as an electric charge. Capacitor element C1 or capacitor element C2 A transistor M1 is electrically connected to one electrode or the other electrode of the transistor M 4, and the transistor M5 are turned on to turn on the capacitance element C1 or the capacitance element C2. The transistor M1 and the transistor M2 have the function of applying a charge to the electrode according to a signal. 4, and the transistor M5 are turned off to prevent the capacitance element C1 or the capacitance element C2 from being The transistor M1, the transistor M4, and the When the transistor M5 is turned off, one of the electrodes of the capacitance element C1 or the capacitance element C2 is turned off. The function of this pin is to make the node electrically floating.

[0087] As shown in FIG. 10, one electrode of the capacitance element C1 is connected to a transistor M1. The other electrode of the capacitance element C1 is connected to the line DL_1 via the transistor M4. One electrode of the capacitance element C2 is connected to the wiring D through the transistor M5. The other electrode of the capacitance element C2 is connected to the wiring DL through the transistor M4. Connected to _W.

[0088] The transistors M1, M4, and M5 have a current that flows when they are off. It is preferable that the current (off-state current) is low. This allows the potential of the node NM to be held for a long time. , an OS transistor can be used.

[0089] The capacitance element C3 has the function of holding the voltage between the gate and source of the transistor M2. One electrode of the capacitance element C3 is connected to the gate of the transistor M2. The other electrode of C3 is one of the source or drain electrodes (source side) of transistor M2. The other of the source and drain of the transistor M2 (the drain side) is connected to the wiring A voltage is applied to the wiring ANO to cause a current to flow through the light emitting element OLED. The wiring ANO functions as a current supply line or an anode line. Either the source or the drain of the transistor M2 is switched between the wiring to which a fixed potential is applied. In this configuration, a transistor that functions as a switch is preferably provided. During the signal writing period, the voltage at either the source or drain of the transistor M2 is Fluctuations in position can be suppressed.

[0090] One electrode of the light emitting element OLED is connected to one of the source and drain of the transistor M2 ( The other electrode of the light emitting element OLED is connected to a wiring CAT. The wiring CAT functions as a common potential line or a cathode line. An LED is a display element whose brightness can be controlled according to the amount of current flowing through it. For example, an organic EL element In addition, one of the source and drain of the transistor M2 and the A current flows between one of the electrodes of the light-emitting element OLED except during the non-emitting period. A transistor that acts as a switch to prevent the light from emitting light due to the As a display element other than the light-emitting element such as an organic EL element, a liquid crystal element is used. It is also possible.

[0091] One aspect of the present invention is to provide a signal for performing gray scale display output from the source driver 140. The signals are supplied to the pixels and stored in multiple memory circuits, and the signals are stored in multiple memory circuits. A signal for performing gradation display, which is separate from the signal, is supplied to the pixels from the source driver 140. In the example shown in FIG. 10, the two memory circuits are connected to the source driver 140 to perform gray scale display. The signal for performing gradation display is output from the source driver 140. The signal is supplied to the pixels via the wiring DL_1 and the wiring DL_2.

[0092] With this configuration, two other signals are stored in a memory circuit. The current flowing through the light-emitting element can be controlled based on the four added signals. Therefore, a display unit having such pixels can perform display based on four signals. This allows the source driver to output data to each of the two memory circuits in the pixel. In addition to being able to hold a signal with a certain number of bits (e.g. 8bit: 256 gradations), The number of bits that the source driver can output for each of the two signals that will be written to the pixels later (e.g. For example, a configuration can be realized in which a signal of 8 bits (256 gradations) is written to a pixel. Therefore, the total number of gradations of the four signals is 256+256+256+256=1024. A signal with 10 bits of gradation, that is, a signal with more gradation than the number of bits that the source driver can output. In this configuration, the source driver The display device can display an image corresponding to an image signal having a higher potential than the potential that can be generated by the This makes it possible to increase the dynamic range of the display device.

[0093] The timing charts shown in FIGS. 11A and 11B and the timing charts shown in FIGS. An example of a method for driving the pixel 111E will be described with reference to a circuit diagram. The write operation of the signals to be stored in the circuit MEM1 and the memory circuit MEM2 is shown in FIG. In FIG. 1(B), a different signal is applied to the signals held in the memory circuits MEM1 and MEM2. The figure shows the operation when adding a signal and displaying it. In the timing chart shown in FIG. The signal waveform applied to L_W is shown.

[0094] The signals supplied to the wiring DL_W are designated as W1 and W2, and the memory circuit ME The voltage held in M1 is Vw1, and the voltage held in memory circuit MEM2 by the signal is V In addition, when the memory circuit MEM1 is held at a voltage Vw1, The signal to be written to the pixel 111E is data1, and the memory circuit MEM The voltage applied to the memory circuit MEM2 is Vdata1. The signal written to the pixel 111E via the wiring DL_2 in this state is defined as data2. The voltage applied to the memory circuit MEM2 by the signal is designated as Vdata2.

[0095] First, referring to FIG. 11(A), the data stored in the memory circuits MEM1 and MEM2 are The write operation of the signals W1 and W2 will be described. For the sake of simplicity, the following description will be given with reference to the circuit diagrams in FIGS. 12(A) to 12(D) show the main parts of the circuit diagram in FIG. In FIG. 12(A), a transistor that functions as a switch is shown as a configuration corresponding to that in FIG. The switches SW1 to SW4 and the capacitive elements C1, C2, and C3 are shown in the figure. The capacitance of elements C1, C2, and C3 is C 1 ,C 2 ,C 3 It is illustrated as follows. The switches SW1 to SW3 correspond to the transistors M1, M4, and M5 in FIG. The switch SW4 corresponds to the transistor M2 when a signal is written. The switch is used to suppress fluctuations in the potential at either the source or drain. SW4 is a switch that is turned on when writing a signal. line L EL is a wiring that applies a fixed potential Vel.

[0096] A voltage Vw1 based on the signals W1 and W2 is applied to the memory circuit MEM1 and the memory circuit MEM2. When writing Vw2, first set the wire DL_W to voltage Vw1, then set the wire DL_1 to Vref (reference voltage). The potential of the wiring DL_2 is not particularly set. The Vref given to _1 should be determined so that Vw1-Vref is a positive value. It is preferable that the potential of each wiring is set to a predetermined voltage, as shown in FIG. In other words, the signals to be supplied to the wirings GL_1 and GL_3 are set to H level. As shown in the figure, the switches SW1, SW3, and SW4 are turned on. Then, the capacitance element C1 Voltages Vref and Vw1 are applied to the electrodes at both ends. At this time, the node NM If the amount of charge stored in the electrode on the side is Q1, then equation (9) is given.

[0097] Q1=C 1 (Vw1-Vref)(9)

[0098] Next, the wiring DL_W is set to a voltage Vw2, and the wiring DL_2 is set to Vref. The potential of the line DL_1 is not particularly set. The Vref given to the line DL_2 is Vw2- It is preferable to determine the value so that Vref is a positive value. With the voltage set to 100V, as shown at time T2 in Figure 11(A), wires GL_2 and GL_3 are The signal to be applied is set to H level. That is, as shown in FIG. 12(C), W3 and SW4 are turned on. Then, the electrodes at both ends of the capacitance element C2 are charged with voltages Vref and Vw At this time, the amount of charge stored in the electrode of the capacitance element C2 on the node NM side is Q2 This results in equation (10).

[0099] Q2=C 2 (Vw2-Vref)(10)

[0100] At time T2, that is, in the state shown in FIG. 12(C), the switch SW1 is off. The node of one electrode of the capacitance element C1 (node ​​N r1 ) is electrically floating Therefore, at time T2, that is, in the state shown in FIG. 12(C), The charge Q1 held in the electrodes at both ends of the capacitance element C2 continues to be held in the same manner as in equation (9). do.

[0101] The signals W1 and W2 are written at times T1 and T2 in FIG. The data may be written in separate frame periods, or one value may be written in one horizontal scanning period. You may do so.

[0102] Next, using FIG. 11(B), the signal W1 is applied to the memory circuit MEM1 and the memory circuit MEM2. , W2, the voltage Vw1 and the voltage Vw2 are maintained through the wiring DL_1 and DL_2. Next, the operation of adding the signals data1 and data2 to the pixel 111E will be described.

[0103] Write the signals data1 and data2 to the memory circuits MEM1 and MEM2. In this case, the wiring DL_1 is set to Vdata1, the wiring DL_2 is set to Vdata2, and the wiring DL When _W is set to the L level such as VSS, the signal given to the wiring GL_1 and GL_2 is set to the H level. The signal to be applied to the wiring GL_3 is set to L level. Switches SW1, SW2, and SW4 are turned on, and switch SW3 is turned off. One electrode of each of the capacitance elements C1, C2, and C3 is electrically floating, and the capacitance elements C1 and C2 The voltage of the other electrode changes from Vw1, Vw2 to Vdata1, Vdata2, respectively. The voltage of the node NM is Vg. The charge stored in the electrode of the capacitance element C1 on the node NM side is If the capacitance is Q1', then we have equation (11). Vg is the voltage that changes due to capacitive coupling. be.

[0104] Q1'=C 1 (Vdata1-Vg) (11)

[0105] Similarly, the electric current stored in the electrodes of the capacitance elements C2 and C3 on the node NM side is If the loads are Q2' and Q3', then we have equations (12) and (13).

[0106] Q2'=C 2 (Vdata2-Vg) (12)

[0107] Q3'=C 3 (Vg-Vel)(13)

[0108] Between the operations of FIG. 11(A) and FIG. 11(B), at node NM, switches SW1 to SW4 Since the off-state current of is extremely low, the charge conservation principle holds, i.e., equation (7) holds.

[0109] Q1+Q2+Q3=Q1'+Q2'+Q3'(7)

[0110] By solving equation (7) for Vg, equation (14) is obtained. Note that equation (14) is simplified as follows: Therefore, the reference voltages Vref and Vdata1 are set for the voltages Vw1, Vw2, Vdata1, and Vdata2. and Vel are set to 0V, and the capacitance C 1 and C. 2 and the capacitance C 3 is the capacity C 1 and C 2 To It is assumed to be sufficiently small.

[0111] [Number 2]

[0112] From equation (14), the voltage Vg is calculated by the voltage Vw1, the voltage Vw2, the voltage Vdata1, and the voltage Vda Since the signal stored in the memory circuit and the signal to be written later are obtained by adding up ta2, The voltages Vw1, Vw2, and V By writing a signal so that data1 and voltage Vdata2 are negative values, the signal is added. In addition to combining, it is also possible to perform signal subtraction.

[0113] In the display device of one embodiment of the present invention, signals W1 and W2 are stored in a memory circuit, and then written. By using the signals data1 and data2 written to the illuminator, the illuminator can be set based on up to four signals. Therefore, the current flowing through the pixel can be controlled. In the pixel area, it is possible to display images based on four signals. This allows the two memories in the pixel to be The number of bits that the source driver can output for each circuit (e.g. 8bit: 256 gradations) In addition to being able to hold the signal, the two signals that are written to the pixel later can also be stored. The source driver converts this into a signal with the number of bits it can output (for example, 8 bits: 256 gradations), Therefore, it is possible to realize a configuration in which the number of gray levels of the four signals is 2 A signal with 56+256+256+256=1024 levels (10bit), that is, The display is configured to write a number of gradations greater than or equal to the number of bits that the source driver can output. In this configuration, an image signal having a potential higher than the potential that a source driver or the like can generate can be generated. The image corresponding to the signal can be displayed on the display device, improving the dynamic range of the display device. This can improve the quality of your business.

[0114] The effect of the display device according to one embodiment of the present invention described above is shown in a graph in FIG. In the graph shown in FIG. 13, the horizontal axis represents the number of gradations, and the vertical axis represents the output, specifically, the light emission It represents the luminance of the element.

[0115] As described above, in the configuration of one embodiment of the present invention, a maximum of four signals are used to control the light emitting element. For example, the current flowing through the signal W 1 The source driver can output When the signal is written in 8 bits, which is the maximum number of bits that can be written, 1 Only 256 gradations Although it can only express numbers, the output of the source driver such as signals W2, data1, and data2 By combining this with an 8-bit signal, which is the maximum number of bits that can be input, the number of gradations that can be expressed is increased. This makes it possible to display a maximum of 1024 gradations, or the equivalent of 10 bits. .

[0116] Next, a modified example of the pixel 111E will be described. The pixel 111E is shown in FIG. The pixel 111F may have a configuration similar to that of the pixel 111E. This configuration adds the M3 and M6.

[0117] The transistors M3 and M6 are connected to the wiring VL and the source or drain of the transistor M2. It functions as a switch that controls the conduction state between one side of the transistor (the source side). The gate of the transistor M3 is connected to the wiring GL_1. One of the drains is connected to one of the source and drain of the transistor M2. The other of the source and the drain of the transistor M3 is connected to the wiring VL. The gate of the transistor M6 is connected to the wiring GL_2. The first terminal is connected to one of the source and drain of the transistor M2. The other of the source and drain is connected to a wiring VL. The wiring VL is connected to a constant potential, e.g. For example, the wiring is a wiring for applying the voltage Vel described above. The wiring VL is connected to the transistor M2. The device may have a function for outputting the flowing current to the outside. This allows the current flowing through transistor M2 to be monitored periodically. It is possible to perform correction according to the variation of the stam M2.

[0118] Also, the pixel 111F shown in FIG. 14A has the same structure as the pixel 111G shown in FIG. 14B. The pixel 111G can be configured as a pixel 111F shown in FIG. Each transistor has a back gate. It is electrically connected to the back gate, which has the effect of increasing the on-state current. A constant potential different from that of the front gate may be supplied to the gate electrode. The threshold voltage of the transistor can be controlled. Although the figure shows a configuration in which all transistors are provided with back gates, The semiconductor device may have a transistor that is not connected to the semiconductor device.

[0119] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0120] (Embodiment 3) In this embodiment, the details of the OS transistors described in Embodiments 1 and 2 will be described. explain.

[0121] The semiconductor material used in the OS transistor is preferably a material having an energy gap of 2 eV or more. Preferably, a metal oxide having a polarization energy of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium, for example, a CAAC -OS, CAC-OS, etc. can be used. CAAC-OS is the atom that constitutes the crystal. CAC-OS is suitable for transistors that require high reliability. Because it exhibits high mobility characteristics, it is suitable for transistors that operate at high speed.

[0122] OS transistors have a large energy gap and therefore exhibit extremely low off-state current characteristics. In addition, OS transistors have the following problems: impact ionization, avalanche breakdown, and short-channel It has characteristics different from silicon transistors, such as no effect, and forms highly reliable circuits. It is possible.

[0123] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). , titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In-M-Zn oxides containing metals such as In, tin, neodymium or hafnium It may be a membrane.

[0124] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, The atomic ratio of metal elements in the sputtering target used to form a film of the oxide is In≧ It is preferable that M and Zn satisfy the condition M. The atomic ratio of In:M:Zn is 1:1:1, In:M:Zn is 1:1:1.2, and I n:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4 .1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5 The atomic ratio of the semiconductor layers to be formed is preferably 1:1:8. The atomic ratio of metal elements contained in the target varies by ±40%. .

[0125] For the semiconductor layer, an oxide semiconductor having a low carrier density is used. For example, the semiconductor layer Carrier density is 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3 The following is further Preferably 1 x 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Below, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a high-purity intrinsic or This is called a high-purity intrinsic oxide semiconductor. This results in a low impurity concentration and a low defect state density. Since the thermal expansion coefficient is low, it can be said that the oxide semiconductor has stable characteristics.

[0126] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer are determined. It is preferable to appropriately set the density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. stomach.

[0127] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase and the semiconductor layer becomes n-type. The concentrations of com and carbon (obtained by secondary ion mass spectrometry) were 2 × 10 18 ato ms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0128] In addition, when alkali metals and alkaline earth metals combine with oxide semiconductors, they generate carriers. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The resulting concentration is 1 x 10 18 atoms / cm 3 Less than or equal to 2×10 16 at oms / cm 3 To the following:

[0129] In addition, when nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, the electron This causes an increase in carrier density, making it easier to convert to n-type. Transistors using semiconductors tend to be normally-on. The nitrogen concentration in the sample (obtained by secondary ion mass spectrometry) was 5×10 18 atoms / cm 3 It is preferable to do the following:

[0130] The semiconductor layer may have a non-single crystal structure. The non-single crystal structure may have a non-single crystal structure, for example, a structure in which the crystal is aligned along the c-axis. CAAC-OS (C-Axis Aligned Crystallography) ine oxide semiconductor), polycrystalline structure, microcrystalline structure, or non-crystalline structure Among non-single crystal structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0131] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not contain a crystalline component. Alternatively, the oxide film having an amorphous structure is, for example, a completely amorphous structure having no crystalline portion. stomach.

[0132] In addition, the semiconductor layer may have an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAA The film may be a mixed film having two or more of the C-OS region and the single crystal structure region. The composite film may be, for example, a single-layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0133] In the following, a CAC (Cloud-Aligned Crystal) layer, which is one aspect of a non-single crystal semiconductor layer, will be described. This paper explains the structure of the Composite-OS.

[0134] CAC-OS is, for example, an oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. A structure of a material unevenly distributed in a size range of 1 nm to 2 nm or less, preferably 1 nm to 2 nm or less, or in the vicinity thereof. In the following, it is assumed that one or more metal elements are present in the oxide semiconductor. The region having the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixture of particles with sizes of 2 nm or more or less, or close to that size, is also called a mosaic or patch pattern. say.

[0135] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably included. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more elements selected from tantalum, tungsten, magnesium, etc. It's fine.

[0136] For example, CAC-OS in In-Ga-Zn oxide (In- The Ga-Zn oxide may be specifically referred to as CAC-IGZO. (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (GaO X3 (X3 is a real number greater than 0). ), or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 are The material is separated into the mosaic shape, and the mosaic shape is created by dividing the material into the mosaic shape. InO X1 , or InX2 Zinc Y2 O Z2 is uniformly distributed in the film (hereafter , also called cloud-like.

[0137] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Assume that the In concentration is higher than in region 2.

[0138] Note that IGZO is a common name and refers to a compound made of In, Ga, Zn, and O. A typical example is InGaO 3 (ZnO) m1 (m1 is a natural number), or In (1 +x0) Ga (1-x0) O 3 (ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include those that are

[0139] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0140] On the other hand, CAC-OS refers to the material composition of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some of the nanoparticles are observed to be mainly composed of Ga. The regions where the In nanoparticles are observed are the same as those where the In nanoparticles are observed as the main component. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0141] Note that CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, Not at all.

[0142] In addition, GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the region of the main component and the region of the main component may not be observed.

[0143] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium are used. Aluminum, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more of the following elements are included, CAC-OS will The area observed is that of nanoparticles mainly composed of metal elements, and in some areas, nanoparticles mainly composed of In. This refers to a structure in which the regions observed as particles are randomly dispersed in a mosaic pattern. .

[0144] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. Any one or more of the above may be used. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is preferable that the content be 0% or more and 10% or less.

[0145] CAC-OS is a method for measuring X-ray diffraction (XRD). When measured using the out-of-plane θ / 2θ scan, In other words, no clear peaks are observed in the measurement area from the X-ray diffraction. It can be seen that the orientation of the regions in the ab plane direction and the c axis direction is not observed.

[0146] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron beam diffraction pattern obtained by irradiating the sample with light, a ring-shaped region of high brightness and Several bright spots are observed in the ring region. Therefore, the electron diffraction pattern indicates that CAC The crystal structure of -OS has no orientation in the planar direction and cross-sectional direction. It can be seen that the crystalline structure is o-crystal.

[0147] For example, in the case of CAC-OS using In-Ga-Zn oxide, the energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectrometry) The EDX mapping obtained using oscopy revealed that GaO X3 The area where is the main component Area and In X2 Zinc Y2 O Z2 , or InO X1 The areas where the main component is It can be confirmed that the compound has a structure similar to that shown in FIG.

[0148] CAC-OS has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. It has different properties from GZO compounds. That is, CAC-OS is GaO X3 The main components are In a certain area, X2 Zinc Y2 O Z2 , or InO X1 The area where is the principal component and It has a phase-separated structure with a mosaic of regions each consisting of one element as the main component.

[0149] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y2 O Z2 , or InO X1 The carriers flow through the region where the oxide semiconductor is the main component. The electrical conductivity of the conductor is expressed. X2 Zinc Y2 O Z2 , or InO X1 The region mainly composed of ZnO is distributed in a cloud-like shape in the oxide semiconductor, which leads to a high field effect transition. Mobility (μ) can be achieved.

[0150] On the other hand, GaO X3 The area where In etc. are the main components is X2 Zinc Y2 O Z2 , or InO X1 This region has higher insulating properties than the region where GaO is the main component. X3 The main components are The distribution of the regions with the junction structure in the oxide semiconductor suppresses leakage current and provides good switching performance. This allows for realizing a switching operation.

[0151] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by And, In X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ) can.

[0152] In addition, semiconductor devices using CAC-OS have high reliability. is suitable as a constituent material for various semiconductor devices.

[0153] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0154] (Embodiment 4) In this embodiment mode, a configuration example of a display device using an EL element will be described.

[0155] In FIG. 15A, a display unit 215 is provided on a first substrate 4001. A sealant 4005 is provided, and the display portion 215 is disposed between the sealant 4005 and the second substrate 4. Sealed by 006.

[0156] The display unit 215 has a pixel array having the pixels described in the first embodiment.

[0157] The number of pixels provided in the pixel array is 3840 x 2160, 7680 x 43 20 ultra-high definition ("4K resolution", "4K2K", "4K"), Pixels capable of displaying images in super high definition ("8K resolution", "8K4K", "8K") By adopting this configuration, a large display device can be provided with high resolution. The image can be viewed.

[0158] When displaying images such as 8K4K or 4K2K, the driver circuit is It is preferable to arrange the electrodes on both sides of the array to increase the number of wiring lines such as scanning lines and signal lines. By configuring the display in a single pixel configuration, it is possible to reduce signal delays and voltage drops caused by the increase in wiring resistance that accompanies an increase in the number of pixels. It is possible to reduce defects.

[0159] In FIG. 15A, a scanning line driving circuit 221a, a signal line driving circuit 231a, The common line driver circuit 232a and the common line driver circuit 241a are provided on a printed circuit board 4041. The integrated circuits 4042 are made of a single crystal semiconductor or a polycrystalline semiconductor. The signal line driver circuit 231a and the signal line driver circuit 232a are formed of a conductor. The scanning line driver circuit 221a has a function of a gate driver shown in the above embodiment. The common line driver circuit 241a has a function of supplying a specified potential to the common line. Possesses the ability.

[0160] A scanning line driver circuit 221a, a common line driver circuit 241a, a signal line driver circuit 231a, and a signal Various signals and potentials are applied to the line driver circuit 232a via a flexible printed circuit (FPC). The input voltage is supplied via a 4018 printed circuit.

[0161] The integrated circuit 4042 included in the scanning line driver circuit 221a and the common line driver circuit 241a is The signal line driver circuit 231a and the signal line driver The integrated circuit 4042 in the circuit 232a has a function of supplying an image signal to the display unit 215. The integrated circuit 4042 is surrounded by a sealant 4005 on the first substrate 4001. It is implemented in a different area than the area in which it is installed.

[0162] The method of connecting the integrated circuit 4042 is not particularly limited, and may be wire bonding. COG (Chip On Glass) method, TCP (Tape Carrier Package method, COF (Chip On Film) method, etc. can be used. .

[0163] FIG. 15B shows an integrated circuit included in the signal line driver circuit 231a and the signal line driver circuit 232a. An example is shown in which the circuit 4042 is implemented by the COG method. The display unit 215 may be formed integrally on the same substrate to form a system-on-panel. do.

[0164] In FIG. 15B, the scanning line driver circuit 221a and the common line driver circuit 241a are In this example, the driving circuit is formed on the same substrate as the pixel circuit in the display unit 215. By forming the parts at the same time, the number of parts can be reduced, which increases productivity. can.

[0165] In FIG. 15B, the display portion 215 and the scanning line A sealant 4005 is provided to surround the driver circuit 221a and the common line driver circuit 241a. A display unit 215, a scanning line driver circuit 221a, and a common line driver circuit 221b are also provided. A second substrate 4006 is provided on the display unit 215 and the scanning line driver 41a. The circuit 221a and the common line driver circuit 241a are formed on a first substrate 4001 and a sealant 4005. The display element is sealed by the second substrate 4006 and the second substrate 4007 .

[0166] In addition, in FIG. 15B, a signal line driver circuit 231a and a signal line driver circuit 232a are separately 4001 and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as a part of the signal line driver circuit or a scanning line driver circuit. Alternatively, a part of the operating circuit may be formed separately and mounted.

[0167] The display device includes a panel in which a display element is sealed, and a controller for the panel. The term "module" may also include a module on which an IC including a laser is mounted.

[0168] The display portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment may be used as the transistor. can be done.

[0169] Structure of a transistor included in a peripheral driver circuit and a transistor included in a pixel circuit of a display unit The transistors in the peripheral driver circuit may be the same or different. The structures may be the same, or two or more structures may be used in combination. Similarly, the transistors in the pixel circuit may all be of the same structure, or may have two or more different structures. Combinations of structures may also be used.

[0170] As shown in FIG. 16, an input device 4200 is provided on the second substrate 4006. The display device shown in FIG. 15(A) and FIG. 15(B) is provided with an input device 4200. It can function as a chip panel.

[0171] There is no limitation on the detection element (also referred to as a sensor element) included in the touch panel of one embodiment of the present invention. Various sensors that can detect the proximity or contact of a detection object such as a finger or stylus are available. It can be used as a sensing element.

[0172] The sensor type may be, for example, a capacitance type, a resistive film type, a surface acoustic wave type, or an infrared type. Various methods such as a pressure-sensitive method, an optical method, or a pressure-sensitive method can be used.

[0173] In this embodiment, a touch panel having a capacitance type sensing element will be described as an example. do.

[0174] The capacitance type includes the surface capacitance type and the projected capacitance type. The shadow type capacitance method includes the self-capacitance method and the mutual capacitance method. This is preferable because it enables simultaneous multi-point detection.

[0175] The touch panel according to one embodiment of the present invention is formed by bonding a display device and a sensing element that are separately manufactured. A structure in which a substrate supporting a display element and / or an opposing substrate are provided with electrodes constituting a sensing element. Various configurations can be applied, such as a configuration in which a pole or the like is provided.

[0176] 16(A) and (B) show an example of a touch panel. FIG. 16(A) shows a touch panel. 16B is a perspective view of the input device 4200. ,For clarity, only representative components are shown.

[0177] The touch panel 4210 is constructed by bonding a display device and a sensing element that are separately manufactured. It is.

[0178] The touch panel 4210 has an input device 4200 and a display device, which are stacked on top of each other. It is being done.

[0179] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, and a plurality of wirings 423. 7, a plurality of wirings 4238 and a plurality of wirings 4239. For example, the electrode 4227 is a wiring The electrode 4228 can be electrically connected to the wiring 4237 or the wiring 4239. The FPC 4272b can be electrically connected to the wiring 4237 and and electrically connects to each of the plurality of wirings 4238. can be provided.

[0180] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. In the case where a touch sensor is provided between the first substrate 4001 and the second substrate 4006, In addition to capacitive touch sensors, optical touch sensors using photoelectric conversion elements are also used. may be applied.

[0181] FIG. 17 is a cross-sectional view of the portion indicated by the chain line N1-N2 in FIG. 15(B). The display device shown has an electrode 4015, which is connected to a terminal of an FPC 4018. 17, the electrode 4 is electrically connected to the anisotropic conductive layer 4019. 015 is a diagram showing an example of a structure in which an insulating layer 4112, an insulating layer 4111, and an insulating layer 4110 are provided with an opening. The wiring 4014 is electrically connected thereto.

[0182] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. It is formed of a conductive layer.

[0183] The display unit 215 and the scanning line driver circuit 221a provided on the first substrate 4001 are The display unit 215 includes a transistor 40 in FIG. 10 and a transistor 4011 included in the scan line driver circuit 221a. In FIG. 17, the transistors 4010 and 4011 are bottom-gate transistors. However, a top-gate transistor may be used.

[0184] In FIG. 17, an insulating layer 4112 is provided over the transistor 4010 and the transistor 4011. In addition, a partition wall 4510 is formed over the insulating layer 4112.

[0185] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed on an insulating layer 4111. The electrode 4017 functions as a back gate electrode. This can be done.

[0186] The display device shown in FIG. 17 further includes a capacitor 4020. An electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and a source electrode and The capacitor 4020 has a gate electrode and a drain electrode formed in the same process. The electrodes overlap with each other with an insulating layer 4103 interposed therebetween.

[0187] In general, the capacitance of a capacitive element provided in a pixel portion of a display device is determined by the capacitance of a transistor disposed in the pixel portion. The capacitance is set so that the charge can be held for a predetermined period of time, taking into consideration the leakage current of the transistor. The capacitance of the element may be set in consideration of the off-state current of the transistor and the like.

[0188] The transistor 4010 provided in the display portion 215 is electrically connected to a display element.

[0189] The display device shown in FIG. 17 includes an insulating layer 4111 and an insulating layer 4104. The insulating layer 4111 and the insulating layer 4104 are made of an insulating layer that is not easily permeated by impurity elements. The semiconductor layer of the transistor is sandwiched between the insulating layer 4104 and the semiconductor layer 11, so that the intrusion of impurities from the outside is prevented. This can be prevented.

[0190] As a display element included in the display device, a light-emitting element using electroluminescence ( An EL element can be applied. An EL element contains a light-emitting compound between a pair of electrodes. A layer having a voltage higher than the threshold voltage of the EL element is provided between a pair of electrodes. When a large potential difference is generated, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting material contained in the EL layer It glows.

[0191] EL elements are also classified according to whether the luminescent material is an organic compound or an inorganic compound. In general, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0192] When a voltage is applied to an organic EL element, electrons flow from one electrode and positive electrons flow from the other electrode. Holes are injected into the EL layer, respectively. Then, the carriers (electrons and holes) recombine. This causes the light-emitting organic compound to form an excited state, which then returns to the ground state. Due to this mechanism, this type of light-emitting element is called a current-excited light-emitting element. is called a child.

[0193] In addition to the light-emitting compound, the EL layer may also contain a material with high hole injection properties and a material with high hole transport properties. materials, hole blocking materials, materials with high electron transport properties, materials with high electron injection properties, or bipolar The insulating layer may include a material having high electron-transporting and hole-transporting properties.

[0194] The EL layer can be produced by deposition (including vacuum deposition), transfer, printing, inkjet, or coating methods. The above-mentioned method can be used for forming the insulating film.

[0195] Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-based ion exchange reaction that utilizes the donor and acceptor levels. This is an acceptor recombination type emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of metal ions. This is a localized light emission that utilizes organic EL elements. do.

[0196] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. A transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. Top emission structure, which emits light from the top surface of the substrate, and bottom emission structure, which emits light from the bottom surface of the substrate. (bottom emission) structure and dual emission (double emission) structure that emits light from both sides There are light emitting elements having a light-emitting (emission) structure, and light emitting elements having any of the emission structures can be applied.

[0197] FIG. 17 shows a light-emitting display device (also called an "EL display device") that uses light-emitting elements as display elements. The light-emitting element 4513, which is a display element, is a transistor provided in the display portion 215. The light-emitting element 4513 is electrically connected to the first electrode. The layer 4030, the light-emitting layer 4511, and the second electrode layer 4031 are laminated together. The direction of the light emitted from the light emitting element 4513 is not determined. The configuration can be changed as appropriate.

[0198] The partition 4510 is formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4030 using a resin material, and the side of the opening is continuous. It is preferable to form the inclined surface so as to have a curvature.

[0199] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it's

[0200] The color of light emitted by the light emitting element 4513 can be white, red, green, or blue depending on the material that constitutes the light emitting layer 4511. It can be blue, cyan, magenta, or yellow, for example.

[0201] To achieve color display, a light-emitting element (4513) that emits white light is combined with a colored layer. There are two methods: one is to combine the two, and the other is to provide a light-emitting element 4513 with a different light-emitting color for each pixel. The first method has higher productivity than the latter method. On the other hand, the latter method requires a light-emitting layer 451 for each pixel. Since it is necessary to separately make 1, this method is less productive than the former method. However, the latter method In addition to the latter method, the emission color with higher color purity can be obtained. By adding a microcavity structure to the optical element 4513, the color purity can be further improved. This can be done.

[0202] The light-emitting layer 4511 may contain an inorganic compound such as quantum dots. The child dots can be used in a light-emitting layer to function as a light-emitting material.

[0203] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513, the second electrode A protective layer may be formed on the layer 4031 and the partition wall 4510. The protective layer may be formed of silicon nitride. Silicon oxide nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, Forming aluminum oxide nitride, DLC (Diamond Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealant 400 The space sealed by 5 is sealed with a filler 4514. A protective film (lamination film) that is highly airtight and has little outgassing so as not to be exposed to the outside air. It is preferable to package (enclose) the product in a cover material (such as a plastic film or ultraviolet curing resin film). stomach.

[0204] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resins, and polyvinyl chloride. Imide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) or the like can be used. Agents may also be included.

[0205] The sealing material 4005 is a glass material such as glass frit, or a room temperature material such as a two-liquid mixed resin. Resin materials such as photocurable resins, photocurable resins, and thermosetting resins can be used. Furthermore, the sealant 4005 may contain a desiccant.

[0206] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0207] In addition, by making the light-emitting element a microcavity structure, it is possible to extract light with high color purity. In addition, by combining a microcavity structure with a color filter, This reduces interference and improves the visibility of the displayed image.

[0208] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, In the case of the counter electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmitting property or the light reflecting property can be selected depending on the pattern structure of the electrode layer.

[0209] The first electrode layer 4030 and the second electrode layer 4031 are made of indium tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide oxide, indium tin oxide, indium tin oxide with titanium oxide, indium zinc oxide A conductive material having light transmission properties, such as indium tin oxide doped with silicon oxide, is used. This can be done.

[0210] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum (Mo). Mo, Zirconium (Zr), Hafnium (Hf), Vanadium (V), Niobium ( Nb), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Metals such as tungsten (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or an alloy thereof, or a metal nitride thereof.

[0211] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer may be a conductive composition containing a conductive polymer. For this purpose, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives Conductor, or a copolymer of two or more of aniline, pyrrole and thiophene, or Derivatives of the above are also included.

[0212] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the driver circuit is also required. It is preferable that the protection circuit is configured using a non-linear element.

[0213] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0214] (Embodiment 5) In this embodiment mode, the transistors described in the above embodiment modes can be replaced with An example of a transistor that can be implemented will be described with reference to the drawings.

[0215] The display device of one embodiment of the present invention includes a bottom-gate transistor or a top-gate transistor. The present invention can be fabricated using various types of transistors, such as a conventional transistor. The semiconductor layer materials and transistor structures used can be easily replaced to suit the production line. It is possible.

[0216] [Bottom-gate transistor] FIG. 18(A1) shows a channel protection transistor, which is a type of bottom gate transistor. 18A1 is a cross-sectional view of a transistor 810. In FIG. The transistor 810 is formed on a substrate 771 with an insulating layer 772 formed thereon. The semiconductor layer 742 is disposed on the electrode 746 with an insulating layer 726 interposed therebetween. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer. It can function as such.

[0217] In addition, an insulating layer 741 is provided over a channel formation region of the semiconductor layer 742. An electrode 744a and an electrode 744b are provided on the insulating layer 726 in contact with a part of the insulating layer 742. Electrode 744a can function as either a source or drain electrode. A part of the electrode 744a and the electrode 74 A part of 4b is formed on the insulating layer 741.

[0218] The insulating layer 741 can function as a channel protection layer. By providing the insulating layer 1, the exposure of the semiconductor layer 742 that occurs when the electrodes 744a and 744b are formed can be prevented. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer 7 This can prevent the channel formation region 42 from being etched. As a result, a transistor with good electrical characteristics can be realized.

[0219] The transistor 810 has an insulating layer 741 formed on the electrode 744a, the electrode 744b, and the insulating layer 741. A layer 728 is provided, and an insulating layer 729 is provided on the insulating layer 728 .

[0220] When an oxide semiconductor is used for the semiconductor layer 742, at least At least in the portion in contact with the semiconductor layer 742, oxygen is taken from a portion of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material capable of generating oxygen vacancies in the semiconductor layer 742. The resulting region has an increased carrier concentration, which makes it n-type, and the region is called an n-type region (n + layer). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, oxygen is taken from the semiconductor layer 742, causing oxygen vacancies. Examples of materials that can be used include tungsten and titanium. .

[0221] The source region and the drain region are formed in the semiconductor layer 742, whereby the electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the resultant mobility and threshold voltage, can be improved. do.

[0222] When a semiconductor such as silicon is used for the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a Between the semiconductor layer 742 and the electrode 744b, It is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. The MOS transistor can function as a source or drain region of the transistor.

[0223] The insulating layer 729 has a function of preventing or reducing diffusion of impurities from the outside into the transistor. It is preferable to form the insulating layer 729 using a material having the above structure. It is also possible.

[0224] The transistor 811 shown in FIG. 18A2 has an insulating layer 729 over which a backgate electrode is formed. The transistor 810 differs from the transistor 810 in that it has an electrode 723 that can function as a It may be made of the same materials and methods as pole 746 .

[0225] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the gate electrode. The back gate electrode can be made to function in the same manner as the gate electrode. Alternatively, the potential may be a ground potential (GND potential) or an arbitrary potential. By changing the potential of the gate electrode independently of the potential of the gate electrode, the transistor can be The threshold voltage can be varied.

[0226] Both the electrode 746 and the electrode 723 can function as a gate electrode. The insulating layers 726, 728, and 729 each serve as a gate insulating layer. The electrode 723 is provided between the insulating layer 728 and the insulating layer 729. Good too.

[0227] When one of the electrodes 746 and 723 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 811, the electrode 723 is called a "gate electrode." When the term "electrode" is used, the electrode 746 is referred to as the "back gate electrode." When the transistor 811 is used as a top gate electrode, In addition, either the electrode 746 or the electrode 723 can be considered as a "first The first gate electrode is sometimes referred to as the "gate electrode" and the other as the "second gate electrode."

[0228] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, 6 and the electrode 723 are set to the same potential, the region in which carriers flow in the semiconductor layer 742 Since the thickness of the film is larger, the amount of carrier movement increases. As the on-current of the transistor 811 increases, the field effect mobility increases.

[0229] Therefore, the transistor 811 is a transistor having a large on-current relative to its area. That is, the area occupied by the transistor 811 is According to one embodiment of the present invention, the area occupied by a transistor can be reduced. It may be a display device.

[0230] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, the outside of the transistor The function of preventing the electric field generated by the electrostatic discharge from acting on the semiconductor layer in which the channel is formed (especially the electrostatic discharge The back gate electrode is made larger than the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0231] In addition, by forming the back gate electrode with a conductive film having a light shielding property, This prevents light from entering the semiconductor layer from the electrode side. This can prevent deterioration of electrical characteristics such as a shift in the threshold voltage of a transistor. .

[0232] According to one embodiment of the present invention, a display device including a highly reliable transistor can be provided. .

[0233] FIG. 18(B1) shows a channel-protection transistor, which is one of the bottom-gate transistors. 8 shows a cross-sectional view of transistor 820. Transistor 820 is similar to transistor 810. 7, except that an insulating layer 741 covers the edge of a semiconductor layer 742. In addition, a part of the insulating layer 741 overlapping the semiconductor layer 742 is selectively removed to form an opening. In the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a are electrically connected to each other. In another opening formed by selectively removing a part of the insulating layer 741 overlapping the semiconductor layer The insulating layer 741 overlaps the channel forming region and the electrode 744b. This region can function as a channel protection layer.

[0234] The transistor 821 illustrated in FIG. 18B2 has a backgate electrode over the insulating layer 729. The transistor 820 differs from the transistor 820 in that it has an electrode 723 that can function as a transistor.

[0235] By providing the insulating layer 741, the semiconductor generated when the electrodes 744a and 744b are formed can be prevented. Therefore, the layer 742 can be prevented from being exposed during the formation of the electrodes 744a and 744b. This can prevent the semiconductor layer 742 from becoming thin.

[0236] In addition, the transistors 820 and 821 are the same as the transistors 810 and The distance between electrodes 744a and 746 and the distance between electrodes 744b and 746 are larger than the distance between electrodes 744a and 746 and the distance between electrodes 744b and 746. Therefore, the parasitic capacitance between the electrode 744a and the electrode 746 is reduced. In addition, the parasitic capacitance between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. do.

[0237] The transistor 825 shown in FIG. 18C1 is a bottom-gate transistor. The transistor 825 is a channel etched transistor. The electrodes 744a and 744b are formed without using the electrode 744a. When 744b is formed, a part of the semiconductor layer 742 that is exposed may be etched. Since the insulating layer 741 is not provided, productivity of the transistor can be increased.

[0238] A transistor 826 shown in FIG. 18C2 has an insulating layer 729 over which a backgate electrode is formed. The transistor 724 differs from the transistor 825 in that it has an electrode 723 that can function as a transistor.

[0239] [Top-gate transistor] The transistor 842 illustrated in FIG. 19A1 is a top-gate transistor. The electrode 744a and the electrode 744b are formed in the insulating layer 728 and the insulating layer 729. The semiconductor layer 742 is electrically connected in the opening.

[0240] In addition, a portion of the insulating layer 726 that does not overlap the electrode 746 is removed, and the electrode 746 and the remaining insulating layer 726 are separated. Impurities 755 are introduced into the semiconductor layer 742 using the layer 726 as a mask, thereby forming a semiconductor Impurity regions may be formed in layer 742 in a self-aligned manner. Transistor 842 has an area where insulating layer 726 extends beyond the edge of electrode 746. When the impurity 755 is introduced into the semiconductor layer 742, the impurity 755 is introduced through the insulating layer 726 of the semiconductor layer 742. The impurity concentration in the region where the impurity 755 is introduced is determined by the impurity 755 not passing through the insulating layer 726. Therefore, the semiconductor layer 742 does not overlap with the electrode 746. A lightly doped drain (LDD) region is formed in the region.

[0241] The transistor 843 shown in FIG. 19A2 has an electrode 723. 42. The transistor 843 has an electrode 723 formed on a substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. 3 can function as a back gate electrode.

[0242] In addition, the transistor 844 shown in FIG. 19B1 and the transistor As in the case of the electrode 845, the insulating layer 726 may be entirely removed from areas that do not overlap with the electrode 746. In addition, the transistor 846 shown in FIG. 19C1 and the transistor The insulating layer 726 may be left as shown at 847 .

[0243] The transistors 843 to 847 are also formed with the electrode 74 after the electrode 746 is formed. 6 as a mask, impurities 755 are introduced into the semiconductor layer 742, forming a semiconductor layer 74 According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner in the integrated Thus, a display device including transistors having high efficiency and good electrical characteristics can be realized.

[0244] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0245] (Embodiment 6) In this embodiment, a semiconductor device applicable to the display device exemplified in the above embodiment will be described. The semiconductor device exemplified below can function as a memory device.

[0246] In this embodiment, a DOSRAM (registered trademark) is used as an example of a memory device including an oxide semiconductor. The name "DOSRAM" is a trademark of Dynamic Oxid The name comes from e Semiconductor Random Access Memory. DOSRAM is a type of memory cell that is 1T1C (1 transistor 1 capacitance). and a write transistor including an oxide semiconductor. That is the thing.

[0247] An example of the stacked structure of the DOSRAM 1000 will be described with reference to FIG. 1000 is a sense amplifier unit 1002 that reads data and a cell that stores the data. The array section 1003 is laminated.

[0248] As shown in FIG. 20, the sense amplifier unit 1002 includes a bit line BL, a Si transistor The Si transistors Ta10 and Ta11 are single crystal The silicon wafer has a semiconductor layer. The Si transistors Ta10 and Ta11 are sense amplifiers. The memory cell 10 constitutes a buffer and is electrically connected to the bit line BL.

[0249] The cell array section 1003 has a plurality of memory cells 1001. The memory cells 1001 are The cell array unit 1003 includes a transistor Tw1 and a capacitance element C1. The transistor Tw1 shares a semiconductor layer. The semiconductor layer and the bit line BL are connected by a conductive layer (not shown). It is electrically connected by the body.

[0250] The laminated structure shown in FIG. 20 is constructed by laminating multiple circuits each having a group of transistors. The present invention can be applied to various semiconductor devices.

[0251] The metal oxides, insulators, conductors, etc. in FIG. 20 may be single-layered or multi-layered. The methods are sputtering, molecular beam epitaxy (MBE), and pulse laser ablation. Various film formation methods such as polystyrene (PLA) method, CVD method, and atomic layer deposition (ALD) method are used. The CVD method includes plasma CVD, thermal CVD, and metal organic CVD. etc.

[0252] Here, the semiconductor layer of the transistor Tw1 is made of a metal oxide (oxide semiconductor). Here, an example is shown in which the semiconductor layer is composed of three metal oxide layers. The conductor layer is preferably composed of a metal oxide containing In, Ga, and Zn.

[0253] Here, the metal oxide is a metal oxide that is formed by adding an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. The addition of a metal oxide increases the carrier density and may result in a lower resistance. By selectively lowering the resistance of the semiconductor layer using A region can be provided.

[0254] Representative elements that reduce the resistance of metal oxides include boron and phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gases, etc. can also be used. Representative examples of rare gases are helium, neon, argon, krypton, and xenon. The concentration of the element is measured by secondary ion mass spectrometry (SIMS). Measurements can be performed using techniques such as Ion Mass Spectrometry (IMMS).

[0255] In particular, boron and phosphorus are used in the manufacturing process of amorphous silicon or low-temperature polysilicon. This is preferable because existing equipment can be used. Existing facilities can be repurposed. Capital investment can be reduced.

[0256] A transistor having a semiconductor layer selectively reduced in resistance is, for example, a transistor using a dummy gate. Specifically, a dummy gate is provided on a semiconductor layer. The Mie gate may be used as a mask to add an element that reduces the resistance of the semiconductor layer. That is, the element is added to the region of the semiconductor layer that does not overlap with the dummy gate, and a low resistance The element is added by using an ionized source gas. The ion implantation method adds ionized source gas without mass separation. The ion doping method and plasma immersion ion implantation method are used. It is possible.

[0257] The conductive material used for the conductor is polycrystalline silicon doped with impurity elements such as phosphorus. Semiconductors such as nickel silicide, molybdenum, titanium, tungsten Metals such as aluminum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or metal nitrides containing the above-mentioned metals (tantalum nitride, titanium nitride, molybdenum nitride, etc.) In addition, indium tin oxide, indium oxide containing tungsten oxide, etc. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium zinc oxide, silicon oxide A conductive material such as indium tin oxide doped with silicon can be used.

[0258] The insulating materials used for the insulator include aluminum nitride, aluminum oxide, and aluminum nitride oxide. Aluminum, aluminum oxide nitride, magnesium oxide, silicon nitride, silicon oxide, Silicon oxide nitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide , Zirconium oxide, Lanthanum oxide, Neodymium oxide, Hafnium oxide, Tantalum oxide In this specification, the term "oxynitride" refers to an oxide, A compound in which the amount of oxygen is greater than the amount of nitrogen is called a nitride compound. It refers to many compounds.

[0259] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0260] (Embodiment 7) Examples of electronic devices that can use the display device according to one embodiment of the present invention include display devices, a mobile phone; a mobile phone; Game consoles, including those of the 1990s, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of such electronic devices are shown in Figure 21.

[0261] FIG. 21A shows a television. The television includes a housing 971, a display unit 973, an operation key 974, A speaker 975, a communication connection terminal 976, an optical sensor 977, etc. are shown. A touch sensor is provided on the display portion 973 so that an input operation can be performed. By using a display device, the amount of computational processing required when images are superimposed and displayed on the display unit 973 is reduced. Alternatively, the display device of one embodiment of the present invention may be used for the display portion 973. This makes it possible to display more gradations than the number of bits that the source driver can output. do.

[0262] FIG. 21B is a diagram showing an information processing terminal, which includes a housing 901, a display unit 902, and a display unit 90 3, sensor 904, etc. The display unit 902 and the display unit 903 are each composed of a single display panel. The housing 901 is also flexible and can be folded as shown in the figure. It can also be used in a flat form like a tablet. The sensor 904 can sense the shape of the housing 901, for example, when the housing is bent. The display on the display unit 902 and the display unit 903 can be switched. By using the display device of one embodiment of the present invention for the display portion 903, images can be displayed on the display portions 902 and 903. When images are superimposed and displayed, the amount of computational processing can be reduced. By using the display device of one embodiment of the present invention for the source driver 902 and the display portion 903, It is possible to display a number of gradations greater than the number of bits that can be output.

[0263] FIG. 21C is a diagram showing a digital camera, which includes a housing 961 and a shutter button 962. , a microphone 963, a speaker 967, a display unit 965, an operation key 966, and a zoom lever 968 965, a lens 969, and the like are illustrated. When images are superimposed and displayed on the display unit 965, the amount of calculation processing can be reduced.

[0264] FIG. 21(D) is a diagram showing a digital signage. A large display unit 921 is attached to the side of a pillar 921. The display device of one embodiment of the present invention is used for the display portion 922. As a result, the amount of computational processing can be reduced when images are superimposed and displayed on the display unit 922. Alternatively, by using the display device of one embodiment of the present invention for the display portion 922, It is possible to display more gradations than the number of bits that the driver can output.

[0265] FIG. 21E is a diagram showing an example of a mobile phone. The mobile phone includes a housing 951, a display unit 952, and an operation button. A touch panel 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone has a touch sensor on the display 952. All operations, such as inputting characters, are performed by touching the display unit 952 with a finger or a stylus. In addition, the housing 951 and the display unit 952 are flexible and can be folded as shown in the figure. The display device of one embodiment of the present invention can be used for the display portion 952. This makes it possible to reduce the amount of computational processing required when displaying images in a superimposed manner on the display unit 952. Alternatively, by using the display device of one embodiment of the present invention for the display portion 952, It is possible to display a greater number of gradations than the number of bits that the driver can output.

[0266] FIG. 21F shows a portable data terminal. The portable data terminal includes a housing 911, a display unit 912, and a speaker. The display unit 912 has a touch panel function for inputting information. By using the display device of one embodiment of the present invention for the display portion 912, When images are superimposed and displayed on the display unit 912, the amount of calculation processing can be reduced. Alternatively, by using the display device of one embodiment of the present invention for the display portion 912, It is possible to display more gradations than the number of bits that can be output.

[0267] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible. EXAMPLES

[0268] In this embodiment, a signal in the pixel circuit configuration shown in FIG. The output obtained by adding the signals W1, W2, data1, and data2 is It was confirmed whether the desired gradation was obtained.

[0269] The parameters used in the circuit simulation are as follows. The transistor sizes are: The transistor M2 has a channel length L / width W of 9 μm / 6 μm. The transistors other than the transistor M2 have an L / W of 4 μm / 4 μm. The capacitance of the capacitance element C2 was set to 100 fF, and the capacitance of the capacitance element C3 was set to 30 fF. FN diode model, wire ANO is +10V as anode potential, reference voltage Vref The potential of the CAT wire was changed in steps of 1V from -9V to -5V as the cathode potential. The minimum value of signal W1, signal W2, signal data1, and signal data2 is 0V, and the maximum value is + The voltage was set to 5 V. SPICE was used as the software for circuit simulation.

[0270] FIG. 22A shows the signals W1, W2, data1, and data2. By changing each of these and adding multiple signals, the possible gradations (equivalent to 10 bits. How does the amount of current flowing through the light-emitting element per pixel change with respect to the number of pixels? In FIG. 22(A), the voltage of the wiring CAT is set to -9V or less. Change the signal W1, signal W2, signal data1, and signal da from -5V to -5V in increments of 1V. Estimate the amount of current (Ioled) flowing through the light-emitting element per pixel when ta2 is changed. I did.

[0271] Similarly, FIG. 22B shows signals W1, W2, data1, and data2. By changing each of these and adding multiple signals, the gradation that can be expressed (equivalent to 10 bits) 0 to 1024.) is changed by adding up multiple signals written Estimate how the gate-source voltage (Vgs) of transistor M2 changes when In FIG. 22(B), the voltage of the wiring CAT is The signal W1, the signal W2, the signal data1, and the signal W2 are changed by 1V from -9V to -5V. The voltage applied between the gate and source of transistor M2 when the signal data2 is changed was estimated.

[0272] From the graphs shown in FIGS. 22(A) and 22(B), it can be seen that the pixel shown in FIG. 10 is It was confirmed that good gradation display was possible by operating the device using the driving method explained in Figure 12. Ta. [Explanation of symbols]

[0273] 100: display device, 110: display unit, 111: pixel, 112: memory circuit, 113: memory memory circuit, 114: transistor, 115: capacitance element, 116: capacitance element, 117: transistor 118: transistor, 119: capacitance element, 120: transistor, 121: Transistor, 122: transistor, 123: light emitting element, 124: wiring, 130: gate Driver, 140: Data driver

Claims

[Claim 1] A method for driving a display device including a pixel including a display element, a first memory circuit, a second memory circuit, and a first transistor, comprising the steps of: causing the first memory circuit to hold a first signal; causing the second memory circuit to hold a second signal; A method for driving a display device, comprising the steps of: supplying a third signal to the first memory circuit in which the first signal is held; supplying a fourth signal to the second memory circuit in which the second signal is held; and controlling on / off of switches in the first memory circuit and the second memory circuit, thereby combining the first signal, a signal obtained by adding the first signal and the second signal, a signal obtained by adding the first signal to the third signal, and a signal obtained by adding the first signal to the fourth signal to display an image.

Images