Display device and method for manufacturing the same

Abstract

To suppress lowering of reliability.SOLUTION: A display device includes: a resin substrate having flexibility; a circuit layer including a display region displaying an image and a plurality of insulation layers arranged across a peripheral region outside the display region, on the resin substrate; a first organic insulation layer arranged across the display region and the peripheral region, on the circuit layer; a first inorganic insulation layer arranged across the display region and the peripheral region, on the first organic insulation layer; and a first partition wall having a first lower part arranged on the first inorganic insulation layer and a first upper part which is arranged on the first lower part and projects from the side face of the first lower part, in the peripheral region. The circuit layer has a belt-like region where at least one of the plurality of insulation layers is missed in a belt shape, and the first partition wall is arranged in the belt-like region.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. This display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer that covers the lower electrode, and an upper electrode that covers the organic layer. In the process of manufacturing such display elements, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability and a manufacturing method thereof. [Means for solving the problem]

[0005] According to one embodiment, the display device comprises: The display device comprises a flexible resin substrate; a circuit layer including a plurality of insulating layers arranged on the resin substrate over a display region for displaying an image and a peripheral region outside the display region; a first organic insulating layer arranged on the circuit layer over the display region and the peripheral region; a first inorganic insulating layer arranged on the first organic insulating layer over the display region and the peripheral region; and a first partition having a first lower portion arranged on the first inorganic insulating layer in the peripheral region and a first upper portion arranged on the first lower portion and protruding from a side surface of the first lower portion, wherein the circuit layer has a band-shaped region in which at least one of the plurality of insulating layers is missing in a band shape, and the first partition is arranged in the band-shaped region.

[0006] According to one embodiment, the display device comprises: The display panel has a display area for displaying an image and a peripheral area outside the display area, and is folded at a band-shaped area, the display panel comprising: a flexible resin substrate; a first organic insulating layer arranged above the resin substrate across the display area and the peripheral area; a first inorganic insulating layer arranged on the first organic insulating layer across the display area and the peripheral area; and a first partition having a first lower portion arranged on the first inorganic insulating layer in the band-shaped area, and a first upper portion arranged on top of the first lower portion and protruding from a side surface of the first lower portion.

[0007] According to one embodiment, a method for manufacturing a display device includes the steps of: The present invention comprises: forming a circuit layer including a plurality of insulating layers on a flexible resin substrate, the circuit layer including the display region for displaying an image and the peripheral region outside the display region; forming a first organic insulating layer on the circuit layer, the first inorganic insulating layer on the first organic insulating layer, the first inorganic insulating layer on the display region and the peripheral region; and forming a first partition in the peripheral region, the first partition having a first lower portion located on the first inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion; the circuit layer has a band-shaped region in which at least one of the plurality of insulating layers is missing in a band shape, and the first partition is located in the band-shaped region. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing an example of the configuration of a display device DSP. [Diagram 2] FIG. 2 is a perspective view showing a state in which the display panel PNL shown in FIG. 1 is folded. [Diagram 3] FIG. 3 is a plan view showing another configuration example of the display device DSP. [Figure 4] FIG. 4 is a perspective view showing a state in which the display panel PNL shown in FIG. 3 is folded. [Diagram 5] FIG. 5 is a plan view showing another configuration example of the display device DSP. [Figure 6] FIG. 6 is a perspective view showing a state in which the display panel PNL shown in FIG. 5 is folded. [Figure 7] FIG. 7 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Figure 8] FIG. 8 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG. [Figure 9A] FIG. 9A is a plan view showing an example of the shape of the partition wall 7. As shown in FIG. [Figure 9B] FIG. 9B is a plan view showing another example of the shape of the partition wall 7. As shown in FIG. [Figure 9C] FIG. 9C is a plan view showing another example of the shape of the partition wall 7. As shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view of the display device DSP taken along a partition 7 intersecting with a strip-shaped area BA. [Figure 11] FIG. 11 is a cross-sectional view of the display device DSP taken along line CD in FIG. [Figure 12] FIG. 12 is a cross-sectional view of a display device DSP including metal wiring ML intersecting with strip-shaped regions BA. [Figure 13] FIG. 13 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 14A] FIG. 14A is a diagram for explaining a manufacturing method of the display device DSP. [Figure 14B] FIG. 14B is a diagram for explaining a manufacturing method of the display device DSP. [Figure 15A] FIG. 15A is a diagram for explaining a manufacturing method of the display device DSP. [Figure 15B] FIG. 15B is a diagram for explaining a manufacturing method of the display device DSP. [Figure 16A] FIG. 16A is a diagram for explaining a manufacturing method of the display device DSP. [Figure 16B] FIG. 16B is a diagram for explaining a manufacturing method of the display device DSP. [Figure 17] FIG. 17 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 18] FIG. 18 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 19] FIG. 19 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 20] FIG. 20 is a cross-sectional view for explaining a state in which the laminated film FL1 is formed in the strip-shaped region BA. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiment will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0010] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view.

[0011] The display device according to this embodiment is an organic electroluminescence display device having an organic light emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] FIG. 1 is a plan view showing an example of the configuration of a display device DSP.

[0013] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 is a flexible resin substrate.

[0014] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0015] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixels PX include a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, the second color, and the third color are different from each other. The pixel PX may include a subpixel SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0016] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0018] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] The display element DE is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0020] The peripheral area SA has a terminal portion TP, a convex portion PR, and a partition wall 7.

[0021] The terminal portion TP includes a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along a first direction X. Each of the terminals TE extends in a second direction Y, but this is not limited thereto. For example, some of the plurality of terminals TE may extend in an oblique direction. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit board or an IC chip.

[0022] The convex portion PR is formed in a frame shape surrounding the display area DA. Such a convex portion PR is formed by utilizing an organic insulating layer disposed in the display area DA.

[0023] The partition 7 is disposed between the display area DA and the convex portion PR, and outside the convex portion PR. Such a partition 7 can be formed in various shapes, such as a lattice shape, a straight line shape, a curved shape, a folded line shape, and an island shape. Such a partition 7 is conductive and electrically connected to a terminal TE of a common potential. Therefore, compared to a case where a large-area partition 7 is electrically floating, it is possible to suppress electrostatic breakdown during the manufacturing process at a position where the partition 7 and a conductive layer (including other partitions) are adjacent to each other. The specific shape of the partition wall 7 will be described in detail later.

[0024] Such a display panel PNL has strip areas BA. In the illustrated example, two strip areas BA are located in the peripheral area SA, and both extend in the second direction Y. The display area DA and the terminal portion TP are located between the two strip areas BA. Such a strip area BA is an area that can be bent around an axis AX along the second direction Y. The partition wall 7 is also arranged in the strip areas BA.

[0025] FIG. 2 is a perspective view showing a state in which the display panel PNL shown in FIG. 1 is folded. The strip area BA is curved. The area of ​​the display panel PNL that is outside the strip area BA (or the area on the opposite side of the display area DA across the strip area BA) is located on the rear side of the display area DA. In this way, by bending the display panel PNL at the strip area BA, the width of the periphery of the display area DA in the first direction X can be reduced in the display device DSP, thereby realizing a narrower frame.

[0026] FIG. 3 is a plan view showing another configuration example of the display device DSP. The configuration example shown in Fig. 3 differs from the configuration example shown in Fig. 1 in that the strip area BA extends in the first direction X. In the illustrated example, the strip area BA is located between the display area DA and the terminal portion TP in the peripheral area SA. Such a strip area BA is an area that can be bent around an axis line AX along the first direction X. The partition wall 7 is disposed in the peripheral area SA including the strip area BA.

[0027] FIG. 4 is a perspective view showing a state in which the display panel PNL shown in FIG. 3 is folded. The strip area BA is curved. The area of ​​the display panel PNL on the opposite side of the display area DA across the strip area BA is located on the rear side of the display area DA. In this manner, by folding the display panel PNL at the strip area BA, the width of the periphery of the display area DA in the second direction Y in the display device DSP can be reduced, thereby realizing a narrower frame.

[0028] FIG. 5 is a plan view showing another configuration example of the display device DSP. The configuration example shown in Fig. 5 differs from the configuration example shown in Fig. 1 in that the strip area BA is located in the peripheral area SA and intersects with the display area DA. In the illustrated example, the strip area BA is located between two terminal portions TP in the peripheral area SA. Such a strip area BA is a region that can be bent around an axis line AX along the second direction Y. The partition wall 7 is disposed in the peripheral area SA including the strip area BA.

[0029] FIG. 6 is a perspective view showing a state in which the display panel PNL shown in FIG. 5 is folded. The strip area BA is curved. In this manner, the display panel PNL can be folded at the strip area BA that intersects with the display area DA, thereby providing a foldable display device DSP.

[0030] FIG. 7 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3.

[0031] In the illustrated example, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0032] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0033] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0034] An insulating layer 5 and partition walls 6 are disposed in the display area DA. The insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0035] The partition 6 overlaps with the insulating layer 5 in a plan view. The partition 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition 6 has openings in the subpixels SP1, SP2, and SP3, similar to the insulating layer 5. The partition 6 is conductive and is electrically connected to the partition 7 and the common potential terminal TE shown in FIG. 1.

[0036] The sub-pixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0037] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the aperture AP1. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 overlap with the insulating layer 5 in a planar view.

[0038] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the lower electrode LE2, the organic layer OR2, and the upper electrode UE2 overlap with the insulating layer 5 in a planar view.

[0039] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the aperture AP3. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 overlap with the insulating layer 5 in a planar view.

[0040] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dashed lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes illustrated in the drawings do not necessarily reflect the exact shapes.

[0041] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or a common electrode, and are in contact with the partition walls 6.

[0042] In the illustrated example, the areas of the openings AP1, AP2, and AP3 are different from one another. The area of ​​the openings AP1 is larger than the area of ​​the openings AP2, and the area of ​​the openings AP2 is larger than the area of ​​the openings AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0043] FIG. 8 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0044] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in FIG. 1, and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 also includes insulating layers 111, 112, 113, 114, 115, 116, and 117, which will be described later. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that is disposed on the insulating layer 116 or the insulating layer 117 of the circuit layer 11, and flattens unevenness caused by the circuit layer 11.

[0045] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and are spaced apart from each other. The insulating layer 5 is an inorganic insulating layer and is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. An opening AP1 in the insulating layer 5 overlaps the lower electrode LE1, an opening AP2 overlaps the lower electrode LE2, and an opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3 through contact holes provided in the insulating layer 12. Note that the contact holes in the insulating layer 12 are omitted in FIG. 8.

[0046] The partition 6 includes a conductive lower portion 61 disposed on the insulating layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. Both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition 6 is called an overhang shape.

[0047] In the illustrated example, the lower part 61 has a bottom layer 63 disposed on the insulating layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In addition, in the illustrated example, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0048] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has a peripheral portion located on the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower portion 61.

[0049] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has a peripheral portion located on the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower portion 61.

[0050] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has a peripheral portion located on the insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower portion 61.

[0051] In the illustrated example, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. The cap layers CP1, CP2, and CP3 may be omitted.

[0052] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0053] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3.

[0054] In the illustrated example, parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are located on the partition wall 6 around the subpixel SP1. These parts are separated from parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located in the aperture AP1 (parts constituting the display element DE1). Similarly, portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 are located on the partition 6 surrounding the subpixel SP2, and these portions are spaced apart from portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 that are located in the opening AP2 (portions that constitute the display element DE2). Similarly, portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 are located on the partition 6 surrounding the subpixel SP3, and these portions are spaced apart from portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 that are located in the opening AP3 (portions that constitute the display element DE3).

[0055] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 is referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 is referred to as a laminate film FL3.

[0056] Ends of the sealing layers SE1, SE2, and SE3 and ends of the stacked films FL1, FL2, and FL3 are located on the partition wall 6. In the illustrated example, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE3 on the partition wall 6.

[0057] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0058] The insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0059] The lower portion 61 of the partition wall 6 is made of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The upper portion 62 of the partition wall 6 is made of, for example, a conductive material, but may be made of an insulating material. The lower portion 61 and the upper portion 62 are made of a material different from each other.

[0060] The lower electrodes LE1, LE2, and LE3 are multi-layer structures including a transparent electrode made of an oxide conductive material such as indium tin oxide (ITO) and a metal electrode made of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multi-layer structures including a metal electrode between a pair of transparent electrodes.

[0061] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in a blue wavelength range, the emitting layer EM2 is formed of a material that emits light in a green wavelength range, and the emitting layer EM3 is formed of a material that emits light in a red wavelength range. In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers, such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0062] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0063] The cap layers CP1, CP2, and CP3 are multilayer structures made up of a plurality of thin films, all of which are transparent and have different refractive indices.

[0064] The illustrated circuit layer 11, insulating layer 12, insulating layer 5, resin layer 13, resin layer 15, and sealing layer 14 are disposed across the display area DA and the peripheral area SA.

[0065] Next, examples of the shape of the partition walls 7 intersecting with the strip-like region BA will be described.

[0066] FIG. 9A is a plan view showing an example of the shape of the partition wall 7. As shown in FIG. The partition wall 7 is formed in a lattice shape in a plan view. Each portion of the partition wall 7 forming a closed loop extends so as to intersect with the axis AX of the strip-shaped region BA. Therefore, when the strip-shaped region BA is curved, the partition wall 7 is easily stretched, and breakage of the partition wall 7 can be suppressed. Furthermore, since the partition wall 7 is formed in a lattice shape, even if a part of the partition wall 7 breaks, electrical continuity can be ensured in the other parts.

[0067] FIG. 9B is a plan view showing another example of the shape of the partition wall 7. As shown in FIG. The partition 7 is formed in a folded line shape in a plan view. Each straight line component of the partition 7 extends so as to intersect with the axis AX of the band-shaped region BA. Therefore, when the band-shaped region BA is curved, the partition 7 is easily stretched, and breakage of the partition 7 can be suppressed.

[0068] FIG. 9C is a plan view showing another example of the shape of the partition wall 7. As shown in FIG. The partition 7 has a plurality of annular portions connected to each other in a direction intersecting the axis AX. Each of the annular portions is formed in an elliptical or oval shape extending in a direction intersecting the axis AX. Therefore, when the band-shaped region BA is curved, the partition 7 is easily stretched, and breakage of the partition 7 can be suppressed.

[0069] FIG. 10 is a cross-sectional view of the display device DSP taken along a partition 7 intersecting with a strip-shaped area BA.

[0070] Circuit layer 11 on substrate 10 includes multiple insulating layers such as insulating layers 111, 112, 113, 114, 115, 116, and 117.

[0071] Insulating layer 111 is an inorganic insulating layer and is disposed on substrate 10. Insulating layer 112 is an inorganic insulating layer and is disposed on insulating layer 111. Insulating layer 113 is an inorganic insulating layer and is disposed on insulating layer 112. Insulating layer 114 is an inorganic insulating layer and is disposed on insulating layer 113. Insulating layer 115 is an inorganic insulating layer and is disposed on insulating layer 114.

[0072] The insulating layer 116 is an organic insulating layer and is disposed on the insulating layer 115. In the illustrated example, the insulating layer 116 is in contact with the substrate 10 in the strip region BA.

[0073] The insulating layer 117 is an inorganic insulating layer, and is disposed on the insulating layer 116 .

[0074] The strip-shaped region BA corresponds to a region where at least one of these insulating layers 111 to 117 is missing in a strip shape. For example, in the example shown in Fig. 1, at least one of the insulating layers 111 to 117 is missing in a strip shape along the second direction Y to form the strip-shaped region BA. Also, in the example shown in Fig. 3, at least one of the insulating layers 111 to 117 is missing in a strip shape along the first direction X to form the strip-shaped region BA. 10, insulating layers 111 to 115, 117, which are inorganic insulating layers, are missing in strip region BA. Note that insulating layer 116, which is an organic insulating layer, may also be missing in strip region BA. From the viewpoint of suppressing cracks in the insulating layers when strip region BA is curved, it is desirable that all of the inorganic insulating layers included in circuit layer 11 are missing.

[0075] As described above, the insulating layer 12 is an organic insulating layer, and is disposed on the insulating layer 116 and the insulating layer 117. In the illustrated example, the insulating layer 12 is in contact with the insulating layer 116 in the strip region BA.

[0076] As described above, the insulating layer 5 is an inorganic insulating layer, and is disposed on the insulating layer 12. The insulating layer 5 is also disposed in the strip region BA. In the dummy pixels DP located outside the strip region BA (or between the strip region BA and the display region), the insulating layer 5 has no opening and covers the insulating layer 12.

[0077] The partition 7 includes a conductive lower portion 71 disposed on the insulating layer 5, and an upper portion 72 disposed on the lower portion 71. The upper portion 72 has a width greater than that of the lower portion 71. Both ends of the upper portion 72 protrude beyond the side surfaces of the lower portion 71. The dummy pixels DP are surrounded by the partition 7.

[0078] In the illustrated example, the lower part 71 has a bottom layer 73 disposed on the insulating layer 5 and a shaft layer 74 disposed on the bottom layer 73. For example, the bottom layer 73 is formed thinner than the shaft layer 74. In addition, in the illustrated example, both ends of the bottom layer 73 protrude from the side surfaces of the shaft layer 74.

[0079] Such a partition wall 7 can be formed in the same manner as the partition wall 6 in the display area DA. That is, the lower portion 61 and the lower portion 71 are formed of the same material, and the upper portion 62 and the upper portion 72 are formed of the same material.

[0080] The organic layer OR1 is disposed on the partition 7, and is disposed on the insulating layer 5 in the dummy pixel DP surrounded by the partition 7. The upper electrode UE1 is disposed on the organic layer OR1 directly above the partition 7, and is disposed on the organic layer OR1 in the dummy pixel DP and is in contact with the lower portion 71. The cap layer CP1 is disposed on the upper electrode UE1 directly above the partition 7, and is disposed on the upper electrode UE1 in the dummy pixel DP. The sealing layer SE1 continuously covers the cap layer CP1 and the partition 7. The sealing layer SE1 is covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0081] FIG. 11 is a cross-sectional view of the display device DSP taken along line CD in FIG. The partition 7 is disposed in the strip region BA. In the strip region BA, the organic layer OR1 including the light-emitting layer is disposed on the partition 7 and the insulating layer 5. The upper electrode UE1 is disposed on the organic layer OR1 and is in contact with the partition 7. The cap layer CP1 is disposed on the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 surrounded by the partition 7 are spaced apart from the organic layer OR1, the upper electrode UE1, and the cap layer CP1 disposed on the partition 7. The sealing layer SE1 is disposed on the cap layer CP1 and continuously covers the cap layer CP1 and the surrounding partition 7.

[0082] FIG. 12 is a cross-sectional view of a display device DSP including metal wiring ML intersecting with strip-shaped regions BA. The circuit layer 11 includes metal wiring ML. For example, the metal wiring ML is a wiring that electrically connects various wirings in the display area DA to the terminal TE. The metal wiring ML is disposed on the insulating layer 117, and is disposed on the insulating layer 116 in the strip area BA. The metal wiring ML is covered with the insulating layer 12. That is, in the strip area BA, the metal wiring ML is disposed between the insulating layer 116 and the insulating layer 12. As described above, the insulating layer 116 and the insulating layer 12 are organic insulating layers that are more flexible than inorganic insulating layers. Therefore, even if the strip area BA is curved, breakage of the metal wiring ML can be suppressed.

[0083] Next, a method for manufacturing the display device DSP will be described. Note that the portion below the insulating layer 12 is not shown in FIGS.

[0084] First, on the substrate 10, the circuit layer 11 and the insulating layer 12 are formed across the display area DA and the peripheral area SA, and then, as shown in FIG. 13, the lower electrode LE1 of the subpixel SP1, the lower electrode LE2 of the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 are formed on the insulating layer 12. The process of forming the lower electrodes LE1, LE2, and LE3 includes, for example, the following steps. That is, an ITO layer is formed on the insulating layer 12, a silver layer is formed on the ITO layer, and an ITO layer is formed on the silver layer. Then, the ITO layer, the silver layer, and the ITO layer are patterned. As a result, the lower electrodes LE1, LE2, and LE3 are formed. In the process of forming the circuit layer 11, a strip-shaped area BA as shown in FIG. 10 is also formed.

[0085] 14A, an insulating layer 5 is formed across the display region DA and the peripheral region SA, and then a partition wall 6 having a lower portion 61 located on the insulating layer 5 and an upper portion 62 located on the lower portion 61 is formed. Then, openings AP1, AP2, and AP3 are formed in the insulating layer 5. The opening AP1 overlaps the lower electrode LE1 of the subpixel SP1, the opening AP2 overlaps the lower electrode LE2 of the subpixel SP2, and the opening AP3 overlaps the lower electrode LE3 of the subpixel SP3. The process of forming the openings AP1, AP2, and AP3 may be performed before the process of forming the partition wall 6.

[0086] 14B, in the strip region BA, a partition wall 7 is formed having a lower portion 71 located on the insulating layer 5 and an upper portion 72 located on the lower portion 71. The lower portion 71 is formed simultaneously with the lower portion 61, and the upper portion 72 is formed simultaneously with the upper portion 62. Note that no opening is formed in the insulating layer 5 in the strip region BA.

[0087] Next, the display element DE1 is formed in the display area DA.

[0088] First, as shown in FIG. 15A, a laminated film FL1 is formed. The laminated film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the opening AP1, an upper electrode UE1 that covers the organic layer OR1 and contacts the lower portion 61 of the partition wall 6, and a cap layer CP1 located on the upper electrode UE1. The organic layer OR1 also includes a hole injection layer, a hole transport layer, an electron blocking layer, an emitting layer EM1, a hole blocking layer, an electron transport layer, an electron injection layer, and the like. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by deposition using the partition wall 6 as a mask. The laminated film FL1 is divided into a plurality of parts by the overhanging partition wall 6. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are continuously formed while maintaining a vacuum environment.

[0089] Then, the sealing layer SE1 is formed on the laminated film FL1. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each of the divided portions of the laminated film FL1 and the partition walls 6.

[0090] At this time, as shown in Fig. 15B, the laminated film FL1 is also formed in the strip region BA. The process of forming the laminated film FL1 includes a process of forming an organic layer OR1 including an emitting layer EM1 on the partition wall 7 and the insulating layer 5, a process of forming an upper electrode UE1 covering the organic layer OR1 and in contact with a lower portion 71 of the partition wall 7, and a process of forming a cap layer CP1 on the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by deposition using the partition wall 7 as a mask. In the strip region BA as well, the laminated film FL1 is divided into a plurality of portions by the overhanging partition wall 7.

[0091] Then, the sealing layer SE1 is formed on the laminated film FL1. The sealing layer SE1 is formed by CVD. The sealing layer SE1 continuously covers each of the divided portions of the laminated film FL1 and the partition walls 7.

[0092] 16A, a resist R patterned into a predetermined shape is formed on the sealing layer SE1. The resist R overlaps the subpixel SP1 and a part of the partition wall 6 around it. At this time, the sealing layer SE1 is covered with the resist R in the strip-shaped region BA, as shown in FIG. 16B.

[0093] 17, etching is performed using the resist R as a mask. As a result, the sealing layer SE1 and the stacked film FL1 exposed from the resist R are removed. In this etching, the sealing layer SE1 exposed from the resist R, the cap layer CP1 exposed from the sealing layer SE1, the upper electrode UE1 exposed from the cap layer CP1, and the organic layer OR1 exposed from the upper electrode UE1 are sequentially removed. As a result, the lower electrode LE2 of the subpixel SP2 and the lower electrode LE3 of the subpixel SP3 are exposed. Thereafter, the resist R is removed, thereby forming a display element DE1 in the subpixel SP1.

[0094] Next, as shown in FIG. 18, a display element DE2 is formed. The procedure for forming the display element DE2 is the same as that for forming the display element DE1. That is, an organic layer OR2 including an emitting layer EM2, an upper electrode UE2, and a cap layer CP2 are formed in this order on the lower electrode LE2 to form a laminated film FL2. Then, a sealing layer SE2 is formed on the laminated film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. As a result, a display element DE2 is formed in the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 is exposed.

[0095] Next, as shown in FIG. 19, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as that for forming the display element DE1. That is, an organic layer OR3 including an emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are formed in this order on the lower electrode LE3 to form a laminated film FL3. Then, a sealing layer SE3 is formed on the laminated film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. This forms a display element DE3 in the subpixel SP3.

[0096] Thereafter, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in Fig. 8 are formed in this order, thereby completing the display device DSP.

[0097] In the above manufacturing process, it is assumed that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed, but the order of formation of display elements DE1, DE2, and DE3 is not limited to this example.

[0098] FIG. 20 is a cross-sectional view for explaining a state in which the laminated film FL1 is formed in the strip-shaped region BA.

[0099] Here, the laminated film FL1 includes an organic layer OR1 for forming a display element DE1, an upper electrode UE1, and a cap layer CP1. The laminated film FL1 is formed on an insulating layer 5 and a partition wall 7. The partition wall 7 is disposed on the insulating layer 5, and is covered together with the laminated film FL1 with a sealing layer SE1.

[0100] Therefore, the insulating layer 5 is held down by the partition walls 7 and the sealing layer SE1, and the insulating layer 5 is prevented from lifting up from the insulating layer 12. In addition, the laminated film FL1 is divided into smaller pieces by the partition walls 7. Therefore, compared to when the laminated film FL1 is not divided, the area of ​​the continuous laminated film FL1 is reduced, and stress that may occur in the laminated film FL1 is dispersed. In addition, the laminated film FL1 is held down by the partition walls 7 and the sealing layer SE1. Therefore, lifting of the laminated film FL1 from the insulating layer 5 is suppressed. Therefore, separation of the insulating layer 5 from the insulating layer 12, and separation of the laminated film FL1 from the insulating layer 5 can be suppressed.

[0101] Here, we will explain the problems that may occur when the insulating layer 5 and the laminated film FL1 are detached. The detached insulating layer 5 and the laminated film FL1 become foreign matter and float in the manufacturing equipment, and may become a source of contamination. Furthermore, if the floating foreign matter adheres to the processing substrate, it may cause various defects.

[0102] In contrast, according to this embodiment, although a relatively large step is formed in the strip area BA where the insulating layer included in the circuit layer 11 is missing, the above configuration can suppress the detachment of the insulating layer 5 and the laminated film FL1. This suppresses contamination of the manufacturing equipment and the generation of undesired foreign matter. Moreover, even if the strip area BA is curved, the detachment of the insulating layer 5 and the laminated film FL1 can be suppressed. Therefore, a decrease in reliability is suppressed.

[0103] In the above embodiment, for example, insulating layer 5 corresponds to the first inorganic insulating layer, insulating layers 111 to 115 correspond to the second inorganic insulating layer, insulating layer 12 corresponds to the first organic insulating layer, and insulating layer 116 corresponds to the second organic insulating layer. Also, partition 7 corresponds to the first partition, lower portion 71 corresponds to the first lower portion, upper portion 72 corresponds to the first upper portion, partition 6 corresponds to the second partition, lower portion 61 corresponds to the second lower portion, and upper portion 62 corresponds to the second upper portion.

[0104] As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability and a manufacturing method thereof.

[0105] All display devices and manufacturing methods thereof that can be implemented by a person skilled in the art through appropriate design modifications based on the display device and manufacturing method thereof described above as embodiments of the present invention are within the scope of the present invention as long as they include the gist of the present invention.

[0106] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0107] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0108] DSP: Display device PNL: Display panel DA: Display area SA: Peripheral area BA: Strip area 10...Substrate 5...Insulating layer AP1, AP2, AP3...Openings 6...Bulkhead 61...Lower 62...Upper 7...Bulkhead 71...Lower 72...Upper SP1, SP2, SP3...Subpixels DE1, DE2, DE3...Display element (organic EL element) LE1, LE2, LE3...lower electrode UE1, UE2, UE3...upper electrode OR1, OR2, OR3…Organic layer 11...circuit layer 111-117...insulating layer 12...insulating layer ML...metal wiring

Claims

1. A flexible resin substrate; a circuit layer including a plurality of insulating layers disposed on the resin substrate across a display area for displaying an image and a peripheral area outside the display area; a first organic insulating layer disposed on the circuit layer across the display area and the peripheral area; a first inorganic insulating layer disposed on the first organic insulating layer across the display area and the peripheral area; a first partition wall having a first lower portion disposed on the first inorganic insulating layer in the peripheral region and a first upper portion disposed on the first lower portion and protruding from a side surface of the first lower portion; Equipped with the circuit layer has a strip-shaped region in which at least one of the insulating layers is missing in a strip shape; The first partition is disposed in the band-shaped region. Display device.

2. The first partition is disposed so as to intersect with the strip-shaped region. The display device according to claim 1 .

3. The first lower portion is formed of a conductive material and is electrically connected to a terminal of a common potential. The display device according to claim 1 .

4. the circuit layer includes a second organic insulating layer; In the stripe region, the first organic insulating layer and the second organic insulating layer are in contact with each other. The display device according to claim 1 .

5. the plurality of insulating layers include a plurality of second inorganic insulating layers disposed between the resin substrate and the second organic insulating layer, In the strip-shaped region, at least one of the plurality of second inorganic insulating layers is missing in a strip-shaped manner. The display device according to claim 4.

6. In the stripe region, the resin substrate and the second organic insulating layer are in contact with each other. The display device according to claim 5 .

7. The circuit layer includes a metal wiring and a second organic insulating layer, In the strip-shaped region, the metal wiring is disposed between the first organic insulating layer and the second organic insulating layer. The display device according to claim 1 .

8. moreover, an organic layer including a light-emitting layer, the organic layer being disposed on the first partition and the first inorganic insulating layer in the strip-shaped region; an upper electrode disposed on the organic layer; the organic layer and the upper electrode are surrounded by the first partition wall in a plan view, the upper electrode is in contact with the first partition wall; The display device according to claim 1 .

9. moreover, a cap layer disposed on the upper electrode; a sealing layer formed of an inorganic insulating material and covering the cap layer and the first partition wall; The display device according to claim 8.

10. moreover, a lower electrode disposed on the first organic insulating layer in the display region and overlapping an opening in the first inorganic insulating layer; an organic layer including a light-emitting layer, the organic layer being disposed on the lower electrode in the opening; an upper electrode disposed on the organic layer; The display device according to claim 1 .

11. a second partition wall is provided in the display region, the second partition wall having a second lower portion disposed on the first inorganic insulating layer and made of a conductive material, and a second upper portion disposed on the second lower portion and protruding from a side surface of the second lower portion; the lower electrode, the organic layer, and the upper electrode are surrounded by the second partition wall in a plan view, the upper electrode is in contact with the second partition wall; The display device according to claim 10.

12. moreover, a cap layer disposed on the upper electrode; a sealing layer formed of an inorganic insulating material and covering the cap layer and the second partition wall. The display device according to claim 11.

13. the first lower portion and the second lower portion are formed of the same material; The first upper portion and the second upper portion are formed of the same material. The display device according to claim 11.

14. a display panel having a display area for displaying an image and a peripheral area outside the display area, the display panel being folded at a band-shaped area; The display panel includes: A flexible resin substrate; a first organic insulating layer disposed over the resin substrate across the display area and the peripheral area; a first inorganic insulating layer disposed on the first organic insulating layer across the display area and the peripheral area; a first partition wall having a first lower portion disposed on the first inorganic insulating layer in the strip-shaped region and a first upper portion disposed on the first lower portion and protruding from a side surface of the first lower portion; Equipped with Display device.

15. The strip region is located in the peripheral region. The display device according to claim 14.

16. The strip area intersects with the display area. The display device according to claim 14.

17. forming a circuit layer including a plurality of insulating layers on a flexible resin substrate over a display area for displaying an image and a peripheral area outside the display area; forming a first organic insulating layer on the circuit layer across the display area and the peripheral area; forming a first inorganic insulating layer on the first organic insulating layer across the display area and the peripheral area; forming a first partition wall in the peripheral region, the first partition wall having a first lower portion located on the first inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion; Equipped with the circuit layer has a strip-shaped region in which at least one of the insulating layers is missing in a strip shape; The first partition is located in the band-shaped region. A method for manufacturing a display device.

18. Furthermore, after forming the first partition wall, forming an organic layer including a light-emitting layer on the first partition and the first inorganic insulating layer; forming an upper electrode on the organic layer; each of the organic layer and the upper electrode is formed by deposition using the first partition wall as a mask; The method for manufacturing the display device according to claim 17 .

19. Furthermore, after forming the upper electrode, performing deposition using the first partition as a mask to form a cap layer on the upper electrode; forming a sealing layer that covers the cap layer and the first partition wall using an inorganic insulating material; The method for manufacturing the display device according to claim 18 .

20. Furthermore, after forming the sealing layer, forming a patterned resist on the sealing layer; performing etching using the resist as a mask to sequentially remove a portion of the sealing layer, a portion of the cap layer, a portion of the upper electrode, and a portion of the organic layer in the display region; In the stripe region, the sealing layer is covered with the resist. The method for manufacturing the display device according to claim 19 .

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