Liquid crystal display device and control method thereof

Abstract

To provide a liquid crystal display device and a control method thereof that can reduce deterioration of image quality.SOLUTION: A liquid crystal display device comprises: a ramp signal generation circuit that shifts a plurality of ramp signals by respectively different shift amounts to output; a signal processing circuit that respectively adds a correction value depending on the shift amount of the ramp signal allocated for a plurality of video signals of a row number of a plurality of pixels; a horizontal shift register that sequentially fetches the plurality of video signals processed by the signal processing circuit; a latch circuit that concurrently outputs the plurality of video signals fetched by the horizontal shift register; a gradation counter; a plurality of comparators that output a matching signal when each of the plurality of video signals output from the latch circuit matches with a count value of a gradation counter; and a switching circuit that outputs any voltage depending on a pixel of the plurality of ramp signals to a pixel of a row corresponding to the comparator which the matching signal is output to.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a liquid crystal display device and a control method thereof, and more particularly to a liquid crystal display device and a control method thereof that are suitable for reducing degradation in image quality. [Background technology]

[0002] There is a demand for reducing degradation of image quality in LCOS (Liquid Crystal on Silicon) type liquid crystal display devices mounted in projector devices etc. Technology relating to liquid crystal display devices is disclosed in, for example, Patent Document 1.

[0003] The liquid crystal display device disclosed in Patent Document 1 includes a plurality of pixels arranged in a two-dimensional matrix, a shift register circuit, a one-line latch circuit, a plurality of comparators, and a plurality of analog switches. The shift register circuit sequentially captures a plurality of video signals corresponding to the number of columns of the pixels. The one-line latch circuit simultaneously outputs the plurality of video signals captured by the shift register. The plurality of comparators compare each of the plurality of video signals output from the one-line latch circuit with a count value of a grayscale counter, and generate a match pulse when the two match. Each of the plurality of analog switches samples a ramp voltage at the time when it receives a match pulse from the corresponding comparator, and outputs the sampled voltage to the pixel of the corresponding column.

[0004] Here, in this liquid crystal display device, the power supply line through which the first ramp voltage propagates is connected to a plurality of analog switches corresponding to the pixels in the even-numbered columns, and the power supply line through which the second ramp voltage propagates is connected to a plurality of analog switches corresponding to the pixels in the odd-numbered columns. As a result, this liquid crystal display device can suppress the fluctuation of the load applied to each power supply line of the ramp voltage even when a large number of analog switches are turned on simultaneously when a large number of video signals of the same gradation level are written to a large number of pixels. As a result, this liquid crystal display device can suppress the fluctuation (ringing) of each ramp voltage, thereby reducing deterioration of image quality. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2012-226381 A Summary of the Invention [Problem to be solved by the invention]

[0006] The liquid crystal display device disclosed in Patent Document 1 can suppress the fluctuation in the load applied to each lamp voltage supply line when multiple video signals of the same gradation level are each written to multiple pixels, even when multiple analog switches are turned on simultaneously, and therefore can suppress the fluctuation (ringing) of each lamp voltage. However, there is a problem in that it cannot suppress the fluctuation in the power supply voltage, and therefore cannot sufficiently reduce degradation of image quality.

[0007] The present disclosure has been made in consideration of the above-mentioned points, and has an object to provide a liquid crystal display device suitable for reducing degradation in image quality and a control method thereof. [Means for solving the problem]

[0008] a signal processing circuit that adds a correction value corresponding to the shift amount of an assigned ramp signal to a plurality of video signals used in one horizontal scanning period, the number of which corresponds to the number of columns of the plurality of pixels; a horizontal shift register that sequentially takes in the plurality of video signals processed by the signal processing circuit; a latch circuit that simultaneously outputs the plurality of video signals taken in by the horizontal shift register; a gradation counter that performs a count-up operation in a horizontal scanning period; a plurality of comparators that output a match signal when each of the plurality of video signals output from the latch circuit matches a count value of the gradation counter; and a switch circuit that outputs, to a pixel in a column corresponding to a comparator from which a match signal is output, a voltage of one of the plurality of ramp signals corresponding to the pixel at the timing when the match signal is output.

[0009] A liquid crystal display device according to one aspect of the present disclosure includes an image display unit having a plurality of pixels arranged in a two-dimensional matrix, a ramp signal generation circuit that shifts first and second ramp signals, the potentials of which increase linearly in a horizontal scanning period, by different shift amounts and outputs the shifted signals, and a signal processing circuit that adds a correction value according to the shift amount of the first ramp signal to a video signal corresponding to the first ramp signal among a plurality of video signals for the number of columns of the plurality of pixels used in one horizontal scanning period, and adds a correction value according to the shift amount of the second ramp signal to a video signal corresponding to the second ramp signal, and a horizontal shift register which sequentially takes in the video signals, a latch circuit which simultaneously outputs the multiple video signals taken in by the horizontal shift register, a gradation counter which performs a count-up operation in a horizontal scanning period, a plurality of comparators which output a match signal when each of the multiple video signals output from the latch circuit matches a count value of the gradation counter, and a switch circuit which outputs, to a pixel in a column corresponding to a comparator from which a match signal is output, either the first ramp signal or the second ramp signal at the timing when the match signal is output.

[0010] A method for controlling a liquid crystal display device according to one aspect of the present disclosure includes: an image display unit having a plurality of pixels arranged in a two-dimensional matrix; a ramp signal generating circuit outputting a plurality of ramp signals whose potentials increase linearly in a horizontal scanning period; a signal processing circuit; a horizontal shift register which sequentially takes in the plurality of video signals processed by the signal processing circuit; a latch circuit which simultaneously outputs the plurality of video signals taken in by the horizontal shift register; a gradation counter which performs a count-up operation in a horizontal scanning period; and a switch circuit that outputs, to a pixel in a column corresponding to a comparator among the plurality of comparators that has output a coincidence signal, one of the plurality of ramp signals corresponding to the pixel at the timing when the coincidence signal is output, wherein the ramp signal generation circuit shifts the plurality of ramp signals by different shift amounts, and the signal processing circuit adds a correction value corresponding to the shift amount of the ramp signal assigned to a plurality of video signals used in one horizontal scanning period, the number of which corresponds to the number of columns of the plurality of pixels. Effect of the Invention

[0011] According to the present disclosure, it is possible to provide a liquid crystal display device capable of reducing degradation in image quality and a method for controlling the same. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing an example of a configuration of a liquid crystal display device according to a first embodiment. [Diagram 2] 2 is a diagram showing a specific example of the configuration of a ramp signal generating circuit provided in the liquid crystal display device shown in FIG. [Diagram 3] 3 is a timing chart showing an operation of the ramp signal generating circuit shown in FIG. 2. [Figure 4] 2 is a diagram showing a specific example of the configuration of a signal processing circuit provided in the liquid crystal display device shown in FIG. [Diagram 5] 5 is a timing chart showing the operation of the signal processing circuit shown in FIG. [Figure 6] 2 is a timing chart showing a part of the operation of the liquid crystal display device shown in FIG. [Figure 7] FIG. 11 is a diagram showing an example of a configuration of a liquid crystal display device according to a second embodiment. [Figure 8] 8 is a diagram showing a specific example of the configuration of a ramp signal generating circuit provided in the liquid crystal display device shown in FIG. 7. [Figure 9] 8 is a timing chart showing a part of the operation of the liquid crystal display device shown in FIG. [Figure 10] FIG. 1 is a diagram showing a first configuration example of a liquid crystal display device that has been previously examined. [Figure 11] 11 is a timing chart showing the operation of the liquid crystal display device shown in FIG. [Figure 12] FIG. 13 is a diagram showing a second configuration example of a liquid crystal display device that has been previously examined. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] <Preliminary review by the inventor> First, a liquid crystal display device previously examined by the present inventors will be described with reference to Fig. 10 and Fig. 11. Fig. 10 is a diagram showing a configuration example of a liquid crystal display device 50 previously examined. Fig. 11 is a timing chart showing the operation of the liquid crystal display device 50.

[0014] The liquid crystal display device 50 is an active matrix type liquid crystal display device, and includes a pixel display unit 501, a ramp signal generator 503, a vertical drive circuit 505, a shift register circuit 506, a one-line latch circuit 507, a comparator group 508, a gradation counter 509, and a switch circuit 510.

[0015] In the pixel arrangement region of the pixel display unit 501, n rows (n is an integer of 2 or more) of row scanning lines G1 to Gn extending in the horizontal direction (X-axis direction) and m columns (m is an integer of 2 or more) of data lines D1 to Dm extending in the vertical direction (Y-axis direction) are wired. The pixel display unit 101 also has a plurality of pixels (not shown) of n rows and m columns regularly arranged. These multiple pixels are arranged in a two-dimensional matrix at a total of n×m intersections where the n rows of row scanning lines G1 to Gn extending in the horizontal direction (X-axis direction) and the m columns of data lines D1 to Dm extending in the vertical direction (Y-axis direction) intersect.

[0016] Each pixel has a liquid crystal display element. The liquid crystal display element is composed of, for example, a pixel drive electrode (reflective electrode) PE having light reflecting properties, a common electrode CE having light transmitting properties arranged facing the pixel drive electrode PE at a distance, and liquid crystal LCM charged and sealed in the spatial region between them. A common electrode Vcom is applied to the common electrode CE. In each pixel, a voltage corresponding to a video signal is applied to the pixel drive electrode PE, thereby displaying an image with a grayscale level corresponding to the video signal.

[0017] A row scanning line Gj (j is an integer from 1 to n) which is a row scanning line of any row among n row scanning lines G1 to Gn is commonly connected to each of m pixels arranged in the jth row. Also, a data line Di (i is an integer from 1 to m) which is a data line of any column among m data lines D1 to Dm is commonly connected to each of n pixels arranged in the ith column.

[0018] The shift register circuit 506 starts a shift operation when a pulse signal of a horizontal synchronization signal HST (not shown) is supplied. Specifically, the shift register circuit 506 sequentially takes in m columns of q (q is an integer of 2 or more)-bit video signals Din used in one horizontal scanning period in synchronization with a clock signal HCK.

[0019] The one-line latch circuit 507 simultaneously outputs the m columns of video signals captured by the shift register circuit 506 at the timing when the trigger signal LP temporarily becomes active.

[0020] The grayscale counter 509 counts up in synchronization with the rising edge of the clock signal CCK, and outputs a grayscale signal Cout with a grayscale level represented by the count value. For example, the grayscale counter 509 outputs a grayscale signal Cout with a count value of "0" which is the lowest grayscale at the start of one horizontal scanning period (at the rising edge of the horizontal synchronization signal HST), increases the grayscale level of the grayscale signal Cout as the count value increases, and then outputs a grayscale signal Cout with a count value of "(2^q)-1" which is the maximum grayscale at the end of one horizontal scanning period (just before the next rising edge of the horizontal synchronization signal HST). The count value of the grayscale counter 509 is initialized to "0" when the reset signal RST becomes active with the rising edge of the horizontal synchronization signal HST, for example.

[0021] The comparator group 508 is composed of m comparators C1 to Cm corresponding to m columns of pixels. Each of the m comparators C1 to Cm outputs a match signal when each of the m video signals output from the one-line latch circuit 507 matches the count value (grayscale signal Cout) of the grayscale counter 509.

[0022] The ramp signal generator 503 generates a ramp signal Rmp whose potential increases linearly from a reference potential in a horizontal scanning period. The ramp signal Rmp is a sweep signal whose video level changes from black to white from the start to the end of each horizontal scanning period. The horizontal scanning period is one horizontal scanning period, and is the access period to m pixels in one row. The horizontal scanning period is also the pulse period of the horizontal synchronization signal HST.

[0023] The switch circuit 510 includes m switch elements S1 to Sm corresponding to the pixels in m columns. The switch circuit 510 outputs, as a write voltage to the pixel, the voltage of the ramp signal Rmp at the timing when the coincidence signal is output to the pixel in the column corresponding to the comparator that outputs the coincidence signal among the m comparators C1 to Cm.

[0024] Specifically, the switch elements S1 to Sm are simultaneously turned on when the start signal SW_Start becomes active (e.g., H level) at the start of the horizontal scanning period. After that, the switch elements S1 to Sm are switched from on to off when the match signals output from the comparators C1 to Cm become active (e.g., L level). At the end of the horizontal scanning period, the start signal SW_Start becomes inactive (e.g., L level).

[0025] In the example of Fig. 11, a waveform SPs indicates a timing for switching on / off a switch element Sr (r is any integer from 1 to m) provided corresponding to a pixel to which a video signal of gradation level s is written. Referring to Fig. 11, the switch element Sr is turned on at the rising edge of a start signal SW_Start, and then switched from on to off when a match signal becomes active. Here, the switch element Sr samples the potential of the ramp signal Rmp (potential at point P in Fig. 11) at the timing when it switches from on to off. This sampled potential at point P is supplied to a data line Dr. In other words, the potential at point P, which is the result of DA conversion of the video signal of gradation level s, is supplied to the data line Dr.

[0026] As described above, the switch elements S1 to Sm are simultaneously turned on at the start of each horizontal scanning period, but are turned off at any timing according to the grayscale level of the image to be displayed on the corresponding pixel. That is, the switch elements S1 to Sm may be turned off all at the same time, or may be turned off at different times. The order in which they are turned off is also not fixed.

[0027] The vertical drive circuit 505 outputs n scanning pulses from the first row scanning line G1 to the nth row scanning line Gn, one row at a time, every time one horizontal scanning period elapses. Then, it becomes possible to write a voltage corresponding to a video signal to m columns of pixels connected to the row scanning line to which the scanning pulse is supplied among the n row scanning lines G1 to Gn. In other words, it becomes possible to write a voltage corresponding to a video signal to m columns of pixels in the jth row at the timing when a scanning pulse is supplied to the jth row scanning line Gj.

[0028] However, in the liquid crystal display device 50, when a large number of video signals of the same gradation level are written to a large number of pixels (for example, when black is displayed in most of the screen), the ramp signal is sampled by simultaneously turning on a large number of switch elements provided in the switch circuit 510, which causes a large fluctuation in the load applied to the signal line through which the ramp signal propagates. This causes a large voltage fluctuation (ringing) in the ramp signal, which increases image quality degradation such as gradation error and false contour generation.

[0029] Therefore, the inventor next examined the liquid crystal display device 60. 12 is a diagram showing a configuration example of a liquid crystal display device 60 that was previously examined. The liquid crystal display device 60 differs from the liquid crystal display device 50 in that a signal line through which a ramp signal Rmp propagates is branched into four via four buffers. Hereinafter, the four branched signal lines are referred to as signal lines Rmp61 to Rmp64.

[0030] The m columns of data lines D1 to Dm are divided into four data line groups DG1 to DG4 corresponding to the four signal lines Rmp61 to Rmp64. For example, the first data line group DG1 is composed of data lines of a multiple of 4+1 column, such as the 1st, 5th, and 9th columns, among the m columns of data lines D1 to Dm. The second data line group DG2 is composed of data lines of a multiple of 4+2 column, such as the 2nd, 6th, and 10th columns, among the m columns of data lines D1 to Dm. The third data line group DG3 is composed of data lines of a multiple of 4+3 column, such as the 3rd, 7th, and 11th columns, among the m columns of data lines D1 to Dm. The fourth data line group DG4 is composed of data lines of a multiple of 4, such as the 4th, 8th, and 12th columns, among the m columns of data lines D1 to Dm.

[0031] Here, the signal line Rmp61 is connected to the first data line group DG1 via the switch circuit 510. The signal line Rmp62 is connected to the second data line group DG2 via the switch circuit 510. The signal line Rmp63 is connected to the third data line group DG3 via the switch circuit 510. The signal line Rmp64 is connected to the fourth data line group DG4 via the switch circuit 510.

[0032] In the case where a large number of video signals having the same gradation level are written to a large number of pixels, the liquid crystal display device 60 can suppress the fluctuation in the load applied to each ramp signal line even when a large number of switch elements provided in the switch circuit 510 are simultaneously turned on. This allows the liquid crystal display device 60 to suppress the voltage fluctuation (ringing) of each ramp signal, thereby reducing degradation in image quality such as gradation errors and the occurrence of false contours.

[0033] However, although the liquid crystal display device 60 can suppress the fluctuation (ringing) of each lamp voltage by suppressing the fluctuation of the load applied to each power supply line of the lamp voltage, it has a problem that it cannot suppress the fluctuation of the power supply voltage, and therefore cannot reduce image quality degradation such as in-plane luminance unevenness and vertical streak-like fixed noise. In other words, the liquid crystal display device 60 has a problem that it cannot sufficiently reduce pixel degradation.

[0034] Therefore, a liquid crystal display device 1 capable of reducing the above-mentioned deterioration of pixels has been discovered.

[0035] <Embodiment 1> 1 is a diagram showing a configuration example of a liquid crystal display device 1 according to a first embodiment. The liquid crystal display device 1 is an active matrix type liquid crystal display device, and includes a pixel display unit 101, a control circuit 102, a ramp signal generating circuit 103, a signal processing circuit 104, a vertical driving circuit 105, a shift register circuit (horizontal shift register) 106, a one-line latch circuit (latch circuit) 107, a comparator group 108, a gradation counter 109, and a switch circuit 110. The shift register circuit 106, the one-line latch circuit 107, the comparator group 108, the gradation counter 109, and the switch circuit 110 form a data line driving circuit. The basic operation flow of the liquid crystal display device 1 is similar to that of the liquid crystal display devices 50 and 60.

[0036] In the pixel arrangement region of the pixel display unit 101, n rows (n is an integer of 2 or more) of row scanning lines G1 to Gn extending in the horizontal direction (X-axis direction) and m columns (m is an integer of 2 or more) of data lines D1 to Dm extending in the vertical direction (Y-axis direction) are wired. The pixel display unit 101 also has a plurality of pixels (not shown) of n rows and m columns regularly arranged. These multiple pixels are arranged in a two-dimensional matrix at a total of n×m intersections where the n rows of row scanning lines G1 to Gn extending in the horizontal direction (X-axis direction) and the m columns of data lines D1 to Dm extending in the vertical direction (Y-axis direction) intersect.

[0037] Each pixel has a liquid crystal display element. The liquid crystal display element is composed of, for example, a pixel drive electrode (reflective electrode) PE having light reflecting properties, a common electrode CE that is disposed opposite the pixel drive electrode PE at a distance and has light transmitting properties, and liquid crystal LCM that is charged and sealed in the spatial region between them. A common electrode Vcom is applied to the common electrode CE. In each pixel, a voltage corresponding to a video signal is applied to the pixel drive electrode PE, thereby displaying an image with a grayscale level corresponding to the video signal.

[0038] A row scanning line Gj (j is an integer from 1 to n) which is a row scanning line of any row among n row scanning lines G1 to Gn is commonly connected to each of m pixels arranged in the jth row. Also, a data line Di (i is an integer from 1 to m) which is a data line of any column among m data lines D1 to Dm is commonly connected to each of n pixels arranged in the ith column.

[0039] The shift register circuit 106 starts a shift operation when a pulse signal of a horizontal synchronization signal HST (not shown) is supplied. Specifically, the shift register circuit 106 sequentially takes in m columns of q (q is an integer of 2 or more)-bit video signals Din used in one horizontal scanning period in synchronization with a clock signal HCK.

[0040] The one-line latch circuit 107 simultaneously outputs the m columns of video signals captured by the shift register circuit 106 at the timing when the trigger signal LP temporarily becomes active.

[0041] The grayscale counter 109 counts up in synchronization with the rising edge of the clock signal CCK, and outputs a grayscale signal Cout with a grayscale level represented by the count value. For example, the grayscale counter 109 outputs a grayscale signal Cout with a count value of "0" which is the lowest grayscale at the start of one horizontal scanning period (at the rising edge of the horizontal synchronization signal HST), increases the grayscale level of the grayscale signal Cout as the count value increases, and then outputs a grayscale signal Cout with a count value of "(2^q)-1" which is the maximum grayscale at the end of one horizontal scanning period (just before the next rising edge of the horizontal synchronization signal HST). The count value of the grayscale counter 109 is initialized to "0" when the reset signal RST becomes active with the rising edge of the horizontal synchronization signal HST, for example.

[0042] The comparator group 108 is composed of m comparators C1 to Cm corresponding to the pixels in m columns. Each of the m comparators C1 to Cm outputs a match signal when each of the m video signals output from the one-line latch circuit 107 matches the count value (grayscale signal Cout) of the grayscale counter 109.

[0043] The ramp signal generating circuit 103 generates a ramp signal whose potential increases linearly from a reference potential in a horizontal scanning period. The ramp signal is a sweep signal whose image level changes from a black level to a white level from the start to the end of each horizontal scanning period. The details of the ramp signal generating circuit 103 will be described later together with the signal processing circuit 104.

[0044] The switch circuit 110 includes m switch elements S1 to Sm corresponding to m columns of pixels. The switch circuit 110 outputs, as a write voltage to the pixel, the voltage of a ramp signal at the timing when a match signal is output to a pixel in a column corresponding to a comparator from among the m comparators C1 to Cm that outputs the match signal.

[0045] More specifically, the switch elements S1 to Sm are simultaneously turned on when the start signal SW_Start becomes active (e.g., H level) at the start of the horizontal scanning period. After that, the switch elements S1 to Sm are switched from on to off when the match signals output from the comparators C1 to Cm become active (e.g., L level). At the end of the horizontal scanning period, the start signal SW_Start becomes inactive (e.g., L level).

[0046] As described above, the switch elements S1 to Sm are simultaneously turned on at the start of each horizontal scanning period, but are turned off at any timing according to the grayscale level of the image to be displayed on the corresponding pixel. That is, the switch elements S1 to Sm may be turned off all at the same time, or may be turned off at different times. The order in which they are turned off is also not fixed.

[0047] The vertical drive circuit 105 outputs n scanning pulses to the first row scanning line G1 to the nth row scanning line Gn, one row at a time, every time one horizontal scanning period elapses. Then, it becomes possible to write a voltage corresponding to a video signal to m columns of pixels connected to the row scanning line to which the scanning pulse is supplied among the n row scanning lines G1 to Gn. In other words, it becomes possible to write a voltage corresponding to a video signal to m columns of pixels in the jth row at the timing when the scanning pulse is supplied to the jth row scanning line Gj.

[0048] More specifically, the ramp signal generating circuit 103 generates a ramp signal (first ramp signal) Rmp1, a ramp signal (second ramp signal) Rmp2, a ramp signal Rmp3, and a ramp signal Rmp4, each of which has a timing at which the potential starts to increase linearly shifted by a different shift amount. Hereinafter, the four signal lines through which the ramp signals Rmp1 to Rmp4 propagate will be referred to as signal lines Rmp1 to Rmp4, respectively.

[0049] The m columns of data lines D1 to Dm are divided into four data line groups DG1 to DG4 corresponding to the four signal lines Rmp1 to Rmp4. For example, the first data line group DG1 is composed of data lines of a multiple of 4+1 column, such as the 1st, 5th, and 9th columns, among the m columns of data lines D1 to Dm. The second data line group DG2 is composed of data lines of a multiple of 4+2 column, such as the 2nd, 6th, and 10th columns, among the m columns of data lines D1 to Dm. The third data line group DG3 is composed of data lines of a multiple of 4+3 column, such as the 3rd, 7th, and 11th columns, among the m columns of data lines D1 to Dm. The fourth data line group DG4 is composed of data lines of a multiple of 4, such as the 4th, 8th, and 12th columns, among the m columns of data lines D1 to Dm. However, the combination of the multiple data lines constituting each of the data line groups DG1 to DG4 may be determined arbitrarily.

[0050] Here, the signal line Rmp1 is connected to the first data line group DG1 via the switch circuit 110. The signal line Rmp2 is connected to the second data line group DG2 via the switch circuit 110. The signal line Rmp3 is connected to the third data line group DG3 via the switch circuit 110. The signal line Rmp4 is connected to the fourth data line group DG4 via the switch circuit 110.

[0051] The signal processing circuit 104 adds a correction value according to the shift amount of the ramp signal Rmp1 to the video signal corresponding to the ramp signal Rmp1 among the video signals for m columns used in one horizontal scanning period. In this example, the shift amount of the ramp signal Rmp1 is 0. The signal processing circuit 104 adds a correction value according to the shift amount of the ramp signal Rmp2 to the video signal corresponding to the ramp signal Rmp2 among the video signals for m columns used in one horizontal scanning period. The signal processing circuit 104 adds a correction value according to the shift amount of the ramp signal Rmp3 to the video signal corresponding to the ramp signal Rmp3 among the video signals for m columns used in one horizontal scanning period. The signal processing circuit 104 adds a correction value according to the shift amount of the ramp signal Rmp4 to the video signal corresponding to the ramp signal Rmp4 among the video signals for m columns used in one horizontal scanning period.

[0052] Here, the video signal corresponding to the ramp signal Rmp1 is a video signal used for sampling the ramp signal Rmp1, and is a video signal written to pixels connected to the first data line group DG1. The video signal corresponding to the ramp signal Rmp2 is a video signal used for sampling the ramp signal Rmp2, and is a video signal written to pixels connected to the second data line group DG2. The video signal corresponding to the ramp signal Rmp3 is a video signal used for sampling the ramp signal Rmp3, and is a video signal written to pixels connected to the third data line group DG3. The video signal corresponding to the ramp signal Rmp4 is a video signal used for sampling the ramp signal Rmp4, and is a video signal written to pixels connected to the fourth data line group DG4.

[0053] The control circuit 102 controls each of the ramp signal generating circuit 103 and the signal processing circuit 104. For example, the control circuit 102 adjusts the shift amount of each of the ramp signals Rmp1 to Rmp4 generated by the ramp signal generating circuit 103 and the correction value (addition value) added to each video signal in the signal processing circuit 104. In this way, the control circuit 102 can offset the influence of the shift applied to each of the ramp signals Rmp1 to Rmp4 by the correction value added to each video signal.

[0054] Specifically, the control circuit 102 adjusts the shift amount of each of the ramp signals Rmp1 to Rmp4 and the correction value (additive value) added to each video signal in the signal processing circuit 104 so that the potential of the pre-shift ramp signals Rmp1 to Rmp4 sampled by each video signal before the correction value is added is the same as the potential of the shifted ramp signals Rmp1 to Rmp4 sampled by each video signal to which the correction value has been added.

[0055] (Specific example of the ramp signal generating circuit 103) Fig. 2 is a diagram showing a specific configuration example of the ramp signal generating circuit 103. As shown in Fig. 2, the ramp signal generating circuit 103 includes logical product circuits (hereinafter referred to as AND circuits) 1031_1 to 1031_4, q-bit counters 1032_1 to 1032_4, and DA converters 1033_1 to 1033_4.

[0056] The AND circuit 1031_1 outputs the logical product of the clock signal CK and the enable signal EN1 as the clock signal CK1. That is, the AND circuit 1031_1 outputs the clock signal CK as the clock signal CK1 while the enable signal EN1 is active (H level). The AND circuit 1031_2 outputs the logical product of the clock signal CK and the enable signal EN2 as the clock signal CK2. That is, the AND circuit 1031_2 outputs the clock signal CK as the clock signal CK2 while the enable signal EN2 is active (H level). The AND circuit 1031_3 outputs the logical product of the clock signal CK and the enable signal EN3 as the clock signal CK3. That is, the AND circuit 1031_3 outputs the clock signal CK as the clock signal CK3 while the enable signal EN3 is active (H level). The AND circuit 1031_4 outputs the logical product of the clock signal CK and the enable signal EN4 as the clock signal CK4. That is, the AND circuit 1031_4 outputs the clock signal CK as the clock signal CK4 while the enable signal EN4 is active (H level).

[0057] The q-bit counter 1032_1 counts up a q-bit count value CO1 in synchronization with the rising edge of the clock signal CK1. The q-bit counter 1032_2 counts up a q-bit count value CO2 in synchronization with the rising edge of the clock signal CK2. The q-bit counter 1032_3 counts up a q-bit count value CO3 in synchronization with the rising edge of the clock signal CK3. The q-bit counter 1032_4 counts up a q-bit count value CO4 in synchronization with the rising edge of the clock signal CK4. The count values ​​CO1 to CO4 of the q-bit counters 1032_1 to 1032_4 are initialized to "0" by a reset signal RST every time one horizontal scanning period elapses.

[0058] The DA converter 1033_1 converts the digital count value CO1 into an analog ramp signal Rmp1 in synchronization with the rising edge of the clock signal CKDA and outputs the signal. The DA converter 1033_2 converts the digital count value CO2 into an analog ramp signal Rmp2 in synchronization with the rising edge of the clock signal CKDA and outputs the signal. The DA converter 1033_3 converts the digital count value CO3 into an analog ramp signal Rmp3 in synchronization with the rising edge of the clock signal CKDA and outputs the signal. The DA converter 1033_4 converts the digital count value CO4 into an analog ramp signal Rmp4 in synchronization with the rising edge of the clock signal CKDA and outputs the signal.

[0059] Fig. 3 is a timing chart showing the operation of the ramp signal generating circuit 103. As shown in Fig. 3, the active periods of the enable signals EN1 to EN4 are equal, and the active start times of the enable signals EN1 to EN4 are different.

[0060] First, when the enable signal EN1 becomes active, the AND circuit 1031_1 starts outputting the clock signal CK as the clock signal CK1 (time t11). This causes the q-bit counter 1032_1 to start counting up the count value CO1 (time t11). This causes the DA converter 1033_1 to start a linear increase in the potential of the ramp signal Rmp1 (time t11). When the enable signal EN1 becomes inactive, the potential of the ramp signal Rmp1 stops the linear increase and is initialized to the reference potential (0V).

[0061] Furthermore, when the enable signal EN2 becomes active after a predetermined period Tofs has elapsed since the enable signal EN1 became active, the AND circuit 1031_2 starts outputting the clock signal CK as the clock signal CK2 (time t12). This causes the q-bit counter 1032_2 to start counting up the count value CO2 (time t12). This causes the DA converter 1033_2 to start a linear increase in the potential of the ramp signal Rmp2 (time t12). The potential of the ramp signal Rmp2 stops the linear increase as the enable signal EN2 becomes inactive, and is initialized to the reference potential (0V).

[0062] Furthermore, when the enable signal EN3 becomes active after a predetermined period Tofs has elapsed since the enable signal EN2 became active, the AND circuit 1031_3 starts outputting the clock signal CK as the clock signal CK3 (time t13). This causes the q-bit counter 1032_3 to start counting up the count value CO3 (time t13). This causes the DA converter 1033_3 to start a linear increase in the potential of the ramp signal Rmp3 (time t13). The potential of the ramp signal Rmp3 stops the linear increase as the enable signal EN3 becomes inactive, and is initialized to the reference potential (0V).

[0063] Furthermore, when the enable signal EN4 becomes active after a predetermined period Tofs has elapsed since the enable signal EN3 became active, the AND circuit 1031_4 starts outputting the clock signal CK as the clock signal CK4 (time t14). This causes the q-bit counter 1032_4 to start counting up the count value CO4 (time t14). This causes the DA converter 1033_4 to start a linear increase in the potential of the ramp signal Rmp4 (time t14). The potential of the ramp signal Rmp4 stops the linear increase as the enable signal EN4 becomes inactive, and is initialized to the reference potential (0V).

[0064] In this way, the ramp signal generating circuit 103 generates the ramp signal Rmp1 and the ramp signals Rmp2, Rmp3, and Rmp4 obtained by shifting the ramp signal Rmp1 backward by a predetermined period Tofs, Tofs×2, and Tofs×3, respectively. Note that the ramp signal generating circuit 103 can be appropriately changed to another configuration capable of realizing the same operation as the configuration shown in FIG. 2.

[0065] (Specific example of signal processing circuit 104) Fig. 4 is a diagram showing a specific example of the configuration of the signal processing circuit 104. As shown in Fig. 4, the signal processing circuit 104 includes an addend switching circuit 1041 and an adder circuit 1042. The addend switching circuit 1041 outputs an addend (correction value) Da according to control signals Sa and Sb. The adder circuit 1042 adds an unprocessed video signal Din_pre and the addend Da, and outputs the result as a processed video signal Din. The video signal Din processed by the signal processing circuit 104 is captured by a shift register circuit 106.

[0066] Fig. 5 is a timing chart showing the operation of the signal processing circuit 104. In the example of Fig. 5, video signals "d1", "d2", "d3", "d4", "d5", "d6", "d7", and "d8" are input in this order to the signal processing circuit 104 as the video signal Din_pre.

[0067] Note that video signal "d1" is the video signal written to the pixels in the first column. Video signal "d2" is the video signal written to the pixels in the second column. Video signal "d3" is the video signal written to the pixels in the third column. Video signal "d4" is the video signal written to the pixels in the fourth column. Video signal "d5" is the video signal written to the pixels in the fifth column. Video signal "d6" is the video signal written to the pixels in the sixth column. Video signal "d7" is the video signal written to the pixels in the seventh column. Video signal "d8" is the video signal written to the pixels in the eighth column.

[0068] The additional value switching circuit 1041 periodically outputs four types of additional values ​​(correction values) according to the control signals Sa and Sb. For example, the additional value switching circuit 1041 outputs an additional value "0" when the control signal Sa is at L level and the control signal Sb is at L level. Thereafter, the additional value switching circuit 1041 outputs an additional value "k" when the control signal Sa is at H level and the control signal Sb is at L level. Thereafter, the additional value switching circuit 1041 outputs an additional value "2k" when the control signal Sa is at L level and the control signal Sb is at H level. Thereafter, the additional value switching circuit 1041 outputs an additional value "3k" when the control signal Sa is at H level and the control signal Sb is at H level. The additional value switching circuit 1041 repeats such an operation. The additional value "k" is set so that the count time of the additional value "k" by the grayscale counter 109 is the same as a predetermined period Tofs, which is a shift amount of the ramp signal Rmp2, but is not limited thereto.

[0069] The addition circuit 1042 adds an additional value "0" to the video signal "d1" and outputs the video signal "d1", then adds an additional value "k" to the video signal "d2" and outputs the video signal "d2+k", then adds an additional value "2k" to the video signal "d3" and outputs the video signal "d3+2k", and then adds an additional value "3k" to the video signal "d4" and outputs the video signal "d4+3k". Similarly, the adder circuit 1042 adds the additional value "0" to the video signal "d5" to output the video signal "d5", then adds the additional value "k" to the video signal "d6" to output the video signal "d6+k", then adds the additional value "2k" to the video signal "d7" to output the video signal "d7+2k", and then adds the additional value "3k" to the video signal "d8" to output the video signal "d8+3k". The signal processing circuit 104 performs similar processing on the video signals "d9" and onwards.

[0070] Then, the signal processing circuit 104 outputs the video signals “d1”, “d2+k”, “d3+2k”, “d4+3k”, “d5”, “d6+k”, “d7+2k”, and “d8+3k” in that order as the processed video signal Din. The processed video signal Din is captured by the shift register circuit 106.

[0071] Fig. 6 is a timing chart showing a part of the operation of the liquid crystal display device 1. In the example of Fig. 6, the video signals "d1", "d2", "d3", and "d4" before being processed by the signal processing circuit 104 have the same gradation levels, but this is not limited thereto.

[0072] 6, the timing at which the ramp signal Rmp2 starts to increase linearly is shifted a predetermined period Tofs after the timing at which the ramp signal Rmp1 starts to increase linearly. The timing at which the ramp signal Rmp3 starts to increase linearly is shifted a predetermined period Tofs2 (=Tofs×2) after the timing at which the ramp signal Rmp1 starts to increase linearly. The timing at which the ramp signal Rmp4 starts to increase linearly is shifted a predetermined period Tofs3 (=Tofs×3) after the timing at which the ramp signal Rmp1 starts to increase linearly.

[0073] Here, the count time of the added value "k" included in the processed video signal "d2+k" by the grayscale counter 109 is equal to the predetermined period Tofs. Therefore, the sampling timing of the ramp signal Rmp2 by the video signal "d2+k" is shifted to the predetermined period Tofs later than the sampling timing of the ramp signal Rmp1 by the video signal "d1".

[0074] Furthermore, the count time of the added value "2k" included in the processed video signal "d3+2k" by the grayscale counter 109 is equal to the predetermined period Tofs2. Therefore, the sampling timing of the ramp signal Rmp3 based on the video signal "d3+2k" is shifted to the predetermined period Tofs2 later than the sampling timing of the ramp signal Rmp1 based on the video signal "d1".

[0075] Furthermore, the count time of the added value "3k" included in the processed video signal "d4+3k" by the grayscale counter 109 is equal to the predetermined period Tofs3. Therefore, the sampling timing of the ramp signal Rmp4 by the video signal "d4+3k" is shifted to the predetermined period Tofs3 later than the sampling timing of the ramp signal Rmp1 by the video signal "d1".

[0076] As a result, the sampled voltage of ramp signal Rmp1 based on video signal "d1", the sampled voltage of ramp signal Rmp2 based on video signal "d2+k", the sampled voltage of ramp signal Rmp3 based on video signal "d3+2k", and the sampled voltage of ramp signal Rmp4 based on video signal "d4+3k" show the same value.

[0077] In this way, the liquid crystal display device 1 can shift the sampling timings of the ramp signals Rmp1 to Rmp4 based on the video signals "d1", "d2", "d3", and "d4" of the same gradation level, thereby suppressing fluctuations in the power supply voltage that occur when the sampling timings of the ramp signals based on multiple video signals of the same gradation level are simultaneous.

[0078] As described above, the liquid crystal display device 1 according to the present embodiment can shift the sampling timing of the ramp signals from a plurality of video signals of the same gradation level, thereby suppressing the fluctuation of the power supply voltage that occurs when the ramp signals from a plurality of video signals of the same gradation level are sampled simultaneously. As a result, the liquid crystal display device 1 according to the present embodiment can reduce deterioration of image quality.

[0079] In the present embodiment, the ramp signal generating circuit 103 generates ramp signals Rmp1 to Rmp4 in which the timings at which the potential starts to increase linearly are shifted by different amounts, but the present invention is not limited to this. The ramp signal generating circuit 103 may be configured to generate two or more ramp signals in which the timings at which the potential starts to increase linearly are shifted by different amounts. In this case, the m columns of data lines D1 to Dm are divided into two or more data line groups corresponding to the two or more ramp signals. The two or more signal lines through which the two or more ramp signals propagate are connected to the two or more data line groups via the switch circuit 110.

[0080] <Embodiment 2> 7 is a diagram showing a configuration example of a liquid crystal display device 2 according to embodiment 2. Compared to the liquid crystal display device 1, the liquid crystal display device 2 includes a control circuit 202 instead of the control circuit 102, and a ramp signal generating circuit 203 instead of the ramp signal generating circuit 103.

[0081] The ramp signal generating circuit 203 generates ramp signals Rmp1 to Rmp4 by shifting the potential at the start of the linear increase by different shift amounts. The control circuit 202 controls the ramp signal generating circuit 203 and the signal processing circuit 104. For example, the control circuit 202 adjusts the shift amounts of the ramp signals Rmp1 to Rmp4 generated by the ramp signal generating circuit 203 and the correction values ​​(additive values) added to each video signal in the signal processing circuit 104. This allows the control circuit 202 to offset the influence of the shift applied to each of the ramp signals Rmp1 to Rmp4 by the correction values ​​added to each video signal. The other configurations of the liquid crystal display device 2 are similar to those of the liquid crystal display device 1, and therefore description thereof will be omitted.

[0082] (Specific Example of Ramp Signal Generating Circuit 203) Fig. 8 is a diagram showing a specific example of the configuration of the ramp signal generating circuit 203. As shown in Fig. 8, the ramp signal generating circuit 203 includes a q-bit counter 2031, a DA converter 2032, operational amplifiers OP1 to OP4, resistive elements R11 to R14, resistive elements R21 to R24, resistive elements R31 to R34, resistive elements R41 to R44, and voltage sources Vofs1 to Vofs3.

[0083] The q-bit counter 2031 counts up a q-bit count value CO1 in synchronization with the rising edge of the clock signal CK. The count value CO1 of the q-bit counter 2031 is initialized to "0" by a reset signal RST every time one horizontal scanning period elapses. The DA converter 2032 converts the digital count value CO1 into an analog ramp signal Rmp0 in synchronization with the rising edge of the clock signal CKDA and outputs it.

[0084] The resistor R11 is provided between the output terminal of the DA converter 2032 and the non-inverting input terminal of the operational amplifier OP1. The resistor R12 is provided between the non-inverting input terminal of the operational amplifier OP1 and a reference voltage supply terminal to which a reference voltage VSS is supplied. The resistor R13 is provided between the inverting input terminal of the operational amplifier OP1 and the reference voltage supply terminal. The resistor R14 is provided between the output terminal and the inverting input terminal of the operational amplifier OP1. The output voltage of the operational amplifier OP1 is used as the ramp signal Rmp1. The operational amplifier OP1 and the resistors R11 to R14 function as a subtraction circuit that subtracts 0V from the potential of the ramp signal Rmp0 and outputs the result as the ramp signal Rmp1.

[0085] The resistor R21 is provided between the output terminal of the DA converter 2032 and the non-inverting input terminal of the operational amplifier OP2. The resistor R22 is provided between the non-inverting input terminal of the operational amplifier OP2 and the reference voltage supply terminal. The resistor R23 and the voltage source Vofs1 are provided between the inverting input terminal of the operational amplifier OP2 and the reference voltage supply terminal. The voltage source Vofs1 outputs a voltage Vofs. The resistor R24 ​​is provided between the output terminal and the inverting input terminal of the operational amplifier OP2. The output voltage of the operational amplifier OP2 is used as the ramp signal Rmp2. The operational amplifier OP2 and the resistors R21 to R24 function as a subtraction circuit that subtracts the voltage Vofs from the potential of the ramp signal Rmp0 and outputs the result as the ramp signal Rmp2.

[0086] The resistor R31 is provided between the output terminal of the DA converter 2032 and the non-inverting input terminal of the operational amplifier OP3. The resistor R32 is provided between the non-inverting input terminal of the operational amplifier OP3 and the reference voltage supply terminal. The resistor R33 and the voltage source Vofs2 are provided between the inverting input terminal of the operational amplifier OP3 and the reference voltage supply terminal. The voltage source Vofs2 outputs a voltage Vofs2 (=Vofs×2). The resistor R34 is provided between the output terminal and the inverting input terminal of the operational amplifier OP3. The output voltage of the operational amplifier OP3 is used as the ramp signal Rmp3. The operational amplifier OP3 and the resistors R31 to R34 function as a subtraction circuit that subtracts the voltage Vofs2 from the potential of the ramp signal Rmp0 and outputs the result as the ramp signal Rmp3.

[0087] The resistor R41 is provided between the output terminal of the DA converter 2032 and the non-inverting input terminal of the operational amplifier OP4. The resistor R42 is provided between the non-inverting input terminal of the operational amplifier OP4 and the reference voltage supply terminal. The resistor R43 and the voltage source Vofs3 are provided between the inverting input terminal of the operational amplifier OP4 and the reference voltage supply terminal. The voltage source Vofs3 outputs a voltage Vofs3 (=Vofs×3). The resistor R44 is provided between the output terminal and the inverting input terminal of the operational amplifier OP4. The output voltage of the operational amplifier OP4 is used as the ramp signal Rmp4. The operational amplifier OP4 and the resistors R41 to R44 function as a subtraction circuit that subtracts the voltage Vofs3 from the potential of the ramp signal Rmp0 and outputs the result as the ramp signal Rmp4.

[0088] Fig. 9 is a timing chart showing a part of the operation of the liquid crystal display device 2. In the example of Fig. 9, the video signals "d1", "d2", "d3", and "d4" before being processed by the signal processing circuit 104 have the same gradation levels, but this is not limited thereto.

[0089] 9, the potential of the ramp signal Rmp2 at the start of its linear increase is shifted to a potential that is a predetermined voltage Vofs lower than the potential of the ramp signal Rmp1 at the start of its linear increase. Also, the potential of the ramp signal Rmp3 at the start of its linear increase is shifted to a potential that is a predetermined voltage Vofs2 lower than the potential of the ramp signal Rmp1 at the start of its linear increase. Furthermore, the potential of the ramp signal Rmp4 at the start of its linear increase is shifted to a potential that is a predetermined voltage Vofs3 lower than the potential of the ramp signal Rmp1 at the start of its linear increase.

[0090] Here, the count time of the added value "k" included in the processed video signal "d2+k" by the grayscale counter 109 is the same as the time Tofs taken for the ramp signal Rmp2 to return to the reference potential from a potential that is lower by a voltage Vofs than the reference potential (0 V). Therefore, the sampling timing of the ramp signal Rmp2 based on the video signal "d2+k" is shifted a predetermined period Tofs later than the sampling timing of the ramp signal Rmp1 based on the video signal "d1".

[0091] Furthermore, the count time of the added value "2k" included in the processed video signal "d3+2k" by the grayscale counter 109 is the same as the time Tofs2 (=Tofs×2) required for the ramp signal Rmp3 to return to the reference potential from a potential that is lower than the reference potential by a voltage Vofs2. Therefore, the sampling timing of the ramp signal Rmp3 based on the video signal "d3+2k" is shifted a predetermined period Tofs2 later than the sampling timing of the ramp signal Rmp1 based on the video signal "d1".

[0092] Furthermore, the count time of the added value "3k" included in the processed video signal "d4+3k" by the grayscale counter 109 is the same as the time Tofs3 (=Tofs×3) required for the ramp signal Rmp4 to return to the reference potential from a potential that is lower than the reference potential by a voltage Vofs3. Therefore, the sampling timing of the ramp signal Rmp4 by the video signal "d4+3k" is shifted a predetermined period Tofs3 later than the sampling timing of the ramp signal Rmp1 by the video signal "d1".

[0093] As a result, the sampled voltage of ramp signal Rmp1 based on video signal "d1", the sampled voltage of ramp signal Rmp2 based on video signal "d2+k", the sampled voltage of ramp signal Rmp3 based on video signal "d3+2k", and the sampled voltage of ramp signal Rmp4 based on video signal "d4+3k" show the same value.

[0094] In this way, the liquid crystal display device 2 can shift the sampling timings of the ramp signals Rmp1 to Rmp4 based on the video signals "d1", "d2", "d3", and "d4" of the same gradation level, thereby suppressing fluctuations in the power supply voltage that occur when the sampling timings of the ramp signals based on multiple video signals of the same gradation level are simultaneous.

[0095] As described above, the liquid crystal display device 2 according to the present embodiment can shift the sampling timing of the ramp signals from a plurality of video signals of the same gradation level, thereby suppressing the fluctuation of the power supply voltage that occurs when the ramp signals from a plurality of video signals of the same gradation level are sampled simultaneously. As a result, the liquid crystal display device 2 according to the present embodiment can reduce deterioration of image quality.

[0096] Furthermore, in the liquid crystal display device 2 according to this embodiment, the ramp signal generating circuit 203 can be simply configured with a set of a q-bit counter and a DA converter, and four operational amplifiers, so that an increase in costs can be suppressed. Note that in this embodiment, a condition may occur in which the sampling timing of the video signal to which the addition value is added exceeds the end point of the ramp signal. Therefore, in this embodiment, it is preferable that a clipping process is performed on the video signal on the high gradation side so that a timing failure does not occur, or that a level limiting process is performed on the video signal by applying a gain of less than 1 to the video signal.

[0097] In the present embodiment, the ramp signal generating circuit 203 generates ramp signals Rmp1 to Rmp4 in which the potential at the start of the linear increase is shifted by different amounts, but the present invention is not limited to this. The ramp signal generating circuit 203 may be configured to generate two or more ramp signals in which the potential at the start of the linear increase is shifted by different amounts. In this case, the m columns of data lines D1 to Dm are divided into two or more data line groups corresponding to the two or more ramp signals. Then, the two or more signal lines through which the two or more ramp signals propagate are connected to the two or more data line groups via the switch circuit 110.

[0098] The present disclosure is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit and scope of the present disclosure.

[0099] In addition, in the present disclosure, a part or all of the control processing in the liquid crystal display device 1 can be realized by causing a CPU (Central Processing Unit) to execute a computer program.

[0100] The above-mentioned program includes a set of instructions (or software code) for making the computer perform one or more functions described in the embodiment when the program is loaded into the computer. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or the tangible storage medium includes a random-access memory (RAM), a read-only memory (ROM), a flash memory, a solid-state drive (SSD) or other memory technology, a CD-ROM, a digital versatile disc (DVD), a Blu-ray® disk or other optical disk storage, a magnetic cassette, a magnetic tape, a magnetic disk storage or other magnetic storage device. The program may be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or the communication medium includes an electrical, optical, acoustic, or other form of propagating signal.

[0101] Furthermore, some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0102] (Appendix 1) an image display unit having a plurality of pixels arranged in a two-dimensional matrix; a ramp signal generating circuit that outputs first and second ramp signals whose potentials increase linearly in a horizontal scanning period; A signal processing circuit; a horizontal shift register that sequentially receives a plurality of video signals, the number of which corresponds to the number of columns of the plurality of pixels, and that have been processed by the signal processing circuit; a latch circuit that simultaneously outputs the plurality of video signals captured by the horizontal shift register; A grayscale counter that performs a count-up operation in a horizontal scanning period; a plurality of comparators that output a match signal when each of the plurality of video signals output from the latch circuit matches a count value of the gradation counter; a switch circuit that outputs, to a pixel in a column corresponding to a comparator that outputs a coincidence signal among the plurality of comparators, one of the first ramp signal and the second ramp signal at a timing when the coincidence signal is output, the voltage corresponding to the pixel; A method for controlling a liquid crystal display device, comprising: In the ramp signal generating circuit, the first ramp signal and the second ramp signal are shifted by different shift amounts, in the signal processing circuit, among a plurality of video signals used in one horizontal scanning period, the number of which corresponds to the number of columns of the plurality of pixels, a correction value corresponding to a shift amount of the first ramp signal is added to a video signal corresponding to the first ramp signal, and a correction value corresponding to a shift amount of the second ramp signal is added to a video signal corresponding to the second ramp signal; A method for controlling a liquid crystal display device.

[0103] (Appendix 2) an image display unit having a plurality of pixels arranged in a two-dimensional matrix; a ramp signal generating circuit that outputs first and second ramp signals whose potentials increase linearly in a horizontal scanning period; A signal processing circuit; a horizontal shift register that sequentially receives a plurality of video signals, the number of which corresponds to the number of columns of the plurality of pixels, and that have been processed by the signal processing circuit; a latch circuit that simultaneously outputs the plurality of video signals captured by the horizontal shift register; A grayscale counter that performs a count-up operation in a horizontal scanning period; a plurality of comparators that output a match signal when each of the plurality of video signals output from the latch circuit matches a count value of the gradation counter; a switch circuit that outputs, to a pixel in a column corresponding to a comparator that outputs a coincidence signal among the plurality of comparators, one of the first ramp signal and the second ramp signal at a timing when the coincidence signal is output, the voltage corresponding to the pixel; A control program for causing a computer to execute a control process in a liquid crystal display device, comprising: A process of shifting the first ramp signal and the second ramp signal by different shift amounts in the ramp signal generating circuit; a process in the signal processing circuit of adding a correction value according to a shift amount of the first ramp signal to a video signal corresponding to the first ramp signal among a plurality of video signals corresponding to the number of columns of the plurality of pixels used in one horizontal scanning period, and adding a correction value according to the shift amount of the second ramp signal to a video signal corresponding to the second ramp signal; A control program that causes a computer to execute the above. [Explanation of symbols]

[0104] 1 LCD display device 2 LCD display device 101 pixel display 102 Control circuit 103 Ramp signal generating circuit 104 Signal Processing Circuit 105 Vertical drive circuit 106 Shift Register Circuit 107 1-line latch circuit 108 Comparator Group 109 Gradation Counter 110 Switch Circuit 202 Control circuit 203 Ramp signal generating circuit 1031_1~1031_4 AND circuit 1032_1~1032_4 q-bit counter 1033_1~1033_4 DA converter 1041 Addition value switching circuit 1042 Addition circuit 2031 q-bit counter 2032 DA converter C1~Cm Comparator D1~Dm Data line G1~Gn row scanning line OP1~OP4 Op-amps R11~R14 Resistance elements R21~R24 Resistance elements R31 to R34 Resistance elements R41 to R44 Resistance elements S1~Sm Switch

Claims

1. an image display unit having a plurality of pixels arranged in a two-dimensional matrix; a ramp signal generating circuit that outputs a plurality of ramp signals whose potentials increase linearly in a horizontal scanning period by shifting the signals by different shift amounts; a signal processing circuit that adds a correction value corresponding to a shift amount of an assigned ramp signal to each of a plurality of video signals, the number of which corresponds to the number of columns of the plurality of pixels, used in one horizontal scanning period; a horizontal shift register that sequentially receives the plurality of video signals processed by the signal processing circuit; a latch circuit that simultaneously outputs the plurality of video signals captured by the horizontal shift register; A grayscale counter that performs a count-up operation in a horizontal scanning period; a plurality of comparators that output a match signal when each of the plurality of video signals output from the latch circuit matches a count value of the gradation counter; a switch circuit that outputs, to a pixel in a column corresponding to a comparator that outputs a coincidence signal among the plurality of comparators, a voltage among the plurality of ramp signals corresponding to the pixel at a timing when the coincidence signal is output; A liquid crystal display device comprising:

2. the ramp signal generating circuit outputs the plurality of ramp signals by shifting the timings of the start of a linear increase in the potential of each of the plurality of ramp signals by different shift amounts. The liquid crystal display device according to claim 1 .

3. the ramp signal generating circuit shifts potentials of the plurality of ramp signals at the start of a linear increase by different shift amounts and outputs the shifted potentials. The liquid crystal display device according to claim 1 .

4. an image display unit having a plurality of pixels arranged in a two-dimensional matrix; a ramp signal generating circuit that outputs first and second ramp signals whose potentials increase linearly in a horizontal scanning period by shifting the first and second ramp signals by different shift amounts; a signal processing circuit that adds a correction value corresponding to a shift amount of the first ramp signal to a video signal corresponding to the first ramp signal among a plurality of video signals corresponding to the number of columns of the plurality of pixels used in one horizontal scanning period, and adds a correction value corresponding to the shift amount of the second ramp signal to a video signal corresponding to the second ramp signal; a horizontal shift register that sequentially receives the plurality of video signals processed by the signal processing circuit; a latch circuit that simultaneously outputs the plurality of video signals captured by the horizontal shift register; A grayscale counter that performs a count-up operation in a horizontal scanning period; a plurality of comparators that output a match signal when each of the plurality of video signals output from the latch circuit matches a count value of the gradation counter; a switch circuit that outputs, to a pixel in a column corresponding to a comparator that outputs a coincidence signal among the plurality of comparators, one of the first ramp signal and the second ramp signal at a timing when the coincidence signal is output, the voltage corresponding to the pixel; A liquid crystal display device comprising:

5. an image display unit having a plurality of pixels arranged in a two-dimensional matrix; a ramp signal generating circuit that outputs a plurality of ramp signals whose potentials increase linearly in a horizontal scanning period; A signal processing circuit; a horizontal shift register that sequentially receives a plurality of video signals, the number of which corresponds to the number of columns of the plurality of pixels, and that have been processed by the signal processing circuit; a latch circuit that simultaneously outputs the plurality of video signals captured by the horizontal shift register; A grayscale counter that performs a count-up operation in a horizontal scanning period; a plurality of comparators that output a match signal when each of the plurality of video signals output from the latch circuit matches a count value of the gradation counter; a switch circuit that outputs, to a pixel in a column corresponding to a comparator that outputs a coincidence signal among the plurality of comparators, a voltage among the plurality of ramp signals corresponding to the pixel at a timing when the coincidence signal is output; A method for controlling a liquid crystal display device, comprising: In the ramp signal generating circuit, the plurality of ramp signals are shifted by different shift amounts, In the signal processing circuit, a correction value according to a shift amount of an assigned ramp signal is added to each of a plurality of video signals, the number of which corresponds to the number of columns of the plurality of pixels, used in one horizontal scanning period. A method for controlling a liquid crystal display device.

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