Buffer circuit and semiconductor integrated circuit

Abstract

To provide a buffer circuit capable of accurately receiving a signal whose amplitude is smaller than VDD / 2.SOLUTION: A CMOS inverter 210 receives a reception signal S1. A current limiting element 220 is provided between the source of a PMOS transistor of the CMOS inverter 210 and a power supply line. A Schmitt trigger circuit 230 receives the output of the CMOS inverter 210. An auxiliary circuit 240 is enabled in a high input state in which an output S4 of the Schmitt trigger circuit 230 assumes a level corresponding to a high level of the reception signal S1, and can supply a current I1 to the source of the PMOS transistor of the CMOS inverter 210.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a buffer circuit for receiving a binary signal. [Background technology]

[0002] Semiconductor integrated circuits (ICs) are configured to be able to transmit and receive binary signals to each other. A buffer circuit is provided at the input stage of the receiving IC. The buffer circuit generally has a hysteresis setting to remove noise.

[0003] If the first stage of the buffer circuit is composed of a normal CMOS (Complementary Metal Oxide Semiconductor) inverter, its threshold voltage is V DD1 and the amplitude is V DD1 On the other hand, the amplitude of the transmission signal output by the transmitting IC is the power supply voltage V DD2 is limited to V DD2 Therefore, V DD2 <V DD1 In a system where the input signal is 1 / 2, the buffer circuit of the receiving IC cannot receive the output signal of the transmitting IC with the correct input signal.

[0004] V DD2 <V DD1 In a system with a 1 / 2 ratio, the first stage of the buffer circuit needs to be configured differently from a CMOS inverter. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2009-124537 A

[0006] [overview] The present disclosure has been made in this context, and one exemplary object of an embodiment of the present disclosure is to provide a method for detecting a voltage having an amplitude of V DDTo provide a buffer circuit capable of accurately receiving a signal smaller than 1 / 2.

[0007] A buffer circuit according to an embodiment of the present disclosure includes a CMOS (Complementary Metal Oxide Semiconductor) inverter that receives a received signal, a current limiting element provided between a source of a P (P-channel) MOS transistor of the CMOS inverter and a power supply line, a Schmitt trigger circuit that receives an output of the CMOS inverter, and an auxiliary circuit that is enabled in a high input state in which the output of the Schmitt trigger circuit has a level corresponding to the high level of the received signal and is capable of supplying a current to the source of the PMOS transistor of the CMOS inverter.

[0008] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc., are also effective as aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram of a semiconductor integrated circuit including a buffer circuit according to the embodiment. [Diagram 2] FIG. 2 is a circuit diagram of the buffer circuit according to the first embodiment. [Diagram 3] FIG. 3 is a circuit diagram showing a configuration example of the buffer circuit of FIG. [Figure 4] FIG. 4 is a circuit diagram of a buffer circuit according to a comparative technique. [Diagram 5] FIG. 5 is an operational waveform diagram of the buffer circuit of FIG. [Figure 6] FIG. 6 is an operational waveform diagram of the buffer circuit of FIG. [Figure 7] FIG. 7 is a circuit diagram of a buffer circuit in accordance with the second embodiment. [Figure 8]FIG. 8 is a circuit diagram of a buffer circuit in accordance with a third embodiment. [Figure 9] FIG. 9 is a circuit diagram showing a configuration example of the buffer circuit of FIG. [Figure 10] FIG. 10 is a detailed circuit diagram of the buffer circuit of FIG. [Figure 11] FIG. 11 is a circuit diagram of a buffer circuit according to the first modification. [Figure 12] FIG. 12 is a circuit diagram of a buffer circuit according to the second modification.

[0010] [Detailed Description] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0011] A buffer circuit according to one embodiment includes a CMOS (Complementary Metal Oxide Semiconductor) inverter that receives a received signal, a current limiting element provided between a source of a P (P-channel) MOS transistor of the CMOS inverter and a power supply line, a Schmitt trigger circuit that receives an output of the CMOS inverter, and an auxiliary circuit that is enabled in a high input state in which the output of the Schmitt trigger circuit has a level corresponding to a high level of the received signal and is capable of supplying a current to the source of the PMOS transistor of the CMOS inverter.

[0012] In this configuration, by providing a current limiting element on the power supply side of the CMOS inverter, the current is limited even if the PMOS transistor and NMOS transistor of the CMOS inverter try to turn on at the same time, so the signal can be transmitted. In a configuration with only a current limiting element and no auxiliary circuit, when the received signal is high (V DD2 ) to low (0V), the NMOS transistor is completely off and the PMOS transistor is on, so the output of the CMOS inverter transitions from low to high at high speed. On the other hand, when the received signal transitions from low to high (V DD2 ), the NMOS transistor is fully on, but the gate voltage of the PMOS transistor (V DD2 ) is the power supply voltage of the CMOS inverter (V DD1 ), the gate-source voltage does not become zero and the CMOS inverter is not completely turned off. This slows down the transition of the output of the CMOS inverter. In the above embodiment, the auxiliary circuit supplies additional current to the CMOS inverter, so that the output of the CMOS inverter can transition from high to low at high speed.

[0013] In one embodiment, the auxiliary circuit may include a capacitor and a first switch that is turned on in a high input state, connected in series between the source of the PMOS transistor and ground. When the first switch is turned on, the charge stored in the capacitor can be supplied as a current to the source of the PMOS transistor.

[0014] In one embodiment, the auxiliary circuit may further include a precharge circuit configured to apply a precharge voltage across the capacitor in a low input state in which the output of the Schmitt trigger circuit is at a level corresponding to the low level of the received signal. If the voltage of the capacitor fluctuates, the transition speed (slew rate) of the output of the CMOS inverter fluctuates. By providing the precharge circuit, the voltage of the capacitor can be determined when the auxiliary circuit is enabled, and the circuit operation can be further stabilized.

[0015] In one embodiment, the first switch may be provided on a higher potential side than the capacitor. The precharge circuit may be configured to apply a precharge voltage to a connection node between the first switch and the capacitor in a low input state.

[0016] In one embodiment, the first switch is provided on the higher potential side of the capacitor, and the precharge circuit may include a constant voltage source that generates a precharge voltage, and a second switch that is connected between a connection node between the first switch and the capacitor and an output of the constant voltage source and is turned on in a low input state.

[0017] In one embodiment, the constant voltage source may include a first current source and an impedance element connected between the first current source and ground, and may output a voltage at a connection node between the first current source and the impedance element.

[0018] In one embodiment, the impedance element may include a first transistor that is a P (N-channel) MOS transistor that is turned on in a low input state, thereby reducing the power consumption of the constant voltage source.

[0019] In one embodiment, the first switch may be provided on a lower potential side of the capacitor, and the precharge circuit may be configured to apply a precharge voltage across the capacitor in a low input state.

[0020] In one embodiment, the current limiting element may include a second current source.

[0021] In one embodiment, the second current source may include a reference current source that generates a reference current, and a current mirror circuit that is connected to the reference current source and mirrors the reference current.

[0022] In one embodiment, the current limiting element may include a resistor.

[0023] In one embodiment, the auxiliary circuit may include a third current source and a second switch connected between the third current source and the source of the PMOS transistor, the second switch being on in a high input state.

[0024] In one embodiment, the current limiting element may include a second current source.

[0025] In one embodiment, the second current source may include a reference current source that generates a reference current, and a current mirror circuit that is connected to the reference current source and mirrors the reference current.

[0026] In one embodiment, the current limiting element may include a resistor.

[0027] A semiconductor integrated circuit according to one embodiment includes any of the buffer circuits described above and is monolithically integrated on a single semiconductor substrate. "Monolithic integration" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are monolithically integrated, and some resistors and capacitors for adjusting circuit constants may be provided outside the semiconductor substrate. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0028] (Embodiment) In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0029] Similarly, "a state in which component C is connected (provided) between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0030] FIG. 1 is a circuit diagram of a semiconductor integrated circuit 100 including a buffer circuit 200 according to an embodiment.

[0031] The semiconductor integrated circuit 100 is connected to another semiconductor integrated circuit 2. The semiconductor integrated circuit 2 transmits a digital signal S1 having two values, high and low. The low level of the digital signal S1 is 0V (ground voltage) and the high level V H is the power supply voltage V of the semiconductor integrated circuit 2. DD2 The semiconductor integrated circuit 100 receives this digital signal S1 as a received signal.

[0032] The semiconductor integrated circuit 100 includes a buffer circuit 200 and a logic circuit 110. A power supply voltage V DD1 This power supply voltage V DD1 is the amplitude (high level) voltage V of the received signal S1 H (i.e., power supply voltage V DD2 ) higher.

[0033] The buffer circuit 200 receives the received signal S1 and passes the internal signal S2 to the logic circuit 110. The internal signal S2 has a high level equal to or lower than the power supply voltage V DD1 and the low level is 0V.

[0034] The buffer circuit 200 includes a CMOS inverter 210 , a current limiting element 220 , a Schmitt trigger circuit 230 , an auxiliary circuit 240 , and an output buffer 250 .

[0035] The first-stage CMOS inverter 210 includes a PMOS transistor MP1 and an NMOS transistor MN1. A received signal S1 is input to the CMOS inverter 210. In general, the capabilities of PMOS transistors and NMOS transistors are matched when used, so the threshold voltage of the CMOS inverter 210 is V DD1 / 2, but in this embodiment, the amplitude is V DD2 The received signal S1 is DD1 (V DD1>V DD2 ) must be received by the CMOS inverter 210 operating at the threshold voltage V TH1 V DD2 To achieve this, the size (capability) of the NMOS transistor in the CMOS inverter 210 is changed.

[0036] The received signal S1 is at high level V H When the NMOS transistor MN1 is fully on, the gate-source voltage of the PMOS transistor MP1 is V DD1 -V H Therefore, the received signal S1 is at high level V H At this time, a through current flows through the CMOS inverter 210. The current limiting element 220 is provided between the power supply node PS of the CMOS inverter 210, i.e., the source of the PMOS transistor MP1, and the power supply line 102. The current limiting element 220 limits the amount of the through current flowing through the CMOS inverter 210 to I0.

[0037] The Schmitt trigger circuit 230 receives the output S3 of the CMOS inverter 210. In this embodiment, the Schmitt trigger circuit 230 is of the inverting type, and the output S4 of the Schmitt trigger circuit 230 has the same logic value as the received signal S1.

[0038] The auxiliary circuit 240 is enabled when the output of the Schmitt trigger circuit 230 assumes a level corresponding to the high level of the received signal S1 (referred to as a high input state). In the enabled state, the auxiliary circuit 240 is configured to be able to supply an auxiliary current I1 to the power supply node PS of the CMOS inverter 210, i.e., the source of the PMOS transistor MP1.

[0039] The output buffer 250 receives the output of the Schmitt trigger circuit 230 and generates an internal signal S2. In this example, the output buffer 250 is a non-inverting buffer, and the internal signal S2 has the same logical value as the received signal S1. Note that, although the output of the output buffer 250 is considered to be the buffer circuit 200 here, the output buffer 250 may be considered as a component of the logic circuit 110. Alternatively, if the output impedance of the Schmitt trigger circuit 230 is sufficiently low, the output buffer 250 may be omitted.

[0040] The basic configuration of the buffer circuit 200 has been described above.

[0041] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram in Fig. 1 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described in order to aid in understanding the essence and operation of the present disclosure and the present invention and to clarify them, without narrowing the scope of the present disclosure.

[0042] 2 is a circuit diagram of a buffer circuit 200A according to Example 1. In this example, a current limiting element 220A is a constant current source and is configured to supply a constant current I0 to a power supply node (the source of a PMOS transistor) PS of a CMOS inverter 210.

[0043] The auxiliary circuit 240A includes a capacitor C1 and a first switch SW1. The capacitor C1 and the first switch SW1 are connected in series between the source S of the PMOS transistor of the CMOS inverter 210 and the ground. In this example, the first switch SW1 is provided on the low potential side, and the capacitor C1 is provided on the high potential side.

[0044] The first switch SW1 is turned on in a high input state. When the first switch SW1 is configured to be turned on in response to a high control input and turned off in response to a low control input, the output signal of the Schmitt trigger circuit 230 can be used as the control input of the first switch SW1.

[0045] FIG. 3 is a circuit diagram showing a configuration example (200Aa) of the buffer circuit 200A of FIG.

[0046] The current limiting element 220Aa includes a reference current source 222 and a current mirror circuit 224. The reference current source 222 outputs a reference current I REF The input node of the current mirror circuit 224 is connected to the reference current source 222, and the output node of the current mirror circuit 224 is connected to the source S of the PMOS transistor of the CMOS inverter 210. The current mirror circuit 224 generates a reference current I REF A current I0 proportional to the input current Ip is supplied to the power supply node PS of the CMOS inverter 210.

[0047] The first switch SW1 of the auxiliary circuit 240Aa is composed of an NMOS transistor MN2, and its gate is input with the output S4 of the Schmitt trigger circuit 230. The first switch SW1 is turned on when the output S4 of the Schmitt trigger circuit 230 is high, that is, when the received signal S1 is in a high input state.

[0048] Next, the operation of the buffer circuit 200A will be described in comparison with the comparative technique. First, the configuration of the comparative technique will be described.

[0049] 4 is a circuit diagram of a buffer circuit 200R according to a comparative technique, which is obtained by omitting the auxiliary circuit 240A from the buffer circuit 200A in FIG.

[0050] Next, the operation of the buffer circuit 200R will be described. FIG. 5 is a waveform diagram showing the operation of the buffer circuit 200R shown in FIG. DD1 = 5V, high level V of received signal S1 H is set to 2V.

[0051] Before time t0, the receive signal S1 is in a low input state φ LAt this time, the NMOS transistor of the CMOS inverter 210 is off and the PMOS transistor is on. At this time, the internal signal S2 is at a high level (V DD1 =5V).

[0052] At time t1, the reception signal S1 transitions from a low level to a high level, and the high input state φ H This turns on the NMOS transistor MN1 of the CMOS inverter 210. This causes the output signal S3 of the CMOS inverter 210 to transition to a low level at high speed, and the internal signal S2 also transitions to a high level at high speed without any delay.

[0053] High input state φ H During this period, the gate-source voltage of the PMOS transistor MP1 of the CMOS inverter 210 is not 0V, so the PMOS transistor MP1 is also in an on state. Therefore, a through current flows through the CMOS inverter 210. The through current causes the voltage V PS is the power supply voltage V DD1 will be lower than

[0054] At time t1, the receiving signal S1 transitions from high to low. This causes the PMOS transistor MP1 of the CMOS inverter 210 to be fully on. At this time, the current that the CMOS inverter 210 draws from the power supply node PS increases, so that the voltage V PS Then, the power supply voltage V DD1 The output signal S3 of the CMOS inverter 210 is at a high level, but its voltage level is higher than the voltage V PS Since the slew rate of the output signal S3 is substantially equal to the voltage V PS is limited by

[0055] At time t2, the voltage level of the output signal S3 of the CMOS inverter 210 becomes equal to the threshold voltage V THS, the output signal S4 of the Schmitt trigger circuit 230 transitions to low.

[0056] That is, in the comparative technique, when the received signal S1 transitions from high to low, the output signal S4 of the output buffer 250 is delayed by the time difference τ between t1 and t2 with respect to the received signal S1. In this way, the buffer circuit 200R according to the comparative technique has different responses to the positive edge (rising edge) and the negative edge (falling edge) of the received signal S1.

[0057] Next, the operation of the buffer circuit 200A according to the first embodiment will be described.

[0058] Fig. 6 is an operation waveform diagram of the buffer circuit 200A of Fig. 2. In Fig. 6, an operation waveform S3' of the buffer circuit 200R according to the comparative technique is shown by a dashed line. The operation up to time t1 is similar to that of the comparative technique.

[0059] At time t1, the receiving signal S1 transitions from high to low. This causes the PMOS transistor MP1 of the CMOS inverter 210 to be fully on. At this time, the current that the CMOS inverter 210 draws from the power supply node PS increases. At this time, the auxiliary circuit 240 is in an enabled state, and the current supply capability for the CMOS inverter 210 is increased to I0+I1. Therefore, the voltage V of the power supply node PS PS At time t2′, the output signal S3 of the CMOS inverter 210 decreases the threshold voltage V THS , the output signal S4 of the Schmitt trigger circuit 230 transitions to low, which disables the auxiliary circuit 240A.

[0060] As a result, in the buffer circuit 200A of FIG. 2, the rising timing t2' of the output signal S3 is earlier than the timing t2 of the buffer circuit 200R of FIG. 4, and the delay time τ' is shorter.

[0061] The above is the operation of the buffer circuit 200. With this buffer circuit 200, the response to the negative edge (falling edge) of the received signal S1 can be made closer to the response to the positive edge (rising edge).

[0062] Example 2 7 is a circuit diagram of a buffer circuit 200B according to Example 2. In this buffer circuit 200B, the configuration of an auxiliary circuit 240B is different from that of the auxiliary circuit 240A. In the auxiliary circuit 240B, a switch SW1 is provided on the high potential side, and a capacitor C1 is provided on the low potential side.

[0063] In this embodiment, the first switch SW1 is a PMOS transistor MP2, and an enable signal EN (inverted logic) is input to the gate of the PMOS transistor MP2. For example, the enable signal EN can be the output signal S5 of the first inverter 252 of the output buffer 250.

[0064] According to the buffer circuit 200B of the second embodiment, it is possible to obtain the same effects as those of the buffer circuit 200A of the first embodiment.

[0065] Example 3 8 is a circuit diagram of a buffer circuit 200C according to Example 3. The buffer circuit 200C is obtained by adding a precharge circuit 260 to the buffer circuit 200B in FIG.

[0066] The precharge circuit 260 is in a high input state φ where the output S4 of the Schmitt trigger circuit 230 is at a level corresponding to the high level of the received signal S1. H The precharge circuit 260 is enabled in the high input state φ H A predetermined precharge voltage V PC is applied.

[0067] 9 is a circuit diagram showing a configuration example (200Ca) of the buffer circuit 200C of FIG. 8. The precharge circuit 260 includes a constant voltage source 262 and a second switch SW2. The second switch SW2 is connected between the output of the constant voltage source 262 and the second end of the capacitor C1. The second switch SW2 is in a low input state φ in which the output of the Schmitt trigger circuit 230 takes a level corresponding to the low level of the received signal S1. L It is turned on at

[0068] When the second switch SW2 is configured to be turned on in response to a low control input and turned off in response to a high control input, the output signal S2 of the output buffer 250 or the output signal S4 of the Schmitt trigger circuit 230 can be used as the control input of the second switch SW2.

[0069] Fig. 10 is a detailed circuit diagram of the buffer circuit 200Ca of Fig. 9. The second switch SW2 of the precharge circuit 260 is composed of a PMOS transistor MP3, and the output signal S2 of the output buffer 250 (or the output S4 of the Schmitt trigger circuit 230) is input to the gate thereof.

[0070] The constant voltage source 262 includes a current source 264 and an impedance element 266. In this embodiment, the impedance element 266 is a PMOS transistor MP4, which is turned on in a low input state. The received signal S1 is input to the gate of the PMOS transistor MP4. A capacitor C2 is connected between the gate and drain of the PMOS transistor MP4. In a low input state where the received signal S1 is low, the PMOS transistor MP4 is turned on, and a voltage V proportional to the on-resistance Ron of the PMOS transistor MP4 is applied to the source of the PMOS transistor MP4. PC occurs. V PC =I REF ×Ron Since the PMOS transistor MP4 is turned off in a high input state, a current flows through the constant voltage source 262 only in a low input state, thereby reducing power consumption. The signal S2 or S4 may be supplied to the gate of the PMOS transistor MP4.

[0071] If an increase in current consumption is permissible, a resistor may be used as the impedance element 266 instead of the PMOS transistor MP4.

[0072] (Modification) The above-described embodiment is merely an example, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each processing step. Such modifications will be described below.

[0073] (Variation 1) 11 is a circuit diagram of a buffer circuit 200D according to Modification 1. In this modification, a resistor is used as a current limiting element 220D instead of a current source.

[0074] (Variation 2) 12 is a circuit diagram of a buffer circuit 200E according to Modification 2. In this modification, instead of a capacitor as the auxiliary circuit 240, a current source that can be switched between disabled and enabled is used.

[0075] The embodiments are merely examples, and it will be understood by those skilled in the art that there are various modifications in the combination of each component and each treatment process, and that such modifications are also included within the scope of the present disclosure or the present invention.

[0076] (Additional Note) The present specification discloses the following techniques:

[0077] (Item 1) a CMOS (Complementary Metal Oxide Semiconductor) inverter that receives a received signal; A current limiting element provided between a source of a P (P-channel) MOS transistor of the CMOS inverter and a power supply line; a Schmitt trigger circuit receiving an output of the CMOS inverter; an auxiliary circuit, the auxiliary circuit being enabled when the output of the Schmitt trigger circuit assumes a high input state corresponding to the high level of the received signal, and capable of supplying a current to the source of the PMOS transistor of the CMOS inverter; A buffer circuit comprising:

[0078] (Item 2) The auxiliary circuit includes: 2. The buffer circuit of claim 1, further comprising: a capacitor and a first switch, the first switch being on in the high input state, connected in series between the source of the PMOS transistor and ground.

[0079] (Item 3) The buffer circuit of item 2, wherein the auxiliary circuit further includes a precharge circuit configured to apply a precharge voltage across the capacitor in a low input state in which the output of the Schmitt trigger circuit has a level corresponding to the low level of the received signal.

[0080] (Item 4) the first switch is provided on a higher potential side than the capacitor, 4. The buffer circuit of claim 3, wherein the precharge circuit is configured to apply the precharge voltage to a connection node between the first switch and the capacitor in the low input state.

[0081] (Item 5) the first switch is provided on a higher potential side than the capacitor, The precharge circuit includes: a constant voltage source for generating the precharge voltage; a second switch connected between a connection node of the first switch and the capacitor and an output of the constant voltage source, the second switch being turned on in the low input state; 4. The buffer circuit of item 3, comprising:

[0082] (Item 6) The constant voltage source is A first current source; an impedance element connected between the first current source and ground; and outputs a voltage of a connection node between the first current source and the impedance element.

[0083] (Item 7) 7. The buffer circuit of claim 6, wherein the impedance element includes a first transistor that is a P (N-channel) MOS transistor that is turned on in the low input state.

[0084] (Item 8) the first switch is provided on a lower potential side than the capacitor, 4. The buffer circuit of claim 3, wherein the precharge circuit is configured to apply the precharge voltage across the capacitor in the low input state.

[0085] (Item 9) 9. The buffer circuit of any one of items 2 to 8, wherein the current limiting element includes a second current source.

[0086] (Item 10) The second current source is A reference current source that generates a reference current; a current mirror circuit connected to the reference current source and mirroring the reference current; 10. The buffer circuit of item 9, comprising:

[0087] (Item 11) 9. The buffer circuit of any of items 2 to 8, wherein the current limiting element includes a resistor.

[0088] (Item 12) The auxiliary circuit includes: A third current source; a second switch connected between the third current source and the source of the PMOS transistor, the second switch being turned on in the high input state; 2. The buffer circuit of claim 1,

[0089] (Item 13) Item 13. The buffer circuit of item 12, wherein the current limiting element includes a second current source.

[0090] (Item 14) The second current source is A reference current source that generates a reference current; a current mirror circuit connected to the reference current source and mirroring the reference current; Item 14. The buffer circuit of item 13, comprising:

[0091] (Item 15) Item 13. The buffer circuit of item 12, wherein the current limiting element includes a resistor.

[0092] (Item 16) 16. A semiconductor integrated circuit comprising the buffer circuit according to any one of items 1 to 15 and integrated on a single semiconductor substrate. [Explanation of symbols]

[0093] 100 Semiconductor integrated circuit 110 Logic Circuits 200 Buffer circuit 210 CMOS Inverter 220 Current limiting element 222 Reference current source 224 Current Mirror Circuit 230 Schmitt Trigger Circuit 240 Auxiliary circuit C1 Capacitor SW1 First switch 250 output buffers 260 Precharge Circuit 262 Constant Voltage Source 264 Current Source 266 Impedance Element

Claims

1. a CMOS (Complementary Metal Oxide Semiconductor) inverter for receiving a received signal; A current limiting element provided between a source of a P (P-channel) MOS transistor of the CMOS inverter and a power supply line; a Schmitt trigger circuit receiving an output of the CMOS inverter; an auxiliary circuit that is enabled when the output of the Schmitt trigger circuit is in a high input state corresponding to the high level of the received signal and is capable of supplying a current to the source of the PMOS transistor of the CMOS inverter; A buffer circuit comprising:

2. The auxiliary circuit includes:

2. The buffer circuit of claim 1 further comprising: a capacitor and a first switch, the first switch being on in the high input state, connected in series between the source of the PMOS transistor and ground.

3. 3. The buffer circuit according to claim 2, wherein the auxiliary circuit further includes a precharge circuit configured to be able to apply a precharge voltage across the capacitor in a low input state in which an output of the Schmitt trigger circuit has a level corresponding to a low level of the received signal.

4. the first switch is provided on a higher potential side than the capacitor, 4. The buffer circuit according to claim 3, wherein the precharge circuit is configured to apply the precharge voltage to a connection node between the first switch and the capacitor in the low input state.

5. the first switch is provided on a higher potential side than the capacitor, The precharge circuit includes: a constant voltage source for generating the precharge voltage; a second switch connected between a connection node of the first switch and the capacitor and an output of the constant voltage source, the second switch being turned on in the low input state; 4. The buffer circuit of claim 3, comprising:

6. The constant voltage source is A first current source; an impedance element connected between the first current source and ground; 6. The buffer circuit according to claim 5, further comprising: a first current source connected to said impedance element; and a voltage at a connection node between said first current source and said impedance element being output.

7. 7. The buffer circuit of claim 6, wherein the impedance element includes a first transistor that is a P (N-channel) MOS transistor that is turned on in the low input state.

8. the first switch is provided on a lower potential side than the capacitor, The buffer circuit of claim 3 , wherein the precharge circuit is configured to apply the precharge voltage across the capacitor in the low input state.

9. 9. The buffer circuit of claim 2, wherein the current limiting element includes a second current source.

10. The second current source is A reference current source that generates a reference current; a current mirror circuit connected to the reference current source and mirroring the reference current; 10. The buffer circuit of claim 9, comprising:

11. The buffer circuit of claim 2 , wherein the current limiting element includes a resistor.

12. The auxiliary circuit includes: A third current source; a second switch connected between the third current source and the source of the PMOS transistor, the second switch being turned on in the high input state; 2. The buffer circuit of claim 1, comprising:

13. The buffer circuit of claim 12 , wherein the current limiting element comprises a second current source.

14. The second current source is A reference current source that generates a reference current; a current mirror circuit connected to the reference current source and mirroring the reference current; 14. The buffer circuit of claim 13, comprising:

15. The buffer circuit of claim 12 , wherein the current limiting element comprises a resistor.

16. 9. A semiconductor integrated circuit comprising the buffer circuit according to claim 1, and integrated on a single semiconductor substrate.

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