Image processing device, image processing method, and program

Abstract

To efficiently utilize a memory in image processing for generating image data from print data.SOLUTION: Classification is performed on memory usage characteristics in a processing module unit or a task or subtask unit. The memory usage characteristics are characterized by each item of a required memory amount to be allocated at a time, allocation frequency of each required memory amount, and a life time (a time from allocation to release). The memory usage characteristics of a plurality of processing modules are collected to perform cluster analysis, and the plurality of processing modules are classified into a plurality of classes. Then, a design parameter of a memory allocator for increasing memory usage efficiency in each class is calculated on the basis of the memory usage characteristics of processing modules classified into the same class. The memory allocator with the design parameter calculated in each class is applied as a memory allocator common to processing modules classified into the same class.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to an image processing technique for generating image data from print data. [Background technology]

[0002] Conventionally, a rendering method has been widely used to draw a figure by extracting contour information (also called edge information) of the figure from the coordinate information etc. that the figure has, and generating image data based on the contour information. Generally, it is an important requirement for rendering processing to always be able to perform the drawing processing at high speed, but since the time actually required for rendering processing varies depending on the type and number of figures, it is not easy to achieve this.

[0003] Figure 1 is an overview diagram explaining the operation when parallel processing is performed to speed up RIP processing. When figure 1 and figure 2 exist, they are processed in separate, mutually independent threads-1 and-2, so that edge data of the two figures and fill information within the outlines of the figures are simultaneously extracted through color information extraction processing. Thread-3 performs data synthesis processing using the extracted edge data and color information. However, if the number of cores is increased to increase the number of parallel processes, access to the shared memory becomes a bottleneck in a multiprocessor system in which multiple processors share the main memory, and the processing efficiency of the entire system decreases.

[0004] Patent Document 1 proposes a multiprocessor system that uses a loosely coupled multiprocessor in which a plurality of processors each have an independent main memory, and has short latency and a relatively light processing load on each processor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2009-87335 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, even with the technology described in Patent Document 1, memory usage increases due to the execution of separate processes at the same time through parallel processing, and there are cases where the work memory is used up. In such cases, there is no choice but to deal with the problem by releasing small units of free space (fragmentation) that occur in the internal memory, or by releasing a large amount of unnecessary memory space (garbage collection). However, it is not easy to accurately predict fragmentation, and it is difficult to secure sufficient memory space by releasing fragmentation, and there is also the problem that garbage collection reduces processing speed. [Means for solving the problem]

[0007] The present invention is an image processing device that processes input data using a plurality of processing modules to generate image data, and is characterized in that it comprises a classification means that classifies the plurality of processing modules into a plurality of classes based on memory usage characteristics, and an application means that applies a common memory allocator having design parameters set based on the usage characteristics of the memory corresponding to the class to processing modules classified into the same class by the classification means. Effect of the Invention

[0008] In the present invention, memory can be used efficiently in image processing for generating image data from print data. [Brief description of the drawings]

[0009] [Figure 1] Overview of intermediate data generation process (parallel processing) [Diagram 2] A graph showing how processing time changes depending on input data [Diagram 3] Block diagram showing the configuration of a conventional printing system [Figure 4]Overview of memory usage in a conventional parallel processing system [Diagram 5] FIG. 1 is a block diagram showing a hardware configuration of an image processing apparatus according to a first embodiment. [Figure 6] FIG. 1 is a block diagram outlining a processing module for generating intermediate data according to the first embodiment; [Figure 7] Overview of the relationship between processing modules and memory allocators [Figure 8] Table showing an example of classification of memory allocators in the first embodiment [Figure 9] FIG. 1 is a flow diagram illustrating a recovery process according to the first embodiment. [Figure 10] Example of memory allocator configuration in multi-thread mode in embodiment 1 [Figure 11] Example of memory allocator configuration in single-thread mode in embodiment 1 [Figure 12] FIG. 1 is a schematic diagram for explaining memory usage in the first embodiment; [Figure 13] FIG. 13 is a diagram showing a histogram of the memory amount required in different processing modules and an example of classification of memory allocators in the second embodiment. [Figure 14] Example of memory allocator configuration applied to classified processing modules in embodiment 2 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] FIG. 2 is a graph showing the change in the rendering processing time mentioned above. In FIG. 2, the vertical axis indicates the processing time (milliseconds), and the horizontal axis indicates the pages of the print job. In the example shown in FIG. 2, it takes about 400 milliseconds to complete the processing of the first page, and about 550 milliseconds to complete the processing of the second page. In FIG. 2, the line graph changing with triangular dots indicates the number (relative value) of simple figures included in the job, and the line graph changing with circular dots indicates the number (relative value) of figures other than simple figures (for convenience, referred to as complex figures here). Simple figures are simple figures such as rectangles and triangles, and complex figures include polygons with pentagons or more. In both cases where simple figures are included and where complex figures are included, although there is a difference in the data processing time, it can be confirmed that there is generally a similar correlation with the number of graphic objects.

[0011] 3 is a diagram showing the configuration of a conventional image processing device. In a conventional image processing device, when printing is started, input data (PDL data) 310 is passed to an intermediate data generation module 311, which performs PDL interpretation and drawing processing (contour extraction) and the like. Then, the graphics data and the like of each page are converted into data in a format suitable for the image generation processing at the subsequent stage (hereinafter referred to as intermediate data). The intermediate data is sometimes called a display list or the like. The intermediate data is temporarily stored in an intermediate data spooler 312, and then transferred to an image generation module 313 at the subsequent stage.

[0012] The image generation module 313 loads pixel data into memory based on the information of the intermediate data. The pixel data loaded into memory is temporarily stored in a bitmap data buffer memory 314, and then transferred to a printer engine 316 via an engine interface (I / F) 315. The intermediate data generation module 311, image generation module 313, and engine I / F 315 are controlled by the control unit 300.

[0013] 4 is an overview diagram explaining a general memory usage pattern when the intermediate data generation module 211 operates. The PDL interpreter 411 uses the memory allocated in ALLOC-1, and the data receiving unit 412 uses the memory area allocated in ALLOC-2. The threads that extract the edges of figures use the memory areas allocated in ALLOC-3, 4, and 5, respectively, and the data synthesis process uses the memory area allocated in ALLOC-6. The process of generating image data after intermediate data is generated is configured to use ALLOC-7.

[0014] As mentioned above, processing can be made faster if the internal processing structure of the RIP is configured to enable parallel processing, but in the case of multi-core processors, the burden on memory increases as the number of available cores increases. Furthermore, even if the issue of shared memory is resolved, there is still the issue of increased working memory due to parallel processing executing separate processes at the same time. Generally, the amount of installed memory differs depending on the operating environment, but the maximum value is fixed in all cases, so there is the issue that printing becomes impossible when the work memory is used up. Actual measurements showed that there were jobs containing large amounts of images and graphics, and that even in a typical PC environment, there were cases where the installed memory was exceeded.

[0015] Even in cases where a large amount of memory is consumed, it may be possible to deal with the problem by performing a recovery process to reduce memory. In fact, even when memory is exhausted, there are cases where there is freed space inside (or there is space that can be freed, and the problem can be solved by freeing memory at that time). In addition, it is possible to increase some free space by investigating the fragmentation status at appropriate times. However, it is not easy to predict or investigate the fragmentation status with high accuracy while processing is proceeding. Even if it is possible to investigate, it is difficult to take effective measures because the fragmentation status changes with time. A similar approach would be to perform a process such as garbage collection on a large area, but in that case the processing speed will drop significantly, so it will not solve the problem either.

[0016] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0017] [Embodiment 1] FIG. 5 is a diagram illustrating an example of a hardware configuration of the image processing device.

[0018] The CPU 101 executes programs such as the OS and general applications loaded from the ROM 103 or the hard disk 111 to the RAM 102, and realizes the functions of the software and the processing of flowcharts which will be described later.

[0019] The RAM 102 functions as a main memory, a work area, etc. for the CPU 101. The input device controller 105 accepts input from an input device 110 such as a keyboard or a pointing device (not shown). The display controller 106 controls the display on the display 111. The storage controller 107 controls access to a storage 112 such as a hard disk (HD) or a flexible disk (FD) that stores a boot program, various applications, font data, user files, etc. The printer controller 108 controls the exchange of signals with a connected printer 113. The network controller 109 is connected to a network and executes communication control processing with other devices connected to the network.

[0020] In this embodiment, the functions of the image processing device described below are described as being realized by software, but each function may be implemented in the image processing device by dedicated hardware.

[0021] In this embodiment, the CPU 101 is a multi-core CPU, but the image processing apparatus may have a plurality of CPUs or processors.

[0022] Fig. 6 is a block diagram outlining the processing module that generates intermediate data in the first embodiment. The processing module is composed of a plurality of processing modules that perform various processes on input data (print job) to generate intermediate data. As shown in Fig. 6, the processing module group in this embodiment is broadly classified into four tasks, T1 to T4, and each is configured to operate independently over time. Furthermore, subtasks are further assigned to each of tasks T2 and T3.

[0023] Each task exists to perform parallel processing as shown in FIG. 1, and each task is composed of a plurality of processing modules (functions). In order for these processing modules to operate, memory must be reserved to generate an instance (an information area for storing operating conditions, setting information, etc.) for each function. Alternatively, memory must be reserved for the purpose of transferring processing data (image and object information). The memory reserved for these processing modules plays a different role depending on the purpose of use, so the required memory size varies. In addition, there are areas that share memory and areas that are exclusive to each processing module, and the shared areas further include areas that are shared on the premise of parallel processing and areas that do not assume parallel processing. In addition, it is important for the above-mentioned processing modules to use memory efficiently, but in order to give top priority to high-speed processing, memory fragmentation and the like are configured to operate while allowing it to a certain extent. In addition, in this embodiment, processing that takes time and reduces processing speed, such as garbage collection, is not performed. In addition, all memory reserved for the above-mentioned modules is assigned to a memory area (physical memory) that can be executed at high speed.

[0024] The operation of each task (T1 to T4) will be described in more detail below.

[0025] Task T1 is also known as the PDL task, and performs processing as a PDL interpreter, drawing IF, and data receiving section. As a PDL interpreter, it receives PDL data including print commands and performs analysis for each page from the start page to the end page. As a drawing IF, it generates drawing commands based on the analysis results in the PDL interpreter and outputs them to the data receiving section. As a data receiving section, it appropriately stores the received drawing commands in a queue (standby memory).

[0026] Task T2 is an edge processing module that appropriately retrieves drawing commands stored in the queue and starts internal subtask T2 to process them. If the retrieved drawing command is a command to draw a figure, subtask T2 executes a process to extract edge information (edge ​​data) of the figure and outputs it to the downstream task T3.

[0027] Task T3 is a synthesis processing module that receives edge data output from task T2, activates internal T3 subtasks, and sequentially performs synthesis processing according to the status of each edge data. Task T3 recursively executes synthesis processing on the received edge data, generates final intermediate data for each page in tile format, and stores it in the intermediate data spool.

[0028] Task T4 extracts the intermediate data from the intermediate data spool, performs image generation processing for each tile, and outputs image data (pixel data).

[0029] Next, the configuration of the memory allocator will be described with reference to FIG.

[0030] Case A shown in Figure 7(a) is a typical form in which a memory allocator is used by multiple modules. In contrast, case B is a form in which each module uses an independent memory allocator. However, in case B, the number of memory allocators increases, and wasteful free space occurs in the management area of ​​each memory allocator, which is not desirable from the viewpoint of memory utilization efficiency.

[0031] Therefore, in this embodiment 1, as shown in FIG. 7(b), memory usage characteristics (allocation patterns) are classified for each processing module, or for each task or subtask. In this embodiment, memory usage characteristics are characterized by the amount of memory required to be allocated at one time (number of bytes), the frequency of allocation for each required memory amount (number of allocations), and the lifetime (time from allocation to release). Memory usage characteristics are collected for multiple processing modules and cluster analysis is performed to classify the multiple processing modules into multiple classes. Then, based on the memory usage characteristics of the processing modules classified into the same class, design parameters of a memory allocator that increases memory utilization efficiency for each class are obtained. The memory allocator to which the design parameters obtained for each class are set is applied as a common memory allocator for processing modules classified into the same class. In order to set design parameters that increase memory utilization efficiency, for example, the smaller the required memory amount and the shorter the lifetime in one allocation, the smaller the block size of the memory allocator should be set. Conversely, the larger the required memory amount and the longer the lifetime, the larger the block size of the memory allocator should be set.

[0032] Basically, memory alignment should be set large, such as "32" or "64", but if there is a tendency for requested sizes to vary, it can be set small, such as "16", to improve utilization efficiency. Analysis and classification of memory usage characteristics of each processing module, and determination of design parameters of memory allocators corresponding to the classified classes can be performed experimentally when the processing modules are designed and implemented. Note that an analysis means may be provided within the image processing device, and the analysis and classification of memory usage characteristics of each processing module, and determination of design parameters of memory allocators corresponding to the classified classes may be performed as appropriate.

[0033] FIG. 8 is a schematic diagram illustrating an example of class classification.

[0034] In this embodiment, the RIP can operate in both a multi-thread mode (MT mode) in which multiple tasks are processed in parallel, and a single-thread mode (ST mode) in which each task is processed, and is configured to be changeable between the two operation modes. The inside of each processing module has a common module configuration for both the MT mode and the ST mode, and each processing module is configured to be uniformly classifiable.

[0035] The configuration shown in the table in Example 1 is a simple configuration example, and the class classification in MT mode and the class classification in ST mode are the same.

[0036] On the other hand, the configuration shown in the table of Example 2 is slightly different between the class classification in MT mode and the classification in ST Red. In MT mode, the processing modules classified into Class D and Class E are different, but in ST mode, the processing modules classified into Class D and Class E are the same, so the classification configuration is different between MT mode and ST mode.

[0037] The design parameters of the memory allocators applied to each processing module classified into each class are individually optimized. Type A has a locking function using MUTEX (or semaphore), whereas Type B does not have this function. In addition, the block size (BS) is set to one of 512KB, 256KB, or 128KB. The memory alignment (MA) is specified as 32 bits or 16 bits.

[0038] The above-mentioned classification work may be performed when the processing module is designed and implemented, or may be configured to be performed appropriately by providing classification means within the image processing device.

[0039] In this manner, this embodiment is configured so that memory allocators with different design parameters are assigned to a plurality of processing module groups classified into a plurality of predetermined classes.

[0040] FIG. 9 is a flow diagram illustrating the basic operation in this embodiment.

[0041] When a print job is submitted, processing begins, and the printer is configured to operate in MT mode the first time (first time). As shown in the flowchart in Fig. 9, in this embodiment, the printer basically operates in MT mode, but if an error occurs due to a lack of memory capacity, the printer also supports ST operation as a recovery process, and changes the configuration of the memory allocator.

[0042] Below is an overview of switching between MT mode and ST mode.

[0043] In S901, the number of threads is set to the same number as the number of available cores from the system information. For example, if four cores are available, the number of threads is set to "4".

[0044] In S902, the thread mode is set according to the set number of threads. If the number of threads is more than one, the thread mode is set to MT mode, and if the number of threads is one, the thread mode is set to ST mode.

[0045] In S903, if the thread mode is the MT mode, the process proceeds to S904, and if the thread mode is the ST mode, the process proceeds to S907.

[0046] In S904, a memory allocator for the MT mode applied to a processing module that performs PDL processing, image generation processing, and the like is configured.

[0047] In S905, a processing module to which a memory allocator for MT mode is applied is executed.

[0048] In S906, during execution of a processing module to which the memory allocator for MT mode is applied, it is determined whether or not an error has occurred due to insufficient memory, such as a heavy print job causing memory consumption to exceed a set threshold. If no error has occurred, all processing modules are executed and the series of processes is terminated, and if it is determined that an error has occurred, the number of threads is set to "1" and the process returns to S902.

[0049] When the process returns from S906 to S902, the thread mode is switched to the ST mode in S902, and the process proceeds to S907 via S903.

[0050] In S907, the existing memory allocator for the MT mode is discarded, and in S905, a memory allocator for the ST mode to be applied to the unprocessed processing module is configured.

[0051] In S908, the processing modules not yet processed in S905 in which the memory allocator for the ST mode was reapplied are executed, and then all the processing modules are executed to end the series of processing.

[0052] In this embodiment, the configuration is such that it is determined in S906 whether or not an error has occurred due to insufficient memory, but it may also be possible to determine whether or not the amount of free memory space is equal to or greater than a predetermined threshold, and change the thread mode before an error occurs.

[0053] FIG. 10 is a diagram explaining a memory allocator for multi-thread mode. In the allocator for MT mode, various local allocators are prepared from the base allocator via the throttle setting allocator. Here, the throttle setting allocator is a memory allocator in which a threshold value of the maximum secured memory amount is set. For example, when the threshold value of the maximum secured memory amount is set to 400 MB for the throttle setting allocator, the total amount of memory allocation can be limited for the memory allocators that go through the throttle setting allocator. In the first embodiment, the memory allocator is configured to be set independently for each application (task) used.

[0054] In addition, when operating in MT mode, data objects stored in a shared area in memory that can be accessed by multiple processing modules require exclusive control, such as locking the data objects using semaphores as appropriate. However, if the data objects stored in the shared area can be processed independently by processing bands, which are specified unit processing areas, the exclusive control for the data objects can be omitted by separating the memory allocator itself for each band. Reducing the number of data objects that are subject to exclusive control greatly contributes to improving processing speed.

[0055] Furthermore, in the image data generation process, the process is divided by tile, and the independence of each data tends to be further increased. Therefore, as shown in Figure 10, tasks T1 to T4 and memory allocators for the number of cores are prepared and the processes are executed in parallel.

[0056] FIG. 11 is a diagram explaining the memory allocator for single-thread mode. In MT mode, the memory allocator was designed to improve processing speed by parallel execution, but in ST mode, the memory allocator is designed to reduce memory consumption. Therefore, in ST mode, the common area is increased to suppress the overhead of the memory allocator as much as possible. In addition, the memory allocator for intermediate data generation processing, which consumes a lot of memory, is configured to be able to use journal mode. When journal mode is used, a predicted value of the most recent memory consumption is calculated from the data object input history. Then, at the same time as securing the reserved area, if it is determined that the calculated predicted memory amount falls below a predetermined threshold and memory will be depleted, measures to prevent memory depletion are taken, such as switching the processing mode at an early stage.

[0057] FIG. 12 is a schematic diagram explaining the memory usage pattern when the intermediate data generation module in the first embodiment operates. In the first embodiment, all memory allocators are configured on the base allocator. This area is basically configured to be allocated to a physical memory that can be executed at high speed. Task T1 is in charge of processing such as a PDL interpreter, and uses memory allocated to the throttle setting allocator 1. Task T2 is in charge of edge processing, and task T3 is in charge of edge synthesis processing. Each of them uses memory areas allocated to the local allocator 2 and the local allocator 3, but they are configured on the throttle setting allocator 2. Task T4, which generates image data after intermediate data is generated, is configured to use the throttle setting allocator 4, in which a threshold for the maximum reserved memory amount is not set.

[0058] By setting a common memory allocator for each task that exhibits similar behavior in this way, it is no longer necessary to set common management information in individual memory allocators, which reduces the management area. Also, by grouping tasks that require similar amounts of memory together, it is possible to reduce the memory area allocated as a buffer for classes with small fluctuations in the amount of memory required per class.

[0059] [Embodiment 2] Other embodiments than the above-described embodiment will be described below.

[0060] The second embodiment has the same configuration as the first embodiment described above, but differs in the method of analyzing the memory allocation pattern for each processing module (or task or subtask unit) described in Fig. 7. A brief description will be given below with reference to the drawings.

[0061] FIG. 13 is a diagram showing a histogram of the required memory amount in different processing modules and a classification example of memory allocators. In the histogram, the horizontal axis is the required memory size (required memory amount) and the vertical axis is the frequency of occurrence of each required memory amount. FIG. 13(a) is a histogram showing the frequency of occurrence of each required memory amount of processing module A (not shown). In this example, the required memory amount at the average frequency of occurrence of processing module A is 173 bytes. In this case, it can be seen that the required memory is small. On the other hand, FIG. 13(b) is a histogram showing the frequency of occurrence of module B (not shown) for each required memory amount. In this example, the required memory amount at the average frequency of occurrence of processing module B is 4.3 Kbytes, and it can be seen that the variance of the required memory amount is larger than that of module A. When classifying by taking into account the lifetime of each memory in addition to the results of FIG. 13(a) and (b), it can be classified into three classes as shown in the table in FIG. 13(c). In the case of module group A, which tends to have a small variance in the amount of memory required, it is sufficient to increase utilization efficiency by making the block size of the memory allocator closer to the memory size at the average occurrence frequency (class A). In the case of module group B, which tends to have a large variance in the amount of memory required, they are further classified into class B, which has a short memory lifetime, and class C, which has a long memory lifetime. The amount of memory required simultaneously when the lifetime is short is less than the amount of memory required simultaneously when the lifetime is long, so the block size of the memory allocator can be made smaller for class B than for class C. By classifying modules in this way and optimizing the block size of the memory allocator, memory utilization efficiency can be increased.

[0062] FIG. 14 shows an example of the configuration of a memory allocator applied to the processing modules classified into the classes shown in FIG. 13(c). For example, as shown in FIG. 14(a), memory allocators that operate like classes A, B, and C shown in FIG. 13 are assigned to processing modules A, B, and C. In FIG. 14(a), two types of base allocators (one is base allocator 1 that allocates from the heap area in 32KB units, and the other is base allocator 2 that allocates in 512KB units) are prepared from the heap area on the system side. From base allocator 1, local allocator A that allocates memory in 8KB units and local allocator B that allocates memory in 32KB units are prepared in a higher layer. The processing module group A uses local allocator A, and the processing module group B that corresponds to classification B in the table shown in FIG. 13(c) is configured to secure memory from local allocator B. On the other hand, for module group C, which is derived from processing module group B and corresponds to category C in the table shown in Fig. 13(c), memory is directly allocated from the base allocator 2. Since multiple classification patterns are possible, a configuration different from that shown in Fig. 14(a), for example, as shown in Fig. 14(b), may be used.

[0063] [Other Examples] As another embodiment, in the memory allocator set in the MT mode, a small area (called a working allocator) may be temporarily set in the memory allocator area used by tasks T2 and T3. This working allocator has a short lifetime and is effective for information that is released immediately. Alternatively, a dedicated shared allocator may be set to share data between tasks T2 and T3. Furthermore, the boundary between the shared and non-shared areas may be configured to be switched in units of data bands in the Y direction or bands in the Z direction (drawing order). Also, a memory allocator with a journal function may be used in the MT mode. In either case, memory usage efficiency can be improved by analyzing usage patterns according to the memory usage characteristics of each processing module and allocating the optimal memory allocator based on those usage patterns.

[0064] (Other Examples) The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0065] The present disclosure includes the following configurations and methods. [Configuration 1] An image processing device that processes input data using a plurality of processing modules to generate image data, A classification means for classifying the plurality of processing modules into a plurality of classes based on memory usage characteristics; an application means for applying to processing modules classified into the same class by the classification means a common memory allocator having design parameters set based on the usage characteristics of the memory corresponding to the class; An image processing device comprising: [Configuration 2] The memory usage characteristics include at least one of a required memory amount at one time allocation, an allocation frequency for each required memory amount, and a time from allocation to release. 2. The image processing device according to claim 1, [Configuration 3] The design parameters include a block size of the memory allocator, a memory alignment, and a parameter indicating the presence or absence of exclusive control. 3. The image processing device according to configuration 2. [Configuration 4] The application means determines the design parameters based on an average and a variance of the required memory amount for each class. 4. The image processing device according to configuration 3. [Configuration 5] the application means brings the block size of the memory allocator closer to an average of the required memory amounts for the classes as the variance of the required memory amounts for the classes becomes smaller; 5. The image processing device according to configuration 4. [Configuration 6] the application means reduces the block size of the memory allocator as the time from allocation to deallocation for each of the classes becomes shorter; 6. The image processing device according to any one of configurations 3 to 5. [Configuration 7] the application means reduces the block size of the memory allocator as the required memory amount for each of the classes decreases; 7. The image processing device according to any one of configurations 3 to 6, [Configuration 8] measuring means for measuring a usage characteristic of the memory for each of the plurality of processing modules; the classifying means classifies the plurality of processing modules based on the memory usage characteristics measured by the measuring means. 8. The image processing device according to any one of configurations 1 to 7. [Configuration 9] the application means, when an error occurs due to a memory shortage when applying a memory allocator for a multi-thread mode to the plurality of processing modules, reapplies a memory allocator for a single-thread mode to the plurality of processing modules; 9. The image processing device according to any one of configurations 1 to 8. [Configuration 10] the application means applies a memory allocator for a multi-thread mode to the plurality of processing modules when the free memory capacity is equal to or greater than a predetermined threshold, and applies a memory allocator for a single-thread mode to the plurality of processing modules when the free memory capacity is less than a predetermined threshold. 10. The image processing device according to any one of configurations 1 to 9. [Configuration 11] The plurality of processing modules include an edge processing module that extracts edge information from figures included in the input data, a synthesis processing module that synthesizes the edge information of each extracted figure, and an image generation module that generates intermediate data in a tile format from data obtained by the synthesis processing and generates image data from the intermediate data. 11. The image processing device according to any one of configurations 1 to 10. [Configuration 12] 1. An image processing method for generating image data by processing input data using a plurality of processing modules, comprising: classifying the plurality of processing modules into a plurality of classes based on memory usage characteristics; applying a common memory allocator having design parameters set based on the usage characteristics of the memory corresponding to the class to the processing modules classified into the same class by the classifying step; 13. An image processing method comprising: [Configuration 13] A program for causing a computer to function as the image processing device according to any one of configurations 1 to 11.

Claims

1. An image processing device that processes input data using a plurality of processing modules to generate image data, A classification means for classifying the plurality of processing modules into a plurality of classes based on memory usage characteristics; an application means for applying to processing modules classified into the same class by the classification means a common memory allocator having design parameters set based on the usage characteristics of the memory corresponding to the class; An image processing device comprising:

2. The memory usage characteristics include at least one of a required memory amount at one allocation, an allocation frequency for each required memory amount, and a time from allocation to release.

2. The image processing device according to claim 1,

3. The design parameters include a block size of the memory allocator, a memory alignment, and a parameter indicating the presence or absence of exclusive control.

3. The image processing device according to claim 2.

4. The application means determines the design parameters based on an average and a variance of the required memory amount for each class.

4. The image processing device according to claim 3.

5. the application means brings the block size of the memory allocator closer to an average of the required memory amounts for the classes as the variance of the required memory amounts for the classes becomes smaller; 5. The image processing device according to claim 4.

6. the application means reduces the block size of the memory allocator as the time from allocation to deallocation for each of the classes becomes shorter; 4. The image processing device according to claim 3.

7. the application means reduces the block size of the memory allocator as the required memory amount for each of the classes decreases; 4. The image processing device according to claim 3.

8. measuring means for measuring a usage characteristic of the memory for each of the plurality of processing modules; the classifying means classifies the plurality of processing modules based on the memory usage characteristics measured by the measuring means.

2. The image processing device according to claim 1,

9. the application means, when an error occurs due to a memory shortage when applying a memory allocator for a multi-thread mode to the plurality of processing modules, reapplies a memory allocator for a single-thread mode to the plurality of processing modules; 2. The image processing device according to claim 1,

10. the application means applies a memory allocator for a multi-thread mode to the plurality of processing modules when the free memory capacity is equal to or greater than a predetermined threshold, and applies a memory allocator for a single-thread mode to the plurality of processing modules when the free memory capacity is less than a predetermined threshold.

2. The image processing device according to claim 1,

11. The plurality of processing modules include an edge processing module that extracts edge information from figures included in the input data, a synthesis processing module that synthesizes the edge information of each extracted figure, and an image generation module that generates intermediate data in a tile format from data obtained by the synthesis processing and generates image data from the intermediate data.

11. The image processing device according to claim 1,

12. 1. An image processing method for generating image data by processing input data using a plurality of processing modules, comprising: classifying the plurality of processing modules into a plurality of classes based on memory usage characteristics; applying a common memory allocator having design parameters set based on the usage characteristics of the memory corresponding to the class to the processing modules classified into the same class by the classifying step; 13. An image processing method comprising:

13. A program for causing a computer to function as the image processing device according to any one of claims 1 to 10.

Images