Transmitting device and receiving device

Abstract

To transmit data via a transmission system in which a prescribed condition is set in a DE signal.SOLUTION: A transmitting device comprises detection means for outputting a trigger signal indicating a second clock timing based on a first clock timing at which second data transitions to active, and generation means for generating a DE signal based on the trigger signal. The detection means is configured to output the trigger signal in such a manner that the number of clock cycles between two consecutive second clock timings is an even number. The generation means is configured in such a manner that it transitions the DE signal from a second level to a first level at a third clock timing that comes after an even number of clock cycles from the second clock timing based on the trigger signal, and transitions the DE signal from the first level to the second level at a fourth clock timing that comes after an even number of clock cycles from the third clock timing.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to techniques for transmitting data over a transmission system. [Background technology]

[0002] Patent Document 1 discloses a configuration for transmitting data and a data enable signal (hereinafter also referred to as DE) indicating an enable period during which the data is valid in transmitting an image signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-140110 A Summary of the Invention [Problem to be solved by the invention]

[0004] The V-by-One standard for transferring image data has been proposed. The V-by-One standard specifies three transmission modes: single-in single-out (SiSo), dual-in dual-out (DiDo), and single-in dual-out (SiDo) / dual-in single-out (DiSo). SiSo is a mode in which one channel of parallel signals is transmitted as one lane of serial signals. DiDo is a mode in which two channels of parallel signals are transmitted as two lanes of serial signals. SiDо / DiSо are modes in which one channel of parallel signals are transmitted as two lanes of serial signals.

[0005] In the SiDo / DiSo transmission mode, there is a condition (restriction) that the period during which DE is at high level and the period during which DE is at low level must both be an even number of clock cycles. In addition, there is also a condition (restriction) that DE cannot remain at high level regardless of the transmission mode. When transmitting data through such a transmission system, it is necessary to process the data to be transmitted so as to satisfy the conditions of the transmission system.

[0006] The present invention provides a technique for transmitting data over a transmission system in which a predetermined condition is imposed on a data enable signal. [Means for solving the problem]

[0007] According to one aspect of the present invention, there is provided a transmitting device that transmits first data and second data indicating a period during which the first data is valid via a transmission system that transmits a data enable signal, a plurality of first signals, and a second signal, wherein the transmission system enables the plurality of first signals while the data enable signal is at a first level, enables the second signal while the data enable signal is at a second level, and satisfies a condition that both the period during which the data enable signal can be maintained at the first level and the period during which the data enable signal can be maintained at the second level are an even number of clock cycles. The transmitting device includes: a detection means for outputting a trigger signal indicating a second clock timing based on a first clock timing at which the second data has transitioned to active when the transmitting device detects that the second data has transitioned to active; a generation means for generating the data enable signal based on the trigger signal; a delay means for delaying the first data and the second data to output first delayed data and second delayed data; and an output means for outputting the first delayed data as one first signal of the plurality of first signals, and outputting the second delayed data as the second signal or another first signal different from the one first signal of the plurality of first signals. The detection means is configured to output the trigger signal so that the number of clock cycles between two consecutive second clock timings is an even number, and the generation means is configured to transition the data enable signal from the second level to the first level at a third clock timing that is an even number of clock cycles after the second clock timing based on the trigger signal, maintain the data enable signal at the first level until a fourth clock timing that is an even number of clock cycles after the third clock timing, and transition the data enable signal from the first level to the second level at the fourth clock timing. Effect of the Invention

[0008] According to the present invention, data can be transmitted through a transmission system in which a predetermined condition is set for a data enable signal. [Brief description of the drawings]

[0009] [Figure 1] 1 is a system block diagram for transmitting data over a transmission system according to some embodiments. [Diagram 2] An explanatory diagram of SiDo / DiSo transmission mode specifications. [Diagram 3] FIG. 2 is a block diagram of a signal generator according to some embodiments. [Figure 4] FIG. 4 is a block diagram of a signal restoration unit according to some embodiments. [Diagram 5] 4A and 4B illustrate signals at a transmitting device according to one embodiment. [Figure 6] 4A and 4B illustrate signals at a transmitting device according to one embodiment. [Figure 7] 4A and 4B illustrate signals at a transmitting device according to one embodiment. [Figure 8] 4A and 4B illustrate signals at a transmitting device according to one embodiment. [Figure 9] FIG. 2 is a block diagram of a signal generator according to some embodiments. [Figure 10] 4A and 4B illustrate signals at a transmitting device according to one embodiment. [Figure 11] FIG. 4 is a block diagram of a signal restoration unit according to some embodiments. [Figure 12] 4A and 4B illustrate signals at a transmitting device according to one embodiment. [Figure 13] 4A and 4B illustrate signals at a transmitting device according to one embodiment. [Figure 14] 4 illustrates signals at a receiving device according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0011] First Embodiment FIG. 1 is a system configuration diagram for transmitting data via a data transmission system according to the present embodiment. The transmitting unit 110 and the receiving unit 120 in FIG. 1 are integrated circuits (ICs) that perform data transmission according to the V-by-One standard. The transmitting unit 110, the receiving unit 120, and the communication lines connecting them constitute a transmission system that complies with the V-by-One standard. The transmitting device 100 transmits a clock signal (Tx_CLK), a data enable signal (Tx_DE), a synchronization signal (Tx_HSYNC: second signal), and data (Tx_DATA: first signal) to the transmitting unit 110. These signals transmitted by the transmitting device 100 to the transmitting unit 110 must comply with the V-by-One standard. Note that the data (Tx_DATA) is a parallel signal, which can be regarded as a plurality of Tx_DATA (a plurality of first signals). The transmitting unit 110 serially converts these signals from the transmitting device 100 according to the V-by-One standard and transmits them to the receiving unit 120. The receiving unit 120 converts the signal received from the transmitting unit 110 into parallel signals, and outputs a clock signal (Rx_CLK), a data enable signal (Rx_DE), a synchronization signal (Rx_HSYNC), and data (Rx_DATA) to the receiving device 130.

[0012] The transmitting device 100 includes a clock generating unit 103 that generates Tx_CLK. Tx_CLK is input not only to the transmitting unit 110 but also to the data output unit 101 and the signal generating unit 102. Each component of the transmitting device 100 operates according to an edge of Tx_CLK, for example, a rising edge. The data output unit 101 outputs first data (data_in) and second data (sync_in) accompanying the first data to the signal generating unit 102. The second data is, for example, control (or synchronization) data indicating a period during which the first data is valid. In the following description, data_in (first data) is image data, and sync_in (second data) is control data indicating a period during which data_in is valid. sync_in may be, for example, a horizontal synchronization signal that becomes active a predetermined number of clock cycles earlier than the timing when data_in becomes valid. Alternatively, sync_in may be a signal that becomes active in the same period as the period during which data_in is valid. The signal generating unit 102 generates Tx_DE, Tx_HSYNC, and Tx_DATA based on data_in and sync_in, and outputs them to the transmitting unit 110.

[0013] The receiving device 130 outputs Rx_CLK received from the receiving unit 120 to a signal restoration unit 131 and a data processing unit 132. Each component of the receiving device 130 operates according to an edge of Rx_CLK, for example, a rising edge. The signal restoration unit 131 restores sync_out and data_out based on Rx_DE, Rx_HSYNC, and Rx_DATA, and outputs the restored sync_out and data_out to the data processing unit 132. sync_out corresponds to sync_in, and data_out corresponds to data_in. The data processing unit 132 receives sync_out and data_out and performs predetermined processing.

[0014] 1, a transmission system conforming to the V-by-One standard is used to transmit the first data (data_in) and second data (sync_in) output by the data output unit 101 to the data processing unit 132. In order to transmit the first data (data_in) and second data (sync_in) output by the data output unit 101 in accordance with the V-by-One standard, the transmitting device 100 is provided with a signal generating unit 102, and the receiving device 130 is provided with a signal restoring unit 131.

[0015] FIG. 2 is an explanatory diagram of the SiDo / DiSo transmission mode specification. As shown in FIG. 2(A), the transmitting unit 110 transmits Tx_HSYNC as valid data while Tx_DE is at low level, and ignores Tx_DATA as invalid data. On the other hand, the transmitting unit 110 transmits Tx_DATA as valid data while Tx_DE is at high level, and ignores Tx_HSYNC as invalid data. Also, as shown in FIG. 2(B), the receiving unit 120 outputs Tx_HSYNC from the transmitting unit 110 to Rx_HSYNC as valid data while Rx_DE is at low level, and fixes Rx_DATA to low level. On the other hand, the receiving unit 120 outputs Tx_DATA from the transmitting unit 110 to Rx_DATA as valid data while Rx_DE is at high level, and continues to output to Rx_HSYNC the level in the last clock cycle when Rx_DE was at low level.

[0016] As described above, in the SiDo / DiSo transmission mode, it is necessary to generate Tx_DE so as to satisfy the following three conditions. Condition #1: Tx_DE is held high for an even number of clock cycles. Condition #2: Tx_DE is held low for an even number of clock cycles. Condition #3: Tx_DE is not fixed at a high level. The following describes in detail the configuration for satisfying conditions #1 to #3.

[0017] FIG. 3 is a configuration diagram of the signal generating unit 102 of the transmitting device 100 according to this embodiment. In the following description, "clock cycle" is simply written as "cycle". In response to detecting the detection target edge of sync_in, the detection unit 300 outputs a trigger signal tmp_de_trg to the generation unit 310. In this example, tmp_de_trg is a signal that is at a high level for only one cycle. Whether the detection target edge is the rising edge or the falling edge of sync_in can be set to be changeable by the detection unit 300. The detection unit 300 has a toggle counter that alternates between 0 and 1 every time it detects an edge of Tx_CLK, that is, every clock timing. When the toggle counter is one value, for example, 1, the detection unit 300 outputs tmp_de_trg one cycle after the clock timing (detection timing) at which the detection target edge of sync_in is detected. On the other hand, when the toggle counter is at the other value, for example, 0, the detection section 300 outputs tmp_de_trg at the detection timing of the detection target edge of sync_in.

[0018] A first delay setting value and a width setting value are set in the generating unit 310. The first delay setting value and the width setting value are also set in terms of the number of cycles. When the generating unit 310 detects a rising edge of tmp_de_trg, it sets pre_de to a high level the number of cycles set in the first delay setting value after the falling timing of tmp_de_trg. Then, when the generating unit 310 outputs a high level for the number of cycles set in the width setting value, it sets pre_de to a low level. Note that in this embodiment, a constraint is imposed that the number of cycles set in the first delay setting value and the width setting value must be a multiple of 2 (even number).

[0019] The delay unit 320 delays sync_in and data_in by the number of cycles set in the second delay setting value, and outputs them as pre_sync and pre_data to the selection unit 330. Pre_sync and pre_data are delayed versions of sync_in (second data) and data_in (first data), respectively, and are also referred to as second delayed data and first delayed data.

[0020] The selection unit 330 outputs pre_de from the generation unit 310 as Tx_DE. The output unit 331 of the selection unit 330 selects signals to be output as Tx_HSYNC and Tx_DATA in accordance with the first output setting. The output unit 331 is configured to be able to output pre_sync, pre_data, or a fixed high level or low level as Tx_HSYNC in accordance with the first output setting. The output unit 331 is also configured to be able to output pre_sync, pre_data, or a fixed high level or low level as Tx_DATA in accordance with the first output setting.

[0021] 4 is a configuration diagram of the signal restoration unit 131 of the receiving device 130 according to this embodiment. The output unit 431 outputs Rx_HSYNC to either sync_out or data_out in accordance with the second output setting, and outputs Rx_DATA to either sync_out or data_out in accordance with the second output setting.

[0022] Next, a specific example of data transmission will be described with reference to Figs. 5 and 6. In order to facilitate understanding of the number of cycles, the top of Figs. 5, 6, and other similar figures show cycle numbers based on CLK (Tx_CLK or Rx_CLK). Figs. 5 and 6 show an example in which image data data_in is transmitted in 14 consecutive cycles, and sync_in is a signal that is set to active during the period in which the image data (data_in) is valid. It is assumed that sync_in is high-level active. Since data_in becomes valid from the timing when sync_in transitions to high level, the detection unit 300 is set to detect the rising edge of sync_in as the edge to be detected. It is noted that Fig. 5 shows a case in which the toggle counter value is 1 when the edge to be detected of sync_in is detected, and Fig. 6 shows a case in which the toggle counter value is 0 when the edge to be detected of sync_in is detected.

[0023] As shown in Fig. 5, when the toggle counter is 1 at the detection timing of the detection target edge of sync_in, the detection unit 300 transitions tmp_de_trg from low level to high level one cycle after the detection timing. On the other hand, as shown in Fig. 6, when the toggle counter is 0 at the detection timing of the detection target edge of sync_in, the detection unit 300 transitions tmp_de_trg from low level to high level at the detection target timing.

[0024] In this example, the generation unit 310 sets the first delay setting value to 0 and the width setting value to 16. The reason for setting the first delay setting value to 0 and the width setting value to 16 will be described later. As shown in Figures 5 and 6, since the first delay setting value is 0, pre_de transitions to a high level at the falling edge of tmp_de_trg, and after maintaining the high level for 16 cycles in accordance with the width setting value, it goes to a low level.

[0025] In this example, the delay unit 320 is set with a second delay setting value of 2. The reason for setting the second delay setting value of the delay unit 320 to 2 will be described later. Since the second delay setting value is 2, pre_sync and pre_data become signals that are sync_in and data_in delayed by 2 cycles, as shown in Figs. 5 and 6.

[0026] As described above, the selection unit 330 outputs pre_de from the generation unit 310 as Tx_DE. That is, pre_de and Tx_DE are signals with the same waveform. In this example, the output unit 331 outputs both pre_sync and pre_data as Tx_DATA, which is a parallel signal, and the first output setting is performed to fix Tx_HSYNC to a high level. Therefore, as shown in Figs. 5 and 6, Tx_DATA#1 has the same signal waveform as pre_sync, and Tx_DATA#2 has the same signal waveform as pre_data.

[0027] The receiving unit 120 outputs Tx_DE in FIG. 5 and FIG. 6 as Rx_DE. The receiving unit 120 also outputs Tx_DATA#1 and Tx_DATA#2 as Rx_DATA#1 and Rx_DATA#2 while Rx_DE (=Tx_DE) is at high level. The receiving unit 120 also outputs Tx_HSYNC as Rx_HSYNC while Rx_DE is at low level. In this example, the output unit 431 of the signal restoration unit 131 is set to output Rx_DATA#1 to sync_оut and output Rx_DATA#2 to data_оut. As is clear from FIG. 5 and FIG. 6, Tx_DATA#1 (pre_sync) is at high level, and therefore Tx_DE (=Rx_DE) is at high level during the period when valid image data is output to Tx_DATA#2. Therefore, the receiving unit 120 outputs pre_sync and valid pre_data as Rx_DATA#1 and Rx_DATA#2. Therefore, the signal restoration unit 131 outputs pre_sync in Figures 5 and 6 as sync_out, and outputs pre_data as data_out. As is clear from Figures 5 and 6, sync_out is at a high level (active) during the period when data_out is valid.

[0028] Next, the reason why the above conditions #1 to #3 in the SiDo / DiSo transmission mode are satisfied by the configuration of this embodiment will be described. First, in this embodiment, Tx_DE is the same as pre_de, and pre_de is generated based on temp_de_trg. Specifically, the generation unit 310 sets pre_de to a high level from the timing after the number of cycles set in the first delay setting value from the falling edge of temp_de_trg to the timing after the number of cycles set in the width setting value. Here, in this embodiment, as described above, the width setting value set in the generation unit 310 is limited to an even number. Therefore, the above condition #1 (the number of cycles during which Tx_DE is maintained at a high level is an even number) is satisfied. In addition, the generation unit 310 sets pre_de to a low level after the number of cycles set in the width setting value has elapsed. Therefore, the condition #3 (Tx_DE is not fixed to a high level) is also satisfied.

[0029] Furthermore, the detection unit 300 adjusts the timing of outputting temp_de_trg based on the timing (first clock timing) at which the detection target edge of sync_in is detected and the value of the toggle counter. For example, the toggle counter is 1 when the cycle number of Tx_CLK is 2n (n is an integer equal to or greater than 0), that is, an even number, and the toggle counter is 0 when the cycle number is 2n+1, that is, an odd number. In this case, whether the detection target edge of sync_in is detected at the timing of cycle number 2n or cycle number 2n+1, the rising edge of temp_de_trg will be at the timing of cycle number 2n+1. Therefore, the timing of the falling edge of temp_de_trg (second clock timing) will be the timing of cycle number 2n+2, that is, the timing of cycle number even.

[0030] The generating unit 310 transitions pre_de from a low level to a high level at a timing (third clock timing) that is the first delay setting value after the falling edge of temp_de_trg. Here, in this embodiment, as described above, the first delay setting value set in the generating unit 310 is limited to an even number. Therefore, pre_de transitions from a low level to a high level only when the cycle number is an even number. Also, considering that the above-mentioned condition #1 is satisfied, the timing (fourth clock timing) at which pre_de transitions from a high level to a low level also occurs only when the cycle number is an even number. That is, pre_de transitions to a low level when the cycle number is an even number, and transitions to a high level when the cycle number is an even number. Therefore, the low level period of pre_de (=Tx_DE) also becomes an even multiple of the number of cycles, and condition #2 is also satisfied. In the above explanation, it was stated that the toggle counter is 1 when the cycle number is even and 0 when the cycle number is odd, but it is the same even if the toggle counter is 0 when the cycle number is even and 1 when the cycle number is odd.

[0031] For example, in the examples of FIG. 5 and FIG. 6, the detection target edge of sync_in occurs every odd number of cycles, such as every 27 cycles. In this case, the sequences of FIG. 5 and FIG. 6 are repeated alternately every time the detection target edge of sync_in is detected. However, as described above, the configuration of this embodiment satisfies the above conditions #1 to #3, and sync_in and data_in can be transmitted. On the other hand, if the output timing of temp_de_trg is not adjusted in the detection unit 300, at least condition #2 is violated if the interval between detection target edges of sync_in is an odd interval. In this case, sync_in and data_in cannot be transmitted. In this way, in this embodiment, conditions #1 to #3 are satisfied by adjusting the output timing of temp_de_trg and restricting the first delay setting value and width setting value (number of cycles) set in the generation unit 310 to be even numbers.

[0032] Next, the reason for setting the first delay setting value of the generating unit 310 to 0, the width setting value to 16, and the second delay setting value of the delay unit 320 to 2 will be described. In this embodiment, what needs to be transmitted from the data output unit 101 to the data processing unit 132 is information indicating that sync_in is active and valid data of data_in. In the examples of Figs. 5 and 6, the period during which sync_in is active (high level) and the period during which the valid data of data_in are the same. Therefore, in the examples of Figs. 5 and 6, these two are both transmitted by Tx_DATA. Tx_DATA is valid during the period during which Tx_DE is high level (Fig. 2). Note that even if the first delay setting value is set to 0, the rising timing of Tx_DE is delayed by a maximum of two cycles (Fig. 6) from the timing when sync_in becomes active. Therefore, sync_in and data_in must be delayed so that the active period of pre_sync is included in the high level period of Tx_DE.

[0033] Here, since the period during which pre_sync is active is 14 cycles, the width setting value of the generation unit 310 must be 14 or more. In order to satisfy conditions #1 to #3, the timing at which Tx_DE can be set to high level is limited to once every two cycles. Therefore, in the case of FIG. 5, the width setting value can be set to 14, but if the width setting value is set to 14 in the case of FIG. 6, Tx_DE will be at low level while pre_sync is active. Since the width setting value of the generation unit 310 is restricted to an even number, in this example, the width setting value of the generation unit 310 is set to 16, which is 14 plus 2, so that Tx_DE is at high level while pre_sync is active even in the case of FIG. 6. Also, in both the case of FIG. 5 and the case of FIG. 6, the second delay setting value of the delay unit 320 is set to 2 so that pre_sync is active while Tx_DE is at high level. The first delay setting value of the generating unit 310 delays the timing of transitioning Tx_DE to a high level, but in this example, since there is no reason to delay it, it is set to the minimum value of 0. The first delay setting value can also be set to a value of 1 or more, and in that case, the second delay setting value of the delay unit 320 is also changed according to the first delay setting value of the generating unit 310.

[0034] Next, another specific example of data transmission will be described with reference to Figs. 7 and 8. Figs. 7 and 8 show a case where sync_in is used as a main scanning synchronization signal, and valid image data (data_in) is transmitted from the sixth cycle based on the timing when sync_in transitions to a low level. The image data period is eight cycles, and sync_in is active (low level) for a predetermined number of cycles, in this example, four cycles. Since sync_in is low level active, the detection unit 300 is set to detect the falling edge of sync_in as the edge to be detected. Fig. 7 shows a case where the toggle counter value is 1 at the detection timing of the edge to be detected of sync_in, and Fig. 8 shows a case where the toggle counter value is 0 at the detection timing. Therefore, tmp_de_trg in Fig. 7 is the same as that in Fig. 5, and tmp_de_trg in Fig. 8 is the same as that in Fig. 6.

[0035] In this example, unlike the examples of Figs. 5 and 6, the period during which sync_in is active is different from the period during which valid data is output to data_in. For this reason, sync_in is transmitted using Tx_HSYNC transmitted during the period during which Tx_DE is at a low level. Data_in is transmitted using Tx_DATA transmitted during the period during which Tx_DE is at a high level. In order to make Tx_DE low during the period of pre_sync based on sync_in, the generation unit 310 is set to 6, which is obtained by adding 2 to 4 during the period during which sync_in is active, as the first delay setting value. The reason for adding 2 is the same as the reason for adding 2 to 14 during the active period as the width setting value of the generation unit 310 in Figs. 5 and 6. In addition, in order to make Tx_DE high during the period of pre_data based on data_in, the generation unit 310 is set to 10, which is obtained by adding 2 to 8 during the period during which pre_data is valid, as the width setting value. The reason for adding 2 is the same as the reason for adding 2 to the active period of 14 in the width setting value of the generation unit 310 in Figures 5 and 6. Therefore, as shown in Figures 7 and 8, pre_de rises six cycles after the falling timing of tem_trg, and remains at high level for 10 cycles.

[0036] In this example as well, a second delay setting value of 2 is set in the delay section 320. Therefore, as shown in Figures 7 and 8, pre_sync and pre_data become signals that are sync_in and data_in delayed by two cycles.

[0037] The selection unit 330 outputs pre_de from the generation unit 310 as Tx_DE. In this example, the output unit 331 is set to a first output setting of outputting pre_sync to Tx_HSYNC and outputting pre_data as Tx_DATA. Therefore, as shown in Figures 5 and 6, Tx_HSYNC has the same waveform as pre_sync, and Tx_DATA has the same waveform as pre_data.

[0038] The receiving unit 120 outputs Tx_DE in FIG. 7 and FIG. 8 as Rx_DE. Also, the receiving unit 120 outputs Tx_DATA as Rx_DATA while Rx_DE (=Tx_DE) is at high level, and outputs Tx_HSYNC as Rx_HSYNC while Rx_DE is at low level. In this example, the output unit 431 of the signal restoration unit 131 is set to output Rx_HSYN to sync_оut and output Rx_DATA to data_оut. As is clear from FIG. 7 and FIG. 8, Rx_HSYNC outputs a signal indicating the period during which pre_sync is low, and Rx_DATA outputs valid data. Therefore, the signal restoration unit 131 outputs pre_sync in FIG. 7 and FIG. 8 as sync_оut, and outputs pre_data as data_оut. As is clear from FIGS. 7 and 8, valid image data is output for eight cycles starting six cycles after sync_out becomes active.

[0039] As described above, according to this embodiment, data can be transmitted using a transmission system conforming to the V-by-One standard. Note that the setting values ​​used in the examples of Fig. 5 to Fig. 8 are merely examples and do not limit this embodiment, and other values ​​can be used.

[0040] Second Embodiment Next, the second embodiment will be described with a focus on differences from the first embodiment. In the first embodiment, the delay unit 320 delayed sync_in and data_in based on the second delay setting value and output them as pre_sync and pre_data. In this embodiment, the delay unit 320 adjusts the delay given to sync_in and data_in according to the timing at which the detection unit 300 outputs temp_de_trg. FIG. 9 is a configuration diagram of the signal generation unit 102 according to this embodiment. In this embodiment, when the detection unit 300 detects the detection target edge of sync_in, it notifies the delay unit 320 of the value of the toggle counter at that time. Then, when the value of the toggle counter is 1, the delay unit 320 delays sync_in and data_in by two cycles and outputs them as pre_sync and pre_data. On the other hand, when the value of the toggle counter is 0, the delay unit 320 delays sync_in and data_in by one cycle and outputs them as pre_sync and pre_data.

[0041] FIG. 10 shows a specific example of the configuration of this embodiment applied to transmit the same sync_in and data_in as those in FIG. 7 and FIG. 8. FIG. 10 shows a case where the toggle counter value is 0 when the detection unit 300 detects the detection target edge of sync_in. If the toggle counter value is 1 when the detection target edge of sync_in is detected, the delay unit 320 delays sync_in and data_in by two cycles, so that the signal sequence is the same as that in FIG. 7. In FIG. 10, sync_in and data_in are delayed by one cycle, so that the relationship between Tx_DE, Tx_DATA, and Tx_HSYNC is the same as that in FIG. 7. In FIG. 10, the width setting value of the generation unit 310 is 10 as in the explanation in FIG. 7 and FIG. 8, but in this example, it can be 8, which is the same as the period during which image data is valid.

[0042] 9, the detection unit 300 notifies the delay unit 320 of the toggle counter value when the detection target edge of sync_in is detected. However, since sync_in is also input to the delay unit 320, a toggle counter that is synchronized with the toggle counter of the detection unit 300 may be provided in the delay unit 320, and the delay unit 320 may determine the amount of delay based on the value of the toggle counter.

[0043] As described above, in this embodiment, the delay equal to the delay from the detection timing of the detection target edge (first clock timing) to the falling timing of tem_trg (second clock timing) is provided by the delay unit 320. Therefore, the relationship between Tx_DE and pre_syn and pre_data is the same regardless of the detection timing of the detection target edge.

[0044] <Third embodiment> Next, the third embodiment will be described, focusing on the differences from the first and second embodiments. In this embodiment, the configuration of the signal restoration unit 131 of the receiving device 130 is different from the first and second embodiments.

[0045] 11 is a configuration diagram of the signal restoration unit 131 according to the present embodiment. The output unit 931 outputs Rx_HSYNC to either pre_sync_out or pre_data_out in accordance with the third output setting, and outputs Rx_DATA to either pre_sync_out or pre_data_out in accordance with the third output setting.

[0046] The output unit 932 selects the signals to be output as sync_out and data_out while Rx_DE is at high level from among pre_sync_out, pre_data_out, fixed at high level, and fixed at low level in accordance with the H output setting. Also, the output unit 932 selects the signals to be output as sync_out and data_out while Rx_DE is at low level from among pre_sync_out, pre_data_out, fixed at high level, and fixed at low level in accordance with the L output setting.

[0047] Next, a specific example of data transmission in this embodiment will be described with reference to Figs. 12 to 14. Note that sync_in and data_in are the same as those used in the description of Figs. 7 and 8. The configuration of the signal generating unit 102 is the same as that described in the second embodiment. Fig. 12 shows a case where the toggle counter value is 1 when the detecting unit 300 detects the detection target edge of sync_in. Fig. 13 shows a case where the toggle counter value is 0 when the detecting unit 300 detects the detection target edge of sync_in.

[0048] In the examples of Fig. 12 and Fig. 13, unlike the examples described in the above embodiment, sync_in is transmitted by Tx_DATA, not Tx_HSYNC. For this reason, Tx_DE needs to be at high level during the period including pre_sync based on sync_in and pre_data based on data_in. Therefore, the first delay setting value set in the generating unit 310 is set to 0 in order to suppress the delay. On the other hand, the width setting value is set to 16, which is the number of cycles from the timing when sync_in becomes active to the timing of the last valid data of data_in plus 14, which is 2. Therefore, in Fig. 12 and Fig. 13, pre_de (=Tx_DE) is at high level for 16 cycles from the falling edge timing of tmp_de_trg.

[0049] 12 shows a case where the toggle counter value at the detection timing of the detection target edge of sync_in is 1, so pre_sync and pre_data are signals obtained by delaying sync_in and data_in by 2 cycles. On the other hand, in FIG 13, the toggle counter value at the detection timing is 0, so pre_sync and pre_data are signals obtained by delaying sync_in and data_in by 1 cycle.

[0050] The selection unit 330 outputs pre_de from the generation unit 310 as Tx_DE. In this example, the output unit 331 outputs both pre_sync and pre_data as Tx_DATA, which is a parallel signal, and the first output setting is performed to fix Tx_HSYNC to a high level. Therefore, as shown in Figures 12 and 13, Tx_DATA#1 has the same waveform as pre_sync, and Tx_DATA#2 has the same waveform as pre_data.

[0051] Fig. 14 shows a specific example of the processing in the signal restoration unit 131 in this example. As is clear from Fig. 12 and Fig. 13, the relationship between Tx_DE, Tx_DATA#1, Tx_DATA#2, and Tx_HSYNC is the same in Fig. 12 and Fig. 13, so the processing on the receiving side will be described together without distinguishing between the case of Fig. 12 and the case of Fig. 13.

[0052] The receiving unit 120 outputs Tx_DATA#1 and Tx_DATA#2 to Rx_DATA#1 and Rx_DATA#2 while outputting a high level as Rx_DE (=Tx_DE). The receiving unit 120 sets Rx_DATA#1 and Rx_DATA#2 to a low level while outputting a low level as Rx_DE (=Tx_DE). In this example, the output unit 931 of the signal restoration unit 131 is set to output Rx_DATA#1 as pre_sync_оut and output Rx_DATA#2 as pre_data_оut. Therefore, as shown in FIG. 14, during the period when Rx_DE is at a high level, the relationship between pre_sync_оut and pre_data_оut is the same as the relationship between Tx_DATA#1 and Tx_DATA#2 in FIG. 12 and FIG. 13. 2, while Rx_DE is at a low level, pre_sync_out and pre_data_out are at a low level. Therefore, in pre_sync_out, the falling edge from a high level to a low level, which indicates the timing of becoming active, disappears.

[0053] For this reason, in this example, when Rx_DE is at a low level, the output unit 931 is set to an L output setting such that a high level is output to sync_оut and a low level is output to data_оut. Note that when Rx_DE is at a high level, the output unit 931 is set to an H output setting such that pre_sync_оut is output to sync_оut and pre_data_оut is output to data_оut. Therefore, the output unit 931 outputs sync_оut and data_оut as shown in Fig. 14. As shown in Fig. 14, the timing when sync_оut becomes active is shown as a fall from a high level to a low level.

[0054] Above, each embodiment of transmitting data via a transmission system conforming to the V-by-One standard has been described. However, the transmission system to which each of the above embodiments is applied is not limited to one conforming to the V-by-One standard. For example, each of the above embodiments can also be applied to a transmission system conforming to the V-by-One HS standard. More specifically, each of the above embodiments can be applied to a transmission system in which a data enable signal (DE), a plurality of first signals (DATA), and a second signal (HSYNC) are specified, signals are transmitted as shown in FIG. 2, and the above conditions #1 to #3 must be satisfied.

[0055] In addition, the transmitting unit 110 and the transmitting device 100 are separate devices (or ICs), but the transmitting unit 110 can be a functional block in the transmitting device 100, that is, the transmitting unit 110 and the transmitting device 100 can be one device (or IC). Similarly, the receiving unit 120 and the receiving device 130 can be one device (or IC). Furthermore, the transmitting device 100 includes the data output unit 101, but the data output unit 101 may be an external device of the transmitting device 100. In this case, the clock generating unit 103 of the transmitting device 100 outputs Tx_CLK to the data output unit 101, which is an external device. Similarly, the receiving device 130 includes the data processing unit 132, but the data processing unit 132 may be an external device of the receiving device 130. In this case, the receiving device 130 outputs Rx_CLK to the data processing unit 132, which is an external device.

[0056] [Other embodiments] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0057] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0058] 300: detection unit, 310: generation unit, 320: delay unit, 331: output unit

Claims

1. A transmitting device that transmits first data and second data that indicates a period during which the first data is valid or a timing at which the first data becomes valid by becoming active, via a transmission system that transmits a data enable signal, a plurality of first signals, and a second signal, The transmission system comprises: while the data enable signal is at a first level, the first signals are enabled, and while the data enable signal is at a second level, the second signals are enabled; a period during which the data enable signal can be maintained at the first level and a period during which the data enable signal can be maintained at the second level each have a period of an even number of clock cycles; The transmitting device: a detection means for detecting, when the second data has transitioned to active, outputting a trigger signal indicating a second clock timing based on a first clock timing at which the second data has transitioned to active; a generating means for generating the data enable signal based on the trigger signal; a delay means for delaying the first data and the second data and outputting first delayed data and second delayed data; an output means for outputting the first delayed data as one first signal of the plurality of first signals, and outputting the second delayed data as the second signal or another first signal different from the one first signal of the plurality of first signals; Equipped with the detection means is configured to output the trigger signal so that the number of clock cycles between two successive second clock timings is an even number; the generating means is configured to transition the data enable signal from the second level to the first level at a third clock timing that is an even number of first clock cycles after the second clock timing based on the trigger signal, maintain the data enable signal at the first level until a fourth clock timing that is an even number of second clock cycles after the third clock timing, and transition the data enable signal from the first level to the second level at the fourth clock timing.

2. 2. The transmitting device according to claim 1, wherein the detection means has a counter that alternates between a first value and a second value at each clock timing, and outputs the trigger signal so that the number of clock cycles between two consecutive second clock timings is an even number by making the third number of clock cycles from the first clock timing to the second clock timing when the counter has the first value at the first clock timing one less than the third number of clock cycles when the counter has the second value at the first clock timing.

3. 3. The transmitting device according to claim 2, wherein the delay means outputs the first delayed data and the second delayed data by delaying the first data and the second data by a set number of clock cycles.

4. 3. The transmitting device according to claim 2, wherein the delay means outputs the first delayed data and the second delayed data by delaying the first data and the second data by a number of clock cycles from the first clock timing to the second clock timing.

5. 2. The transmitting device according to claim 1, wherein a delay setting value indicating the first number of clock cycles and a width setting value indicating the second number of clock cycles are set in said generating means.

6. the second data is a signal that is set to be active while the first data is valid; a period from the third clock timing to the fourth clock timing includes a period during which the second delayed data is set to active; 2. The transmitting device of claim 1, wherein said output means outputs said second delayed data as said another one of said plurality of first signals.

7. the second data is a signal that is set to be active for a predetermined number of clock cycles before a clock timing at which the first data is valid; a period from the second clock timing to the third clock timing includes a period during which the second delayed data is set to active, and a period from the third clock timing to the fourth clock timing includes a period during which the first delayed data is valid, The transmitting device according to claim 1 , wherein the output means outputs the second delayed data as the second signal.

8. the second data is a signal that is set to be active for a predetermined number of clock cycles before a clock timing at which the first data is valid; a period from the third clock timing to the fourth clock timing includes a period during which the second delayed data is set to active and a period during which the first delayed data is valid; 2. The transmitting device of claim 1, wherein said output means outputs said second delayed data as said another one of said plurality of first signals.

9. The transmitting device according to claim 1 , wherein the transmission system transmits the data enable signal, the first signals, and the second signal according to a V-by-One standard or a V-by-One HS standard.

10. A receiving device that receives the first data and the second data transmitted by the transmitting device according to any one of claims 1 to 7 via the transmission system, A receiving device comprising: an output means for outputting one of the plurality of first signals output by the transmission system as the first data, and for outputting one of the other of the plurality of first signals output by the transmission system and the second signal as the second data.

11. A receiving device that receives the first data and the second data transmitted by the transmitting device according to claim 8 via the transmission system, a first output means for outputting one of the first signals outputted from the transmission system as third data, and outputting another of the first signals outputted from the transmission system as fourth data; a receiving device that outputs the third data as the first data and outputs the fourth data as the second data during a period when the data enable signal output by the transmission system is at the first level, and outputs the first level or the second level as the second data during a period when the data enable signal output by the transmission system is at the second level.

Images