Back contact cell and solar cell module

Abstract

To provide a back contact cell and a solar cell module, capable of enhancing the efficiency and a reliability of the cell as well as increasing the open circuit voltage of the cell.SOLUTION: A back contact cell includes: a semiconductor substrate which has a front surface and a back surface opposite to each other, and in which the back surface includes a plurality of adjacent and alternately arranged segment units, segment spaces are formed between the respective segment units and a backlight surface, the segment spaces each further include a first space, a second space, a third space and a fourth space; a first passivation layer, located only in each first space; a first doped semiconductor layer, located only in each first space, and being adjacent to a side of the first passivation layer away from the semiconductor substrate; a second passivation layer, located only in each second space to each fourth space; and a second doped semiconductor layer located only in each second space to each fourth space and being adjacent to a side of the second passivation layer away from the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This application relates primarily to the field of photovoltaics, and in particular to back-contact cells and solar modules. [Background technology]

[0002] With the maturity and continuous excavation of PERC (Passivated emitter and rear contact) battery technology, its conversion efficiency is gradually approaching the theoretical limit, and the industry has begun to seek next-generation technologies. The mainstream technologies currently being promoted are TOPCon, HJT, IBC, etc.

[0003] Unlike conventional double-sided electrode contact batteries, the biggest feature of back-contact batteries is that the metal electrode is located on the back of the battery, and there is no shielding of the metal electrode on the front, improving the light utilization rate, and therefore the short-circuit current and conversion efficiency are higher. However, the passivation performance and open circuit voltage of back-contact batteries are generally poor, and the photoelectric conversion efficiency is not high. Therefore, how to further improve the cell performance of back-contact batteries is a technical problem that needs to be solved in this field as soon as possible. Summary of the Invention [Problem to be solved by the invention]

[0004] The technical problem to be solved by the present application is to provide a back-contact cell and solar cell module capable of increasing the open-circuit voltage of the cell and improving the efficiency and reliability of the cell. [Means for solving the problem]

[0005] In order to solve the above technical problems, the present application provides a liquid crystal display device having a front and a back surface facing each other, the front surface being close to a light receiving surface of a back contact cell, the back surface being close to a backlight surface of the back contact cell, the back surface being provided with a plurality of segment units arranged adjacent to each other in order, each segment unit being provided with a first segment, a second segment, a third segment, and a fourth segment arranged adjacent to each other in order, a first space, a second space, a third space, and a fourth space being formed between the first segment to the fourth segment and the back surface, respectively, and the first space to the fourth space are segment spaces between each of the segment units and the backlight surface. the first doped semiconductor layer is located only in the first space in each of the segment spaces and adjacent to the side of the first passivation layer away from the semiconductor substrate; the second passivation layer is located only in the second space, the third space, and the fourth space in each of the segment spaces; and the second doped semiconductor layer is located only in the second space, the third space, and the fourth space in each of the segment spaces and adjacent to the side of the second passivation layer away from the semiconductor substrate, the first doped semiconductor layer being located only in the first space in each of the segment spaces.

[0006] In one embodiment of the present application, the semiconductor substrate further comprises a substrate doping layer having the same conductivity type as the semiconductor substrate at a position adjacent to each of the first segments.

[0007] In one embodiment of the present application, the semiconductor device further includes an insulating layer located in the first space, the second space, and the fourth space in each of the segment spaces, located in the first space on a side of the first doped semiconductor layer away from the semiconductor substrate, and adjacent to the back surface of the semiconductor substrate in the second space and the fourth space.

[0008] In one embodiment of the present application, the semiconductor device further comprises a doped oxide layer located in the first space of each of the segment spaces and adjacent to and between the insulating layer and a side of the first doped semiconductor layer away from the semiconductor substrate.

[0009] In one embodiment of the present application, the semiconductor device further includes conductive layers located in the first space, the second space, the third space, and the fourth space in each of the segment spaces, and in the first space, at least a portion of the conductive layers is adjacent to the side of the insulating layer away from the semiconductor substrate, and at least another portion of the conductive layers is adjacent to the side of the first doped semiconductor layer away from the semiconductor substrate, and in the second space to the fourth space, at least a portion of the conductive layers is adjacent to the side of the second doped semiconductor layer away from the semiconductor substrate.

[0010] In one embodiment of the present application, the semiconductor device further includes a first electrode and a second electrode respectively positioned in the first space and the third space in each of the segment spaces, the first electrode being positioned on a side of the conductive layer away from the semiconductor substrate in the first space, and the second electrode being positioned on a side of the conductive layer away from the semiconductor substrate in the third space.

[0011] In one embodiment of the present application, the conductive layer forms a contact groove recessed into the semiconductor substrate within the first space in each of the segment spaces, and the first electrode contacts the conductive layer within the contact groove, and the contact groove contacts the conductive layer on a surface closer to the semiconductor substrate or extends into the first doped semiconductor layer.

[0012] In one embodiment of the present application, the first segment, the second segment, the third segment, and the fourth segment have a first distance L1, a second distance L2, a third distance L3, and a fourth distance L4 from the first segment, the second segment, the third segment, and the fourth segment to the front surface of the semiconductor substrate, respectively, where L3 is less than or equal to L2, L3 is less than or equal to L4, L2 is less than or equal to L1, and L4 is less than or equal to L1.

[0013] In one embodiment of the present application, the battery structures in the second space and the fourth space corresponding to the second segment and the fourth segment are the same, and L2 is equal to L4. In one embodiment of the present application, the semiconductor substrate further comprises a front passivation layer located between the front surface and a light receiving surface of the semiconductor substrate and adjacent to the front surface, the front passivation layer comprising intrinsic amorphous silicon, alumina, silicon nitride, silicon oxynitride and / or silicon oxide.

[0014] In one embodiment of the present application, the semiconductor device further comprises a front anti-reverse layer adjacent to the side of the front passivation layer facing away from the semiconductor substrate, the front anti-reverse layer comprising silicon nitride, silicon oxynitride, silicon oxide and / or a transparent conductive layer.

[0015] In one embodiment of the present application, the front surface of the semiconductor substrate is a pile structure, and the pile structure comprises pyramidal piles and / or erosion pit piles.

[0016] In one embodiment of the present application, the back surface of the semiconductor substrate has the pile structure and / or the polishing surface structure, the third segment is a pile structure or a polishing surface structure, and the first segment, the second segment and the fourth segment are polishing surface structures.

[0017] In one embodiment of the present application, the first passivation layer comprises a tunneling oxide layer, the first doped semiconductor layer comprises doped polysilicon, and the first doped semiconductor layer has a doping type similar to that of the semiconductor substrate.

[0018] In one embodiment of the present application, the semiconductor device further comprises at least one separation groove located in each of the segment spaces, the separation groove being located only in the first space or being located in both the second space and the fourth space.

[0019] In one embodiment of the present application, the semiconductor device further includes two isolation trenches located in the second space and the fourth space in each segment space, and the two isolation trenches penetrate up to the inside of the insulating layer in a direction gradually approaching the semiconductor substrate.

[0020] In one embodiment of the present application, the semiconductor device further includes two isolation grooves located within the first space in each of the segment spaces, the two isolation grooves being located on either side of the contact groove, and the two isolation grooves penetrating up to the inside of the insulating layer in a direction gradually approaching the semiconductor substrate.

[0021] In another aspect, the present application further provides a solar cell module comprising a plurality of series and / or parallel connected back-contact cells as proposed by any of the embodiments of the present application. Compared with the prior art, the present application has the following advantages: The proposed back contact battery designs an alternating segment unit structure on the back of the battery, arranges different battery feature layers in different segments and spatial positions within each segment unit, and further designs different contact grooves and different separation groove positions, which can effectively improve the open circuit voltage of the battery and ensure the battery has higher conversion efficiency and reliability.

[0022] The accompanying drawings are included to provide a further understanding of the present application, constitute a part of the present application, illustrate examples of the present application, and together with the description, serve to explain the principles of the present application. [Brief description of the drawings]

[0023] [Figure 1] 1 is a schematic diagram of a back-contact battery according to an embodiment of the present application; [Diagram 2] FIG. 2 is a schematic diagram of a back contact battery according to another embodiment of the present application; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] In order to more clearly describe the technology of the embodiments of the present application, the drawings necessary for the description of the embodiments are briefly described below. Obviously, the drawings in the following description are only some examples or embodiments of the present application, and those of ordinary skill in the art can also apply the present application to other similar scenarios based on these drawings without paying inventive efforts. Unless it is clear from the language or otherwise described, the same symbols in the drawings represent the same structures or operations.

[0025] As used herein and in the claims, unless the context clearly indicates otherwise, terms such as "a," "one," "a kind," and / or "the" do not specifically refer to the singular but may include the plural. In general, the terms "comprising" and "including" are used only to indicate the inclusion of specifically identified steps and elements, and do not constitute an exclusive list of these steps and elements, and a method or apparatus may include other steps or elements.

[0026] Unless otherwise specified, the relative arrangement of components and steps, numerical expressions and values ​​described in these embodiments are not intended to limit the scope of the present application. Meanwhile, it should be understood that the dimensions of each part shown in the drawings are not drawn in actual proportion to facilitate the description. Although detailed discussion may not be provided for techniques, methods and devices known to those of ordinary skill in the relevant field, such techniques, methods and devices shall be considered as part of the patented specification, where appropriate. In all examples shown and discussed herein, any specific values ​​should be construed as merely illustrative, not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that in the following drawings, similar symbols and letters indicate similar items. Thus, once an item is defined in one drawing, there is no need to further discuss it in subsequent drawings.

[0027] In the present specification, it should be understood that the orientations or positions indicated by directional terms such as "front, back, up, down, left, right", "lateral, longitudinal, vertical, horizontal" and "top, bottom" are generally based on the orientations or positions shown in the drawings, and are only for the purpose of facilitating and simplifying the description of the present application. These directional terms do not indicate or imply that a specified device or element has a particular orientation or must be configured and operated in a particular orientation, unless otherwise stated, and therefore cannot be understood to limit the scope of protection of the present application. The directional terms "inside, outside" mean the inside and outside of the profile relative to each part itself.

[0028] For ease of description, the spatial location of one component or feature relative to another component or feature shown in the drawings may be described herein using spatial relational terms such as "above...", "above...", "on top of...", "at the top of", etc. It will be understood that these spatial relational terms are intended to include orientations of the components in use or operation other than those shown in the drawings. For example, if the components in the drawings are inverted, a component described as "above other components or structures" or "on top of other components or structures" would be positioned as "below other components or structures" or "under other components or structures". Thus, the exemplary term "above..." can include two orientations: "above..." and "below...". The components may also be positioned in other different ways (rotated 90 degrees or at other orientations) and appropriately described with respect to the spatial relative descriptions used herein.

[0029] It should also be explained that the use of terms such as "first" and "second" to limit the components is merely to facilitate distinction between corresponding components, and that unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limitations on the scope of protection of the present application. Furthermore, although the terms used in the present application are selected from known terms, some of the terms described in the specification of the present application are selected by the applicant at his / her own discretion, and their detailed meanings will be explained in the relevant parts of the description of this specification. It is also required to understand the present application not only based on the actual terms used but also on the meanings contained in each term.

[0030] In one embodiment of the present invention, referring to FIG. 1, a back-contact battery 10 is proposed, which can improve the open circuit voltage of the battery, and thus enhance the efficiency and reliability of the battery.

[0031] According to FIG. 1, the back-contact cell 10 mainly comprises a semiconductor substrate 100, a first passivation layer 111, a first doped semiconductor layer 112, a second passivation layer 121, and a second doped semiconductor layer 122. Specifically, the semiconductor substrate 100 has a front surface 101 and a rear surface 102 opposite to each other, the front surface 101 being closer to the light-receiving surface of the back-contact cell 10 (i.e., the top surface of the entire back-contact cell 10 faces the outermost surface of the light source), and the rear surface 102 being closer to the backlight surface of the back-contact cell 10 (i.e., the rear surface of the entire back-contact cell 10 faces the outermost surface of the light source). Combining with FIG. 1, it can be seen that the rear surface 102 comprises a plurality of segment units 20 arranged adjacent to each other in sequence. Further combining with FIG. 1, each segment unit 20 includes a first segment 21, a second segment 22, a third segment 23 and a fourth segment 24 arranged adjacently and alternately, and a first space 210, a second space 220, a third space 230 and a fourth space 240 are formed between the first segment 21 to the fourth segment 24 and the rear surface 102, respectively, and the first space 210 to the fourth space 240 collectively form a segment space 200 between each segment unit 20 and the backlight surface.

[0032] In the present application, the rear surface 102 is divided into a plurality of segment units 20, and further subdivided into the first to fourth segments 21 to 24, and the first to fourth spaces 210 to 240 are formed in the space in order to facilitate the explanation of the positions of each characteristic layer based on the rear surface 102, particularly the positions of the first separation groove 161 and the second separation groove 162 (to be further explained below), and the division of these segments and spaces is not an inherent attribute of the rear-contact battery 10. In addition, since the conclusion of these divisions is not based on battery attributes but belongs to an artificial division method, FIG. 1 also merely shows the morphological characteristics (e.g., right angles, etc.) of the intersecting interfaces of adjacent segments in a schematic manner. In actual production, these intersecting interfaces also change according to the deposition and etching conditions of each actual characteristic layer, so a person skilled in the art can understand that the intersecting interfaces of each segment should not be unreasonably limited as shown in FIG. 1.

[0033] 1, the first passivation layer 111 is located only in the first space 210 in each segment space 200. The first doped semiconductor layer 112 is located only in the first space 210 in each segment space 200 and is adjacent to the side of the first passivation layer 111 that is away from the semiconductor substrate 100. Based on this, the second passivation layer 121 is located only in the second space 220, the third space 230 and the fourth space 240 in each segment space 200. The second doped semiconductor layer 122 is located only in the second space 220, the third space 230 and the fourth space 240 in each segment space 200 and is adjacent to the side of the second passivation layer 121 that is away from the semiconductor substrate 100.

[0034] Based on this design concept, the first passivation layer 111 in the present application can be actually implemented as a tunneling oxide layer, and the first doped semiconductor layer 112 comprises doped polycrystalline silicon, and the first doped semiconductor layer 112 has the same doping type as the semiconductor substrate 100. Meanwhile, in this embodiment, the second passivation layer 121 comprises intrinsic amorphous silicon, and correspondingly, the second doped semiconductor layer 122 comprises doped amorphous silicon or doped microcrystalline silicon, and the second doped semiconductor layer 122 has the opposite doping type to that of the semiconductor substrate 100. Thus, based on the separation and transition of the second segment 22 and the corresponding second space 220, the battery passivation performance is improved on one side of the second space 220 (the first space 210) and the battery open circuit voltage is increased on the other side of the second space 220 (the third space), thereby improving the efficacy and stability of the back contact battery 10.

[0035] Preferably, in this embodiment, the semiconductor substrate 100 further includes a substrate doping layer 113 of the same material and conductivity type as the semiconductor substrate 100 at a position adjacent to each first segment 21. As is clear from FIG. 1, the substrate doping layer 113 is located on the side of the back surface 102 close to the semiconductor deposit 100, so that the lower surface of the substrate doping layer 113 is also the first segment 21 on the back surface 102. By providing the substrate doping layer 113, a back electric field can be formed in the semiconductor substrate 100. Exemplarily, when manufacturing the first doped semiconductor layer 112, particularly when doping, a doping source is driven into the semiconductor substrate 100 to form the substrate doping layer 113.

[0036] In addition, the back contact cell 10 of this embodiment further includes a doped oxide layer 114 located in the first space 210 in each segment space 200 and adjacent to the side of the first doped semiconductor layer 112 that is away from the semiconductor substrate 100. Illustratively, the doped oxide layer 114 has the same doping material as the first doped semiconductor layer 112, and the doped oxide layer 114 can be selected as a doped silicon oxide. It is noted that some other embodiments of the present application may not include the doped oxide layer 114. Specifically, the doped oxide layer 114 can be directly formed during the manufacture of the cell, particularly when the first doped semiconductor layer 112 is doped, and in some embodiments, the layer can be removed in an additional step. In contrast, the doped oxide layer 114 is retained in this embodiment, which can simplify the process flow and reduce production costs. In addition, the back contact cell 10 further includes an insulating layer 13 located in the first space 210, the second space 220, and the fourth space 240 in each segment space 200, adjacent to the side of the doping oxide layer 114 away from the semiconductor substrate 100 in the first space 210, and adjacent to the back surface of the semiconductor substrate in the second space 220 and the fourth space 240. Illustratively, the insulating layer 13 may be composed of one or more compounds such as silicon nitride, silicon oxynitride, and silicon oxide. In this embodiment, the insulating layer 13 is provided to effectively prevent electrical connection between regions of different polarities on the back surface 102, resulting in a short circuit.

[0037] In addition to the above configuration, the back contact battery 10 further includes conductive layers 14 located in the first space 210, the second space 220, the third space 230, and the fourth space 240 in each segment space 200. Specifically, referring to FIG. 1, in the first space 210, at least a part of the conductive layer 14 is adjacent to the side of the insulating layer 13 that is away from the semiconductor substrate 100, and at least another part of the conductive layer 14 is adjacent to the side of the first doping semiconductor layer 112 that is away from the semiconductor substrate 100. On the other hand, in the second space 220 to the fourth space 240, at least a part of the conductive layer 14 is adjacent to the side of the second doping semiconductor layer 122 that is away from the semiconductor substrate 100.

[0038] In addition, in this embodiment, the back-contact battery 10 further includes a first electrode 151 and a second electrode 152 located in the first space 210 and the third space 230, respectively, in each segment space 200, where the first electrode 151 is located on the side of the conductive layer 14 in the first space 210 away from the semiconductor substrate 100, and the second electrode 152 is located on the side of the conductive layer 14 in the third space 230 away from the semiconductor substrate 100.

[0039] More preferably, in this embodiment, the conductive layer 14 forms a contact groove 140 recessed into the semiconductor substrate 100 in the first space 210 in each segment space 200, the first electrode 151 contacts the conductive layer 14 in the contact groove 140, and the contact groove 140 contacts the conductive layer 14 on the surface on the semiconductor substrate 100 side. However, the present application is not limited to the example shown in FIG. 1, and in some other embodiments of the present application, the contact slot extends into the first doped semiconductor layer 112. It is understood that in the manufacture of the back contact cell 10, the manufacture of the cell can be completed by bonding to each other through etching and deposition at the back surface 102. In order to form the contact groove 140, exemplarily, before depositing the conductive layer 14, the doped oxide layer 114 and the insulating layer 13 that have been manufactured in the first space 210 can be locally etched to form the shape of the contact groove 140, and the local etching method includes laser ablation combined wet etching, printing corrosive ink combined wet etching, etc. As a result, as the conductive layer 14 continues to be deposited, it forms groove-like features in the etched areas, creating contact grooves 140 .

[0040] Furthermore, as can be seen from FIG. 1, the back surface 102 has a morphological characteristic of undulations. Specifically, the first segment 21, the second segment 22, the third segment 23, and the fourth segment 24 are defined to have a first distance L1, a second distance L2, a third distance L3, and a fourth distance L4 from the front surface 101 of the semiconductor substrate 100, respectively. Illustratively, since the front surface 101 has a pile structure, the lower edge of the pile structure is selected as a reference line to define the above-mentioned distances. However, the present application is not limited thereto, and in other embodiments of the present application, there may be other forms for determining the reference line depending on the difference in the form of the front surface 101. However, as long as the first to fourth segments 21 to 24 adopt the same reference line determination form, the relative size relationship of the respective distances L1 to L4 from the first segment 21, the second segment 22, the third segment 23, and the fourth segment 24 to the front surface 101 of the semiconductor substrate 100 described in the present application does not change.

[0041] Specifically, in some embodiments of the present application, L3 is equal to or less than L2, L3 is equal to or less than L4, L2 is equal to or less than L1, and L4 is equal to or less than L1. Preferably, in some embodiments of the present application, the battery structures of the corresponding second space 220 and fourth space 240 of the second segment 22 and the fourth segment 24 are the same, and L2 is equal to L4. Therefore, in such embodiments, the second space 220 and the fourth space 240 can be collectively understood as separation or transition areas of the back-contact battery 10. Specifically, the second space 220 can be understood as a separation or transition area between the feature areas of the first space 210 and the third space 230 adjacent to each other for each divided space 200, while the fourth space 240 can be understood as a separation or transition area between the feature area of ​​the third space 230 in the previous segment space 200 and the feature area of ​​the first space 210 in the next segment space 200 adjacent to each other for each adjacent two segment spaces 200.

[0042] In the different embodiments proposed in the present application, the back contact cell further comprises at least one separation groove located in each segment space, located only in the first space, or located in both the second space and the fourth space, as will be described in more detail below with reference to the drawings.

[0043] Illustratively, FIG. 1 shows a case where the isolation groove is located in both the second space 220 and the fourth space 240. In this embodiment, the number of isolation grooves is two, which are the first isolation groove 161 and the second isolation groove 162. Referring to FIG. 1, it can be seen that the first isolation groove 161 is located in the second space 220, and the second isolation groove 162 is located in the fourth space 240. Furthermore, the first isolation groove 161 and the second isolation groove 162 penetrate the conductive layer 14, the second doped semiconductor layer 122, and the second passivation layer 121 in a direction gradually approaching the semiconductor substrate 100, and finally reach the lower end of the insulating layer 13. However, the present application is not limited thereto, and illustratively, based on a further modification of FIG. 1, the first isolation groove 161 can continue to extend upward into the insulating layer 131, but does not penetrate the insulating layer 131. In this embodiment, a first separation groove 161 and a second separation groove 162 are provided in the second space 220 and the fourth space 240, which do not have the first electrode 151 and the second electrode 152, respectively, thereby enabling more complete separation between the two polarity regions in the segment space 200 corresponding to each segment unit 20.

[0044] Meanwhile, FIG. 2 shows another embodiment with different positions of the separation grooves. The back-contact battery 10' shown in FIG. 2 is different from the back-contact battery 10 shown in FIG. 1 only in the positions of the two separation grooves (third separation groove 161' and fourth separation groove 162'), so the same reference numerals are used for the other parts. In the embodiment shown in FIG. 2, the two separation grooves are located in the first space 210 in each segment space 200. As can be seen from FIG. 2, the third separation groove 161' and the fourth separation groove 162' are located on both the left and right sides of the contact groove 140, respectively, and the two separation grooves penetrate to the inside of the insulating layer at the maximum in a direction gradually approaching the semiconductor substrate. Unlike the embodiment shown in FIG. 1, in this embodiment, the position of the separation groove is set to match the position of the contact groove 140, so that the manufacturing process can be appropriately adjusted.

[0045] As described above, the back structure of the back-contact cell 10 has been described, and now the front structure of the back-contact cell 10 will be described. On the front surface 101, the back-contact cell further comprises a front passivation layer 16 located between the front surface 101 and the light-receiving surface of the semiconductor substrate 100 and adjacent to the front surface 101, where the front passivation layer 16 may be composed of one or more of materials such as intrinsic amorphous silicon, alumina, silicon nitride, silicon oxynitride, and silicon oxide.

[0046] In addition, according to FIG. 1 , the back-contact cell 10 further comprises a front anti-reducing layer 17 on the front passivation layer 16 adjacent to the side of the front passivation layer 16 facing away from the semiconductor substrate 100, where the front anti-reducing layer 17 can be composed of one or more of silicon nitride, silicon oxynitride, silicon oxide, and a transparent conductive layer.

[0047] Meanwhile, the front surface 101 of the semiconductor substrate 100 is a pile structure, and the pile structure is a pyramid pile or an etched pit pile, or a combination of both, and in this way, the reflection loss of the incident light can be better reduced and the light absorption can be increased. Correspondingly, the back surface 102 of the semiconductor substrate 100 uses a pile structure, a polished surface structure, or a combination of both. Preferably, referring to the embodiment shown in FIG. 1, on the back surface 102, the third segment 23 is a pile structure or a polished surface structure, and the first segment 21, the second segment 22, and the fourth segment 24 are polished surface structures, and based on this design scheme, the passivation effect can be enhanced and the process technology can be simplified.

[0048] Based on the manufacturing technology of rear contact cells, the present application comprehensively considers the effect of improving the cell performance and the process cost, and designs a plurality of adjacently and alternately arranged first to fourth spaces on the backlight surface side of the solar cell. Each space has the same or different cell structure. Here, the performance of the cell is mainly embodied by the characteristic layers in the first space and the third space, and the first space is set up in a stacked structure having a first passivation layer (e.g., tunnel oxide layer) and a doped semiconductor layer (e.g., doped polycrystalline silicon), which has good passivation contact properties, can reduce the carrier complexation rate in the metal electrode contact area, and can improve the open-circuit voltage of the cell. In addition, the third space is set up in a stacked structure having a second passivation layer (e.g., intrinsic amorphous silicon) and a second doped semiconductor layer (e.g., doped amorphous silicon / doped microcrystalline silicon, etc.), and can further increase the open-circuit voltage of the cell by utilizing its properties such as low surface complexation rate. In addition, the battery structure has a second space and a fourth space, which may be the same or different, and the function of these two spaces is to isolate the first space and the third space, which have opposite polarity, to avoid the occurrence of short circuit and leakage phenomenon, and to ensure higher conversion efficiency and reliability of the battery. In addition, taking into consideration factors such as technical feasibility and process simplification, the application also presents specific position characteristics of other characteristic layers (such as insulating layer, conductive layer, etc.) and separators, thereby ensuring the improvement of battery performance and further ensuring the reliability of the battery under the premise of technical scope permission and controllability.

[0049] The present application further proposes a solar cell module comprising a plurality of series and / or parallel connected back-contact cells as proposed by any of the embodiments of the present application described above. Further details regarding the solar cell module are not of interest to the present application and will not be developed here.

[0050] Although the basic concepts have been described above, it is obvious to those skilled in the art that the above disclosure is merely an example and is not intended to limit the present application. Although not expressly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are proposed in the present application and therefore fall within the spirit and scope of the exemplary embodiments of the present application.

[0051] At the same time, the present application uses certain terms to describe the embodiments of the present application. For example, "one embodiment," "an embodiment," and / or "some embodiments" refer to features, configurations, or characteristics associated with at least one embodiment of the present application. Thus, it should be emphasized and noted that "one embodiment" or "one embodiment" or "an alternative embodiment" referenced two or more times in different places in this specification do not necessarily refer to the same embodiment. Furthermore, some features, configurations, or characteristics in one or more embodiments of the present application may be combined as appropriate.

[0052] For the same reason, it should be noted that in the above description of the embodiments of the present application, multiple features may be combined into one embodiment, drawing, or description thereof in order to simplify the expression disclosed in the present application and facilitate the understanding of one or more embodiments of the present application. However, this method of disclosure does not imply that the subject matter of the present application requires more features than are recited in the claims. In fact, an embodiment may have fewer features than all the features of a single embodiment disclosed above.

[0053] In some examples, numbers describing the number of components, attributes are used, but it should be understood that the numbers describing such examples are modified in some instances using the modifiers "about," "approximately," or "approximately." Unless otherwise specified, "about," "approximately," or "approximately" means that the numerical value is allowed to vary by ±20%. Thus, in some examples, the numerical parameters used in the specification and claims are approximations, and these approximations may be modified depending on the characteristics required for each particular example. In some examples, the numerical parameters should be calculated using a common method of conserving digits, taking into account the number of significant digits given. In some examples of the present application, the numerical fields and parameters used to determine the breadth of their ranges are approximations, but in certain examples, such numerical values ​​are set as precisely as possible within the limits of feasibility.

[0054] Although the present application has been described with reference to the present specific embodiments, it should be noted that a person of ordinary skill in the art should recognize that the above embodiments are only used to describe the present application, and various equivalent modifications or replacements are possible without departing from the spirit of the present application, and therefore, any modifications or variations of the above embodiments within the spirit of the present application should fall within the scope of the claims of the present application. [Explanation of symbols]

[0055] 10 Rear contact battery 13 Insulating layer 14 Conductive layer 16 Front passivation layer 17 Frontal rice production reduction layer 20 Segment Unit 21 First Segment 22 Second Segment 23 Third Segment 24 4th Segment 100 Semiconductor substrate 101 Front 102 Back 111 First passivation layer 112 First doped semiconductor layer 113 Substrate doping layer 114 Doping oxide layer 121 Second passivation layer 122 Second doping semiconductor layer 140 Contact groove 140 151 1st electrode 152 2nd electrode 161 1st separation groove 161' 3rd separation groove 162 2nd separation groove 162' 4th separation groove 200 Segment Space 210 1st space 220 2nd space 230 Third space 240 4th space

Claims

1. a semiconductor substrate having opposing front and back surfaces, the front surface being close to a light receiving surface of a back-contact cell and the back surface being close to a backlight surface of the back-contact cell, the back surface comprising a plurality of segment units arranged adjacent to each other in sequence, each segment unit comprising a first segment, a second segment, a third segment and a fourth segment arranged adjacent to each other in sequence in an alternating manner, a first space, a second space, a third space and a fourth space being formed between the first segment to the fourth segment and the back surface, respectively, and the first space to the fourth space commonly constituting a segment space between each of the segment units and the backlight surface; a first passivation layer located only in the first space of each of the segment spaces; a first doping semiconductor layer located only in the first space of each of the segment spaces and adjacent to a side of the first passivation layer away from the semiconductor substrate; a second passivation layer located only in the second space, the third space, and the fourth space in each of the segment spaces; a second doping semiconductor layer located only in the second space, the third space, and the fourth space in each of the segment spaces and adjacent to a side of the second passivation layer away from the semiconductor substrate; 1. A back contact battery comprising:

2. 10. The back contact cell of claim 1, wherein the semiconductor substrate further comprises a substrate doping layer having the same conductivity type as the semiconductor substrate adjacent each of the first segments.

3. 2. The back contact battery of claim 1, further comprising an insulating layer located in the first space, the second space, and the fourth space in each of the segment spaces, located on a side of the first doped semiconductor layer away from the semiconductor substrate in the first space, and adjacent to the back surface of the semiconductor substrate in the second space and the fourth space.

4. 4. The back contact cell of claim 3, further comprising a doped oxide layer located in the first space of each of the segment spaces and adjacent to the insulating layer and between the side of the first doped semiconductor layer away from the semiconductor substrate.

5. a conductive layer located in the first space, the second space, the third space, and the fourth space in each of the segment spaces, In the first space, at least a portion of the conductive layer is adjacent to a side of the insulating layer that is away from the semiconductor substrate, and at least another portion of the conductive layer is adjacent to a side of the first doped semiconductor layer that is away from the semiconductor substrate, 4. The back contact battery of claim 3, wherein in the second space to the fourth space, at least a portion of the conductive layer is adjacent to a side of the second doped semiconductor layer away from the semiconductor substrate.

6. 6. The back-contact battery of claim 5, further comprising a first electrode and a second electrode located in the first space and the third space, respectively, in each of the segment spaces, the first electrode being located on a side of the conductive layer away from the semiconductor substrate in the first space, and the second electrode being located on a side of the conductive layer away from the semiconductor substrate in the third space.

7. 7. The back contact battery of claim 6, wherein the conductive layer forms a contact groove recessed into the semiconductor substrate within the first space in each of the segment spaces, the first electrode contacts the conductive layer within the contact groove, and the contact groove contacts the conductive layer on a surface closer to the semiconductor substrate or extends into the first doped semiconductor layer.

8. 2. The back contact battery of claim 1, wherein the first, second, third and fourth segments have a first distance L1, a second distance L2, a third distance L3 and a fourth distance L4, respectively, from the first segment, the second segment, the third segment and the fourth segment to the front surface of the semiconductor substrate, L3 being less than or equal to L2, L3 being less than or equal to L4, L2 being less than or equal to L1 and L4 being less than or equal to L1.

9. 9. The back contact battery of claim 8, wherein the battery structures in the second space and the fourth space where the second segment and the fourth segment correspond are the same, and L2 is equal to L4.

10. 10. The back contact cell of claim 1, further comprising a front passivation layer located between and adjacent to the front surface of the semiconductor substrate and the light receiving surface, the front passivation layer comprising intrinsic amorphous silicon, alumina, silicon nitride, silicon oxide nitrate, and / or silicon oxide.

11. 11. The back contact cell of claim 10, further comprising a front anti-reverse layer adjacent to a side of the front passivation layer away from the semiconductor substrate, the front anti-reverse layer comprising silicon nitride, silicon oxynitride, silicon oxide and / or a transparent conductive layer.

12. 12. The back contact cell of claim 11, wherein the front side of the semiconductor substrate is a pile structure, the pile structure comprising pyramidal piles and / or corrosion pit piles.

13. 13. The back contact battery of claim 12, wherein the back surface of the semiconductor substrate has the pile structure and / or the polished surface structure, the third segment is a pile structure or a polished surface structure, and the first segment, the second segment and the fourth segment are polished surface structures.

14. 2. The back contact cell of claim 1, wherein the first passivation layer comprises a tunneling oxide layer, the first doped semiconductor layer comprises doped polycrystalline silicon, and the first doped semiconductor layer has a doping type similar to that of the semiconductor substrate.

15. 15. The back contact cell of claim 14, wherein the second passivation layer comprises intrinsic amorphous silicon and the second doped semiconductor layer comprises doped amorphous silicon and / or doped microcrystalline silicon, the second doped semiconductor layer being opposite in doping type to the semiconductor substrate.

16. 16. The back contact battery of claim 1, further comprising at least one separation groove located in each of the segment spaces, the separation groove being located only in the first space or being located in both the second space and the fourth space.

17. The back contact battery of claim 4, further comprising two separation grooves located in the second space and the fourth space in each segment space, the two separation grooves penetrating up to the inside of the insulating layer in a direction gradually approaching the semiconductor substrate.

18. The back-contact battery of claim 7, further comprising two separation grooves located within the first space in each of the segment spaces, the two separation grooves being located on both sides of the contact groove, and the two separation grooves penetrating up to the inside of the insulating layer in a direction gradually approaching the semiconductor substrate.

19. A solar cell module comprising a plurality of series and / or parallel connected back contact cells according to any one of claims 1 to 18.

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