Active transistor physical unclonable function (PUF) circuit with MEMS uniqueness

Abstract

To provide systems and methods for an active transistor physical unclonable function (PUF) circuit with micro-electromechanical systems (MEMS) uniqueness.SOLUTION: A PUF circuit includes: one or more MEMS structures configured to provide an output, where the output includes active oscillation, charge, resistance, inductance and / or capacitance values; and active transistor PUF circuitry communicatively coupled to the one or more MEMS structures. The active transistor PUF circuitry is configured to receive a challenge input and generate a PUF response in response to the challenge input. The PUF response is generated based on the output provided by the one or more MEMS structures and on manufacturing variation in components of the active transistor PUF circuitry. The PUF response generated by the active transistor PUF circuitry is an output of the PUF circuit.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Application No. 63 / 516,949, entitled “DUAL USE MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICE,” filed August 1, 2023, the contents of which are incorporated by reference in their entirety herein.

[0002] This application is related to U.S. application Ser. No. 18 / 661,373 (Attorney Docket No. H232672-US2), entitled "DUAL USE MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICE," filed on the same day as this application, U.S. application Ser. No. 18 / 661,400 (Attorney Docket No. H233692-US), entitled "CODEPENDENT PHYSICAL UNCLONABLE FUNCTION / RANDOM NUMBER GENERATOR PAIRING FOR PHYSICAL PROVENANCE," filed on the same day as this application, U.S. application Ser. No. 18 / 661,416 (Attorney Docket No. H233693-US), entitled "MEMS BASED PUF FOR MECHANICAL TRUST EXTENSION," filed on the same day as this application, and U.S. application Ser. No. 18 / 661,420 (Attorney Docket No. H233692-US), entitled "ACTIVE TRANSISTOR RANDOM NUMBER GENERATOR (RNG) CIRCUIT WITH MEMS No. 18 / 661,437 (Attorney Docket No. H233699-US), entitled "METHOD FOR HYPERTENSION ENTROPY," all of which are incorporated herein by reference in their entireties. [Background technology]

[0003] A system that can provide assurance regarding the identity of the hardware within the system is needed for cryptography. This capability provides a means to improve the ability to meet and maintain network integrity. Commercial systems require technology that can be integrated into electronic systems through packaging, potting, that can provide a unique digital identity to the software, such that a physical change permanently changes the resulting digital identity. The identity can then be encoded into the cryptographic process of the hardware system. The system must be able to verify the identity of the hardware, such that changing the hardware changes the identifier. Summary of the Invention

[0004] In some aspects, a physical unclonable function (PUF) circuit is described herein. The PUF circuit includes one or more microelectromechanical system (MEMS) structures configured to provide an output, the output including an active oscillation, a charge, a resistance, an inductance, and / or a capacitance value. The PUF circuit further includes active transistor PUF circuitry communicatively coupled to the one or more MEMS structures. The active transistor PUF circuitry is configured to receive a challenge input and generate a PUF response in response to the challenge input. The PUF response is generated based on the output provided by the one or more MEMS structures and manufacturing variations of components of the active transistor PUF circuitry. The PUF response generated by the active transistor PUF circuitry is an output of the PUF circuit.

[0005] In some aspects, a device is described herein. The device includes a PUF circuit. The PUF circuit includes one or more microelectromechanical system (MEMS) structures configured to provide active oscillation, charge, resistance, inductance, and / or capacitance values. The PUF circuit further includes active transistor PUF circuitry communicatively coupled to the one or more MEMS structures. The active transistor PUF circuitry is configured to receive a challenge input and output a PUF response in response to the challenge input. The PUF response output by the active transistor PUF circuitry is generated based on the active oscillation, charge, resistance, inductance, and / or capacitance values ​​output by the one or more MEMS structures and manufacturing variations of components of the active transistor PUF circuitry. The device further includes one or more additional circuits configured to generate a challenge input and / or utilize the PUF response for one or more cryptographic processes.

[0006] In some aspects, a method is described herein. The method includes receiving a PUF challenge using an active-transistor physical unclonable function (PUF) circuit of a PUF circuit. The PUF circuit further includes one or more MEMS structures communicatively coupled to the active-transistor PUF circuitry. The method further includes generating a PUF response to the PUF challenge based on active oscillation, charge, resistance, inductance, and / or capacitance values ​​output by the one or more MEMS structures in response to the PUF challenge and manufacturing variations of components of the active-transistor PUF circuitry. The method further includes outputting the PUF response to an additional circuit. [Brief description of the drawings]

[0007] Example embodiments will be described with additional specificity and detail using the accompanying drawings, with the understanding that the drawings illustrate example embodiments only and should not be considered limiting in scope. [Figure 1A]FIG. 1 is a block diagram of an exemplary physical unclonable function (PUF) circuit including a MEMS structure(s) and an active transistor PUF circuit configuration. [Figure 1B] FIG. 1 is a block diagram of an exemplary physical unclonable function (PUF) circuit including a MEMS structure(s) and an active transistor PUF circuit configuration. [Figure 2A] 1A-1D are diagrams of example configurations of PUF circuits, including MEMS structures and active transistor PUF circuit configurations, based on different manufacturing technologies. [Figure 2B] 1A-1D are diagrams of example configurations of PUF circuits, including MEMS structures and active transistor PUF circuit configurations, based on different manufacturing technologies. [Figure 2C] 1A-1D are diagrams of example configurations of PUF circuits, including MEMS structures and active transistor PUF circuit configurations, based on different manufacturing technologies. [Diagram 3] FIG. 1 is a block diagram of an exemplary system.

[0008] In accordance with common practice, the various features described are not drawn to scale but rather to emphasize particular features relevant to the exemplary embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific illustrative embodiments. It should be understood, however, that other embodiments may be utilized and that logical, mechanical, and electrical changes may be made. Furthermore, the methods presented in the drawings and specification should not be construed as limiting the order in which individual steps may be performed. Accordingly, the following detailed description is not to be construed in a limiting sense.

[0010] Examples described herein include hybrid PUF circuits that include one or more microelectromechanical systems (MEMS) structures and active transistor physical unclonable function (PUF) circuits that utilize the MEMS structures to provide a source of device uniqueness. The active transistor PUF circuit configurations can utilize different PUF topologies that rely on transistor manufacturing variations to provide MEMS outputs that vary based on physical properties of the one or more MEMS structures. The one or more MEMS structures can be active or passive and can be configured to modify the PUF output by providing active oscillation, charge, resistance, inductance, and / or capacitance values ​​as the MEMS output. Different PUF circuit topologies can be used with the unique properties of the MEMS structures to fabricate PUF circuits that are small, low power, and provide low latency PUF outputs.

[0011] 1A is a block diagram of an exemplary physical unclonable function (PUF) circuit 100. In the example shown in FIG. 1A, the PUF circuit 100 is implemented using a combination of one or more MEMS structures 102 and active transistor PUF circuitry 104. In some examples, the PUF circuit 100 is an exemplary implementation of a PUF circuit described in co-pending U.S. patent application Ser. No. 18 / 661,400 (Attorney Docket No. H233692-US), entitled “CODEPENDENT PHYSICAL UNCLONABLE FUNCTION / RANDOM NUMBER GENERATOR PAIRING FOR PHYSICAL PROVENANCE.”

[0012] In some examples, the one or more MEMS structures 102 include a single MEMS structure. In other examples, the one or more MEMS structures 102 include multiple MEMS structures. The one or more MEMS structures 102 may be any type of MEMS device, such as an accelerometer, a gyroscope, a pressure sensor, a temperature sensor, an airflow sensor, or other similar MEMS structures. When included in the PUF circuit 100, the one or more MEMS structures 102 can serve as an additional source of uniqueness for the active-transistor PUF circuitry 104.

[0013] In some examples, the one or more MEMS structures 102 include one or more PUF MEMS structures used exclusively for the PUF circuit 100. In other examples, the one or more MEMS structures 102 include one or more shared MEMS structures shared with another circuit (e.g., a random number generator (RNG) circuit). In some such examples, the RNG circuit generates a sequence of numbers or symbols that cannot be reasonably predicted better than by random chance, or extracts randomness from a physical phenomenon to generate numbers (e.g., a true RNG). In some examples, the one or more MEMS structures 102 include both one or more PUF MEMS structures used exclusively for the PUF circuit 100 and one or more shared MEMS structures shared with another circuit.

[0014] The one or more MEMS structures 102 are configured to modify the PUF output by providing active oscillation, charge, resistance, inductance, and / or capacitance values ​​to the active transistor PUF circuitry 104. In some examples, the one or more MEMS structures 102 are active components. In other examples, the one or more MEMS structures 102 are passive components.

[0015] In some examples, components of the active-transistor PUF circuitry 104 are implemented using transistor-based integrated circuits. For example, the active-transistor PUF circuitry 104 may be implemented in an application specific integrated circuit (ASIC) or another type of integrated circuit.

[0016] In some examples, the active transistor PUF circuitry 104 may include, but is not limited to, circuitry configured to generate a corresponding PUF response based on a particular PUF challenge input to the system. For example, if the active transistor PUF circuitry 104 is configured to implement a ring oscillator PUF, the active transistor PUF circuitry 104 may include an array of ring oscillator loops coupled to multiplexers, frequency counters, comparison circuitry, etc.

[0017] In some examples, the active transistor PUF circuitry 104 is dedicated to the PUF circuit 100. In other examples, at least some components of the active transistor PUF circuitry 104 of the PUF circuit 100 are shared with another circuit (e.g., a random number generator (RNG) circuit).

[0018] In some examples, the circuit connections between one or more MEMS structures 102 and the active transistor PUF circuitry 104 allow the operation of one or more MEMS structures 102 to be influenced by the active transistor PUF circuitry 104, and vice versa, as shown in FIG. 1A using bidirectional arrows between these components. In such examples, one or more MEMS structures 102 should influence the active transistor PUF circuitry 104, and the active transistor PUF circuitry 104 should influence one or more MEMS structures 102, such that these components of the PUF circuit 100 are codependent. In some examples, changes to one or more MEMS structures 102 or the active transistor PUF circuitry 104 result in changes to the PUF output from the PUF circuit 100. These features help prevent situations in which the MEMS structures 102 can be removed, characterized, and replaced to spoof or modify the operation of the PUF circuit 100 for fraudulent purposes.

[0019] In the example shown in FIG. 1A, the PUF circuit 100 is configured to receive a system input (e.g., an input from a user). In particular, the active transistor PUF circuitry 104 is configured to receive the system input. In some examples, the system input includes one or more challenges (e.g., challenge bits), and the PUF circuit 100 is configured to output a response to the one or more challenges. In the example shown in FIG. 1A, the PUF circuit 100 is configured to generate a unique PUF output that corresponds to a particular challenge input. Particular components of the PUF circuit 100 can be selected and configured to implement various PUF architectures (e.g., an arbiter, a ring oscillator, etc.) and can include a variety of different electronic components.

[0020] In the example shown in FIG. 1A, one or more MEMS structures 102 are configured to receive a bias input that can be used in combination with a system input to generate a different PUF output. In some examples, the bias input is static and designed not to change during operation. In other examples, the bias input is dynamic and can be reconfigured during operation. In some such examples, the bias input is used as part of the PUF challenge in addition to the system input described above. In some examples, in addition to or instead of the bias input, one or more inputs can be used as part of the PUF challenge in addition to the system input described above.

[0021] In some examples, the bias input originates from the active transistor PUF circuitry 104. In some such examples, the bias input originates from the active transistor PUF circuitry 104 in the form of an independent generator as part of the PUF challenge. In other examples, the bias input originates from the active transistor PUF circuitry 104 as direct feedback from a unique portion of the active transistor PUF circuitry 104, but is not part of the PUF challenge. In some such examples, the output of a portion of the active transistor PUF circuitry 104 is adjusted to reduce any digital oscillations to an appropriate level required for secure input to one or more MEMS structures 102. In some examples, the bias input may originate from the active transistor PUF circuitry 104 using a combination of the techniques described above. For example, the bias input may be influenced by both an independent generator and direct feedback from a unique portion of the active transistor PUF circuitry 104.

[0022] 1A, the uniqueness of the PUF output is affected by noise and uncontrollable factors inherent in the construction materials, manufacturing processes, etc. of the active transistor PUF circuitry 104 and the one or more MEMS structures 102. In general, the uniqueness of the PUF output of PUF circuit 100 is increased compared to a PUF circuit including only active transistor circuitry by using active oscillation, charge, resistance, inductance, and / or capacitance values ​​output from one or more MEMS structures 102 in addition to the active transistor PUF circuitry 104.

[0023] 1B is a block diagram of an exemplary physical unclonable function (PUF) circuit 110. In the example shown in FIG. 1B, the PUF circuit 110 is implemented using a combination of one or more MEMS structures 102 and active transistor PUF circuitry 104. In some examples, the PUF circuit 110 is an exemplary implementation of a PUF circuit described in co-pending U.S. patent application Ser. No. 18 / 661,400 (Attorney Docket No. H233692-US), entitled “CODEPENDENT PHYSICAL UNCLONABLE FUNCTION / RANDOM NUMBER GENERATOR PAIRING FOR PHYSICAL PROVENANCE.”

[0024] The exemplary PUF circuit 110 shown in Figure 1B is a specific example of the PUF circuit 100 described above with respect to Figure 1A. In the example shown in Figure 1B, the PUF circuit 110 implements a ring oscillator PUF topology. It should be understood that a different topology for the active transistor PUF circuitry 104 (e.g., an arbiter or other PUF topology) can also be used in combination with one or more MEMS structures 102 to implement the PUF circuit 100.

[0025] 1B, the one or more MEMS structures 102 include an array of N MEMS structures 112. The MEMS structures 112 are configured to output active oscillation, charge, resistance, inductance, and / or capacitance values ​​to a ring oscillator loop 114. The MEMS structures 112 impart unique variations to the ring oscillator loop 114, and the measurements used to generate the PUF output (shown as a bit output in FIG. 1B) are relative from one ring oscillator loop 114 to another ring oscillator loop 114.

[0026] In the example shown in Figure 1B, the active transistor PUF circuitry 104 includes an array of multiple ring oscillator loops 114, each including the same number of inverter components. In the example shown in Figure 1B, the frequency of each of the ring oscillator loops 114 is a function of active oscillation, charge, resistance, inductance, and / or capacitance effects from each corresponding MEMS structure 112 coupled to the inverter loop that oscillates at a particular frequency. In the example shown in Figure 1B, each of the ring oscillator loops 114 includes three inverters, although it should be understood that other odd numbers of inverters may also be used for the ring oscillator loops 114.

[0027] 1B, each of the MEMS structures 112 is biased using the same bias input, which may be used to modify the behavior of the MEMS structures 112 to result in different PUF output values. In other examples, there may be an asymmetry in the biasing of the MEMS structures 112. For example, at least one of the MEMS structures 112 may be individually biased in that at least one MEMS structure 112 is biased with a separate bias input compared to the other MEMS structures 112.

[0028] In some examples, the bias input comes from the active transistor PUF circuitry 104. In some such examples, the bias input comes from the active transistor PUF circuitry 104 in the form of an independent generator as a challenge, as described below. In other examples, the bias input comes from the active transistor PUF circuitry 104 not as part of the challenge, but as direct feedback from a unique portion of the active transistor PUF circuitry 104. In such examples, the output of a portion of the active transistor PUF circuitry 104 is adjusted to reduce any digital oscillations to an appropriate level required for safe input to the MEMS structure 112. In the example shown in FIG. 1B, the MEMS structure 112 may be configured to oscillate similarly to the ring oscillator loop 114 based on the bias input, or use the bias input to prevent oscillations generated by the junction of the transistor ring oscillator. In some examples, the bias input may come from the active transistor PUF circuitry 104 using a combination of the techniques described above. For example, the bias input may be influenced by both an independent generator and direct feedback from a unique portion of the active transistor PUF circuitry 104.

[0029] 1B, each of the MEMS structures 112 is coupled to a respective ring oscillator loop 114, and each ring oscillator loop 114 is coupled to the MEMS structure 112. In other examples, there may be an asymmetry in the configuration of the MEMS structures 112 and the ring oscillator loops 114. For example, one or more of the ring oscillator loops 114 may not be coupled to the MEMS structure 112 and thus may not receive active oscillation, charge, resistance, inductance, and / or capacitance values ​​from the MEMS structure 112.

[0030] In the example shown in FIG. 1B , each of the MEMS structures 112 is coupled to the ring oscillator loop 114 via a signal conditioning block. In some examples, the signal conditioning block is configured to perform one or more signal conditioning functions on signals communicated from the MEMS structures 112 to the ring oscillator loop 114 or from the ring oscillator loop 114 to the MEMS structures 112. In some examples, the signal conditioning block includes AC coupling circuits, voltage dividers, and / or other circuitry. In some examples, the signal conditioning block is configured to perform level conversion, amplification, DC offset isolation (e.g., using AC coupling), and / or other signal conditioning functions. In some examples, the signal conditioning block used to interface between each MEMS structure 112 and its corresponding ring oscillator loop 114 provides a unique interface connection between each individual MEMS structure 112 and its corresponding ring oscillator loop 114.

[0031] In general, it is better if the bias input and the ring oscillator PUF circuit are symmetrical, as variations between the frequencies of the ring oscillator loop 114 will be based on active oscillation, charge, resistance, inductance, and / or capacitance effects from the corresponding MEMS structures 112, as well as manufacturing variations in the components of the ring oscillator loop 114.

[0032] In the example shown in FIG. 1B, the active transistor PUF circuitry 104 further includes a first multiplexer 116 and a second multiplexer 118 communicatively coupled, respectively, to each of the ring oscillator loops in the array 114 of ring oscillator loops.

[0033] The first multiplexer 116 is configured to select a particular frequency from one or more ring oscillator loops 114 to output to a first frequency counter 120 (frequency counter A) based on a Challenge A input provided to the first multiplexer 116. Similarly, the second multiplexer 118 is configured to select a particular frequency from one or more ring oscillator loops 114 to output to a second frequency counter 122 (frequency counter B) based on a Challenge B input provided to the second multiplexer 118. The Challenge A and Challenge B inputs to the first multiplexer 116 and second multiplexer 118, respectively, determine which of the ring oscillator loops 114 is selected for comparison.

[0034] The count value of the first frequency counter 120 and the count value of the second frequency counter 122 are compared to each other using a comparator 124. Depending on the result of the comparison by the comparator 124, a single PUF bit is output (shown as Bit Out in FIG. 1B). Bit Out is a function of the Challenge A input, the Challenge B input, and the bias applied to the MEMS structure 112. The particular function that determines Bit Out depends on the active oscillation, charge, resistance, inductance, and / or capacitance values ​​output from the MEMS structure 112. In some examples, the PUF output can be a single bit (as shown in FIG. 1B) or a series of bits. In examples where the PUF output is a series of bits, the series of bits can be generated by multiple PUF circuits operating in time separated or in parallel.

[0035] 1B, a start / stop / reset count is provided to both the first frequency counter 120 and the second frequency counter 122. The start count and stop count set the period over which the output frequencies from the first multiplexer 116 and the second multiplexer 118 are counted. A reset count is provided to reset the first frequency counter 120 and the second frequency counter 122 after the set period has elapsed.

[0036] As described above, each PUF circuit 110 provides a different and unique PUF output that depends on the challenge A input, the challenge B input, and the bias input applied to the MEMS structure 112. In some examples, the bias input(s) received by the MEMS structure 112 are also used to generate different PUF outputs in combination with the challenge inputs provided to the first multiplexer 116 and the second multiplexer 118, and thus the bias inputs may also be used as part of the PUF challenge. In some examples, in addition to or instead of the bias inputs, one or more inputs may be used as part of the PUF challenge in addition to the system inputs described above.

[0037] In an example where the bias input is dynamic and used as part of the PUF challenge, the MEMS structure 112 associated with the ring oscillator loop 114 selected by the first multiplexer 116 and the second multiplexer 118 based on the challenge input A and the challenge input B, respectively, is manipulated as part of the challenge input. In such an example, the MEMS structure 112 behaves differently and outputs different active oscillation, charge, resistance, inductance, and / or capacitance values ​​in response to the particular challenge bias input. For example, each of the MEMS structures 112 can be made to resonate, which will introduce frequency variations in the ring oscillator loop 114. By outputting different active oscillation, charge, resistance, inductance, and / or capacitance values, the frequency of the corresponding ring oscillator loop 114 is altered and thus the result of the comparison by the comparator 124 may be different, which results in a different PUF output. A PUF circuit 110 that uses both multiplexer selection and dynamic bias input to the MEMS structures 112 as part of the PUF challenge produces more dynamic PUF results, which makes the PUF circuit 110 more difficult to spoof because each of the MEMS structures 112 responds differently to a bias or stimulus.

[0038] 1A-1B, it should be understood that other configurations are possible. For example, two or more instances of the PUF circuits 100, 110 may be included in a single device or system (e.g., to generate a sequence of bits). Furthermore, the PUF circuits 100, 110 may be integrated into a larger device or system that includes additional circuitry beyond that shown for the PUF circuits 100, 110, and may perform additional functions, such as generating system inputs for the PUF circuits 100, 110 and / or utilizing the PUF outputs for cryptographic processes.

[0039] 2A-2C are diagrams of example PUF circuits including one or more MEMS structures and active transistor PUF circuitry configurations fabricated using different fabrication techniques. The example configurations of PUF circuits and fabrication techniques described with respect to FIGs. 2A-2C are not intended to be exhaustive. It should be understood that other configurations of PUF circuits including one or more MEMS structures and active transistor PUF circuitry configurations may also be fabricated using other fabrication techniques.

[0040] FIG. 2A shows a diagram of a PUF circuit 200 that includes one or more MEMS structures 202 and active transistor PUF circuitry 204 and is fabricated using a first fabrication technique.

[0041] 2A , the one or more MEMS structures 202 are fabricated separately from the active transistor PUF circuitry 204 and connected to the active transistor PUF circuitry 204 using a substrate 206. In some examples, the one or more MEMS structures 202 and the active transistor PUF circuitry 204 may be fabricated on separate dies, but then the one or more MEMS structures 202 and the active transistor PUF circuitry 204 are mounted on the substrate 206. In some examples, the one or more MEMS structures 202 are packaged separately from the active transistor PUF circuitry 204 and connected on a circuit substrate.

[0042] Interconnects are used between the one or more MEMS structures 202 and the active transistor PUF circuitry 204 to connect the one or more MEMS structures 202 to the active transistor PUF circuitry 204. It is beneficial to reduce the length of the interconnects between the one or more MEMS structures 202 and the active transistor PUF circuitry 204 because longer interconnects introduce undesirable unpredictability into the PUF circuit 200. Thus, in some implementations of the example PUF circuit 200, the one or more MEMS structures 202 and the active transistor PUF circuitry 204 are positioned as close together as feasible on the substrate 206.

[0043] FIG. 2B shows a diagram of a second PUF circuit 210 including one or more MEMS structures 212 and active transistor PUF circuitry 214 and fabricated using a second fabrication technique.

[0044] 2B , the one or more MEMS structures 212 are fabricated separately from the active transistor PUF circuitry 214 and stacked on top of the active transistor PUF circuitry 214. In some examples, the one or more MEMS structures 212 and the active transistor PUF circuitry 214 may be fabricated on separate dies, but then the one or more MEMS structures 212 are stacked on top of the active transistor PUF circuitry 214. In some examples, the one or more MEMS structures 212 are packaged separately from the active transistor PUF circuitry 214 and stacked (e.g., on a circuit board) on top of the active transistor PUF circuitry 214.

[0045] To connect the one or more MEMS structures 212 to the active transistor PUF circuitry 214, vertical interconnects are used between the one or more MEMS structures 212 and the active transistor PUF circuitry 214. Vertical connections are generally more effective in reducing the length of the interconnects between the one or more MEMS structures 212 and the active transistor PUF circuitry 214 compared to the interconnects used in FIG. 2A. When the one or more MEMS structures 212 are aligned with corresponding components of the active transistor PUF circuitry 214, the length of the interconnects is further reduced. Thus, in some implementations of the exemplary PUF circuit 210, the one or more MEMS structures 212 and the active transistor PUF circuitry 214 are stacked and aligned to reduce the length of the vertical interconnects as much as possible. In some circumstances, the vertical stacking of the one or more MEMS structures 212 and the active transistor PUF circuitry 214 may also improve resistance to physical tampering.

[0046] FIG. 2C shows a diagram of a third PUF circuit 220 including one or more MEMS structures 222 and active transistor PUF circuitry 224 and fabricated using a third fabrication technique.

[0047] 2C, one or more MEMS structures 222 are fabricated with active-transistor PUF circuitry 224. In some examples, one or more MEMS structures 222 and the active-transistor PUF circuitry 224 may be fabricated on the same die, but then one or more MEMS structures 202 are stacked on top of the active-transistor PUF circuitry 204.

[0048] To connect the one or more MEMS structures 222 to the active transistor PUF circuitry 224, interconnects are used between the one or more MEMS structures 222 and the active transistor PUF circuitry 224. Because the one or more MEMS structures 222 and the active transistor PUF circuitry 224 are fabricated on the same die, the one or more MEMS structures 222 and the active transistor PUF circuitry 224 are closer to each other. Thus, the length of the interconnects between the one or more MEMS structures 222 and the active transistor PUF circuitry 224 is shorter compared to the interconnects used in FIG. 2A. In some implementations of the exemplary PUF circuit 220, the one or more MEMS structures 222 and the active transistor PUF circuitry 224 are located as close as feasible on the same die.

[0049] 3 is a block diagram of a system 300 including secure communication between nodes 301 in an exclusive community over a network 303 using a unique component generated by a PUF circuit 302 in the node 301. Several example protocols for creating a unique component from a PUF circuit 302 are described in more detail herein.

[0050] In the example shown in Figure 3, system 300 is shown with two nodes 301, labeled node 301-A and node 301-B. It should be understood that system 300 may include any suitable number of nodes 301, and thus system 300 is not limited to a system having two nodes 301. Furthermore, Figure 3 shows node 301-A coupled to node 301-B via network 303. It should be understood that network 303 may comprise one or more of wireless access points, communication links, a wide area network (WAN), a local area network (LAN) such as an Ethernet network, cable groups, optical fibers, direct connections, or any other suitable system for communicatively coupling the nodes 301 of system 300.

[0051] 3, node 301-A and node 301-B each include similar components for secure communications in system 300. Thus, for the sake of brevity and simplicity, only node 301-A will be described in detail using reference numbers for each component followed by the designator "-A." It should be understood that similar components are also included in node 301-B, identified by the same reference numbers followed by the designator "-B."

[0052] In the example shown in FIG. 3, node 301-A includes PUF circuit 302-A. In some examples, PUF circuit 302-A may be implemented as PUF circuit 100 or PUF circuit 110, as described above with respect to FIGS. 1A-1B. In some examples, PUF circuit 302-A supports two or more functions for node 301-A by providing one or more outputs. In some examples, the output may include a standard component and a unique component. In some examples, the unique component includes a PUF response output, as described above.

[0053] A first function supported by the PUF circuit 302-A uses a standard component of the output from the PUF circuit 302-A. For example, the PUF circuit 302-A may include a sensor (e.g., a MEMS sensor) and the standard component may be acceleration, rotational speed, pressure, temperature, airflow, or other measurement associated with the sensor.

[0054] A second function supported by the PUF circuit 302-A uses the unique component for secure communication with other nodes 301 of the system 300. In some examples, the PUF circuit 302-A allows for harvesting of the unique component due to process variations during manufacturing that generate unique aspects of the PUF circuit 302-A. In some examples, the unique component output by the PUF circuit 302-A may be derived from active transistor circuitry and / or one or more MEMS structures included in the PUF circuit 302-A.

[0055] In some examples, node 301-A also includes one or more processors and memory for storing software or instructions for implementing functionality for node 301-A. In the example shown in Figure 3, node 301-A includes standard functionality 307-A that supports a first functionality of node 301-A. Standard functionality 307-A, among other things, uses a standard component of the output of PUF circuit 302-A to cause node 301-A to implement its standard functionality that is implemented based on the output of PUF circuit 302-A.

[0056] Node 301-A also includes instructions or software for implementing a second function of node 301-A. In the example shown in FIG. 3, node 301-A includes provenance determination function 308-A, encryption / decryption circuitry 312-A, and verification / validation function 314-A. In some examples, PUF circuitry 302-A is configured to output a PUF response output from the PUF circuitry, and the PUF output is used in conjunction with verification / validation function 314-A to implement authentication that data received or transmitted by node 301-A is from an authorized node in system 300. In some examples, provenance determination function 308-A uses a unique component from PUF circuitry 302-A to implement a PUF for node 301-A, and provenance determination function 308-A is used in conjunction with verification / validation function 314-A to implement authentication that data received or transmitted by node 301-A is from an authorized node in system 300.

[0057] 3, the system 300 also includes a master node 320 that is used to set up trust relationships between the nodes 301 of the system 300 that are in the exclusive community. The master node 320 is communicatively coupled to each of the nodes 301 via the network 303.

[0058] In some examples, each corresponding node 301 generates several registries (e.g., thousands or tens of thousands of registries) using the origination function 308 and a unique component of the output of the PUF circuit 302-A of each node 301. These registries uniquely identify the particular node 301 as part of the trusted system 300. The master node 320 takes the registries generated by each node 301 (e.g., when the node 301 is set up) and provides the registries to all other nodes 301 in the system 300. These registries are stored as part of the origination function 308 of each node 301 in the exclusive community, and effectively become a library of authorized users in the exclusive community of the system 300. By using these registry values, a given node 301 only recognizes data received from similarly equipped nodes 301. When data is received over the network 303, the receiving node 301 uses the registry in the origination function 308 together with the verification / validation function 314 to authenticate that the input originated from an authorized user. For example, the receiving node 301 can verify that the node 301 sending the data generated an output of the origin determination function 308 that corresponds to one of the registries provided by the master node 320 and included in its own origin determination function 308.

[0059] In another example, the master node 320 is configured to act as a certification authority (CA) for applications that use asymmetric cryptography. In such an example, the master node 320 is configured to issue digital certificates to the nodes 301, and the verification / validation function 314 uses the issued digital certificates to authenticate that input originates from an authorized user.

[0060] In the example shown in Figure 3, node 301-A also includes a transceiver 316-A that provides an interface for communicating with other nodes 301, such as node 301-B, over network 303. Although a single transceiver 316-A is shown in Figure 3, it should be understood that the single transceiver 316-A may be replaced with separate and distinct transmitter and receiver components.

[0061] In various aspects, the system elements, method steps, or examples (e.g., systems or components thereof) described throughout this disclosure may be implemented on one or more computer systems, including central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and / or similar devices with hardware to execute code to implement those elements, processes, or examples, which code is stored in non-transitory data storage devices. These devices include or function with software programs, firmware, or other computer readable instructions to perform various method, process tasks, computations, and control functions.

[0062] These instructions are typically stored on any suitable computer-readable medium used for storing computer-readable instructions or data structures. Computer-readable media can be implemented as any available medium that can be accessed by a general purpose or specialized computer or processor, or any programmable logic device. Suitable processor-readable media can include storage or memory media, such as magnetic or optical media. For example, storage or memory media may include volatile or non-volatile media, such as conventional hard disks, Compact Disk-Read Only Memory (CD-ROM), Random Access Memory (RAM) (including, but not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate (DDR) RAM, RAMBUS Dynamic RAM (RDRAM), Static RAM (SRAM), etc.), Read Only Memory (ROM), Electrically Erasable Programmable ROM (EEPROM), and Flash memory. Suitable processor-readable media may also include transmission media, such as electrical, electromagnetic, or digital signals conveyed over a communications medium, such as a network and / or wireless link.

[0063] The methods and techniques described herein may be implemented in digital electronic circuitry, or with a programmable processor (e.g., a special purpose processor or a general purpose processor such as a computer), firmware, software, or combinations thereof. Apparatus embodying these techniques may include suitable input and output devices, a programmable processor, and a storage medium tangibly embodying program instructions for execution by the programmable processor. Processes embodying these techniques may be performed by a programmable processor executing a program of instructions to perform a desired function by operating on input data and generating appropriate output. The techniques may be advantageously implemented in one or more programs executable on a programmable system including at least one programmable processor coupled to receive data and instructions from and transmit data and instructions to a data storage system, at least one input device, and at least one output device. In general, the processor receives instructions and data from a read-only memory and / or a random access memory. Suitable storage devices for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including, for example, semiconductor memory devices (EPROM, EEPROM, and Flash memory devices), magnetic disks (internal hard disk or removable disk), magneto-optical disks, and DVD disks. Any of the foregoing may be supplemented by, or incorporated in, specially designed application-specific integrated circuits (ASICs).

[0064] Exemplary embodiments Example 1 is a physical unclonable function (PUF) circuit, the PUF circuit comprising one or more microelectromechanical system (MEMS) structures configured to provide an output, the output including an active oscillation, a charge, a resistance, an inductance, and / or a capacitance value; and an active transistor PUF circuitry communicatively coupled to the one or more MEMS structures, the active transistor PUF circuitry configured to receive a challenge input and generate a PUF response in response to the challenge input, the PUF response generated based on the output provided by the one or more MEMS structures and manufacturing variations of components of the active transistor PUF circuitry, and the PUF response generated by the active transistor PUF circuitry is an output of the PUF circuit.

[0065] Example 2 includes the PUF circuit of example 1, where one or more MEMS structures and / or active transistor PUF circuit configurations are dedicated to the PUF circuit.

[0066] A third embodiment includes the PUF circuit of any one of the first and second embodiments, and the one or more MEMS structures includes only a single MEMS structure.

[0067] A fourth embodiment includes the PUF circuit of any one of the first to third embodiments, and the one or more MEMS structures includes a plurality of MEMS structures.

[0068] Example 5 includes the PUF circuit of example 4, further comprising a respective signal conditioning circuit coupled between each respective MEMS structure of the plurality of MEMS structures and the active transistor PUF circuitry.

[0069] A sixth embodiment includes the PUF circuit of any of the first to fifth embodiments, wherein the PUF circuit is configured to implement an arbiter PUF topology.

[0070] Example 7 includes the PUF circuit of any of Examples 1-6, wherein the active-transistor PUF circuit configuration includes an array of ring oscillator loops, each of the ring oscillator loops including the same number of inverter components.

[0071] Example 8 includes the PUF circuit of example 7, wherein each respective one of the one or more MEMS structures is communicatively coupled to a respective ring oscillator loop.

[0072] Example 9 includes the PUF circuit of any of Examples 1-8, wherein each MEMS structure of the one or more MEMS structures is configured to receive a bias input.

[0073] Example 10 includes the PUF circuit of example 9, where the bias input comes from an active-transistor PUF circuit configuration.

[0074] Example 11 includes the PUF circuit of Example 10, where the bias input is dynamic and reconfigurable during operation.

[0075] Example 12 includes the PUF circuit of any of Examples 10-11, wherein the bias input resulting from the active transistor PUF circuit configuration is adjusted to reduce the digital oscillations to an appropriate level required for safe input to the one or more MEMS structures.

[0076] Example 13 includes the PUF circuit of any of Examples 9 to 12, wherein a bias input received by at least a first MEMS structure of the one or more MEMS structures is different from a bias input received by another MEMS structure of the one or more MEMS structures.

[0077] Example 14 includes a device including a physical unclonable function (PUF) circuit, the physical unclonable function (PUF) circuit including one or more microelectromechanical systems (MEMS) structures configured to provide active oscillation, charge, resistance, inductance, and / or capacitance values; and an active transistor PUF circuitry communicatively coupled to the one or more MEMS structures, the active transistor PUF circuitry configured to receive a challenge input and output a PUF response in response to the challenge input, the PUF response output by the active transistor PUF circuitry being generated based on the active oscillation, charge, resistance, inductance, and / or capacitance values ​​output by the one or more MEMS structures and manufacturing variations of components of the active transistor PUF circuitry; and one or more additional circuits configured to generate the challenge input and / or utilize the PUF response for one or more cryptographic processes.

[0078] Example 15 includes the device of example 14, wherein the one or more MEMS structures includes a plurality of MEMS structures.

[0079] Example 16 includes the device of any of Examples 14-15, wherein the PUF circuit is configured to implement a ring oscillator PUF topology, and the active transistor PUF circuit configuration includes a plurality of ring oscillators communicatively coupled to the one or more MEMS structures.

[0080] Example 17 includes the device of example 16, in which the PUF circuitry further includes a respective signal conditioning circuit coupled between each respective one of the one or more MEMS structures and the active transistor PUF circuitry.

[0081] Example 18 includes the device of any of examples 14-17, wherein each MEMS structure of the one or more MEMS structures is configured to receive a bias input.

[0082] Example 19 includes a method including receiving a PUF challenge using an active transistor physical unclonable function (PUF) circuit of a PUF circuit, the PUF circuit further including one or more MEMS structures communicatively coupled to the active transistor PUF circuit configuration, and generating a PUF response to the PUF challenge based on active oscillation, charge, resistance, inductance, and / or capacitance values ​​output by the one or more MEMS structures and manufacturing variations of components of the active transistor PUF circuit configuration in response to the PUF challenge, and outputting the PUF response to an additional circuit.

[0083] Example 20 includes the method of example 19, further including using the PUF response for one or more cryptographic processes.

[0084] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that any configuration which is expected to achieve the same purpose may be substituted for the specific embodiments shown. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

Claims

1. A physically unclonable function (PUF) circuit (100, 110), one or more microelectromechanical systems (MEMS) structures (102) configured to provide an output including an active oscillation, a charge, a resistance, an inductance, and / or a capacitance value; active transistor PUF circuitry (104) communicatively coupled to the one or more MEMS structures (102); the active transistor PUF circuitry (104) is configured to receive a challenge input and generate a PUF response in response to the challenge input; the PUF response is generated based on the output provided by the one or more MEMS structures (102) and manufacturing variations of components of the active transistor PUF circuitry (104); The PUF response generated by the active transistor PUF circuitry (104) is an output of the PUF circuit.

2. The PUF circuit (100, 110) of claim 1 , wherein the one or more MEMS structures (102) comprises a plurality of MEMS structures.

3. The PUF circuit (100, 110) of claim 1 or 2, wherein each MEMS structure of the one or more MEMS structures (102) is configured to receive a bias input.

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