Semiconductor device and image reading device

Abstract

To provide a semiconductor device capable of reducing an offset amount of a pixel signal caused by power supply voltage fluctuation.SOLUTION: A semiconductor device includes: a first capacitance element for storing a first pixel signal or a second pixel signal output from a first pixel circuit when a first switch element is in a conduction state; a second capacitance element for storing the first pixel signal transferred from the first capacitance element when a second switch element is in the conduction state; a third capacitance element for storing the second pixel signal transferred from the first capacitance element; a fourth capacitance element for storing a third pixel signal or a fourth pixel signal output from a second pixel circuit; a fifth capacitance element for storing the third pixel signal transferred from the fourth capacitance element; and a sixth capacitance element for storing the fourth pixel signal transferred from the fourth capacitance element, wherein a fourth switch element transits from the conduction state to a non-conduction state after transition of the first switch element from the conduction state to the non-conduction state.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and an image reading device. [Background technology]

[0002] Patent Document 1 describes a photoelectric conversion element having a plurality of pixels arranged in one direction for each color of received light and converting light into an electrical signal, a parallel processing unit which processes in parallel for each pixel group a plurality of electrical signals converted by the pixels in synchronization with a spread spectrum clock, with a predetermined number of pixels being treated as pixel groups, and a correction unit which corrects an offset level for each of the electrical signals processed in parallel by the parallel processing unit based on a value common to each pixel group. The photoelectric conversion element described in Patent Document 1 makes it possible to reduce the occurrence of streaks in a read image caused by the spread spectrum clock while suppressing an increase in circuit size. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-103679 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the photoelectric conversion element described in Patent Document 1, when the signals output from each pixel are simultaneously stored in each memory capacitance by turning on each selection switch at the same time, the power supply voltage fluctuates significantly, and it is therefore not possible to reduce the amount of offset in the pixel signal caused by fluctuations in the power supply voltage. [Means for solving the problem]

[0005] One aspect of the semiconductor device according to the present invention is A first pixel circuit that converts incident light into an electrical signal; A second pixel circuit that converts incident light into an electrical signal; A first storage circuit; A second storage circuit; Equipped with The first memory circuit is a first switch element, a second switch element, a third switch element, a first capacitance element, a second capacitance element, and a third capacitance element; having the first switch element is connected between the first pixel circuit and the first capacitive element; the first capacitance element stores a first pixel signal after reset or a second pixel signal corresponding to the incident light, the first pixel signal being output from the first pixel circuit when the first switch element is in a conductive state; the second switch element is connected between the first capacitance element and the second capacitance element, the second capacitance element stores the first pixel signal transferred from the first capacitance element when the second switch element is in a conductive state; the third switch element is connected between the first capacitance element and the third capacitance element; the third capacitance element stores the second pixel signal transferred from the first capacitance element when the third switch element is in a conductive state; The second memory circuit is a fourth switch element, a fifth switch element, a sixth switch element, a fourth capacitive element, a fifth capacitive element, and a sixth capacitive element; having the fourth switch element is connected between the second pixel circuit and the fourth capacitive element; the fourth capacitance element stores a third pixel signal after reset or a fourth pixel signal corresponding to the incident light, which is output from the second pixel circuit when the fourth switch element is in a conductive state; the fifth switch element is connected between the fourth capacitive element and the fifth capacitive element; the fifth capacitance element stores the third pixel signal transferred from the fourth capacitance element when the fifth switch element is in a conductive state; the sixth switch element is connected between the fourth capacitive element and the sixth capacitive element, the sixth capacitive element stores the fourth pixel signal transferred from the fourth capacitive element when the sixth switch element is in a conductive state; After the first switch element transitions from a conductive state to a non-conductive state, the fourth switch element transitions from a conductive state to a non-conductive state.

[0006] One aspect of the image reading device according to the present invention is One aspect of the semiconductor device; A light source; Equipped with. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is an external perspective view showing a multifunction peripheral according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a perspective view showing the internal structure of the scanner unit. [Diagram 3] FIG. 2 is an exploded perspective view illustrating a schematic configuration of an image sensor module. [Figure 4] FIG. 4 is a plan view illustrating the arrangement of image reading chips. [Diagram 5] FIG. 2 is a diagram showing the functional configuration of a scanner unit. [Figure 6] FIG. 2 is a diagram showing a circuit configuration of an image reading chip according to the embodiment. [Figure 7] FIG. 2 is a diagram showing an example of the configuration of a pixel circuit and a line memory. [Figure 8] FIG. 2 is a diagram showing a configuration example of a first CDS circuit. [Figure 9] FIG. 2 is a diagram showing a configuration example of second to n-th CDS circuits. [Figure 10] FIG. 4 is a timing chart showing an example of the timing of an image reading operation by the image reading chip. [Figure 11] FIG. 11 is a detailed timing chart of the period from time t15 to time t16 in FIG. [Figure 12] 5A and 5B are diagrams showing an example of voltage waveforms of a readout signal, a power supply voltage, and a pixel signal in a comparative example. [Figure 13]4A to 4C are diagrams showing examples of voltage waveforms of a read signal, a power supply voltage, and a pixel signal in the semiconductor device of the embodiment; [Figure 14] FIG. 2 is a diagram showing an example of a circuit layout of an image reading chip. [Figure 15] 15 is an enlarged view of the wiring of the third wiring layer in the area A1 of FIG. 14. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. The drawings are used for the convenience of explanation. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] Hereinafter, a multifunction machine 1 to which an image reading device of the present invention is applied will be described with reference to the attached drawings.

[0010] 1. Structure of the multifunction printer Fig. 1 is an external perspective view showing a multifunction device 1. As shown in Fig. 1, the multifunction device 1 includes a printer unit 2 which is an image recording device, and a scanner unit 3 which is an image reading device. Specifically, the multifunction device 1 integrally includes the printer unit 2 which is the device main body, and the scanner unit 3 which is an upper unit disposed on top of the printer unit 2. In the following description, the front-to-back direction in Fig. 1 is defined as the X-axis direction, and the left-to-right direction is defined as the Y-axis direction.

[0011] 1, the printer unit 2 includes a transport section (not shown) that transports recording media such as print paper and cut sheets along a feed path, a printing section (not shown) that is disposed above the feed path and performs printing processing on the recording media using an inkjet method, a panel-type operation section 63 disposed on the front, an apparatus frame (not shown) that mounts the transport section, printing section, and operation section 63, and an apparatus housing 65 that covers these. The apparatus housing 65 is provided with an outlet 66 through which the recording media is discharged after printing. Although not shown, a USB port and a power port are also disposed on the lower rear surface of the printer unit 2. In other words, the multifunction device 1 is configured to be connectable to a computer or the like via the USB port.

[0012] The scanner unit 3 is rotatably supported by the printer unit 2 via a hinge section 4 at the rear end, and covers the top of the printer unit 2 in a manner that allows it to be opened and closed freely. That is, by lifting the scanner unit 3 in the rotation direction, the top opening of the printer unit 2 is exposed, and the interior of the printer unit 2 is exposed through this top opening. Meanwhile, by pulling the scanner unit 3 down in the rotation direction and placing it on the printer unit 2, the top opening is closed by the scanner unit 3. In this way, by opening the scanner unit 3, it is possible to replace ink cartridges, clear paper jams, and so on.

[0013] FIG. 2 is a perspective view showing the internal structure of the scanner unit 3. As shown in FIG. 1 and FIG. 2, the scanner unit 3 includes an upper frame 11, which is a housing, an image reading unit 12 housed in the upper frame 11, and an upper cover 13 rotatably supported on the upper part of the upper frame 11. As shown in FIG. 2, the upper frame 11 includes a box-shaped lower case 16 that houses the image reading unit 12, and an upper case 17 that covers the top surface of the lower case 16. A glass document placement plate (not shown) is widely arranged in the upper case 17, and a medium to be read is placed on it with the surface to be read facing down. On the other hand, the lower case 16 is formed in a shallow box shape with the top surface open.

[0014] As shown in FIG. 2, the image reading unit 12 includes a line sensor type sensor unit 31, a sensor carriage 32 on which the sensor unit 31 is mounted, a guide shaft 33 extending in the Y-axis direction and supporting the sensor carriage 32 so as to be freely slidable, and a self-propelled sensor movement mechanism 34 for moving the sensor carriage 32 along the guide shaft 33. The sensor unit 31 has an image sensor module 41 which is a CMOS line sensor extending in the X-axis direction, and is reciprocated in the Y-axis direction along the guide shaft 33 by the motor-driven sensor movement mechanism 34. CMOS is an abbreviation for Complementary Metal-Oxide-Semiconductor. This allows the image of the medium to be read on the document placement plate to be read. The sensor unit 31 may be a CCD line sensor. CCD is an abbreviation for Charge Coupled Device.

[0015] FIG. 3 is an exploded perspective view showing a schematic configuration of the image sensor module 41. In the example shown in FIG. 3, the image sensor module 41 includes a case 411, a light source 412, a lens 413, a module board 414, and an image reading chip 415 which is a semiconductor device for reading an image. The light source 412, the lens 413, and the image reading chip 415 are housed between the case 411 and the module board 414. A slit is provided in the case 411. The light source 412 has, for example, R, G, and B light emitting diodes, and the R, G, and B light emitting diodes, i.e., red LED, green LED, and blue LED, are switched at high speed to emit light in sequence. LED is an abbreviation for Light emitting diode. The light emitted by the light source 412 is irradiated to the medium to be read through the slit, and the light from the medium to be read is input to the lens 413 through the slit. The lens 413 guides the input light to the image reading chip 415. The image reading chip 415 reads an image formed on the medium to be read based on the light irradiated from the light source 412 and reflected by the medium to be read.

[0016] Fig. 4 is a plan view showing a schematic arrangement of image reading chips 415. As shown in Fig. 4, a plurality of image reading chips 415 are arranged in one dimension, specifically in the X-axis direction, on module substrate 414. Each image reading chip 415 has a large number of light receiving elements arranged in a row, and the higher the density of the light receiving elements in each image reading chip 415, the higher the resolution of the scanner unit 3 that reads images can be realized. Also, the more image reading chips 415 there are, the more a scanner unit 3 that can read large images can be realized.

[0017] 2. Functional configuration of the scanner unit FIG. 5 is a functional block diagram showing the functional configuration of the scanner unit 3, which is an image reading device. In the example shown in FIG. 5, the scanner unit 3 includes a control unit 300, an analog front end 302, a red LED 412R, a green LED 412G, a blue LED 412B, and a plurality of image reading chips 415. As described above, the red LED 412R, the green LED 412G, and the blue LED 412B are provided in the light source 412, and the plurality of image reading chips 415 are arranged side by side on the module substrate 414. There may be a plurality of each of the red LED 412R, the green LED 412G, and the blue LED 412B. In addition, the control unit 300 and the analog front end 302 are provided on the module substrate 414 or a substrate (not shown) different from the module substrate 414. The control unit 300 and the analog front end 302 may each be realized by an integrated circuit.

[0018] The control unit 300 supplies a drive signal DrvR to the red LED 412R for a fixed exposure time Δt at a predetermined timing, causing the red LED 412R to emit light. Similarly, the control unit 300 supplies a drive signal DrvG to the green LED 412G for the exposure time Δt at a predetermined timing, causing the green LED 412G to emit light, and supplies a drive signal DrvB to the blue LED 412B for the exposure time Δt at a predetermined timing, causing the blue LED 412B to emit light. The control unit 300 causes the red LED 412R, green LED 412G, and blue LED 412B to emit light one by one.

[0019] The control unit 300 also supplies a clock signal CLK and a command signal CMD to the multiple image reading chips 415. The clock signal CLK is an operation clock signal for the image reading chip 415, and the command signal CMD is a signal including various commands such as a command for setting the resolution of image reading by the scanner unit 3 and a command for instructing the start and end of image reading. In the following, it is assumed that the resolution of image reading by the scanner unit 3 is set to any one of 4800 dpi, 2400 dpi, 1200 dpi, 600 dpi, and 300 dpi by the command signal CMD. dpi is an abbreviation for dots per inch.

[0020] Each image reading chip 415 operates in synchronization with a clock signal CLK, and generates and outputs an image signal OS having image information of a set resolution based on the light received by each light receiving element from an image formed on a medium to be read by the light emitted by the red LED 412R, green LED 412G, or blue LED 412B. The detailed circuit configuration and operation of this image reading chip 415 will be described later.

[0021] The analog front end 302 receives multiple image signals OS output by each image reading chip 415, performs amplification and A / D conversion processing on each image signal OS, converts it into a digital signal including a digital value corresponding to the amount of light received by each light receiving element, and transmits each digital signal in sequence to the control unit 300.

[0022] The control unit 300 receives each digital signal transmitted in sequence from the analog front end 302 and generates image information read by the image sensor module 41 .

[0023] 3. Image reading chip configuration FIG. 6 is a diagram showing a circuit configuration of the image reading chip 415. As shown in FIG. 6, the image reading chip 415 includes a logic circuit 101, a scanning circuit 102, N pixel circuits 110, N line memories 120, n CDS circuits 130, a preamplifier 140, an output buffer 150, and a VREFH amplifier 160. In FIG. 6, each pixel circuit 110 is represented as "P", each line memory 120 is represented as "LM", and each CDS circuit 130 is represented as "CDS". CDS is an abbreviation for Correlated Double Sampling. Each of these circuits operates by receiving a power supply voltage VDD and a ground voltage VSS from the external terminals of the image reading chip 415.

[0024] 6, n blocks 103-1 to 103-n all have the same configuration, and each includes m pixel circuits 110, m line memories 120, and one CDS circuit 130. That is, the integer N is m times the integer n, and the integers n and m are each equal to or greater than 1. For example, N may be 3456, n may be 24, and m may be 144.

[0025] The VREFH amplifier 160 is a reference voltage circuit that generates and outputs a reference voltage VREFH, which is a voltage between the power supply voltage VDD and the ground voltage VSS, based on the power supply voltage VDD and the ground voltage VSS. The reference voltage VREFH is supplied to each of the n CDS circuits 130.

[0026] The logic circuit 101 operates in synchronization with a clock signal CLK, and controls the N pixel circuits 110, the N line memories 120, the n CDS circuits 130, the preamplifier 140, the output buffer 150, and the VREFH amplifier 160. Specifically, the logic circuit 101 has a counter (not shown) that counts pulses of the clock signal CLK, and generates various control signals that control the operation of each circuit based on the count value of the counter.

[0027] In this embodiment, the logic circuit 101 generates a power-down signal PD and supplies it to the VREFH amplifier 160. The logic circuit 101 also generates a pixel reset signal PIX_RST and supplies it to each pixel circuit 110. The logic circuit 101 also generates four read signals READ[0] to READ[3], four read signals READN[0] to READN[3], and read signals READS[0] to READS[3]. For example, assuming that the integer N is a multiple of 4 and s is an integer between 1 and N / 4, the three read signals READ[0], READN[0], and READS[0] are supplied to the 4s-th line memories 120. The three read signals READ[1], READN[1], and READS[1] are supplied to the 4s+1-th line memories 120. The three read signals READ[2], READN[2], and READS[2] are supplied to the 4s+2-th line memories 120. The three read signals READ[3], READN[3], and READS[3] are supplied to the 4s+3-th line memories 120, respectively.

[0028] The logic circuit 101 also generates a standby signal PD_STBY, a CDS reset signal CDS_RST, and a dummy end signal DUMMY_END, and supplies them to each CDS circuit 130. The logic circuit 101 also generates n-1 start signals ST_BLK[0] to ST_BLK[n-1] that are mutually exclusively at high level. The start signal ST_BLK[0] is commonly supplied to the n CDS circuits 130, and the start signals ST_BLK[i-2] and ST_BLK[i-1] are supplied to the i-th CDS circuit 130 among the second to n-th CDS circuits 130. The logic circuit 101 also generates various control signals that control the operations of the scanning circuit 102, the preamplifier 140, and the output buffer 150.

[0029] The scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1] based on a control signal from the logic circuit 101. When the resolution is set to 4800 dpi, the scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1] that go high one by one in sequence. When the resolution is set to 2400 dpi, the scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1] that go high two by two in sequence at the same time. When the resolution is set to 1200 dpi, the scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1] that go high four by four in sequence at the same time. When the resolution is set to 600 dpi, the scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1] that go high eight by eight in sequence at the same time. When the resolution is set to 300 dpi, the scanning circuit 102 outputs N selection signals SEL[0] to SEL[N-1], each of which is set to high level in sequence, 16 at a time. The N selection signals SEL[0] to SEL[N-1] are supplied to N line memories 120, respectively.

[0030] Light emitted from the light source 412 and reflected by the medium to be read is incident on the N pixel circuits 110. Then, each of the N pixel circuits 110 converts the incident light into a pixel signal, which is an electrical signal. Specifically, each pixel circuit 110 outputs a pixel signal having a voltage corresponding to the light received from the medium to be read during the exposure time Δt by emitting light from the red LED 412R, green LED 412G, or blue LED 412B. The pixel signal is reset to a predetermined voltage when the pixel reset signal PIX_RST is at a high level. In other words, the pixel reset signal PIX_RST is a reset signal that initializes the N pixel circuits 110.

[0031] Each of the N line memories 120 is a storage circuit that stores pixel signals output from the N pixel circuits 110 at a predetermined timing. For each integer between 1 and N / 4, each 4s-th line memory 120 acquires a reference pixel signal, which is a pixel signal output from each 4s-th pixel circuit 110, during a period when the read signal READ[0] is at a high level, and stores the acquired reference pixel signal during a period when the read signal READN[0] is at a high level. Then, each 4s-th line memory 120 acquires a detection pixel signal, which is a pixel signal output from each 4s-th pixel circuit 110, during the next period when the read signal READ[0] is at a high level, and stores the acquired detection pixel signal during a period when the read signal READS[0] is at a high level.

[0032] Each 4s+1th line memory 120 acquires a reference pixel signal which is a pixel signal output from each 4s+1th pixel circuit 110 during a period when the read signal READ[1] is at a high level, and stores the acquired reference pixel signal during a period when the read signal READN[1] is at a high level. Then, each 4s+1th line memory 120 acquires a detection pixel signal which is a pixel signal output from each 4s+1th pixel circuit 110 during the next period when the read signal READ[1] is at a high level, and stores the acquired detection pixel signal during a period when the read signal READS[1] is at a high level.

[0033] Each 4s+2th line memory 120 acquires a reference pixel signal which is a pixel signal output from each 4s+2th pixel circuit 110 during a period when the read signal READ[2] is at a high level, and stores the acquired reference pixel signal during a period when the read signal READN[2] is at a high level. Then, each 4s+2th line memory 120 acquires a detection pixel signal which is a pixel signal output from each 4s+2th pixel circuit 110 during the next period when the read signal READ[2] is at a high level, and stores the acquired detection pixel signal during a period when the read signal READS[2] is at a high level.

[0034] Each 4s+3th line memory 120 acquires a reference pixel signal which is a pixel signal output from each 4s+3th pixel circuit 110 during a period when the read signal READ[3] is at a high level, and stores the acquired reference pixel signal during a period when the read signal READN[3] is at a high level. Then, each 4s+3th line memory 120 acquires a detection pixel signal which is a pixel signal output from each 4s+3th pixel circuit 110 during the next period when the read signal READ[3] is at a high level, and stores the acquired detection pixel signal during a period when the read signal READS[3] is at a high level.

[0035] When the selection signal SEL[j-1] is at a high level, the j-th line memory 120 outputs the two stored pixel signals, where j is an integer between 1 and N.

[0036] In this embodiment, when the resolution is set to 4800 dpi, the N selection signals SEL[0] to SEL[N-1] are sequentially set to high level one by one, so that the reference pixel signals and the detection pixel signals are sequentially output one by one from the N line memories 120. When the resolution is set to 2400 dpi, the N selection signals SEL[0] to SEL[N-1] are sequentially set to high level two by two at the same time, so that the reference pixel signals and the detection pixel signals are sequentially output two by two from the N line memories 120. When the resolution is set to 1200 dpi, the N selection signals SEL[0] to SEL[N-1] are sequentially set to high level four by four at the same time, so that the reference pixel signals and the detection pixel signals are sequentially output four by four from the N line memories 120. Furthermore, when the resolution is set to 600 dpi, eight of the N selection signals SEL[0] to SEL[N-1] go high in sequence at the same time, so that eight reference pixel signals and eight detection pixel signals are output in sequence from the N line memories 120. When the resolution is set to 300 dpi, sixteen of the N selection signals SEL[0] to SEL[N-1] go high in sequence at the same time, so that sixteen reference pixel signals and sixteen detection pixel signals are output in sequence from the N line memories 120.

[0037] Each of the n CDS circuits 130 is a differential amplifier circuit that receives a first signal and a second signal, and outputs a third signal obtained by differentially amplifying the first signal and the second signal. In this embodiment, when the resolution is set to 4800 dpi, the i-th CDS circuit 130 receives the reference pixel signal and the detection pixel signal output from the m line memories 120, which are (i-1)×m+1th to i×mth, in order, one by one. i is an integer between 1 and n. For example, N may be 3456, n may be 24, and m may be 144. That is, the i-th CDS circuit 130 receives the reference pixel signal and the detection pixel signal stored in each line memory 120 as the first signal and the second signal, respectively, and outputs the pixel signal CDSO[i-1] obtained by differentially amplifying the reference pixel signal and the detection pixel signal as the third signal.

[0038] When the resolution is set to 2400 dpi, the reference pixel signal and the detection pixel signal outputted in sequence from the (i-1)×m+1th to i×mth m line memories 120 are simultaneously inputted to the i-th CDS circuit 130. Therefore, the i-th CDS circuit 130 outputs, as the third signal, a pixel signal CDSO[i-1] obtained by differentially amplifying a first signal obtained by voltage-adding two reference pixel signals and a second signal obtained by voltage-adding two detection pixel signals. When the resolution is set to 1200 dpi, the reference pixel signal and the detection pixel signal outputted in sequence from the (i-1)×m+1th to i×mth m line memories 120 are simultaneously inputted to the i-th CDS circuit 130. Therefore, the i-th CDS circuit 130 outputs, as a third signal, a pixel signal CDSO[i-1] obtained by differentially amplifying a first signal obtained by voltage-adding four reference pixel signals and a second signal obtained by voltage-adding four detection pixel signals. When the resolution is set to 600 dpi, the i-th CDS circuit 130 simultaneously receives reference pixel signals and detection pixel signals output in sequence, eight at a time, from m line memories 120, the (i-1)×m+1th to the i×mth. Therefore, the i-th CDS circuit 130 outputs, as a third signal, a pixel signal CDSO[i-1] obtained by differentially amplifying a first signal obtained by voltage-adding eight reference pixel signals and a second signal obtained by voltage-adding eight detection pixel signals. Furthermore, when the resolution is set to 300 dpi, reference pixel signals and detection pixel signals output in sequence, 16 at a time, from the (i-1)×m+1th to i×mth m line memories 120 are simultaneously input to the i-th CDS circuit 130. Therefore, the i-th CDS circuit 130 outputs, as a third signal, a pixel signal CDSO[i-1] obtained by differentially amplifying a first signal obtained by voltage-adding 16 reference pixel signals and a second signal obtained by voltage-adding 16 detection pixel signals.

[0039] In this embodiment, each line memory 120 acquires a pixel signal during a predetermined period after the pixel reset signal PIX_RST changes from high level to low level and stores it as a reference pixel signal, and acquires a pixel signal during a predetermined period after the end of exposure and stores it as a detection pixel signal. Therefore, the voltage difference between the detection pixel signal and the reference pixel signal corresponds to a voltage corresponding to the light received by each pixel circuit 110 from the medium to be read during the exposure time Δt. Therefore, the i-th CDS circuit 130 removes noise contained in the detection pixel signal output from each pixel circuit 110 by correlated double sampling, and outputs a pixel signal CDSO[i-1] having a voltage corresponding to the light received by each pixel circuit 110.

[0040] The n CDS circuits 130 operate in sequence one by one to output pixel signals CDSO[0] to CDSO[n-1] in a mutually exclusive manner.

[0041] As shown in FIG. 6, a line memory block 170 is formed of N line memories 120, and a CDS circuit block 172 is formed of n CDS circuits 130.

[0042] The pixel signals CDSO[0] to CDSO[n-1] are input in order as a pixel signal CDSO to a preamplifier 140. The preamplifier 140 outputs a signal obtained by amplifying the pixel signal CDSO. The signal output from the preamplifier 140 is input to an output buffer 150 as an image signal PAO corresponding to an image read by the N pixel circuits 110.

[0043] The output buffer 150 buffers the image signal PAO and outputs the image signal OS. The image signal OS is output from an external terminal of the image reading chip 415 and is supplied to the analog front end 302 shown in FIG.

[0044] 4. Pixel circuit and line memory configuration The N pixel circuits 110 shown in Fig. 6 all have the same configuration. Similarly, the N line memories 120 all have the same configuration. Fig. 7 is a diagram showing an example of the configuration of the pixel circuit 110 and the line memory 120. As shown in Fig. 7, the pixel circuit 110 includes a light receiving element 111, an inverting amplifier 112, a capacitance element 113, and a switch element 114.

[0045] The light receiving element 111 converts the incident light into an electric signal, that is, performs photoelectric conversion. Specifically, the light receiving element 111 receives light that is irradiated from the light source 412 and reflected by the medium to be read, and converts it into an electric signal. In this embodiment, the light receiving element 111 is configured with a photodiode, and the anode is grounded and the cathode is connected to the input terminal of the inverting amplifier 112.

[0046] The inverting amplifier 112 is electrically connected to the light receiving element 111 and amplifies an electrical signal generated by photoelectric conversion by the light receiving element 111. Specifically, the input terminal of the inverting amplifier 112 is connected to the cathode of the light receiving element 111, and the inverting amplifier 112 outputs a voltage obtained by inverting and amplifying the voltage at the input terminal from the output terminal.

[0047] The capacitive element 113 is electrically connected to both ends of the inverting amplifier 112 in parallel with the inverting amplifier 112. That is, both ends of the capacitive element 113 are connected to the input terminal and the output terminal of the inverting amplifier 112, respectively, and function as a feedback capacitance provided in the signal feedback path from the output terminal to the input terminal of the inverting amplifier 112.

[0048] The switch element 114 is electrically connected to both ends of the inverting amplifier 112 in parallel with the inverting amplifier 112. That is, both ends of the switch element 114 are connected to the input terminal and the output terminal of the inverting amplifier 112, respectively. A pixel reset signal PIX_RST is input to a control terminal of the switch element 114, and when the pixel reset signal PIX_RST is at a high level, both ends of the switch element 114 are conductive, and when the pixel reset signal PIX_RST is at a low level, both ends of the switch element 114 are non-conductive. When the pixel reset signal PIX_RST is at a high level, both ends of the switch element 114 are conductive, and therefore, both ends of the capacitance element 113 are short-circuited and the accumulated charge is reset.

[0049] The signal output from the output terminal of the inverting amplifier 112 is input to the line memory 120 as a pixel signal PIXO.

[0050] The voltage V of the reference pixel signal, which is the pixel signal PIXO immediately after being reset by the pixel reset signal PIX_RST. PIXO1 is expressed as in equation (1). In addition, the voltage V of the detection pixel signal, which is the pixel signal PIXO after exposure, is expressed as PIXO2 is expressed as formula (2). In formulas (1) and (2), V rst is the voltage of the pixel signal PIXO immediately after the charge of the capacitance element 113 is reset. pd is the current flowing through the light receiving element 111 due to exposure, Δt is the exposure time, and C d is the capacitance value of the capacitive element 113.

[0051]

number

[0052]

number

[0053] As is clear from equation (2), the sensitivity of the pixel circuit 110, that is, the current I PDVoltage V PIXO2 The change in the capacitance value C of the capacitance element 113 d Therefore, in order to increase the sensitivity of the pixel circuit 110, and in turn the sensitivity of the image reading chip 415 and the scanner unit 3, the capacitance value C d It is preferable that is small.

[0054] The line memory 120 includes a switch element 121, a capacitance element 122, an NMOS transistor 123, a constant current source 124, a switch element 125, a switch element 126, a capacitance element 127, a capacitance element 128, a switch element 129p, and a switch element 129n. The switch element 121, the switch element 125, the switch element 126, the switch element 129p, and the switch element 129n are each a MOS transistor, for example, an NMOS transistor.

[0055] One end of the switch element 121 is connected to the output terminal of the inverting amplifier 112 and the other end of the capacitive element 113, and the other end is connected to one end of the capacitive element 122. That is, the switch element 121 is connected between the pixel circuit 110 and the capacitive element 122. A read signal READ[k] is input to a control terminal of the switch element 121. k is an integer between 0 and 3. That is, the read signal READ[k] is a control signal for the switch element 121. When the read signal READ[k] is at a high level, both ends of the switch element 121 are conductive, and when the read signal READ[k] is at a low level, both ends of the switch element 121 are non-conductive.

[0056] One end of the capacitance element 122 is connected to the other end of the switch element 121, and the other end is grounded. When the read signal READ[k] is at a high level, both ends of the switch element 121 are conductive, and a charge corresponding to the difference between the voltage of the pixel signal PIXO output from the pixel circuit 110 and the ground voltage VSS is accumulated in the capacitance element 122. That is, when the read signal READ[k] is at a high level, the capacitance element 122 temporarily stores the pixel signal PIXO output from the pixel circuit 110. Here, in this embodiment, the read signal READ[k] becomes a high level during a predetermined period after the pixel reset signal PIX_RST changes from a high level to a low level, and the pixel signal PIXO during the period when this read signal READ[k] is at a high level is temporarily stored in the capacitance element 122 as a reference pixel signal. In addition, the read signal READ[k] goes high for a predetermined period after the exposure is completed, and the pixel signal PIXO during the period in which the read signal READ[k] is high is temporarily stored in the capacitive element 122 as a detected pixel signal.

[0057] The voltage V of the capacitance element 122 in which the reference pixel signal PIXO, which is the pixel signal PIXO immediately after reset by the pixel reset signal PIX_RST, is stored mem1 The voltage V of the capacitance element 122 in which the detected pixel signal PIXO after exposure is stored is expressed as in equation (3). mem2 is expressed as equation (4).

[0058]

number

[0059]

number

[0060] In this way, when the switch element 121 is in a conductive state, the capacitive element 122 stores a reference pixel signal, which is the pixel signal PIXO after reset, output from the pixel circuit 110, or a detection pixel signal, which is the pixel signal PIXO corresponding to the light incident on the pixel circuit 110.

[0061] The gate of the NMOS transistor 123 is connected to the other end of the switch element 121 and one end of the capacitance element 122. A power supply voltage VDD is supplied to the drain of the NMOS transistor 123. The source of the NMOS transistor 123 is connected to one end of a constant current source 124, one end of a switch element 125, and one end of a switch element 126. The other end of the constant current source 124 is grounded. The constant current source 124 generates a constant current. The NMOS transistor 123 and the constant current source 124 form a source follower circuit, and the source of the NMOS transistor 123 becomes a voltage corresponding to the voltage of the gate of the NMOS transistor 123, i.e., a voltage corresponding to the charge stored in the capacitance element 122.

[0062] The switch element 121, the capacitance element 122, the NMOS transistor 123, and the constant current source 124 constitute a primary memory 120a.

[0063] One end of the switch element 125 is connected to the source of the NMOS transistor 123, one end of the constant current source 124, and one end of the switch element 126, and the other end is connected to one end of the capacitive element 127. A read signal READN[k] is input to a control terminal of the switch element 125, and when the read signal READN[k] is at a high level, both ends of the switch element 125 are conductive, and when the read signal READN[k] is at a low level, both ends of the switch element 125 are non-conductive.

[0064] One end of the capacitance element 127 is connected to the other end of the switch element 125, and the other end is grounded. When the read signal READN[k] is at a high level, both ends of the switch element 125 are conductive, and a charge corresponding to the difference between the voltage of the source of the NMOS transistor 123 and the ground voltage VSS is stored in the capacitance element 127. Since the source of the NMOS transistor 123 has a voltage corresponding to the charge stored in the capacitance element 122, when the read signal READN[k] is at a high level, a charge corresponding to the charge stored in the capacitance element 122 is stored in the capacitance element 127. Here, in this embodiment, when the pixel signal PIXO as the reference pixel signal is temporarily stored in the capacitance element 122, the read signal READN[k] becomes a high level, and the pixel signal PIXO as the reference pixel signal is stored in the capacitance element 127.

[0065] In this manner, the switch element 125 is connected between the capacitive element 122 and the capacitive element 127, and the capacitive element 127 stores the pixel signal PIXO as a reference pixel signal transferred from the capacitive element 122 when the switch element 125 is in a conductive state.

[0066] One end of the switch element 126 is connected to the source of the NMOS transistor 123, one end of the constant current source 124, and one end of the switch element 125, and the other end is connected to one end of the capacitive element 128. A read signal READS[k] is input to a control terminal of the switch element 126, and when the read signal READS[k] is at a high level, both ends of the switch element 126 are conductive, and when the read signal READS[k] is at a low level, both ends of the switch element 126 are non-conductive.

[0067] One end of the capacitance element 128 is connected to the other end of the switch element 126, and the other end is grounded. When the read signal READS[k] is at a high level, both ends of the switch element 126 are conductive, and a charge corresponding to the difference between the voltage of the source of the NMOS transistor 123 and the ground voltage VSS is stored in the capacitance element 128. Since the source of the NMOS transistor 123 has a voltage corresponding to the charge stored in the capacitance element 122, when the read signal READS[k] is at a high level, a charge corresponding to the charge stored in the capacitance element 122 is stored in the capacitance element 128. Here, in this embodiment, when the pixel signal PIXO as the detection pixel signal is temporarily stored in the capacitance element 122, the read signal READS[k] becomes a high level, and the pixel signal PIXO as the detection pixel signal is stored in the capacitance element 128.

[0068] In this manner, the switch element 126 is connected between the capacitive element 122 and the capacitive element 128, and the capacitive element 128 stores the pixel signal PIXO as the detected pixel signal transferred from the capacitive element 122 when the switch element 126 is in a conductive state.

[0069] One end of the switch element 129p is connected to the other end of the switch element 125 and one end of the capacitance element 127. A selection signal SEL[j-1] is input to a control terminal of the switch element 129p, and when the selection signal SEL[j-1] is at a high level, both ends of the switch element 129p are conductive, and when the selection signal SEL[j-1] is at a low level, both ends of the switch element 129p are non-conductive. When the selection signal SEL[j-1] is at a high level, both ends of the switch element 129p are conductive, and the voltage of the other end of the switch element 129p is equal to the voltage of one end of the capacitance element 127. That is, when the selection signal SEL[j-1] is at a high level, the reference pixel signal stored in the capacitance element 127 is output from the other end of the switch element 129p.

[0070] One end of the switch element 129n is connected to the other end of the switch element 126 and one end of the capacitance element 128. A selection signal SEL[j-1] is input to a control terminal of the switch element 129n, and when the selection signal SEL[j-1] is at a high level, both ends of the switch element 129n are conductive, and when the selection signal SEL[j-1] is at a low level, both ends of the switch element 129n are non-conductive. When the selection signal SEL[j-1] is at a high level, both ends of the switch element 129n are conductive, and the voltage of the other end of the switch element 129n is equal to the voltage of one end of the capacitance element 128. That is, when the selection signal SEL[j-1] is at a high level, the detection pixel signal stored in the capacitance element 128 is output from the other end of the switch element 129n.

[0071] The voltage V of the capacitance element 127 in which the reference pixel signal PIXO immediately after resetting by the pixel reset signal PIX_RST is stored N is expressed by equation (5). Also, the voltage V of the capacitance element 128 in which the detected pixel signal PIXO after exposure is stored is expressed by equation (5). S In equations (5) and (6), V t is the threshold voltage of the NMOS transistor 123.

[0072]

number

[0073]

number

[0074] The switch element 125, the switch element 126, the capacitive element 127, the capacitive element 128, the switch element 129p, and the switch element 129n constitute the secondary memory 120b.

[0075] 5. CDS circuit configuration Of the n CDS circuits 130 shown in Fig. 6, the second to n-th CDS circuits 130 all have the same configuration, and the first CDS circuit 130 has a configuration that is partially different from the second to n-th CDS circuits 130. Fig. 8 is a diagram showing an example of the configuration of the first CDS circuit 130 shown in Fig. 6. Also, Fig. 9 is a diagram showing an example of the configuration of the second to n-th CDS circuits 130 shown in Fig. 6.

[0076] As shown in FIGS. 8 and 9, the CDS circuit 130 includes a capacitance element 131p, a capacitance element 131n, a switch element 132p, a switch element 132n, an operational amplifier 133, an NMOS transistor 134, a constant current source 135, a switch element 136, a switch element 137, and a logic circuit 138.

[0077] One end of the capacitance element 131p is connected to the non-inverting input terminal of the operational amplifier 133 and one end of the switch element 132p, and the other end is connected to the other end of the switch element 132p and one end of the switch element 136. The other end of the switch element 136 is connected to a reference voltage node N VREFH The reference voltage node N VREFH is a node at which the VREFH amplifier 160 outputs the reference voltage VREFH, and the other end of the switch element 136 is supplied with the reference voltage VREFH.

[0078] Both ends of the capacitance element 131n are connected to the inverting input terminal and the output terminal, respectively, of the operational amplifier 133. That is, the capacitance element 131n functions as a feedback capacitance provided in the signal feedback path from the output terminal to the inverting input terminal of the operational amplifier 133.

[0079] Both ends of the switch element 132n are connected to the inverting input terminal and the output terminal of the operational amplifier 133, respectively. A CDS reset signal CDS_RST is input to the control terminal of the switch element 132p and the control terminal of the switch element 132n. When the CDS reset signal CDS_RST is at a high level, both ends of the switch elements 132p and 132n are conductive, and when the CDS reset signal CDS_RST is at a low level, both ends of the switch elements 132p and 132n are non-conductive. When the CDS reset signal CDS_RST is at a high level, both ends of the switch elements 132p and 132n are conductive, so that both ends of the capacitance elements 131p and 131n are shorted and the accumulated charges are reset.

[0080] A non-inverting input terminal of the operational amplifier 133 is electrically connected to one end of each of the m capacitance elements 127 when each of the m switch elements 129p is conductive. Also, an inverting input terminal of the operational amplifier 133 is electrically connected to one end of each of the m capacitance elements 128 when each of the m switch elements 129n is conductive.

[0081] When the resolution is set to 4800 dpi, in the i-th block 103-i, the m selection signals SEL[(i-1)×m] to SEL[i×m-1] become high level one by one in sequence, so that the m switch elements 129p become conductive one by one in sequence and one end of the m capacitance elements 127 are electrically connected one by one in sequence to the non-inverting input terminal of the operational amplifier 133, and the m switch elements 129n become conductive one by one in sequence and one end of the m capacitance elements 128 are electrically connected one by one in sequence to the inverting input terminal of the operational amplifier 133. Therefore, the reference pixel signals stored in the m capacitive elements 127 are input one by one in sequence to the non-inverting input terminal of the operational amplifier 133 as non-inverting input signals CDS_INP[i-1], and the detection pixel signals stored in the m capacitive elements 128 are input one by one in sequence to the inverting input terminal of the operational amplifier 133 as inverting input signals CDS_INN[i-1].

[0082] Furthermore, when the resolution is set to 2400 dpi, the m selection signals SEL[(i-1)×m] to SEL[i×m-1] become high level in sequence, two by two, so that the m switch elements 129p become conductive in sequence, two by two, and one end of the m capacitance elements 127 are electrically connected to the non-inverting input terminal of the operational amplifier 133 in sequence, and the m switch elements 129n become conductive in sequence, two by two, and one end of the m capacitance elements 128 are electrically connected to the inverting input terminal of the operational amplifier 133 in sequence. Therefore, a pixel signal obtained by voltage-adding two by two of the reference pixel signals stored in the m capacitive elements 127 in sequence is input to the non-inverting input terminal of the operational amplifier 133 as a non-inverting input signal CDS_INP[i-1], and a pixel signal obtained by voltage-adding two by two of the detection pixel signals stored in the m capacitive elements 128 in sequence is input to the inverting input terminal of the operational amplifier 133 as an inverting input signal CDS_INN[i-1].

[0083] Furthermore, when the resolution is set to 1200 dpi, the m selection signals SEL[(i-1)×m] to SEL[i×m-1] become high level in sequence, four by four, so that the m switch elements 129p become conductive in sequence, and one end of the m capacitance elements 127 is electrically connected to the non-inverting input terminal of the operational amplifier 133 in sequence, four by four, and the m switch elements 129n become conductive in sequence, and one end of the m capacitance elements 128 is electrically connected to the inverting input terminal of the operational amplifier 133 in sequence, four by four. Therefore, a pixel signal obtained by sequentially adding four reference pixel signals stored in the m capacitive elements 127 with voltages, is input to the non-inverting input terminal of the operational amplifier 133 as a non-inverting input signal CDS_INP[i-1], and a pixel signal obtained by sequentially adding four detection pixel signals stored in the m capacitive elements 128 with voltages, is input to the inverting input terminal of the operational amplifier 133 as an inverting input signal CDS_INN[i-1].

[0084] Furthermore, when the resolution is set to 600 dpi, the m selection signals SEL[(i-1)×m] to SEL[i×m-1] become high level in sequence, eight by eight, so that the m switch elements 129p become conductive in sequence, and one end of the m capacitance elements 127 is electrically connected to the non-inverting input terminal of the operational amplifier 133 in sequence, eight by eight, and the m switch elements 129n become conductive in sequence, and one end of the m capacitance elements 128 is electrically connected to the inverting input terminal of the operational amplifier 133 in sequence, eight by eight. Therefore, a pixel signal obtained by sequentially adding eight reference pixel signals stored in the m capacitive elements 127 with voltages, is input to the non-inverting input terminal of the operational amplifier 133 as a non-inverting input signal CDS_INP[i-1], and a pixel signal obtained by sequentially adding eight detection pixel signals stored in the m capacitive elements 128 with voltages, is input to the inverting input terminal of the operational amplifier 133 as an inverting input signal CDS_INN[i-1].

[0085] Furthermore, when the resolution is set to 300 dpi, the m selection signals SEL[(i-1)×m] to SEL[i×m-1] become high level in sequence, 16 at a time, so that the m switch elements 129p become conductive in sequence, 16 at a time, and the m capacitance elements 127 are electrically connected at one end to the non-inverting input terminal of the operational amplifier 133 in sequence, 16 at a time, and the m switch elements 129n become conductive in sequence, 16 at a time, and the m capacitance elements 128 are electrically connected at one end to the inverting input terminal of the operational amplifier 133 in sequence. Therefore, a pixel signal obtained by sequentially adding voltages to 16 reference pixel signals stored in the m capacitive elements 127 is input to the non-inverting input terminal of the operational amplifier 133 as a non-inverting input signal CDS_INP[i-1], and a pixel signal obtained by sequentially adding voltages to 16 detection pixel signals stored in the m capacitive elements 128 is input to the inverting input terminal of the operational amplifier 133 as an inverting input signal CDS_INN[i-1].

[0086] A standby signal PD_STBY is input to the standby terminal of the operational amplifier 133, and when the standby signal PD_STBY is at a high level, the inverting input terminal and the non-inverting input terminal of the operational amplifier 133 are pulled up to the power supply voltage VDD.

[0087] The gate of the NMOS transistor 134 is connected to the output terminal of the operational amplifier 133. A power supply voltage VDD is supplied to the drain of the NMOS transistor 134. The source of the NMOS transistor 134 is connected to one end of a constant current source 135 and one end of a switch element 137. The other end of the constant current source 135 is grounded. The constant current source 135 generates a constant current. The NMOS transistor 134 and the constant current source 135 form a source follower circuit, and the source of the NMOS transistor 134 becomes a voltage corresponding to the voltage of the gate of the NMOS transistor 134, i.e., a voltage corresponding to the voltage of the output terminal of the operational amplifier 133.

[0088] 8, in the first block 103-1, the logic circuit 138 included in the CDS circuit 130 generates a CDS enable signal CDS_EN[0] and a VREF switch control signal VREFSW[0] based on the standby signal PD_STBY, the start signal ST_BLK[0], and the dummy end signal DUMMY_END. Specifically, when the standby signal PD_STBY is at a high level, the logic circuit 138 generates a low-level CDS enable signal CDS_EN[0] and a high-level VREF switch control signal VREFSW[0]. In addition, when the standby signal PD_STBY changes from a high level to a low level, the logic circuit 138 changes the CDS enable signal CDS_EN[0] from a low level to a high level. In addition, when the standby signal PD_STBY is at a low level, the logic circuit 138 starts counting the number of pulses of the clock signal CLK when the start signal ST_BLK[0] changes from a low level to a high level, and when the count value reaches a predetermined value, changes the CDS enable signal CDS_EN[0] from a high level to a low level and changes the VREF switch control signal VREFSW[0] from a high level to a low level. The timing at which both the CDS enable signal CDS_EN[0] and the VREF switch control signal VREFSW[0] change from a high level to a low level coincides with the timing at which the start signal ST_BLK[1] changes from a low level to a high level. In addition, when the dummy end signal DUMMY_END changes from a low level to a high level, the logic circuit 138 changes the VREF switch control signal VREFSW[0] from a low level to a high level.

[0089] The CDS enable signal CDS_EN[0] is input to the enable terminal of the operational amplifier 133 and the control terminal of the switch element 137. The operational amplifier 133 operates when the CDS enable signal CDS_EN[0] is at a high level, and stops operating when the CDS enable signal CDS_EN[0] is at a low level. In addition, when the CDS enable signal CDS_EN[0] is at a high level, both ends of the switch element 137 are conductive, and when the CDS enable signal CDS_EN[0] is at a low level, both ends of the switch element 137 are non-conductive. When the CDS enable signal CDS_EN[0] is at a high level, both ends of the switch element 137 are conductive, and the voltage of the other end of the switch element 137 is equal to the voltage of the source of the NMOS transistor 134. That is, when the CDS enable signal CDS_EN[0] is at a high level, the pixel signal CDSO[0] having a voltage corresponding to the voltage of the output terminal of the operational amplifier 133 is output from the other end of the switch element 137.

[0090] The VREF switch control signal VREFSW[0] is input to a control terminal of the switch element 136. When the VREF switch control signal VREFSW[0] is at a high level, both ends of the switch element 136 are conductive, and when the VREF switch control signal VREFSW[0] is at a low level, both ends of the switch element 136 are non-conductive. When the VREF switch control signal VREFSW[0] is at a high level, both ends of the switch element 136 are conductive, and the voltage at the other end of the capacitance element 131p becomes equal to the reference voltage VREFH.

[0091] 9, in the i-th block 103-i of the 2nd to n-th blocks 103-2 to 103-n, the logic circuit 138 included in the CDS circuit 130 generates a CDS enable signal CDS_EN[i-1], a VREF switch control signal VREFSW[i-1], and an output enable signal OUT_EN[i-1] based on the standby signal PD_STBY, the start signal ST_BLK[0], the start signal ST_BLK[i-2], the start signal ST_BLK[i-1], and the dummy end signal DUMMY_END. Specifically, when the standby signal PD_STBY is at a high level, the logic circuit 138 generates a low-level CDS enable signal CDS_EN[i-1] and a high-level VREF switch control signal VREFSW[i-1]. In addition, when the start signal ST_BLK[0] changes from a low level to a high level, the logic circuit 138 changes the VREF switch control signal VREFSW[i-1] from a high level to a low level. Furthermore, when the standby signal PD_STBY is at a low level, the logic circuit 138 starts counting the number of pulses of the clock signal CLK when the start signal ST_BLK[i-2] changes from a low level to a high level, and when the count value reaches a predetermined value, changes the CDS enable signal CDS_EN[i-1] from a low level to a high level. The timing at which the CDS enable signal CDS_EN[i-1] changes from a low level to a high level is a predetermined time before the timing at which the start signal ST_BLK[i-1] changes from a low level to a high level. Furthermore, when the start signal ST_BLK[i-1] changes from a low level to a high level, the logic circuit 138 changes the VREF switch control signal VREFSW[i-1] from a low level to a high level and starts counting the number of pulses of the clock signal CLK. Then, when the count value reaches a predetermined value, the logic circuit 138 changes the CDS enable signal CDS_EN[i-1] from high level to low level, and changes the VREF switch control signal VREFSW[i-1] from high level to low level.The timing at which both the CDS enable signal CDS_EN[i-1] and the VREF switch control signal VREFSW[i-1] change from high level to low level coincides with the timing at which the start signal ST_BLK[i] changes from low level to high level. When the dummy end signal DUMMY_END changes from low level to high level, the logic circuit 138 changes the VREF switch control signal VREFSW[i-1] from low level to high level. The logic circuit 138 also generates a logical AND signal of the CDS enable signal CDS_EN[i-1] and the VREF switch control signal VREFSW[i-1] as the output enable signal OUT_EN[i-1]. In other words, when the CDS enable signal CDS_EN[i-1] and the VREF switch control signal VREFSW[i-1] are both at high level, the output enable signal OUT_EN[i-1] is at high level, and when at least one of the CDS enable signal CDS_EN[i-1] and the VREF switch control signal VREFSW[i-1] is at low level, the output enable signal OUT_EN[i-1] is at low level.

[0092] The CDS enable signal CDS_EN[i-1] is input to an enable terminal of the operational amplifier 133. The operational amplifier 133 operates when the CDS enable signal CDS_EN[i-1] is at a high level, and stops operating when the CDS enable signal CDS_EN[i-1] is at a low level.

[0093] The VREF switch control signal VREFSW[i-1] is input to a control terminal of the switch element 136. When the VREF switch control signal VREFSW[i-1] is at a high level, both ends of the switch element 136 are conductive, and when the VREF switch control signal VREFSW[i-1] is at a low level, both ends of the switch element 136 are non-conductive. When the VREF switch control signal VREFSW[i-1] is at a high level, both ends of the switch element 136 are conductive, and the voltage at the other end of the capacitance element 131p becomes equal to the reference voltage VREFH.

[0094] The output enable signal OUT_EN[i-1] is input to a control terminal of the switch element 137. When the output enable signal OUT_EN[i-1] is at a high level, both ends of the switch element 137 are conductive, and when the output enable signal OUT_EN[i-1] is at a low level, both ends of the switch element 137 are non-conductive. When the output enable signal OUT_EN[i-1] is at a high level, both ends of the switch element 137 are conductive, and the voltage of the other end of the switch element 137 becomes equal to the voltage of the source of the NMOS transistor 134. That is, when the output enable signal OUT_EN[i-1] is at a high level, the pixel signal CDSO[i-1] having a voltage corresponding to the voltage of the output terminal of the operational amplifier 133 is output from the other end of the switch element 137.

[0095] In FIG. 8 or FIG. 9, when both ends of the switch elements 132p and 132n are conductive and both ends of the switch element 136 are conductive, the voltage V CDS_rst is expressed as equation (7).

[0096]

number

[0097] In addition, when both ends of the switch elements 132p and 132n are non-conductive and both ends of the switch element 136 are conductive, the voltage V CDS_sig is expressed as formula (8). In formula (8), C INP is the sum of the capacitances of one or more capacitive elements 127 electrically connected to the non-inverting input terminal of the operational amplifier 133, and C INN is the sum of the capacitances of one or more capacitive elements 128 electrically connected to the inverting input terminal of the operational amplifier 133. f1 is the capacitance of the capacitive element 131p, and C f2 is the capacitance of the capacitive element 131n. INP is the voltage of the non-inverting input signal CDS_INP[i-1] input to the non-inverting input terminal of the operational amplifier 133, and V INNis the voltage of the inverted input signal CDS_INN[i−1] input to the inverting input terminal of the operational amplifier 133.

[0098]

number

[0099] In formula (8), C INP =C INN , C f1 =C f2 Then, the voltage V at the output terminal of the operational amplifier 133 is CDS_sig is expressed as equation (9).

[0100]

number

[0101] 6. Operation of image reading chip Fig. 10 is a timing chart showing an example of the timing of an image reading operation by the image reading chip 415. Note that Fig. 10 is a timing chart when the resolution of image reading by the scanner unit 3 is set to 4800 dpi.

[0102] As shown in FIG. 10, in the period from time t0 to time t1, the read signals READN[0] to READN[3] transition from a low level to a high level in this order.

[0103] In the period from time t1 to time t2, the pixel reset signal PIX_RST goes to high level, and each pixel signal PIXO output from the N pixel circuits 110 is reset to a predetermined voltage.

[0104] The red LED 412R emits light during a period of time Δt from time t2 to time t10. When the read signals READ[0] to READ[3] transition from high level to low level in this order during a period from time t3 to time t4, each pixel signal PIXO of a predetermined voltage output from the N pixel circuits 110 is temporarily stored in each capacitive element 122 of the N line memories 120. The voltage of each capacitive element 122 is a predetermined voltage reset by the pixel reset signal PIX_RST, as shown in the above equation (3).

[0105] During the period from time t5 to time t6, the read signals READN[0] to READN[3] transition from low level to high level in this order, and during the period from time t7 to time t8, when the read signals READN[0] to READN[3] transition from high level to low level in this order, the pixel signals temporarily stored in the capacitance elements 122 in each line memory 120 are stored in the capacitance elements 127. The voltage of each capacitance element 127 is as shown in the above-mentioned equation (5).

[0106] During the period from time t9 to time t10, the read signals READN[0] to READN[3] transition from low level to high level in this order, and during the period from time t11 to time t13, the read signals READ[0] to READ[3] transition from high level to low level in this order, and the pixel signals PIXO output from the N pixel circuits 110 are temporarily stored in the capacitive elements 122 of the N line memories 120. The voltage of each capacitive element 122 is a voltage corresponding to the light received by each light receiving element 111 from the medium to be read during the exposure time Δt due to the emission of the red LED 412R, and is expressed by the above-mentioned formula (4).

[0107] Furthermore, during the period from time t9 to time t10, the read signals READS[0] to READS[3] transition from low level to high level in this order, and during the period from time t12 to time t14, when the read signals READS[0] to READN[3] transition from high level to low level in this order, the pixel signals temporarily stored in the capacitive elements 122 in each line memory 120 are stored in the capacitive elements 128. The voltage of each capacitive element 128 becomes as shown in the above-mentioned equation (6).

[0108] Then, in the period from time t15 to time t16, the image signal OS is output. Fig. 11 is a detailed timing chart of the period from time t15 to time t16 in Fig. 10. Note that in Fig. 11, the pixel signal PIXO output from the j-th pixel circuit 110 is represented as a pixel signal PIXO[j-1].

[0109] 11, in the period from time t15 to time t16, the CDS reset signal CDS_RST periodically repeats low and high levels. Then, the n CDS enable signals CDS_EN[0] to CDS_EN[n-1] sequentially go to high level, and when the CDS reset signal CDS_RST is at low level, the selection signals SEL[0] to SEL[N-1] sequentially go to high level one by one. When the selection signal SEL[i-1] is at high level, the output voltage of the operational amplifier 133 of the i-th CDS circuit 130 becomes as shown in the above formula (8) or formula (9).

[0110] During the period from time t15 to time t16, the image signal OS, which is a time series of voltages corresponding to the light received by each light receiving element 111 due to the emission of light by the red LED 412R, is output.

[0111] At time t15, after the pixel reset signal PIX_RST becomes high level for a predetermined time, the green LED 412G emits light, and the image signal OS, which is a time series of voltages corresponding to the light received by each light receiving element 111 due to the emission of the green LED 412G, is output. The period during which the green LED 412G emits light partially overlaps with the period during which the image signal OS generated by the emission of the red LED 412R is output. After the emission of the green LED 412G ends, the pixel reset signal PIX_RST becomes high level for a predetermined time, and the blue LED 412B emits light, and the image signal OS, which is a time series of voltages corresponding to the light received by each light receiving element 111 due to the emission of the blue LED 412B, is output. The period during which the blue LED 412B emits light partially overlaps with the period during which the image signal OS generated by the emission of the green LED 412G is output. The operation timing from when the green LED 412G or the blue LED 412B starts emitting light to when the output of the image signal OS ends is similar to the operation timing from when the red LED 412R starts emitting light to when the output of the image signal OS ends, so a description thereof will be omitted.

[0112] 7. Reduction of pixel signal offset As described above, in the image reading chip 415 of this embodiment, for each integer k between 0 and 3, the read signals READ[k], READN[k], and READS[k] are supplied to each of the 4s+k-th line memories 120. That is, the read signals READ[0], READN[0], and READS[0] are supplied to N / 4 line memories 120, the read signals READ[1], READN[1], and READS[1] are supplied to N / 4 line memories 120, the read signals READ[2], READN[2], and READS[2] are supplied to N / 4 line memories 120, and the read signals READ[3], READN[3], and READS[3] are supplied to N / 4 line memories 120. In contrast, a comparative example is assumed in which the read signals READ, READN, and READS are commonly supplied to N line memories 120.

[0113] In the comparative example, at the falling edge timing when the read signal READ changes from high level to low level, the N switch elements 121 transition from a conductive state to a non-conductive state at the same time, and the pixel signals stored in the N capacitance elements 122 are determined. For example, if N>1000, when the state of several thousand switch elements 121 transitions at the same time, the parasitic capacitance of each switch element 121, that is, the gate capacitance of each MOS transistor, is charged and discharged by the current output from the logic circuit 101, and the power supply voltage VDD fluctuates greatly. As shown in FIG. 12, this fluctuation in the power supply voltage VDD causes noise to be mixed into the pixel signal PIXO output from each pixel circuit 110, and an offset equivalent to the noise is generated in the pixel signal stored in each capacitance element 122. In FIG. 12, the pixel signal PIXO output from the j-th pixel circuit 110 is represented as pixel signal PIXO[j-1].

[0114] On the other hand, due to thermal noise and 1 / f noise of the MOS, the read signal READ falls in a wavy manner, and the timing at which each switch element 121 changes from a conductive state to a non-conductive state varies, resulting in the offset amount of the pixel signal stored in each capacitance element 122 varying for each line along which the image sensor module 41 reads an image of the medium to be read. In contrast, since the power supply voltage VDD and the read signal READ are commonly input to the N pixel circuits 110 and the N line memories 120, the offset amounts of the N pixel signals stored in the N capacitance elements 122 for each line are approximately the same. Therefore, if the timing at which each switch element 121 changes from a conductive state to a non-conductive state varies for each line, horizontal stripes will appear in the read image. In particular, when the resolution is set to 300 dpi, 16 pixel signals are voltage-added. If the exposure time Δt is reduced to, for example, 1 / 16 in order to read the image quickly, the pixel signal PIXO output from each pixel circuit 110 will be 1 / 16, while the offset amount of the pixel signal stored in each capacitance element 122 will not change. As a result, the offset amount for the voltage-added pixel signal will be 16 times, and the horizontal stripes that appear in the read image will become clearer.

[0115] The shorter the slew rate of the fall of the read signal READ, the smaller the variation in the timing at which each switch element 121 changes from a conductive state to a non-conductive state, but the larger the instantaneous current amount, the larger the variation in the power supply voltage VDD. Therefore, in the comparative example, even if the slew rate of the fall of the read signal READ is changed, it is difficult to reduce the variation in the offset amount of the pixel signal stored in each capacitance element 122. In addition, since the frequency component of the variation in the power supply voltage VDD is, for example, on the order of 100 MHz to GHz, it is generally difficult to realize a circuit that removes such high-frequency variations.

[0116] In the comparative example, at the falling edge when the read signal READN changes from high level to low level, the N switch elements 125 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N capacitance elements 127. Similarly, at the falling edge when the read signal READS changes from high level to low level, the N switch elements 126 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N capacitance elements 128. Therefore, the offset amount of the pixel signals stored in each of the capacitance elements 127 and 128 also becomes large.

[0117] On the other hand, in the image reading chip 415 of this embodiment, the read signals READ[0] to READ[3] change from high level to low level in this order. Therefore, after the switch element 121 of each 4s-th line memory 120 transitions from a conductive state to a non-conductive state, the switch element 121 of each 4s+1-th line memory 120 transitions from a conductive state to a non-conductive state. Also, after the switch element 121 of each 4s+1-th line memory 120 transitions from a conductive state to a non-conductive state, the switch element 121 of each 4s+2-th line memory 120 transitions from a conductive state to a non-conductive state. Also, after the switch element 121 of each 4s+2-th line memory 120 transitions from a conductive state to a non-conductive state, the switch element 121 of each 4s+3-th line memory 120 transitions from a conductive state to a non-conductive state.

[0118] Then, at the falling edge of the read signal READ[0] changing from a high level to a low level, the N / 4 switch elements 121 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitive elements 122. Also, at the falling edge of the read signal READ[1] changing from a high level to a low level, the N / 4 switch elements 121 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitive elements 122. Also, at the falling edge of the read signal READ[2] changing from a high level to a low level, the N / 4 switch elements 121 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitive elements 122. Furthermore, at the falling edge timing when the read signal READ[3] changes from high level to low level, the N / 4 switch elements 121 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitance elements 122. Therefore, as shown in Fig. 13, the amount of fluctuation in the power supply voltage VDD at the falling edge timing when the read signals READ[0] to READ[3] change from high level to low level is 1 / 4 of that in the comparative example, and the noise mixed into the pixel signal PIXO output from each pixel circuit 110 is also 1 / 4. Note that in Fig. 13, the pixel signal PIXO output from the j-th pixel circuit 110 is denoted as pixel signal PIXO[j-1].

[0119] Therefore, if the offset amount of pixel signals stored in N capacitive elements 122 determined at the falling edge timing when the read signal READ changes from high level to low level in the comparative example is ΔVa1, then in the image reading chip 415 of this embodiment, the offset amount ΔVk of pixel signals stored in N / 4 capacitive elements 122 determined at the falling edge timing when the read signal READ[k] changes from high level to low level is ΔVa1 / 4 for each integer k between 0 and 3. Therefore, the offset amount ΔVa2 of pixel signals stored in N capacitive elements 122 is calculated by equation (10) and is reduced to 1 / 2 of the offset amount ΔVa1 in the comparative example.

[0120]

number

[0121] In the image reading chip 415 of this embodiment, the read signals READN[0] to READN[3] change from high level to low level in this order. Therefore, after the switch element 125 of each 4s-th line memory 120 transitions from a conductive state to a non-conductive state, the switch element 125 of each 4s+1-th line memory 120 transitions from a conductive state to a non-conductive state. After the switch element 125 of each 4s+1-th line memory 120 transitions from a conductive state to a non-conductive state, the switch element 125 of each 4s+2-th line memory 120 transitions from a conductive state to a non-conductive state. After the switch element 125 of each 4s+2-th line memory 120 transitions from a conductive state to a non-conductive state, the switch element 125 of each 4s+3-th line memory 120 transitions from a conductive state to a non-conductive state.

[0122] Then, at the falling edge timing when the read signal READN[0] changes from a high level to a low level, the N / 4 switch elements 125 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitive elements 127. Also, at the falling edge timing when the read signal READN[1] changes from a high level to a low level, the N / 4 switch elements 125 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitive elements 127. Also, at the falling edge timing when the read signal READN[2] changes from a high level to a low level, the N / 4 switch elements 125 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitive elements 127. Furthermore, at the falling edge when the read signal READN[3] changes from high level to low level, the N / 4 switch elements 125 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitive elements 127. Therefore, the amount of fluctuation in the power supply voltage VDD at the falling edge when the read signals READN[0] to READN[3] change from high level to low level is 1 / 4 of that in the comparative example, and the offset amount of the pixel signals stored in the capacitive elements 127 is reduced to 1 / 2.

[0123] In the image reading chip 415 of this embodiment, the read signals READS[0] to READS[3] change from high to low in this order. Therefore, after the switch element 126 of each 4s-th line memory 120 transitions from a conductive state to a non-conductive state, the switch element 126 of each 4s+1-th line memory 120 transitions from a conductive state to a non-conductive state. After the switch element 126 of each 4s+1-th line memory 120 transitions from a conductive state to a non-conductive state, the switch element 126 of each 4s+2-th line memory 120 transitions from a conductive state to a non-conductive state. After the switch element 126 of each 4s+2-th line memory 120 transitions from a conductive state to a non-conductive state, the switch element 126 of each 4s+3-th line memory 120 transitions from a conductive state to a non-conductive state.

[0124] Then, at the falling edge of the read signal READS[0] changing from a high level to a low level, the N / 4 switch elements 126 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitive elements 128. Also, at the falling edge of the read signal READS[1] changing from a high level to a low level, the N / 4 switch elements 126 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitive elements 128. Also, at the falling edge of the read signal READS[2] changing from a high level to a low level, the N / 4 switch elements 126 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitive elements 128. Furthermore, at the falling edge when the read signal READS[3] changes from high level to low level, the N / 4 switch elements 126 transition from a conductive state to a non-conductive state all at once, thereby determining the pixel signals stored in the N / 4 capacitive elements 128. Therefore, the amount of fluctuation in the power supply voltage VDD at the falling edge when the read signals READS[0] to READS[3] change from high level to low level is 1 / 4 of that in the comparative example, and the offset amount of the pixel signals stored in the capacitive elements 128 is reduced to 1 / 2.

[0125] 8. Circuit layout of image reading chip Fig. 14 is a diagram showing an example of a circuit layout of the image reading chip 415. As shown in Fig. 14, the circuits constituting the image reading chip 415 are integrally formed on the semiconductor substrate 100 by a semiconductor process including a photolithography method. That is, in this embodiment, the image reading chip 415 is configured as one IC chip.

[0126] In a plan view, the semiconductor substrate 100 has a rectangular shape and has a first long side 100a, a second long side 100b opposite to the first long side 100a, a first short side 100c, and a second short side 100d opposite to the first short side 100c. The semiconductor substrate 100 is, for example, a silicon substrate.

[0127] The N pixel circuits 110 are arranged in a row along the first long side 100a of the semiconductor substrate 100. In addition, a line memory block 170 composed of N line memories 120 is arranged to face the N pixel circuits 110. In other words, the N pixel circuits 110 are arranged between the first long side 100a and the line memory block 170.

[0128] More specifically, the line memory block 170 is composed of a primary memory block 170A composed of N primary memories 120a and a secondary memory block 170B composed of N secondary memories 120b, and the primary memory block 170A is arranged to face the N pixel circuits 110. In other words, the N pixel circuits 110 are arranged between the first long side 100a and the primary memory block 170A. The secondary memory block 170B is arranged to face the primary memory block 170A. In other words, the primary memory block 170A is arranged between the N pixel circuits 110 and the secondary memory block 170B.

[0129] The scanning circuit 102 is disposed opposite the line memory block 170. In other words, the line memory block 170 is disposed between the N pixel circuits 110 and the scanning circuit 102. More specifically, the scanning circuit 102 is disposed opposite the secondary memory block 170B. In other words, the secondary memory block 170B is disposed between the primary memory block 170A and the scanning circuit 102.

[0130] The CDS circuit block 172, which is configured by n CDS circuits 130, is disposed so as to face the scanning circuit 102. In other words, the scanning circuit 102 is disposed between the line memory block 170 and the CDS circuit block 172. More specifically, the scanning circuit 102 is disposed between the secondary memory block 170B and the CDS circuit block 172.

[0131] The pads 180, the logic circuit 101, the preamplifier 140, and the output buffer 150 are arranged in a substantially straight line along the second long side 100b of the semiconductor substrate 100.

[0132] One of the multiple pads 180 is a power supply terminal to which a power supply voltage VDD is supplied, and the other of the multiple pads 180 is a ground terminal to which a ground voltage VSS is supplied. The other two of the multiple pads 180 are input terminals to which a clock signal CLK and a command signal CMD are respectively input, and the other of the multiple pads 180 is an output terminal that outputs an image signal OS.

[0133] In the region between the N pixel circuits 110 and the primary memory block 170A, four readout signal lines 201 to 204 are arranged, extending from the vicinity of the first short side 100c to the vicinity of the second short side 100d. The readout signal line 201 is connected to the control terminal of the switch element 121 of each 4s-th line memory 120, and the logic circuit 101 outputs a readout signal READ[0] to the readout signal line 201. The readout signal line 202 is connected to the control terminal of the switch element 121 of each 4s+1-th line memory 120, and the logic circuit 101 outputs a readout signal READ[1] to the readout signal line 202. The readout signal line 203 is connected to the control terminal of the switch element 121 of each 4s+2-th line memory 120, and the logic circuit 101 outputs a readout signal READ[2] to the readout signal line 203. The read signal line 204 is connected to the control terminal of the switch element 121 of each of the 4s+3-th line memories 120 , and the logic circuit 101 outputs a read signal READ[ 3 ] to the read signal line 204 .

[0134] In the area between the primary memory block 170A and the secondary memory block 170B, four readout signal lines 211-214 and four readout signal lines 221-224 are arranged, which extend from the vicinity of the first short side 100c to the vicinity of the second short side 100d. The readout signal line 211 is connected to the control terminal of the switch element 125 of each 4s-th line memory 120, and the logic circuit 101 outputs a readout signal READN[0] to the readout signal line 211. The readout signal line 212 is connected to the control terminal of the switch element 125 of each 4s+1-th line memory 120, and the logic circuit 101 outputs a readout signal READN[1] to the readout signal line 212. The readout signal line 213 is connected to the control terminal of the switch element 125 of each 4s+2-th line memory 120, and the logic circuit 101 outputs a readout signal READN[2] to the readout signal line 213. The read signal line 214 is connected to the control terminal of the switch element 125 of each of the 4s+3-th line memories 120 , and the logic circuit 101 outputs the read signal READN[ 3 ] to the read signal line 214 .

[0135] The read signal line 221 is connected to the control terminal of the switch element 126 of each 4s-th line memory 120, and the logic circuit 101 outputs the read signal READS[0] to the read signal line 221. The read signal line 222 is connected to the control terminal of the switch element 126 of each 4s+1-th line memory 120, and the logic circuit 101 outputs the read signal READS[1] to the read signal line 222. The read signal line 223 is connected to the control terminal of the switch element 126 of each 4s+2-th line memory 120, and the logic circuit 101 outputs the read signal READS[2] to the read signal line 223. The read signal line 224 is connected to the control terminal of the switch element 126 of each 4s+3-th line memory 120, and the logic circuit 101 outputs the read signal READS[3] to the read signal line 224.

[0136] The readout signal lines 201-204, 211-214, and 221-224 are all disposed in the uppermost layer of a plurality of wiring layers laminated on the semiconductor substrate 100. For example, the readout signal lines 201-204, 211-214, and 221-224 are disposed in the third wiring layer M3, which is the uppermost layer, of a first wiring layer M1, a second wiring layer M2 above the first wiring layer M1, and a third wiring layer M3 above the second wiring layer M2, which are laminated on the semiconductor substrate 100.

[0137] Fig. 15 is an enlarged view of the wiring of the third wiring layer M3 in the region A1 indicated by the dashed line in Fig. 14. In the example of Fig. 15, in a plan view of the semiconductor substrate 100, wirings 234 and 235 are arranged to sandwich the readout signal lines 201 to 204. Also, wirings 236 and 237 are arranged to sandwich the readout signal lines 211 to 214 and 221 to 224. The wirings 234 and 236 are wirings that supply a power supply voltage VDD, and the wirings 235 and 237 are wirings that supply a ground voltage VSS.

[0138] The read signal lines 201-204 supplying the read signals READ[0]-READ[3] to the N line memories 120, the read signal lines 211-214 supplying the read signals READN[0]-READN[3] to the N line memories 120, and the read signal lines 221-224 supplying the read signals READS[0]-READS[3] to the N line memories 120 are long signal lines extending from the first short side 100c to the second short side 100d of the semiconductor substrate 100. In general, signal lines connected to MOS transistors, resistive elements, capacitive elements, etc. are arranged in the first wiring layer M1 or the second wiring layer M2 other than the third wiring layer M3, which is the uppermost layer, and therefore the third wiring layer M3, which is the uppermost layer, has the highest degree of freedom in arranging signal lines. Therefore, in the third wiring layer M3, which is the top layer and has the highest degree of freedom in wiring, the long readout signal lines 201-204, 211-214, and 221-224 can be efficiently arranged in a straight line. For example, the third wiring layer M3, which is the top layer, can be a wiring layer dedicated to arranging power supply wiring, ground wiring, and various signal lines extending from the vicinity of the first short side 100c to the vicinity of the second short side 100d. The wiring arranged in the third wiring layer M3, which is the top layer, also functions as a light shielding film.

[0139] In this embodiment, the first pixel circuit 110 is an example of a "first pixel circuit", the reference pixel signal output from the first pixel circuit 110 is an example of a "first pixel signal", and the detection pixel signal output from the first pixel circuit 110 is an example of a "second pixel signal". The second pixel circuit 110 is an example of a "second pixel circuit", the reference pixel signal output from the second pixel circuit 110 is an example of a "third pixel signal", and the detection pixel signal output from the second pixel circuit 110 is an example of a "fourth pixel signal". The first line memory 120 is an example of a "first memory circuit", and in the first line memory 120, the switch element 121 is an example of a "first switch element", the switch element 125 is an example of a "second switch element", the switch element 126 is an example of a "third switch element", the capacitive element 122 is an example of a "first capacitive element", the capacitive element 127 is an example of a "second capacitive element", and the capacitive element 128 is an example of a "third capacitive element". The second line memory 120 is an example of a "second memory circuit", and in the second line memory 120, the switch element 121 is an example of a "fourth switch element", the switch element 125 is an example of a "fifth switch element", the switch element 126 is an example of a "sixth switch element", the capacitive element 122 is an example of a "fourth capacitive element", the capacitive element 127 is an example of a "fifth capacitive element", and the capacitive element 128 is an example of a "sixth capacitive element". The read signal READ[0] is an example of a "first read signal", and the read signal line 201 is an example of a "first read signal line". The read signal READ[1] is an example of a "second read signal", and the read signal line 202 is an example of a "second read signal line". The read signal READN[0] is an example of a "third read signal", and the read signal line 211 is an example of a "third read signal line". The read signal READN[1] is an example of a "fourth read signal", and the read signal line 212 is an example of a "fourth read signal line". The read signal READS[0] is an example of a "fifth read signal", and the read signal line 221 is an example of a "fifth read signal line". The read signal READS[1] is an example of a "sixth read signal", and the read signal line 222 is an example of a "sixth read signal line".

[0140] 9. Effects As described above, in the image reading chip 415 of this embodiment, in each 4s+k-th line memory 120, when the read signal READ[k] is at a high level, the switch element 121 becomes conductive, and the capacitive element 122 stores a pixel signal after reset or a pixel signal corresponding to incident light, which is output from the 4s+k-th pixel circuit 110. Then, when the read signal READ[k] transitions from a high level to a low level and the switch element 121 transitions from a conductive state to a non-conductive state, the voltage value of the image signal stored in the capacitive element 122 is determined. In this embodiment, first, the read signal READ[0] transitions from a high level to a low level, then the read signal READ[1] transitions from a high level to a low level, then the read signal READ[2] transitions from a high level to a low level, and then the read signal READ[3] transitions from a high level to a low level. Therefore, the timing when the 4sth N / 4 switch elements 121 transition from the conductive state to the non-conductive state at the same time, the timing when the 4s+1th N / 4 switch elements 121 transition from the conductive state to the non-conductive state at the same time, the timing when the 4s+2th N / 4 switch elements 121 transition from the conductive state to the non-conductive state at the same time, and the timing when the 4s+3th N / 4 switch elements 121 transition from the conductive state to the non-conductive state at the same time are shifted from each other. Therefore, in this embodiment, the amount of fluctuation in the power supply voltage VDD at the timing when each switch element 121 transitions from the conductive state to the non-conductive state is reduced compared to the case where N switch elements 121 transition from the conductive state to the non-conductive state at the same time. As a result, the noise mixed into the image signal stored in each capacitance element 122 is reduced.

[0141] In the image reading chip 415 of this embodiment, in each of the 4s+k-th line memories 120, when the read signal READN[k] is at a high level, the switch element 125 is in a conductive state, and the capacitive element 127 stores the pixel signal transferred from the capacitive element 122. Then, when the read signal READN[k] transitions from a high level to a low level and the switch element 125 transitions from a conductive state to a non-conductive state, the voltage value of the image signal stored in the capacitive element 127 is determined. In this embodiment, first, the read signal READN[0] transitions from a high level to a low level, then the read signal READN[1] transitions from a high level to a low level, then the read signal READN[2] transitions from a high level to a low level, and then the read signal READN[3] transitions from a high level to a low level. Therefore, the timing when the 4sth N / 4 switch elements 125 transition from the conductive state to the non-conductive state at the same time, the timing when the 4s+1th N / 4 switch elements 125 transition from the conductive state to the non-conductive state at the same time, the timing when the 4s+2th N / 4 switch elements 125 transition from the conductive state to the non-conductive state at the same time, and the timing when the 4s+3th N / 4 switch elements 125 transition from the conductive state to the non-conductive state at the same time are shifted from each other. Therefore, in this embodiment, the amount of fluctuation in the power supply voltage VDD at the timing when each switch element 125 transitions from the conductive state to the non-conductive state is reduced compared to the case where N switch elements 125 transition from the conductive state to the non-conductive state at the same time. As a result, noise mixed into the image signal stored in each capacitance element 127 is reduced.

[0142] In the image reading chip 415 of this embodiment, in each of the 4s+k-th line memories 120, when the read signal READS[k] is at a high level, the switch element 126 is in a conductive state, and the capacitive element 128 stores the pixel signal transferred from the capacitive element 122. Then, when the read signal READS[k] transitions from a high level to a low level and the switch element 126 transitions from a conductive state to a non-conductive state, the voltage value of the image signal stored in the capacitive element 128 is determined. In this embodiment, first, the read signal READS[0] transitions from a high level to a low level, then the read signal READS[1] transitions from a high level to a low level, then the read signal READNS[2] transitions from a high level to a low level, and then the read signal READS[3] transitions from a high level to a low level. Therefore, the timing at which the 4sth N / 4 switch elements 126 transition from a conductive state to a non-conductive state at the same time, the timing at which the 4s+1th N / 4 switch elements 126 transition from a conductive state to a non-conductive state at the same time, the timing at which the 4s+2th N / 4 switch elements 126 transition from a conductive state to a non-conductive state at the same time, and the timing at which the 4s+3th N / 4 switch elements 126 transition from a conductive state to a non-conductive state at the same time are shifted from each other. Therefore, in this embodiment, the amount of fluctuation in the power supply voltage VDD at the timing at which each switch element 126 transitions from a conductive state to a non-conductive state is reduced compared to the case in which N switch elements 126 transition from a conductive state to a non-conductive state at the same time. As a result, noise mixed into the image signal stored in each capacitance element 128 is reduced.

[0143] Therefore, the image reading chip 415 in this embodiment can reduce the offset amount of pixel signals caused by fluctuations in the power supply voltage VDD. The scanner unit 3 in this embodiment includes the image reading chip 415 that can reduce the offset amount of each pixel signal caused by fluctuations in the power supply voltage VDD, so that horizontal stripes that appear in the read image can be reduced.

[0144] In the image reading chip 415 of this embodiment, the read signal lines 201-203, 211-213, and 221-223 that supply the read signals READ[0]-READ[3], READN[0]-READN[3], and READS[0]-READS[3] to the line memory 120 are long signal lines extending from the first short side 100c to the second short side 100d of the semiconductor substrate 100. In general, signal lines connected to MOS transistors, resistive elements, capacitive elements, and the like are arranged in the first wiring layer M1 or the second wiring layer M2, so that the third wiring layer M3, which is the top layer, has the highest degree of freedom in arranging signal lines. Therefore, according to the image reading chip 415 of this embodiment, the long read signal lines 201-203, 211-213, and 221-223 can be efficiently arranged on a straight line in the third wiring layer M3, which has the highest degree of freedom in wiring.

[0145] 10. Variations The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0146] For example, in the above embodiment, in the image reading chip 415, N line memories 120 are divided into four groups of N / 4 each, and four read signals READ[0] to READ[3] are supplied to the four groups, four read signals READN[0] to READN[3] are supplied to the four groups, and four read signals READS[0] to READS[3] are supplied to the four groups. In contrast, for any integer p, N line memories 120 may be divided into p groups of N / p each, and p read signals READ[0] to READ[p-1] are supplied to the p groups, p read signals READN[0] to READN[p-1] are supplied to the p groups, and p read signals READS[0] to READS[p-1] are supplied to the p groups.

[0147] Also, for example, in the above embodiment, the maximum resolution for reading an image by the scanner unit 3 is 4800 dpi, and the settable resolutions are 4800 dpi, 2400 dpi, 1200 dpi, 600 dpi, or 300 dpi, but the maximum resolution and the settable resolutions are not limited to these, and various resolutions can be set according to the configuration of the image reading chip 415. For example, the maximum resolution may be 1200 dpi, and the settable resolutions may be 1200 dpi, 600 dpi, or 300 dpi. In the above embodiment, each image reading chip 415 is configured to output pixel signals one by one from the line memory 120 when the resolution is set to the highest resolution of 4800 dpi, and to output pixel signals two by two, four by four, eight by eight, or sixteen by sixteen from the line memory 120 and add them together by voltage when the resolution is set to 2400 dpi, 1200 dpi, 600 dpi, or 300 dpi, but the configuration of each image reading chip 415 is not limited to this. For example, the highest resolution may be 1200 dpi, and the image reading chip 415 may be configured to output pixel signals one by one from the line memory 120 when the resolution is set to 1200 dpi, and to output pixel signals two by two or four by four from the line memory 120 and add them together by voltage when the resolution is set to 600 dpi or 300 dpi.

[0148] Although the present invention has been described above with reference to the present embodiment and the modified examples, the present invention is not limited to the present embodiment and the modified examples, and can be embodied in various forms without departing from the spirit of the present invention. For example, the above embodiment and each modified example can be appropriately combined.

[0149] The semiconductor device and image reading device of the present invention are suitable for scanners and image sensors for scanners, but can also be applied to devices and sensors that require high-speed image reading by analog signal processing.

[0150] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations that have the same functions, methods, and results, or configurations that have the same purpose and effect. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that have the same effects as the configurations described in the embodiments, or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0151] The following can be derived from the above-described embodiment and modifications.

[0152] One aspect of the semiconductor device is A first pixel circuit that converts incident light into an electrical signal; A second pixel circuit that converts incident light into an electrical signal; A first storage circuit; A second storage circuit; Equipped with The first memory circuit is a first switch element, a second switch element, a third switch element, a first capacitance element, a second capacitance element, and a third capacitance element; having the first switch element is connected between the first pixel circuit and the first capacitive element; the first capacitance element stores a first pixel signal after reset or a second pixel signal corresponding to the incident light, the first pixel signal being output from the first pixel circuit when the first switch element is in a conductive state; the second switch element is connected between the first capacitance element and the second capacitance element, the second capacitance element stores the first pixel signal transferred from the first capacitance element when the second switch element is in a conductive state; the third switch element is connected between the first capacitance element and the third capacitance element; the third capacitance element stores the second pixel signal transferred from the first capacitance element when the third switch element is in a conductive state; The second memory circuit is a fourth switch element, a fifth switch element, a sixth switch element, a fourth capacitive element, a fifth capacitive element, and a sixth capacitive element; having the fourth switch element is connected between the second pixel circuit and the fourth capacitive element; the fourth capacitance element stores a third pixel signal after reset or a fourth pixel signal corresponding to the incident light, which is output from the second pixel circuit when the fourth switch element is in a conductive state; the fifth switch element is connected between the fourth capacitive element and the fifth capacitive element; the fifth capacitance element stores the third pixel signal transferred from the fourth capacitance element when the fifth switch element is in a conductive state; the sixth switch element is connected between the fourth capacitive element and the sixth capacitive element, the sixth capacitive element stores the fourth pixel signal transferred from the fourth capacitive element when the sixth switch element is in a conductive state; After the first switch element transitions from a conductive state to a non-conductive state, the fourth switch element transitions from a conductive state to a non-conductive state.

[0153] In this semiconductor device, the first capacitance element stores the first pixel signal after reset or the second pixel signal corresponding to incident light, which is output from the first pixel circuit when the first switch element is in a conductive state, so that the voltage value of the first pixel signal or the second pixel signal stored in the first capacitance element is determined when the first switch element transitions from a conductive state to a non-conductive state. Also, the fourth capacitance element stores the third pixel signal after reset or the fourth pixel signal corresponding to incident light, which is output from the second pixel circuit when the fourth switch element is in a conductive state, so that the voltage value of the third pixel signal or the fourth pixel signal stored in the fourth capacitance element is determined when the fourth switch element transitions from a conductive state to a non-conductive state. And, since the first switch element transitions from a conductive state to a non-conductive state, the fourth switch element transitions from a conductive state to a non-conductive state, so that the timing at which the first switch element transitions from a conductive state to a non-conductive state and the timing at which the fourth switch element transitions from a conductive state to a non-conductive state are shifted. Therefore, compared with the case where the timing when the first switch element transitions from a conductive state to a non-conductive state coincides with the timing when the fourth switch element transitions from a conductive state to a non-conductive state, the amount of fluctuation in the power supply voltage at the timing when the first switch element transitions from a conductive state to a non-conductive state is reduced, and the amount of fluctuation in the power supply voltage at the timing when the fourth switch element transitions from a conductive state to a non-conductive state is reduced. As a result, noise mixed into the first pixel signal or the second pixel signal stored in the first capacitance element is reduced, and noise mixed into the third pixel signal or the fourth pixel signal stored in the fourth capacitance element is reduced. Therefore, according to this semiconductor device, it is possible to reduce the amount of offset of the pixel signal caused by fluctuations in the power supply voltage.

[0154] One aspect of the semiconductor device is After the second switch element transitions from a conductive state to a non-conductive state, the fifth switch element transitions from a conductive state to a non-conductive state, After the third switch element transitions from a conductive state to a non-conductive state, the sixth switch element may transition from a conductive state to a non-conductive state.

[0155] In this semiconductor device, the second capacitive element stores the first pixel signal transferred from the first capacitive element when the second switch element is in a conductive state, so that the voltage value of the first pixel signal stored in the second capacitive element is determined when the second switch element transitions from a conductive state to a non-conductive state. The fifth capacitive element stores the third pixel signal transferred from the fourth capacitive element when the fifth switch element is in a conductive state, so that the voltage value of the third pixel signal stored in the fifth capacitive element is determined when the fifth switch element transitions from a conductive state to a non-conductive state. After the second switch element transitions from a conductive state to a non-conductive state, the fifth switch element transitions from a conductive state to a non-conductive state, so that the timing at which the second switch element transitions from a conductive state to a non-conductive state and the timing at which the fifth switch element transitions from a conductive state to a non-conductive state are shifted. Therefore, compared with the case where the timing when the second switch element transitions from a conductive state to a non-conductive state and the timing when the fifth switch element transitions from a conductive state to a non-conductive state coincide with each other, the amount of fluctuation in the power supply voltage at the timing when the second switch element transitions from a conductive state to a non-conductive state is reduced, and the amount of fluctuation in the power supply voltage at the timing when the fifth switch element transitions from a conductive state to a non-conductive state is reduced. As a result, noise mixed into the first pixel signal stored in the second capacitance element is reduced, and noise mixed into the third pixel signal stored in the fifth capacitance element is reduced.

[0156] In this semiconductor device, the third capacitive element stores the second pixel signal transferred from the first capacitive element when the third switch element is in a conductive state, so that the voltage value of the second pixel signal stored in the third capacitive element is determined when the third switch element transitions from a conductive state to a non-conductive state. The sixth capacitive element stores the fourth pixel signal transferred from the fourth capacitive element when the sixth switch element is in a conductive state, so that the voltage value of the fourth pixel signal stored in the sixth capacitive element is determined when the sixth switch element transitions from a conductive state to a non-conductive state. After the third switch element transitions from a conductive state to a non-conductive state, the sixth switch element transitions from a conductive state to a non-conductive state, so that the timing at which the third switch element transitions from a conductive state to a non-conductive state and the timing at which the sixth switch element transitions from a conductive state to a non-conductive state are shifted. Therefore, compared with the case where the timing when the third switch element transitions from a conductive state to a non-conductive state and the timing when the sixth switch element transitions from a conductive state to a non-conductive state coincide with each other, the amount of fluctuation in the power supply voltage at the timing when the third switch element transitions from a conductive state to a non-conductive state is reduced, and the amount of fluctuation in the power supply voltage at the timing when the sixth switch element transitions from a conductive state to a non-conductive state is reduced. As a result, noise mixed into the second pixel signal stored in the third capacitance element is reduced, and noise mixed into the fourth pixel signal stored in the sixth capacitance element is reduced.

[0157] Therefore, according to this semiconductor device, it is possible to reduce the amount of offset in the pixel signal caused by fluctuations in the power supply voltage.

[0158] In one embodiment of the semiconductor device, The first switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element and the sixth switch element may each be a MOS transistor.

[0159] One aspect of the semiconductor device is a first read signal line connected to a control terminal of the first switch element; a second read signal line connected to a control terminal of the second switch element; a third read signal line connected to a control terminal of the third switch element; a fourth read signal line connected to a control terminal of the fourth switch element; a fifth read signal line connected to a control terminal of the fifth switch element; a sixth read signal line connected to a control terminal of the sixth switch element; A logic circuit; Equipped with The logic circuit includes: outputting a first read signal to the first read signal line; outputting a second read signal to the second read signal line; outputting a third read signal to the third read signal line; outputting a fourth read signal to the fourth read signal line; outputting a fifth read signal to the fifth read signal line; A sixth read signal may be output to the sixth read signal line.

[0160] In one embodiment of the semiconductor device, The first readout signal line, the second readout signal line, the third readout signal line, the fourth readout signal line, the fifth readout signal line, and the sixth readout signal line may be arranged in an uppermost layer of a plurality of wiring layers stacked on a semiconductor substrate.

[0161] In this semiconductor device, the read signal line that supplies the read signal to the multiple memory circuits including the first memory circuit and the second memory circuit is a long signal line extending from one end to the other end of the semiconductor substrate. In general, signal lines connected to MOS transistors, resistive elements, capacitive elements, etc. are arranged in a wiring layer other than the topmost layer, so that the topmost layer has the highest degree of freedom in arranging the signal lines. Therefore, according to this semiconductor device, the long read signal line can be efficiently arranged in a straight line in the topmost layer, which has the highest degree of freedom in wiring.

[0162] One aspect of the image reading device is One aspect of the semiconductor device; A light source; Equipped with.

[0163] This image reading device includes a semiconductor device capable of reducing the amount of offset in pixel signals caused by fluctuations in the power supply voltage, and therefore can reduce horizontal stripes that appear in read images. [Explanation of symbols]

[0164] 1...multifunction device, 2...printer unit, 3...scanner unit, 4...hinge section, 11...upper frame, 12...image reading section, 13...upper cover, 16...lower case, 17...upper case, 31...sensor unit, 32...sensor carriage, 33...guide shaft, 34...sensor moving mechanism, 41...image sensor module, 63...operation section, 65...device housing, 66...discharge port, 100...semiconductor substrate, 100a...first long side, 100b...second long side, 100c... First short side, 100d... second short side, 101... logic circuit, 102... scanning circuit, 103-1 to 103-n... blocks, 110... pixel circuit, 111... light receiving element, 112... inverting amplifier, 113... capacitance element, 114... switch element, 120... line memory, 121... switch element, 122... capacitance element, 123... NMOS transistor, 124... constant current source, 125... switch element, 126... switch element, 127... capacitance element, 128... capacitance element, 129p... Switch element, 129n...switch element, 130...CDS circuit, 131p...capacitor element, 131n...capacitor element, 132p...switch element, 132n...switch element, 133...operational amplifier, 134...NMOS transistor, 135...constant current source, 136...switch element, 137...switch element, 138...logic circuit, 140...preamplifier, 150...output buffer, 160...VREFH amplifier, 170...line memory block, 172...CDS circuit block 180: pads, 201, 202, 203, 204: readout signal lines, 211, 212, 213, 214: readout signal lines, 221, 222, 223, 224: readout signal lines, 234, 235, 236, 237: wiring, 300: control unit, 302: analog front end, 411: case, 412: light source, 412R: red LED, 412G: green LED, 412B: blue LED, 413: lens, 414: module board, 415: image reading chip

Claims

1. A first pixel circuit that converts incident light into an electrical signal; A second pixel circuit that converts incident light into an electrical signal; A first storage circuit; A second storage circuit; Equipped with The first memory circuit includes: a first switch element, a second switch element, a third switch element, a first capacitance element, a second capacitance element, and a third capacitance element; having the first switch element is connected between the first pixel circuit and the first capacitive element; the first capacitance element stores a first pixel signal after reset or a second pixel signal corresponding to the incident light, the first pixel signal being output from the first pixel circuit when the first switch element is in a conductive state; the second switch element is connected between the first capacitance element and the second capacitance element, the second capacitance element stores the first pixel signal transferred from the first capacitance element when the second switch element is in a conductive state; the third switch element is connected between the first capacitance element and the third capacitance element, the third capacitance element stores the second pixel signal transferred from the first capacitance element when the third switch element is in a conductive state; The second memory circuit includes: a fourth switch element, a fifth switch element, a sixth switch element, a fourth capacitive element, a fifth capacitive element, and a sixth capacitive element; having the fourth switch element is connected between the second pixel circuit and the fourth capacitive element, the fourth capacitance element stores a third pixel signal after reset or a fourth pixel signal corresponding to the incident light, which is output from the second pixel circuit when the fourth switch element is in a conductive state; the fifth switch element is connected between the fourth capacitance element and the fifth capacitance element, the fifth capacitance element stores the third pixel signal transferred from the fourth capacitance element when the fifth switch element is in a conductive state; the sixth switch element is connected between the fourth capacitive element and the sixth capacitive element, the sixth capacitive element stores the fourth pixel signal transferred from the fourth capacitive element when the sixth switch element is in a conductive state; the fourth switch element transitions from a conductive state to a non-conductive state after the first switch element transitions from a conductive state to a non-conductive state.

2. In claim 1, After the second switch element transitions from a conductive state to a non-conductive state, the fifth switch element transitions from a conductive state to a non-conductive state, the sixth switch element transitions from a conductive state to a non-conductive state after the third switch element transitions from a conductive state to a non-conductive state.

3. In claim 1, the first switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element, and the sixth switch element are each a MOS transistor.

4. In claim 1, a first read signal line connected to a control terminal of the first switch element; a second read signal line connected to a control terminal of the second switch element; a third read signal line connected to a control terminal of the third switch element; a fourth read signal line connected to a control terminal of the fourth switch element; a fifth read signal line connected to a control terminal of the fifth switch element; a sixth read signal line connected to a control terminal of the sixth switch element; A logic circuit; Equipped with The logic circuit includes: outputting a first read signal to the first read signal line; outputting a second read signal to the second read signal line; outputting a third read signal to the third read signal line; outputting a fourth read signal to the fourth read signal line; outputting a fifth read signal to the fifth read signal line; The semiconductor device outputs a sixth read signal to the sixth read signal line.

5. In claim 4, a semiconductor device, wherein the first readout signal line, the second readout signal line, the third readout signal line, the fourth readout signal line, the fifth readout signal line, and the sixth readout signal line are arranged in an uppermost layer of a plurality of wiring layers stacked on a semiconductor substrate.

6. A semiconductor device according to any one of claims 1 to 5, A light source; An image reading device comprising:

Images