Semiconductor electronic device with heterostructure-based electronic components and manufacturing process

Abstract

To provide a semiconductor electronic device including heterostructure-based electronic components and a manufacturing process.SOLUTION: A semiconductor electronic device is formed in a die 3 having a substrate 15 of semiconductor material of a first conductivity type. The device has first electronic components 5A, 5B based on a heterostructure, and the first electronic component has a main body structure 20 of semiconductor material extending in the die over the substrate, and an epitaxial multilayer 21 extending in contact with the main body structure and having a heterostructure 22. The main body structure of the first electronic component has first doped regions 25, 27 of semiconductor material having a second conductivity type different from the first conductivity type, the first doped regions extending between the heterostructure and the substrate.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to semiconductor electronic devices comprising heterostructure-based electronic components and manufacturing processes. [Background technology]

[0002] 2. Description of Related Art Semiconductor electronic devices comprising electronic components based on heterostructures, for example HEMTs (High-Electron-Mobility Transistors), are known.

[0003] In practice, the operation of such electronic components is based on the electronic properties of a heterojunction between two different semiconductor materials.

[0004] In particular, in a HEMT, the conductive channel is based on the formation of a layer of a two-dimensional electron gas (2DEG) with high mobility electrons that is formed at a heterojunction, i.e. at the interface between semiconductor materials with different bandgaps. For example, HEMTs based on a heterojunction between a layer of aluminum and gallium nitride (AlGaN) and a layer of gallium nitride (GaN) are known.

[0005] HEMTs, in particular those based on AlGaN / GaN heterojunctions or heterostructures, offer a wide range of advantages that make them particularly suitable and widely used for different applications: for example, their high breakdown threshold is exploited for high-performance power switches, the high mobility of electrons in the conducting channel makes it possible to obtain high-frequency amplifiers, and furthermore, the high electron concentration in the 2DEG results in a low on-resistance (R ON ) can be obtained.

[0006] Furthermore, HEMTs for radiofrequency (RF) applications typically offer better RF performance than similar silicon LDMOS devices.

[0007] The electronic device is <111> Obtained starting from silicon wafers or from substrates of sapphire (Al2O3) or silicon carbide, electronic components based on heterostructures are integrated in heterostructures epitaxially grown on the wafer.

[0008] However, known electronic components based on heterostructures have electrical performance that, in use, depends on the operating conditions of the electronic device itself, and as a result, the corresponding electronic devices have low reliability.

[0009] For example, the on-state resistance of known HEMTs has a high variability during use and can increase by values ​​comprised between 50% and 200% of the design value, for example, especially when the HEMT is used as a high-side switch in a circuit in a source-follower configuration. Summary of the Invention

[0010] In accordance with the present disclosure, a semiconductor electronic device and manufacturing process includes a die including a substrate of semiconductor material having a first conductivity type, a body structure of the semiconductor material extending over the substrate, and a first electronic component including an epitaxial multilayer extending in contact with the body structure and comprising a heterostructure, and an isolation region extending into the die, surrounding the epitaxial multilayer, and between the epitaxial multilayer and the body structure, the body structure of the first electronic component including a first doped region of semiconductor material having a second conductivity type different from the first conductivity type, extending between the heterostructure and the substrate. [Brief description of the drawings]

[0011] For a better understanding of the present disclosure, embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which: [Figure 1] 1 illustrates a top view of a semiconductor electronic device according to one embodiment. [Diagram 2] 2 is a cross-sectional view of the electronic device of FIG. 1 taken along section line II-II. [Diagram 3] 2 illustrates an electrical equivalent of a portion of the electronic device of FIG. 1, according to one embodiment. [Figure 4A] 3A-3D show cross-sectional views of a portion of the device of FIG. 2 at successive manufacturing steps. [Figure 4B] 3A-3D show cross-sectional views of a portion of the device of FIG. 2 at successive manufacturing steps. [Figure 4C] 3A-3D show cross-sectional views of a portion of the device of FIG. 2 at successive manufacturing steps. [Figure 4D] 3A-3D show cross-sectional views of a portion of the device of FIG. 2 at successive manufacturing steps. [Figure 4E] 3A-3D show cross-sectional views of a portion of the device of FIG. 2 at successive manufacturing steps. [Figure 4F] 3A-3D show cross-sectional views of a portion of the device of FIG. 2 at successive manufacturing steps. [Figure 4G] 3A-3D show cross-sectional views of a portion of the device of FIG. 2 at successive manufacturing steps. [Figure 4H] 3A-3D show cross-sectional views of a portion of the device of FIG. 2 at successive manufacturing steps. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The following description refers to the arrangements illustrated in the accompanying drawings, and therefore terms such as "top," "bottom," "upper," "bottom," "right," "left," "high," "low," and the like, are relative to the drawings and should not be interpreted as limiting.

[0013] FIG. 1 shows a semiconductor electronic device (hereinafter simply referred to as device) 1 in an orthogonal reference system XYZ having a first axis X, a second axis Y and a third axis Z.

[0014] The device 1 comprises a die 3 and one or more electronic components based on a heterostructure 5, of which a first HEMT 5A and a second HEMT 5B are illustrated in FIG. 1 and integrated on the die 3.

[0015] The die 3 is obtained after a step of dicing of the semiconductor wafer.

[0016] The first HEMT 5A is integrated in an active area 7A of the die 3, which is laterally bounded by a respective isolation structure 8.

[0017] The second HEMT 5B is integrated in an active area 7B of the die 3 which is distinct from the active area 7A and which is laterally bounded by a respective insulating structure 9.

[0018] Optionally, device 1 may also include one or more silicon-based electronic components, e.g., active or passive, also integrated on die 3. For example, as illustrated in the embodiment of FIG. 1, device 1 may include one or more MOSFETs 10A, one or more BJTs 10B, and / or one or more passive components 10C, such as diodes and resistors.

[0019] In reality, the operation of silicon-based electronic components is based on the electronic properties of a single semiconductor material, specifically silicon.

[0020] In FIG. 1, MOSFET 10A, BJT 10B, and passive components 10C are each integrated in respective active areas 11A, 11B, 11C of die 3, as indicated by the dashed lines.

[0021] The active areas 11A, 11B, 11C may be electrically isolated from one another or may be in electrical contact with one another, depending on the particular application of the device 1.

[0022] For example, the active areas 11A, 11B, 11C may be electrically isolated from each other by BCD (Bipolar-CMOS-DMOS) technology.

[0023] 1, active areas 11A, 11B, 11C are disposed outside of insulating structures 8, 9. However, one or more of silicon-based electronic components 10 may be integrated into active areas 7A and / or 7B, depending on the particular application.

[0024] Referring to the cross-sectional view of FIG. 2, die 3 comprises a substrate 15 and a device region 16 extending over substrate 15, on which heterostructure-based components 5 and, if present, silicon-based components 10 are integrated.

[0025] The active area 7A forms a first front surface 3A of the die 3 .

[0026] Substrate 15 is of a semiconductor material, particularly a single crystal semiconductor material, and has an upper surface 15A.

[0027] In particular, in this embodiment, the substrate 15 is of single crystal silicon, and in particular, the upper surface 15A is of a crystal orientation <111> is oriented according to

[0028] The substrate 15, in this embodiment, is of P type and has a resistivity comprised between 0.1 Ω·cm and 20 Ω·cm, for example.

[0029] The first HEMT 5A comprises a body structure 20 of semiconductor material extending within the die 3 within the active area 7A on the substrate 15, and an epitaxial multilayer 21 in contact with the body structure 20 and comprising a heterostructure 22 configured to house a layer of a two-dimensional gas of charge carriers.

[0030] In reality, the epitaxial multilayer 21 is a heteroepitaxial multilayer grown starting from the body structure 20 .

[0031] The body structure 20 , here of silicon, may in particular be of monocrystalline type having the same crystal orientation as the substrate 15 .

[0032] The body structure 20 has a conductivity type different from that of the substrate 15 and includes at least one doped region disposed between the heterostructure 22 and the substrate 15, specifically below the heterostructure 22 and facing the heterostructure 22.

[0033] In this embodiment, the body structure 20 includes a number of doped regions, hereinafter referred to as a first epitaxial region 25, a second epitaxial region 26, a third epitaxial region 27, a fourth epitaxial region 28, and a fifth epitaxial region 29.

[0034] Epitaxial regions 25-29 may be formed by one or more epitaxial layers grown on substrate 15, depending on the particular application.

[0035] The first epitaxial region 25 has a conductivity type different from that of the substrate 15, ie, here, N-type.

[0036] The first epitaxial region 25 is arranged parallel to the third axis Z and below the epitaxial multilayer 21. In other words, the first epitaxial region 25 faces the epitaxial multilayer 21 at a distance therefrom in the embodiment of FIG.

[0037] The first epitaxial region 25 may be a buried region within the die 3 .

[0038] In particular, the first epitaxial region 25 extends directly into contact with the substrate 15 .

[0039] In fact, the body structure 20 is defined at the bottom, ie along a third axis Z in the direction of the substrate 15 , by a first epitaxial region 25 .

[0040] The first epitaxial region 25 is, for example, 8·10 Ω·cm so as to have a resistivity of, for example, 0.02 Ω·cm to 20 Ω·cm. 14 atoms / cm 3 ~5·1019 atoms / cm 3 The doping level may be uniform or variable along the first axis, the second axis, and / or the third axis Z, such that the doping level is comprised of:

[0041] In particular, the first epitaxial region 25 may have a peak doping level that is higher than the peak doping level of the substrate 15. This may make it possible to have a depletion region between the first epitaxial region 25 and the substrate 15, in use, that extends primarily into the substrate 15.

[0042] The second epitaxial region 26 extends over the first epitaxial region 25 .

[0043] In particular, the epitaxial region 26 extends from the first front side 3A of the die 3 deep into the die 3 along the third axis Z to the first epitaxial region 25.

[0044] The second epitaxial region 26 may have a doping type that is the same as or different from that of the substrate 15, depending on the particular application, and in particular here the same (P) doping type.

[0045] The second epitaxial region 26 is, for example, 8·10 Ω·cm to have a resistivity of, for example, 0.02 Ω·cm to 20 Ω·cm. 14 atoms / cm 3 ~5·10 19 atoms / cm 3 The doping level may be uniform or variable along the first axis, the second axis, and / or the third axis Z, such that the doping level is comprised of:

[0046] A third epitaxial region 27 faces the epitaxial multilayer 21 parallel to the third axis Z and extends within the die 3 beneath the epitaxial multilayer 21 .

[0047] The third epitaxial region 27 may be a buried region within the die 3 .

[0048] In particular, the third epitaxial region 27 extends into the second epitaxial region 26 at a distance from the first epitaxial region 25 .

[0049] The third epitaxial region 27 may be of P-type or N-type (N-type in the embodiment of FIG. 1) and may be, for example, 8·10 Ω·cm to have a resistivity comprised, for example, of 0.02 Ω·cm to 20 Ω·cm. 14 atoms / cm 3 ~5·10 19 atoms / cm 3 The first HEMT 5A may have doping levels that are uniform or variable along the first axis, the second axis, and / or the third axis Z, such that the first HEMT 5A has a doping level comprised of: If the first HEMT 5A is designed to operate at a high voltage, starting at, for example, about 20 V, e.g., 60 V, 100 V, or 650 V, relative to the substrate 15, the presence of both the first and third epitaxial regions 25, 27 of N type (i.e., a type different from the type of the substrate 15) may be useful to simplify the manufacture of the device 1 and to obtain good electrical performance of the device 1 in use.

[0050] The fourth epitaxial region 28 extends over the third epitaxial region 27 and has a central portion 28A and a peripheral portion 28B surrounding the central portion 28A.

[0051] In this embodiment, the epitaxial multilayer 21 is grown starting from the fourth epitaxial regions 28, in particular from their respective central portions 28A.

[0052] In the embodiment of FIG. 1, peripheral portion 28B is adjacent to central portion 28A.

[0053] 1, the peripheral portion 28B is in contact with the second epitaxial region 26. Specifically, in this embodiment, the peripheral portion 28B of the fourth epitaxial region 28 is laterally adjacent to the second epitaxial region 26, parallel to the first axis X.

[0054] The fourth epitaxial region 28 may be of N-type or P-type (here N-type) and may be, for example, 8·10 Ω·cm to have a resistivity comprised, for example, of 0.02 Ω·cm to 20 Ω·cm. 14 atoms / cm 3 ~5·10 19 atoms / cm 3 The doping level may be uniform or variable, such as having a doping level consisting of

[0055] In particular, the fourth epitaxial region 28 may have a lower peak doping level than the third epitaxial region 27. This may be useful during manufacturing to optimize the growth of the epitaxial multi-layer 21.

[0056] The fifth epitaxial region 29 extends over the fourth epitaxial region 28 and in particular into the second epitaxial region 26 .

[0057] In particular, the fifth epitaxial region 29 extends over, and in particular overlaps, the peripheral portion 28B of the fourth epitaxial region 28.

[0058] The fifth epitaxial region 29 may be of P-type or N-type (here N-type) and may have a uniform or variable doping level, for example to have a resistivity comprised between 0.1 Ω·cm and 20 Ω·cm.

[0059] The epitaxial multilayer 21 extends onto, and in particular in direct contact with, a central portion 28A of the fourth epitaxial region 28 up to a top surface 30. The top surface 30 forms a second front surface of the active area 7A.

[0060] In practice, the epitaxial multilayer 21 is grown starting from the fourth epitaxial region 28 .

[0061] Overall, the thickness along the third axis Z of the body structure 20 below the epitaxial multilayer 21, i.e., measured between the bottom surface of the epitaxial multilayer 21 and the top surface 15A of the substrate 15, may be between 5 μm and 30 μm, for example about 15 μm, depending on the particular application.

[0062] The first HEMT 5A is integrated in a heterostructure 22 of an epitaxial multilayer 21 .

[0063] 2, epitaxial multilayer 21 also comprises a transition region 32, formed by one or more overlapping buffer layers (not illustrated here), located between fourth epitaxial region 28 and heterostructure 22. Transition region 32 may be useful during fabrication of device 1 to aid in epitaxial growth of heterostructure 22 on fourth epitaxial region 28.

[0064] For example, transition region 32 may be formed by a layer of aluminum nitride (AlN) extending over and in direct contact with fourth epitaxial region 28 and a layer of aluminum and gallium nitride (AlGaN) extending over and in direct contact with the AlN layer.

[0065] The heterostructure 22 comprises a compound semiconductor material that includes elements from Groups III and V of the periodic table.

[0066] In this embodiment, the heterostructure 22 forms the upper surface 30 of the epitaxial multilayer 21 .

[0067] The top surface 30 of the epitaxial multilayer 21 may extend at coordinates along a third axis Z that are the same as or different from the coordinates of the first front surface 3A of the die 3, depending on the particular manufacturing steps used to make the device 1.

[0068] In particular, in this embodiment, the top surface 30 of the epitaxial multilayer 21 extends a shorter distance, measured along the third axis Z, from the substrate 15 than the first front surface 3A of the die 3. This may allow for improved manufacturing of the device 1.

[0069] The heterostructure 22 comprises a channel layer 35 and a barrier layer 36 which overlap each other.

[0070] The channel layer 35 is made of a first semiconductor material, for example gallium nitride (GaN) or an alloy containing gallium nitride such as InGaN, here gallium nitride (GaN), and extends over the transition region 32 and in particular is in direct contact with the transition region 32.

[0071] The barrier layer 36 is made of a second semiconductor material, for example Al. x Ga 1-x N, AlInGaN, In x Ga 1-x N, Al x In 1-x A compound based on a ternary or quaternary alloy of gallium nitride, such as Al, AlScN, here of aluminum and gallium nitride (AlGaN), extends onto the channel layer 35, in particular in direct contact with the channel layer 35, up to the upper surface 30 of the epitaxial multilayer 21.

[0072] The channel layer 35 and the barrier layer 36 may be of intrinsic, P-type, or N-type, depending on the particular application. In particular, both the channel layer 35 and the barrier layer 36 may be of N-type.

[0073] For example, when the barrier layer 36 is of AlGaN, the presence of aluminum atoms may cause the barrier layer 36 to be N-type.

[0074] The heterostructure 22 is configured to accommodate a two-dimensional gas of (mobile) charge carriers, in particular here electrons (2DEG), disposed between the channel layer 35 and the barrier layer 36, in particular at the interface between the channel layer 35 and the barrier layer 36.

[0075] Insulating regions may extend, in a manner known per se, on the upper surface 3A, 30, with functions such as passivation, electrical insulation, etc., depending on the particular application.

[0076] The first HEMT 5A further comprises a surface structure extending on the upper surface 30 of the epitaxial multilayer 21 and forming functional regions of the first HEMT 5A, e.g., various conductive and / or insulating regions that may vary depending on the particular type of the first HEMT 5A.

[0077] In this embodiment, the first HEMT 5A comprises a source region 40 and a drain region 41 of conductive material extending at a distance from each other along a first axis X.

[0078] In a top view, the source region 40 may form a closed line having a generally ring shape, two portions of which are illustrated in cross section in Figure 2. For example, the source region 40 may have a circular, polygonal, regular, or irregular shape depending on the particular design layout.

[0079] The drain region 41 may, for example, have the shape of an elongated strip along the second axis Y in top view, or may have a different shape, for example circular, polygonal, regular or irregular.

[0080] The source region 40 and the drain region 41 are in electrical contact, in particular ohmic contact, with the heterostructure 22 and in particular with the two-dimensional gas formed at the interface between the channel layer 35 and the barrier layer 36, and form the source terminal S and the drain terminal D, respectively, of the first HEMT 5A.

[0081] In the embodiment of FIG. 2, the source region 40 and the drain region 41 extend in a direction parallel to the third axis Z to the top surface 30 .

[0082] However, depending on the particular application, the source region 40 and the drain region 41 may also extend parallel to the third axis Z partially through the heterostructure 22, for example through part of the barrier layer 36 or through the entire thickness of the barrier layer 36, in particular up to the interface with the channel layer 35.

[0083] The surface structure of the first HEMT 5A also comprises a gate structure, here formed by a channel modulation region 43 and a gate contact region 44, which may be biased to electrically control the formation of a two-dimensional gas in the heterostructure 22 between the source region 40 and the drain region 41.

[0084] The gate structures 43, 44 extend between the source region 40 and the drain region 41. In a top view, the gate structures 43, 44 may form a closed line having a general ring shape, two portions of which are illustrated in cross section in Figure 2. For example, the gate structures 43, 44 may have a circular, polygonal, regular, or irregular shape depending on the particular design layout.

[0085] In practice, the gate structures 43 , 44 may be disposed internally to the source region 40 , for example substantially concentrically to the source region 40 .

[0086] The gate structures 43, 44 form the gate terminal G of the first HEMT 5A.

[0087] In this embodiment, the first HEMT5A is of a normally-off type, that is, an enrichment type.

[0088] In particular, in this embodiment, the channel modulation region 43 is of a semiconductor material and has a different conductivity type, for example P-type, from the conductivity type of the barrier layer 36. In particular, the channel modulation region 43 may be made of P-type gallium nitride (p-GaN).

[0089] However, the channel modulation region 43 may also be formed by a collection of different materials including dielectric, metallic and / or semiconducting layers used as control electrodes with suitable work functions.

[0090] The channel modulation region 43 extends along a first axis X on the top surface 30 between the source region 40 and the drain region 41 .

[0091] A gate contact region 44 of conductive material extends in electrical contact with the channel modulation region 43 , and in particular here in direct contact with the channel modulation region 43 .

[0092] Device 1 further comprises an isolation region 50 that extends into die 3 within active area 7A.

[0093] In particular, the isolation region 50 extends over the fourth epitaxial region 28 , in particular in direct contact with the fourth epitaxial region 28 , and surrounds the epitaxial multilayer 21 .

[0094] In the embodiment of FIG. 2, the separation region 50 extends parallel to the first axis X between the epitaxial multilayer 21 and the fifth epitaxial region 29 .

[0095] In particular, the isolation region 50 comprises a defined region 52, e.g. comprising an oxide, in particular silicon oxide, extending over and in direct contact with the fourth epitaxial region 28, and a polycrystalline region 53 of the same material (silicon) as the fifth epitaxial region 29, extending over and in direct contact with the defined region 52.

[0096] The defined area 52 may be formed by a single layer, for example an oxide layer, in particular a silicon oxide layer, or it may be formed by a multilayer, for example comprising one or more layers of oxide and / or one or more layers of nitride.

[0097] In particular, according to one embodiment, the defined area 52 may be of silicon oxide.

[0098] According to different embodiments, the demarcation area 52 may comprise an oxide layer, in particular a silicon oxide layer, and a nitride layer. According to one embodiment, the oxide layer may be in direct contact with the semiconductor layer 18.

[0099] The presence of an oxide, in particular a silicon oxide, makes it possible to simplify the production of the heterostructure 22 of the first transistor 5A.

[0100] The defined region 52 may have a thickness along the third axis Z comprised for example between 7 nm and 300 nm, in particular between 70 Å and 200 Å.

[0101] In this embodiment, polycrystalline region 53 has a polycrystalline structure.

[0102] In this embodiment, polycrystalline region 53 is monolithic with fifth epitaxial region 29 .

[0103] The polycrystalline region 53 has an outer sidewall 55 that separates the polycrystalline region 53 from the fifth epitaxial region 29. The outer sidewall 55 has a slope that may depend on the crystal orientation of the fifth epitaxial region 29 and the thickness of the defined region 52 along the third axis Z. For example, if the fifth epitaxial region 29 has a crystal orientation <111> When oriented according to, the outer sidewall 55 may form an angle of approximately 54° with respect to a direction parallel to the first axis X.

[0104] Polycrystalline region 53 also has an inner sidewall 56 opposite an outer sidewall 55 facing epitaxial multilayer 21 .

[0105] Epitaxial multilayer 21 is disposed outside source region 40 and has a peripheral portion that extends in contact with inner sidewall 56 of isolation region 50 .

[0106] The shape of these peripheral portions, which will not be described in detail here and which are only diagrammatically illustrated in FIG. 2, will depend on the particular manufacturing steps used to form device 1.

[0107] For example, the epitaxial multilayer 21 may be conformally grown on the inner sidewalls 56 as well.

[0108] Isolation regions 50 may be useful during fabrication to promote good crystallographic quality of epitaxial multilayer 21, as described in more detail below with reference to Figures 4A-4H.

[0109] Furthermore, the presence of polycrystalline regions 53 may be useful in reducing stress caused by lattice mismatch between the material (e.g., GaN) forming epitaxial multilayer 21 and the material (e.g., silicon) forming body structure 20. As a result, the presence of polycrystalline regions 53 may contribute to reducing the risk of dislocations in die 3 (and thus possible destruction of device 1).

[0110] The shape and structure of the separation region 50 may vary relative to that illustrated and described with reference to Figure 2, depending on the particular manufacturing steps used to make the device 1. For example, the separation region 50 may be absent.

[0111] The device 1 may further comprise one or more insulating or conductive regions at the first front surface 3A depending on the particular application and the particular layout of the active area 7A. For example, Figure 2 shows an insulating region 58, e.g. of silicon oxide, extending from the surface 3A into the body structure 20 around the epitaxial multilayer 21.

[0112] In particular, insulating region 58 contacts (adjacent) epitaxial multi-layer 21 .

[0113] 2, an insulating region 58 is adjacent the interface between the channel layer 35 and the barrier layer 36. This can be useful to electrically isolate the 2DEG from the body structure 20.

[0114] The insulating structure 8 of the first HEMT 5A extends within the die 3 around the body structure 20 of the first HEMT 5A, in particular it is adjacent to (in contact with) the body structure 20.

[0115] In particular, the insulating structure 8 extends within the die 3 from the first front surface 3A to the substrate 15 in contact with the substrate 15 .

[0116] In effect, the insulating structure 8 laterally defines a body structure 20 within the die 3 .

[0117] 2, the isolation structure 8 is a junction isolation structure configured to form a PN junction along, and in particular around, the body structure 20. However, the isolation structure 8 may also be of a different type, for example a deep-trench insulation (DTI) structure.

[0118] In particular, the insulating structure 8 comprises a first junction region 60 of a semiconductor material of N type (here silicon) and a second junction region 61 of a semiconductor material of P type (here silicon) adjacent to each other.

[0119] In particular, in the embodiment of FIG. 2, the first and second bond regions 60, 61 are in contact with each other.

[0120] The first and second junction regions 60, 61 may be formed, in a manner known per se, by growing one or more epitaxial layers on the substrate 15 and then implanting or diffusing dopant species.

[0121] The first bonding area 60 extends in a direction parallel to the third axis Z between the substrate 15 and the first front surface 3A of the die 3 .

[0122] In particular, the first bonding area 60 contacts the substrate 15, and in particular the first bonding area 60 extends from the top surface 15A of the substrate 15 to the first front surface 3A.

[0123] The first junction region 60 extends in a direction parallel to the first axis X adjacent to the body structure 20, in particular adjacent to (in contact with) the first and second epitaxial regions 25, 26. The fact that the first junction region 60 is in contact with the first epitaxial region 25 allows the first junction region 60 to be used to bias the first epitaxial region 25 in use.

[0124] The first junction region 60 has the same conductivity type as the first epitaxial region 25 .

[0125] The first junction region 60 may have a uniform or variable doping level parallel to the third axis Z depending on the particular application. The first junction region 60 may have a doping level of, for example, 1×10 15 atoms / cm 3 ~5×10 18 atoms / cm 3 The doping levels may be comprised of:

[0126] The second bonding area 61 extends parallel to the third axis Z between the substrate 15 and the first front surface 3A of the die 3 .

[0127] In particular, the second bonding area 61 contacts the substrate 15, and in particular the second bonding area 61 extends from the top surface 15A of the substrate 15 to the first front surface 3A.

[0128] The fact that the second bond region 61 is in contact with the substrate 15 allows the second bond region 61 to be used to bias the substrate 15 in use.

[0129] The second junction region 61 has the same conductivity type as the substrate 15 .

[0130] The second junction region 61 may have a uniform or variable doping level parallel to the third axis Z depending on the particular application. The second junction region 61 may have a doping level of, for example, 1×10 15 atoms / cm 3 ~5×10 18 atoms / cm 3 The doping levels may be comprised of:

[0131] What has been described with reference to the first HEMT 5A also applies mutatis mutandis to the second HEMT 5B integrated in the active area 7B. In particular, in the embodiment of Fig. 2, the second HEMT 5B has a structure that is identical to the first HEMT 5A structure. Therefore, elements of the second HEMT 5B that are identical to elements of the first HEMT 5A are indicated with the same reference numbers plus 50 and will not be described in further detail.

[0132] In fact, the second HEMT 5B comprises a body structure 70 and an epitaxial multilayer 71 .

[0133] In the second HEMT 5B, the body structure 70 also includes doped regions having a conductivity type different from that of the substrate 15 .

[0134] In particular, the body structure 70 comprises a first epitaxial region 75, a second epitaxial region 76, a third epitaxial region 77, a fourth epitaxial region 78 (having respective central portions 78A and respective peripheral portions 78B), and a fifth epitaxial region 79.

[0135] However, the size, shape, doping type, and doping level of the epitaxial regions 75-79 of the second HEMT 5A may be the same as or different from the epitaxial regions 25-29 of the first HEMT 5A depending on the particular application.

[0136] The epitaxial multilayer 71 comprises a heterostructure 72 housing a two-dimensional gas of charge carriers, in particular electrons, on which the operation of the second HEMT 5B is based, ie which forms the conduction channel of the second HEMT 5B.

[0137] The heterostructure 72 comprises a channel layer 85 and a barrier layer 86 .

[0138] The epitaxial multilayer 71 also includes a transition region 82 .

[0139] The shape, size, number of layers, and materials of the epitaxial multilayer 71 of the second HEMT 5B may be the same as or different from the epitaxial multilayer 21 of the second HEMT 5A, depending on the particular application.

[0140] The second HEMT 5B further comprises a source region 90, a drain region 91, and a gate structure formed by a channel modulation region 93 and a gate contact region 94.

[0141] The device 1 further comprises an isolation region 100 extending into the die 3 within the active area 7B and comprising a definition region 102 and a polycrystalline region 103. The polycrystalline region 103 has an outer sidewall 105 and an inner sidewall 106.

[0142] The device may also include conductive and / or insulating regions extending into the active area 7B, of which only one, insulating region 108, is illustrated in FIG. 2 as an example.

[0143] What has been described for the insulating structure 8 of the first HEMT 5A applies mutatis mutandis to the insulating structure 9 of the second HEMT 5B. In particular, the insulating structure 9 is also of the junction type and comprises a first junction region 110 and a second insulating region 111.

[0144] In the embodiment of Figure 2, the second junction region 111 forms a single region with the second junction region 61 on the side facing the first transistor 5A. The second junction regions 61, 111 are therefore separated by a dashed line in Figure 2 for clarity.

[0145] In fact, with reference to the first HEMT 5A, the first epitaxial region 25 and the third epitaxial region 27 are buried regions of the body structure 20 extending parallel to the third axis Z between the heterostructure 22 and the substrate 15.

[0146] First epitaxial region 25 has a different conductivity type than substrate 15 , thereby forming a PN junction at upper surface 15 A of substrate 15 .

[0147] Thus, in use, the heterostructure 22 can be electrically isolated from the substrate 15 by appropriately biasing the first epitaxial region 25 and the substrate 15 .

[0148] In other words, in use, it is possible to prevent the substrate 15 from acting as an undesirable conductive channel between the heterostructure 22 and further electronic components integrated on the die 3 (e.g., a second HEMT 5B or an electronic component based on a single semiconductor material 10).

[0149] In practice, it is possible to prevent the electrical performance of the first HEMT 5A from depending on the bias voltage of the substrate 15, in use.

[0150] Moreover, the presence of the insulating structure 8 allows the first HEMT 5A to be electrically isolated laterally as well (parallel to the first and second axes X, Y) from other electronic components integrated on the die 3. In fact, the insulating structure 8 contributes to increasing the electrical isolation of the body structure 20 of the first HEMT 5A from neighboring devices.

[0151] As a result, it is possible to prevent the electrical performance of the first HEMT 5A from depending, in use, on operating voltages applied to other electronic components integrated on the die 3 outside the active area 7A.

[0152] At the same time, both the substrate 15 and the body structure 20 are made of semiconductor materials, here in particular <111> The fact that it is of oriented monocrystalline silicon makes it possible to obtain good crystallographic quality of the heterostructure 22 .

[0153] What has been explained regarding the electrical insulation of the body structure 20 of the first HEMT 5A also applies to the electrical insulation of the body structure 70 of the second HEMT 5B.

[0154] As a result, the body structures 20, 70 of the first and second HEMTs 5A, 5B can be biased independently of each other, in use.

[0155] In fact, device 1 allows the integration of several electronic components based on heterostructures on the same die while at the same time ensuring electrical isolation of the respective body structures, resulting in advantages in terms of area occupation, electrical performance and design versatility compared to solutions in which the electronic components are integrated on different dies.

[0156] For example, according to one embodiment, device 1 may include a conductive region, shown only diagrammatically in FIG. 2, to electrically couple first and second HEMTs 5A, 5B in a source-follower configuration (as illustrated in the electrical equivalent of FIG. 3).

[0157] In Figures 2 and 3, the first HEMT 5A is a low-side switch with its source terminal S coupled to ground, and the second HEMT 5B is a low-side switch with its drain terminal D coupled to an operating voltage V cc (for example, about 48 V). The source terminal S of the second HEMT 5B and the drain terminal D of the first HEMT 5A are coupled to form the output terminal OUT of the source follower circuit.

[0158] As discussed above, the body structures 20, 70 of the first and second HEMTs 5A, 5B are electrically isolated from one another and may therefore be independently biased.

[0159] In the illustrated embodiment, both the body structure 20 of the first HEMT 5A and the body structure 70 of the second HEMT 5B are electrically connected to their respective source regions 40,90.

[0160] The substrate 15 may be connected to ground.

[0161] Since the body structures 20, 70 can be kept isolated from each other, the bias voltages of the body structures 20, 70 can be kept stable. This allows both the first and second HEMTs 5A, 5B to have a stable on-state resistance that is not affected by the potential difference applied between the high-voltage connection terminals of the components and the substrate potential. This can increase the reliability of the use of the device 1, even when the first and second HEMTs 5A, 5B are used in a source-follower configuration.

[0162] Described below with reference to Figures 4A to 4H is a sequence of manufacturing steps that may be used to fabricate the semiconductor electronic device 1.

[0163] In particular, for the sake of simplicity and without loss of generality, FIGS. 4A-4H show only the manufacturing steps relating to a portion of the active area 7A in which the first HEMT 5A is integrated.

[0164] FIG. 4A is a cross-sectional view of a wafer 150 of single crystal semiconductor material, specifically silicon, having a top surface 150A.

[0165] Wafer 150 comprises a substrate 15 on which four epitaxial layers 151, 152, 153, 154 have already been grown, which are intended to form, at least in part, a first epitaxial region 25, a second epitaxial region 26, a third epitaxial region 27, and a fourth epitaxial region 28, respectively (shown in brackets in FIG. 4A for simplicity).

[0166] The fourth epitaxial layer 154 forms the top surface 150 A of the wafer 150 .

[0167] The fourth epitaxial layer 154 comprises a first portion 154A intended to form the peripheral portion 28B of the fourth epitaxial region 28 and a second portion 154B intended to form the central portion 28A of the fourth epitaxial region 28.

[0168] Next (FIG. 4B), a definition layer 156, for example an oxide layer, in particular silicon oxide, is formed on the upper surface 150A.

[0169] The definition layer 156 may have a thickness along the third axis Z comprised for example between 7 nm and 300 nm, in particular between 70 Å and 200 Å.

[0170] Definition layer 156 is intended to form definition region 52 (FIG. 2).

[0171] The definition layer 156 may be formed by oxidation of a surface portion of the fourth epitaxial layer 154 or by deposition on the upper surface 150A. In the case of oxidation, the thickness of the fourth epitaxial layer 154 may be reduced following oxidation, compared to the thickness of layer 18 shown in FIG. 3A. However, considering that the thickness of the definition layer 156 is much smaller compared to the thickness of the fourth epitaxial layer 154, for simplicity, it may be assumed that the thickness of the fourth epitaxial layer 154 remains the same, to a first approximation, before and after oxidation.

[0172] Next (FIG. 4C), the definition layer 156 is removed in a first portion 154A of the fourth epitaxial layer 154 (where the fifth epitaxial region 29 of FIG. 2 will be formed), thus leaving a portion of the definition layer 156, hereinafter also referred to as the growth mask 157.

[0173] In effect, the growth mask 157 exposes a first portion 154A of the fourth epitaxial layer 154 and covers a second portion 154B of the fourth epitaxial layer 154.

[0174] In FIG. 4D, a surface layer 160 of semiconductor material is grown on the wafer 150, specifically the same material as the fourth epitaxial layer 154 (here silicon).

[0175] The surface layer 160 has an upper surface 160A (intended to form the first front surface 3A in FIG. 2).

[0176] The superficial layer 160 comprises an epitaxial portion 161 growing parallel to the third axis Z from the fourth epitaxial layer 154 and a sacrificial portion 162 growing parallel to the third axis Z on the growth mask 157 .

[0177] Epitaxial portion 161 grown from the single crystal substrate is intended to maintain the single crystal structure of fourth epitaxial layer 154 and form fifth epitaxial region 29 (FIG. 2).

[0178] The sacrificial portion 162 is grown from an amorphous substrate and has a polycrystalline structure.

[0179] The wafer 150, which here also comprises a surface layer 160, may further be provided with an insulating structure 8 of FIG. 2, in a manner known per se and not illustrated here.

[0180] In Figure 4E, an etch mask 163 is formed on the surface layer 160. The etch mask 163 may be formed by one or more layers.

[0181] The etch mask 163 forms an opening 166 that at least partially exposes the sacrificial portion 162 .

[0182] Further, an insulating layer 165 may be formed in the surface layer 160, for example by forming an insulating trench, for example a shallow-trench insulation (STI), prior to the formation of the etching mask 163. The insulating layer 165 may be intended to form the insulating region 58 of FIG.

[0183] Next (FIG. 4F), the insulating layer 165 , the sacrificial portion 162 and the growth mask 157 are removed in the openings 166 using the etch mask 163 .

[0184] Thus, the portion of sacrificial portion 162 disposed under etching mask 163 remains, which will form polycrystalline region 53 in FIG. 2, and is still designated 53.

[0185] Thus, only those portions of growth mask 157 remain that are disposed under polycrystalline region 53 and correspond to defined region 52 in FIG. 2 and are therefore designated by the same reference numerals.

[0186] Indeed, following the etching of FIG. 4F, the recesses formed in the sacrificial portion 162 and in the growth mask 157 expose part of the underlying portion 154B of the fourth epitaxial layer 154.

[0187] The etching of the growth mask 157 and the sacrificial portion 162 may be performed using two different etching chemistries, so that the growth mask 157 may be etched using a selective chemistry that, to a first approximation, does not etch the fourth epitaxial layer 154. As a result, the fourth epitaxial layer may maintain good surface crystallographic quality.

[0188] Then (FIG. 4G), a workpiece multilayer 169, intended to form the epitaxial multilayer 21 of FIG.

[0189] In particular, the workpiece multilayer 169 comprises a first buffer layer 170, e.g., of AlN, extending directly onto the exposed portion of the second portion 154B of the fourth epitaxial layer 154, and a second buffer layer 171, e.g., of AlGaN, grown on the first buffer layer 170.

[0190] The first and second buffer layers 170, 171 form the transition region 32 of the epitaxial multilayer 21 (FIG. 2).

[0191] Furthermore, the channel layer 35 and the barrier layer 36 are grown on the second buffer layer 171 .

[0192] In the illustrated embodiment, the workpiece multilayer 169 is conformally grown on the inner sidewalls 56 of the polycrystalline region 53 and also on the etch mask 163 .

[0193] In effect, the workpiece multilayer 169 comprises a raised portion 174 that extends over the etch mask 163 and over the inner sidewall 56 , and a useful portion 175 that extends directly over the fourth epitaxial layer 154 .

[0194] The useful portion 175 has an upper surface that is substantially flat, in particular substantially parallel to the surface 150A of the wafer 150, forming the second front surface 30 (FIG. 2) and is therefore designated by the same reference numeral.

[0195] With further reference to FIG. 4G, a channel modulation region 43 is formed on the upper surface 30 of the useful portion 175 in a manner known per se, for example by growing and defining certain layers.

[0196] Indeed, in this embodiment, the useful portion 175 of the working multilayer 169 also comprises a channel modulation region 43 .

[0197] Next (FIG. 4H), the raised portions 174 of the workpiece multilayer 169 above the etching mask 163 are removed, for example by planarization, for example chemical-mechanical polishing (CMP) or other etching techniques.

[0198] One or more insulating layers (not illustrated here) may be formed on top surface 30 to protect channel modulation region 43 .

[0199] In the illustrated embodiment, after removing raised portion 174 , only the portion extending onto inner sidewall 56 remains, which will form peripheral portion 178 of epitaxial multi-layer 21 .

[0200] 2, the shape of the peripheral portion 178 of the epitaxial multilayer 21 may differ from that illustrated, for example, a further etching step may be performed to at least partially remove the peripheral portion 178.

[0201] The etch mask 163 is then at least partially removed in a manner not illustrated herein.

[0202] Moreover, further manufacturing steps follow, known per se and not illustrated, in order to form the surface structure (metal contact regions, passivation and insulating regions) of the first HEMT 5A.

[0203] Final fabrication steps (not illustrated here), such as forming a top layer of metal interconnects or dicing the wafer 150 , then follow, leading to the formation of device 1 .

[0204] It will be apparent to those skilled in the art that what has been described with reference to FIGS. 4A to 4H can also be applied to the manufacture of the second HEMT 5B.

[0205] Moreover, it will be apparent to those skilled in the art that silicon electronic components 10 may be formed within wafer 150 in particular epitaxial layers grown on substrate 15 .

[0206] As a starting substrate for forming a semiconductor electronic device 1 <111> The possibility of using a silicon substrate 15 makes it possible to obtain a high epitaxial quality of the heterostructure 22, especially when the channel layer 35 is made of GaN. As a result, electronic components based on the heterostructure 5 can have excellent electrical performance. The Applicant has also <111> It has been found that the use of a silicon substrate 15 makes it possible to obtain superior electrical performance of any silicon-based electronic components 10 integrated on the die 3 .

[0207] Finally, it will be apparent that other modifications and variations may be made to the electronic device 1 and the corresponding manufacturing processes described and illustrated herein without departing from the scope of the present disclosure.

[0208] Device 1 may also include other silicon-based electronic components 10 integrated on die 3 in addition to or instead of those illustrated in Figure 1. For example, components 10 may include MOS transistors for applications at low voltages, e.g., below 15V, or at medium voltages, e.g., between 15V and 20V, DMOS transistors and / or drift MOS transistors for applications at operating voltages, e.g., between 20V and 200V, thin film resistors, OTP or MTP memory, phase change memory, etc.

[0209] For example, the conductivity types N or P of the various semiconductor regions may be reversed compared to that illustrated.

[0210] For example, the substrate 15 may be formed by a substrate having a resistivity of 0.002 Ω·cm to 0.1 Ω·cm, on which an epitaxial layer is grown having a thickness of, for example, 1 μm to 40 μm and a resistivity of, for example, 0.1 Ω·cm to 20 Ω·cm.

[0211] For example, the epitaxial multilayers 21, 71 may not comprise the respective transition regions 32, 82. In other words, the heterostructures 21, 71 may be grown directly on the respective body structures 20, 70. Additionally or alternatively, the heterostructures 22, 72 may comprise further layers, for example of semiconducting or insulating materials, depending on the particular application and the particular manufacturing steps used for the growth.

[0212] For example, device 1 may comprise heterostructure-based components other than HEMT.

[0213] For example, the first HEMT 5A and / or the second HEMT 5B may be of a normally-off type, the gate structure may be different from that described above, for example, the gate structure may be recessed, and / or the fabrication of the gate structure may include using a fluorine plasma below the gate structure, or the first HEMT 5A and / or the second HEMT 5B may be of a normally-on type, i.e., a depletion type.

[0214] For example, the number of epitaxial regions forming body structure 20 and / or 70 may vary depending on the particular application.

[0215] For example, in the first (or second) HEMT 5A (or 5B), the fourth epitaxial region 28 (or 78) may not be present and the epitaxial multilayer 21 (or 71) may be grown directly on the third epitaxial region 27 (or 77). This may help reduce manufacturing costs.

[0216] For medium or low voltage applications (e.g. up to about 20V), the body structure 20 and / or 70 may comprise only the respective first epitaxial region 25, 75. Indeed, in this case the epitaxial multilayer 21 and / or 71 may be grown directly on the respective first epitaxial region 25, 75.

[0217] For example, one or more silicon-based electronic components 10 may be integrated within active areas 7A and / or 7B depending on the particular application. In this case, the silicon-based electronic components 10 may be integrated in an epitaxial region adjacent to fifth epitaxial region 29. For example, referring to FIG. 4D , one or more silicon-based electronic components 10 may be integrated in epitaxial portion 161 of surface layer 160.

[0218] For example, electronic component 10 may be an electronic component based on a single semiconductor material other than silicon, such as Ge, SiGe, or the like.

[0219] For example, referring to the use of the first and second HEMTs 5A, 5B in a source follower configuration, the body structure 70 of the second HEMT 5B is connected to an operating voltage V cc 3, or may not be coupled to the respective source region 90 (as shown by the dashed lines in FIG. 3).

[0220] For example, still referring to FIG. 3, the first HEMT 5A may be used as a high-side switch and the second HEMT 5B may be used as a low-side switch.

[0221] For example, according to one embodiment, first junction region 60 and first epitaxial region 25 may be electrically connected to drain terminal D of first HEMT 5A instead of source terminal S of first HEMT 5A, and / or first junction region 110 and first epitaxial region 75 may be electrically connected to drain terminal D of second transistor 5B instead of source terminal S of second transistor 5B. In this way, it is possible to bias regions 75 and 110, in use, to any potential different from, and in particular higher than, the potential applied to region 25.

[0222] For example, the manufacturing steps and respective order of execution described with reference to Figures 4A-4H may differ from that illustrated and described depending on the particular process and machinery used.

[0223] For example, the growth of the epitaxial multilayer 21, 71 may differ from that described with reference to Figure 4G depending on the particular growth parameters used. As described with reference to Figures 2 and 4G, the shape of the peripheral portion of the epitaxial multilayer 21, 71 may differ from that illustrated.

[0224] For example, multilayer 169 may be selectively grown only from exposed portions 154B of fourth epitaxial layer 154. In this case, raised portion 174 may not be present, and as a result, removal as in Figure 4H may not occur.

[0225] For example, the described embodiments may be combined together to provide further solutions.

[0226] A semiconductor electronic device (1) is summarized as comprising a die (3) comprising a substrate (15) of semiconductor material having a first conductivity type (P), a first electronic component (5A, 5B) based on a heterostructure comprising a body structure (20, 70) of semiconductor material extending within the die on the substrate (15) and an epitaxial multilayer (21, 71) extending in contact with the body structure and comprising a heterostructure (22, 72), the body structure of the first electronic component comprising a first doped region (25, 27, 75, 77) of semiconductor material having a second conductivity type (N) different from the first conductivity type, extending between the heterostructure and the substrate.

[0227] A first doped region (25, 27, 75, 77) extends into contact with the substrate.

[0228] The body structure (20, 70) also includes a second doped region (27, 77) having a second conductivity type (N) and spaced apart from the first doped region (25, 75) and extending between the heterostructure and the substrate (15).

[0229] The body structure (20, 70) includes a third doped region (28, 78) having a second conductivity type (N) and a doping level lower than the doping level of the first doped region (25, 27, 75, 77), and the epitaxial multilayer (21, 71) extends over the third doped region.

[0230] The electronic device further includes an insulating structure (8, 9) extending into the die (3) and at least partially surrounding the body structure (20, 70) of the first electronic component (5A, 5B).

[0231] The isolation structure is a junction isolation structure or a deep trench isolation structure.

[0232] The body structure (20, 70) is defined downwardly towards the substrate (15) by a first doped region (25, 75) and laterally by an insulating structure.

[0233] The electronic device further includes an isolation region (50, 100) extending within the die, at least partially surrounding the epitaxial multilayer (21) and positioned between the epitaxial multilayer and the body structure (20, 70), in particular in contact with the epitaxial multilayer and the body structure, the isolation region comprising a region (53, 103) of semiconductor material of polycrystalline type.

[0234] The electronic device further comprises a second electronic component (5B) based on a heterostructure, the second electronic component comprising, on the substrate (15), a respective body structure (70) of semiconductor material extending within the die and a respective epitaxial multilayer (71) extending in contact with the body structure of the second electronic component and comprising a respective heterostructure (72), the body structure (20) of the first electronic component (5A) differs from the body structure (70) of the second electronic component (5B), the epitaxial multilayer (21) of the first electronic component extends at a distance from the epitaxial multilayer (71) of the second electronic component, and the body structure of the second electronic component comprises a first doped region (75, 77) of semiconductor material having a second conductivity type (N) extending between the respective heterostructure (72) and the substrate.

[0235] The first and second electronic components are HEMTs coupled together to form a source-follower type circuit.

[0236] The electronic device further comprises a third electronic component (10) based on a single semiconductor material, for example silicon, and integrated on the die (3).

[0237] A process for manufacturing an electronic device (1) is summarized as comprising providing a wafer (150) comprising a substrate (15) of a semiconductor material having a first conductivity type (P) and forming on the wafer a first electronic component (5A, 5B) based on a heterostructure, where forming the first electronic component comprises forming a body structure (20, 70) of a semiconductor material on the substrate (15) and forming an epitaxial multilayer (21, 71) in contact with the body structure and comprising a heterostructure (21, 71), the body structure comprising a first doped region (25, 27, 75, 77) of a semiconductor material having a second conductivity type (N) different from the first conductivity type, extending between the heterostructure and the substrate.

[0238] The substrate is of silicon and has a top surface (15A), e.g. <111> Oriented according to a crystallographic orientation, the body structure (20, 70) is formed by epitaxial growth of one or more layers on the upper surface of the substrate.

[0239] Forming the epitaxial multilayer (21) includes forming a growth mask (157) on an epitaxial layer (154) grown on a substrate (15), the growth mask comprising an oxide, forming an opening in the growth mask thereby exposing a central portion (154B) of the epitaxial layer, and growing the epitaxial multilayer (21, 169) on the exposed portion of the epitaxial layer.

[0240] Forming the growth mask includes forming a mask layer (156) on the epitaxial layer, removing a portion of the mask layer, thereby exposing a peripheral portion (154A) of the epitaxial layer, and growing a surface layer (160) of the same material as the epitaxial layer on the epitaxial layer (154), the surface layer having a first portion (161) extending onto the peripheral portion (154A) of the epitaxial layer (154) and a second portion (162) extending onto the growth mask (157), and forming an opening in the growth mask (157) further includes forming a recess extending through the second portion (162) of the surface layer to the growth mask.

[0241] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts from various patents, applications, and publications to provide further embodiments.

[0242] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but rather to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. a die including a substrate of a semiconductor material having a first conductivity type; a first electronic component including a body structure of said semiconductor material extending over said substrate and an epitaxial multilayer extending in contact with said body structure and comprising a heterostructure; an isolation region extending into the die, surrounding the epitaxial multilayer, and between the epitaxial multilayer and the body structure; an electronic device, wherein the body structure of the first electronic component includes a first doped region of semiconductor material extending between the heterostructure and the substrate and having a second conductivity type different from the first conductivity type.

2. The electronic device of claim 1 , wherein the first doped region extends into contact with the substrate.

3. 2. The electronic device of claim 1 , wherein the body structure comprises a second doped region having the second conductivity type and extending between the heterostructure and the substrate, the second doped region being separated from the first doped region by a first distance.

4. 2. The electronic device of claim 1, wherein the body structure includes a third doped region having the second conductivity type and a doping level lower than a doping level of the first doped region, and the epitaxial multilayer extends over the third doped region.

5. The electronic device of claim 1 , further comprising an insulating structure extending into the die and surrounding the body structure of the first electronic component.

6. The electronic device of claim 5 , wherein the insulating structure is a bonded insulating structure.

7. 6. The electronic device of claim 5, wherein the body structure is defined downwardly towards the substrate by the first doped region and laterally by the insulating structure.

8. The electronic device of claim 1 , wherein the isolation region comprises a region of polycrystalline semiconductor material.

9. a second electronic component including a respective body structure of the semiconductor material extending into the die on the substrate, and a respective epitaxial multilayer extending in contact with the body structure of the second electronic component and including a respective heterostructure; the body structure of the first electronic component is separate from the body structure of the second electronic component, and the epitaxial multilayer of the first electronic component is separated from the epitaxial multilayer of the second electronic component; 2. The electronic device of claim 1, wherein the body structure of the second electronic component includes a first doped region of semiconductor material having the second conductivity type extending between the respective heterostructure and the substrate.

10. 10. The electronic device of claim 9, wherein the first and second electronic components are HEMTs coupled together to form a source-follower type circuit.

11. The electronic device of claim 1 further comprising a third electronic component on a single semiconductor material and integrated into the die.

12. 1. A process for manufacturing an electronic device, comprising: forming a first electronic component on a wafer including a substrate of a semiconductor material having a first conductivity type; forming the first electronic component; forming a body structure of semiconductor material on the substrate; forming an epitaxial multilayer having a first surface coupled to the body structure and a second surface perpendicular to the first surface; forming a defined region on the body structure and coupled to the second surface of the epitaxial multi-layer; The manufacturing process wherein the body structure includes a first doped region of semiconductor material extending between the heterostructure and the substrate and having a second conductivity type different from the first conductivity type.

13. The manufacturing process of claim 12 , wherein the substrate comprises silicon and has a top surface, and the body structure is formed by epitaxial growth on the top surface of the substrate.

14. forming the epitaxial multi-layer, forming a growth mask on an epitaxial layer grown on the substrate, the growth mask comprising an oxide; forming an opening in the growth mask thereby exposing a central portion of the epitaxial layer; and growing the epitaxial multi-layer on the exposed central portion of the epitaxial layer.

15. forming the growth mask forming a mask layer on the epitaxial layer; removing a portion of the mask layer, thereby exposing a peripheral portion of the epitaxial layer; growing on said epitaxial layer a surface layer of the same material as said epitaxial layer, said surface layer having a first portion extending over said peripheral portion of said epitaxial layer and a second portion extending over said growth mask; 15. The manufacturing process of claim 14, wherein said forming said opening in said growth mask further comprises forming a recess extending through said second portion of said surface layer to said growth mask.

16. A substrate; a body structure on the substrate, the body structure comprising: an epitaxial multilayer having a first surface extending along a first direction and a second plurality of surfaces extending along a second direction perpendicular to the first direction; a first doped region having a first conductivity type; a second doped region between the first doped region and the epitaxial multilayer, the second doped region having a second conductivity type different from the first conductivity type; and a third doped region having the first conductivity type surrounding the second faces of the epitaxial multilayer.

17. 17. The device of claim 16, wherein the epitaxial multilayer has a first width along the first direction that is smaller than a first width of the first doped region along the first direction.

18. 17. The device of claim 16, wherein the second doped region includes a first portion extending along the second direction and includes a first surface that is coplanar with a first surface of the first side of the epitaxial multilayer.

19. 17. The device of claim 16, further comprising a buffer layer between the epitaxial multilayer and the second doped region.

20. and an isolation region between the third doped region and the second faces of the epitaxial multilayer, the isolation region comprising: a silicon oxide definition region coupled to the second doped region; and a polycrystalline region directly bonded to the second plurality of faces of the epitaxial multilayer.

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