Manufacturing process of semiconductor electronic device integrating different electronic components and semiconductor electronic device

Abstract

To provide a manufacturing process of a semiconductor electronic device integrating different electronic components and a semiconductor electronic device.SOLUTION: In order to manufacture a semiconductor electronic device, a wafer is provided that has a substrate layer 10 of a semiconductor material having a first portion 20 and a second portion 21 that is different from the first portion. An epitaxial region 23 of a single semiconductor material is grown on the first portion of a substrate layer 18. An epitaxial multilayer film 49 having a heterostructure 50 is grown on the second portion of the substrate layer. A first electronic component 5A, 5B based on the single semiconductor material is formed starting from the epitaxial region 23. A second electronic component 7 based on a heterostructure is formed starting from the heterostructure. In order to grow the epitaxial multilayer, a growth mask is formed on the substrate layer, an opening is made in the growth mask, thereby exposing a second portion of the substrate layer, and the epitaxial multilayer film is grown on the second portion of the substrate layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a manufacturing process for a semiconductor electronic device integrating different electronic components, and to a semiconductor electronic device. [Background technology]

[0002] 2. Description of Related Art Semiconductor electronic devices are known which include silicon-based active and / or passive electronic components, such as CMOS transistors, DMOS transistors, BJTs, diodes, resistors, etc., integrated in the same silicon die and obtained, for example, by BCD (Bipolar-CMOS-DMOS) technology.

[0003] In reality, the operation of such electronic components is based on the electronic properties of a single semiconductor material: silicon.

[0004] The devices monolithically integrate within the same die digital, analog, and power circuits that operate at very different voltages from each other, for example, from a few volts for CMOS transistors used to implement logic functions, up to hundreds of volts for DMOS transistors used for power applications.

[0005] Silicon-based electronic components <100> It is integrated within a single crystal silicon region grown on a silicon wafer.

[0006] Semiconductor electronic devices including heterostructure-based electronic components, such as High-Electron-Mobility Transistors (HEMTs), are also known.

[0007] In practice, the operation of such electronic components is based on the electronic properties of a heterojunction between two different semiconductor materials.

[0008] In particular, in HEMTs, the conductive channel is based on the formation of a layer of two-dimensional electron gas (2DEG) with high electron mobility formed at a heterojunction, i.e. at the interface between semiconductor materials with different bandgaps. For example, HEMTs based on a heterojunction between a layer of aluminum gallium nitride (AlGaN) and a layer of gallium nitride (GaN) are known.

[0009] In particular, HEMT devices based on AlGaN / GaN heterojunctions or heterostructures have a wide range of advantages that make them particularly suitable and widely used for different applications. For example, the high breakdown threshold of HEMT devices can be exploited for high performance power switches, the high mobility of electrons in the conductive channel allows high frequency amplifiers to be obtained, and furthermore, the high concentration of electrons in the 2DEG allows low on-state resistance (R ON ) can be obtained.

[0010] Furthermore, HEMT devices for radio frequency (RF) applications typically offer better RF performance than similar silicon LDMOS devices.

[0011] Heterostructure-based electronic components include: <111> They are integrated in heterostructures epitaxially grown on silicon wafers or other substrates such as sapphire (Al2O3) or silicon carbide (SiC).

[0012] In order to obtain good crystallographic quality of the respective epitaxial regions and thus good electrical performance of the corresponding electronic components, the heterostructure-based electronic components and the silicon-based electronic components are integrated in different dies starting from two different silicon wafers.

[0013] However, this means that electronic devices incorporating both silicon-based and heterostructure-based components have high area utilization and therefore high manufacturing costs, high energy consumption, and poor electrical performance due to, for example, the parasitic capacitances introduced by the electrical connections between the dies.

[0014] According to one approach, a die having silicon-based components formed therein and a die having heterostructure-based components formed therein are bonded onto each other by die transfer techniques.

[0015] However, the above approach also has disadvantages in terms of manufacturing cost and reliability in use, as well as electrical performance. Summary of the Invention

[0016] According to the present disclosure, a process for manufacturing a semiconductor electronic device and a semiconductor electronic device includes forming an epitaxial region of a single semiconductor material on a first portion of a substrate layer, forming an epitaxial multilayer having a heterostructure on a second portion of the substrate layer different from the first portion, forming a first electronic component in the epitaxial region, and forming a second electronic component in the heterostructure. Forming the epitaxial multilayer includes forming a growth mask on the substrate layer, forming an opening in the growth mask to expose the second portion of the substrate layer, and forming the epitaxial multilayer on the second portion of the substrate layer. [Brief description of the drawings]

[0017] For a better understanding of the present disclosure, embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which: [Figure 1] 1 is a cross-sectional view of a semiconductor electronic device according to an embodiment. [Diagram 2] FIG. 2 shows a top view of the device of FIG. 1. [Figure 3A] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3B] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3C] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3D] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3E] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3F] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3G] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3H] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3I] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3J] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3K] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3L] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3M] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. [Figure 3N] 2A-2D are cross-sectional views of the device of FIG. 1 at successive manufacturing stages. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The following description refers to the orientation illustrated in the accompanying drawings, and therefore terms such as "upper," "lower," "top," "bottom," "right," "left," "high," "low," etc., are relative to the drawings and should not be construed as limiting.

[0019] 1 and 2 show a semiconductor electronic device (hereinafter simply referred to as device) 1 in an orthogonal coordinate system XYZ having a first axis X, a second axis Y and a third axis Z.

[0020] The device 1 is formed in a die 3 and comprises one or more silicon-based electronic components 5, shown in FIG. 1 as PMOS transistor 5A and NMOS transistor 5B, and one or more heterostructure-based electronic components, shown in FIG. 1 as HEMT 7, all integrated within the die 3.

[0021] The die 3 comprises a substrate area 10 and a surface area 12 which extends over the substrate area 10 and in particular is in direct contact with the substrate area 10 .

[0022] Substrate region 10 comprises a substrate 14 and one or more epitaxial layers disposed on substrate 14 .

[0023] Substrate 14 is made of a semiconductor material, particularly a single crystal semiconductor material, and has an upper surface 14A.

[0024] In particular, in this embodiment, the substrate 14 is made of single crystal silicon, and in particular, the upper surface 14A has a crystal orientation <111> is oriented according to

[0025] In this embodiment, the substrate region 10 comprises a first epitaxial layer or first deep layer 15 overlying the upper surface 14A of the substrate 14, a second epitaxial layer or first intermediate layer 16 overlying the first deep layer 15, a third epitaxial layer or second deep layer 17 overlying the first intermediate layer 16, and a fourth epitaxial layer or second intermediate layer 18 overlying the second intermediate layer 17.

[0026] The epitaxial layers 15-18 are made of a semiconductor material, in particular the same material as that of the substrate 14 (here silicon), and are identified by dashed lines in FIG. 1 for the sake of clarity.

[0027] The thickness along the third axis Z, conductivity type (eg, P or N), and doping profile of the substrate 14 and epitaxial layers 15-18 may be selected at the design stage depending on the particular application of the device 1.

[0028] For example, the epitaxial layers 15 to 18 may each have a thickness comprised between 0.1 μm and 7 μm.

[0029] For example, in this embodiment, the substrate 14 is of P type, for example with a resistivity comprised between 0.1 Ωcm and 20 Ωcm, and the epitaxial layers 15-18 are of N type. In this way, the first deep layer 15 can create a PN junction together with the substrate 14a, which can be employed, in use, to isolate the devices 5, 7 integrated in the die 3 from the substrate 14.

[0030] The first deep layer 15 and the second deep layer 17 can have the same or different, in particular higher, doping levels than the first intermediate layer 16 and the second intermediate layer 18. For example, the doping levels of the first deep layer 15 and the second deep layer 17 can be comprised between 0.1 Ωcm and 20 Ωcm, and the doping levels of the first intermediate layer 16 and the second intermediate layer 18 can be comprised between 0.1 Ωcm and 20 Ωcm.

[0031] The high doping level of the first deep layer 15 means that, in use, the depletion region between the first deep layer 15 and the substrate 14 extends primarily into the substrate 14, thereby improving the electrical isolation of the components 5, 7 from the substrate 14.

[0032] Furthermore, the high doping level of the first deep layer 15 may enable the first deep layer 15 to be employed as a current conducting region for electronic components integrated within the die 3, for example when the silicon-based component 5 includes a BJT transistor.

[0033] If the electronic components 5, 7 are designed to operate at high voltages relative to the substrate 14, for example, 5 V applied to their respective terminals, with positive voltages starting from about 20 V relative to the substrate 14, for example described as 60 V, 100 V or 650 V, depending on the particular application and the type of doping used, the presence of both the first deep layer 15 and the second deep layer 17 can be useful to simplify the manufacture of the device 1 and to obtain excellent electrical performance of the device 1 during use.

[0034] The surface region 12 extends onto the second intermediate layer 18, in particular is in direct contact with said intermediate layer, and comprises a first device portion 20 in which the PMOS transistor 5A and the NMOS transistor 5B are integrated, and a second device portion 21 in which the HEMT 7 is integrated.

[0035] The first device part 20 has a top surface 20A and comprises an epitaxial region 23 made of a semiconductor material, in particular the same material as that of the second intermediate layer 18, here monocrystalline silicon.

[0036] Epitaxial region 23 extends from second intermediate layer 18, and here in direct contact with that intermediate layer, to upper surface 20A.

[0037] The thickness along the third axis Z, the conductivity type (eg, P or N), and the doping profile of the epitaxial region 23 may be selected at the design stage depending on the particular application of the device 1.

[0038] For example, in this embodiment, epitaxial region 23 is of N-type.

[0039] The first device portion 20 comprises a plurality of doped regions which extend into the epitaxial region 23 and form the functional region of the silicon-based electronic component 5 .

[0040] 1, P++ type doped regions 25A, 25B extend from top surface 20A into epitaxial region 23. Doped regions 25A, 25B form the source and drain regions, respectively, of PMOS transistor 5A and define channel region 26 of PMOS transistor 5A.

[0041] Additionally, N++ type doped region 27 extends from top surface 20A into epitaxial region 23 and forms a body contact region for PMOS transistor 5A.

[0042] With further reference to the embodiment of FIG. 1, a P-type doped region 28 extends from top surface 20A into epitaxial region 23 and forms the body region of NMOS transistor 5B.

[0043] N++ type doped regions 29A, 29B extend into doped region 28 and form the source and drain regions, respectively, of NMOS transistor 5B and define a channel region 30 of NMOS transistor 5B.

[0044] Additionally, a P++ type doped region 31 extends into doped region 28 and forms the body contact region of NMOS transistor 5B.

[0045] In practice, the doped regions 25A, 25B, 27, 29A, 29B, and 31, i.e., the doped source and drain regions, and the body contact region, have a peak concentration of, for example, 5·10 19 atoms / cm 3 ~5·10 20 atoms / cm 3 Alternatively, the doped region 28, i.e., the body region, may have a peak doping level of, for example, 1·10 16 atoms / cm 3 ~2·10 18 atoms / cm 3 is a lightly doped region having a doping level included in

[0046] The number, arrangement, shape, size, and doping profile of the doped regions may be selected at the design stage depending on the particular silicon-based electronic components 5 integrated within the die 3 and the particular application of the device 1.

[0047] An insulating portion 33 made of an insulating material, for example, an oxide, may extend from the upper surface 20A into the epitaxial region 23, depending on the particular application.

[0048] In particular, in FIG. 1, insulating portions 33 extend parallel to the first axis X between doped regions 27 and 25A, between 25B and 31, and between 31 and 29A.

[0049] A first insulating layer 35 , eg, an oxide or nitride layer, extends over the top surface 20 A of the first device portion 20 .

[0050] A second insulating layer 36 , for example an oxide layer, extends over the first insulating layer 35 .

[0051] The surface structure 38 of the silicon-based component 5 extends over and is in direct contact with the top surface 20A of the first device region 20. The surface structure 38 forms further functional areas of the silicon-based device 5 and may include various conductive and / or insulating regions depending on the particular silicon-based electronic component 5 integrated within the die 3.

[0052] In this embodiment, the surface structure 38 comprises insulated gate regions 40, 41 extending respectively above the channel region 26 of the PMOS transistor 5A and above the channel region 30 of the NMOS transistor 5B. In Figure 1, only the respective conductive regions, here polysilicon regions, of the insulated gate regions 40, 41 are shown for simplicity and are still indicated by 40, 41, each having a respective upper surface 40A, 41A.

[0053] Although not shown in FIG. 1, the insulated gate regions 40, 41 may also each include a respective insulating region disposed between the respective polysilicon region and the top surface 20A, and a respective contact region made of a conductive material, e.g., a metal, in contact with the respective surface 40A, 41A to form a respective gate terminal G.

[0054] In the embodiment of FIG. 1, the surface structure 38 also includes source contact regions 42, 43 and drain contact regions 44, 45 made of a conductive material, which extend through the first insulating layer 35 and the second insulating layer 36 and are in direct contact with the top surface 20A, thereby forming respective source terminals S and drain terminals D.

[0055] In particular, source contact regions 42, 43 extend in direct contact with source region 25A of PMOS transistor 5A and source region 29A of NMOS transistor 5B, respectively.

[0056] Furthermore, in the illustrated embodiment, the source contact regions 42, 43 also each extend into direct contact with a respective body contact region 27, 31.

[0057] Drain contact regions 44, 45 extend in direct contact with drain region 25B of PMOS transistor 5A and drain region 29B of NMOS transistor 5B, respectively.

[0058] The second device portion 21 of the surface region 12 has an upper surface 21A and comprises an epitaxial multilayer 49 extending onto and grown starting from the second intermediate layer 18.

[0059] The epitaxial multilayer 49 comprises a heterostructure 50 in which the HEMT 7 is integrated.

[0060] 1, the epitaxial multilayer 49 also comprises a transition region formed by overlapping first and second buffer layers 52, 53, here located between the second intermediate layer 18 and the heterostructure 50. This transition region may be useful during fabrication of the device 1 to favor the epitaxial growth of the heterostructure 50 on the second intermediate layer 18.

[0061] In particular, a first buffer layer 52, for example of aluminum nitride (AlN), extends over and is in direct contact with the second intermediate layer 18, and a second buffer layer 53, for example of aluminum gallium nitride (AlGaN), extends over and is in direct contact with the first buffer layer 52.

[0062] The heterostructure 50 comprises a compound semiconductor material including elements from groups III and V of the periodic table and forms the top surface 21A of the second device portion 21.

[0063] The top surface 21A of the second device portion 21 may extend at coordinates along a third axis Z that are the same as or different from the coordinates of the top surface 20A of the first device portion 20, depending on the particular manufacturing process used to produce the device 1.

[0064] In particular, in this embodiment, the top surface 21A of the second device portion 21 is arranged at a lower height, measured along the third axis Z, than the top surface 20A of the first device portion 20. This allows for improved manufacturing of the device 1.

[0065] The heterostructure 50 comprises a channel layer 55 and a barrier layer 56 which overlie one another.

[0066] The channel layer 55 is of a first semiconductor material, for example gallium nitride (GaN) or an alloy containing gallium nitride such as InGaN, here gallium nitride (GaN), extends over the transition region, in particular over the second buffer layer 53, and has an upper surface 55A.

[0067] The barrier layer 56 is made of a second semiconductor material, for example Al. x Ga 1-x N, AlInGaN, In x Ga 1-x N, Al x In 1-x A compound based on a ternary or quaternary alloy of gallium nitride, such as Al, AlScN, here aluminum gallium nitride (AlGaN), extends between an upper surface 55A of the channel layer 55 and an upper surface 21A of the second device portion 21.

[0068] The channel layer 55 and the barrier layer 56 may be intrinsic, P-type, or N-type, depending on the particular application. In particular, both the channel layer 55 and the barrier layer 56 may be of N-type.

[0069] For example, if the barrier layer 56 is of AlGaN, the presence of aluminum atoms can make the barrier layer 56 N-type.

[0070] The heterostructure 50 is configured to accommodate a two-dimensional gas (2DEG) of (mobile) charge carriers, in particular here electrons, located at the interface between the channel layer 55 and the barrier layer 56, i.e., at the upper surface 55A of the channel layer 55.

[0071] An insulating layer 58, for example of an oxide such as silicon oxide, having an upper surface 58A extends on the upper surface 21 A. The insulating layer 58 can for example have a thickness comprised between 20 nm and 1 μm.

[0072] Insulating layer 36 also extends over second device portion 21 , and in particular over insulating layer 58 .

[0073] The surface structure 60 of the heterostructure-based component 7 extends onto the upper surface 21A of the second device portion 21.

[0074] Depending on the particular heterostructure-based electronic component 7 integrated within the die 3, the surface structures 60 may be various conductive and / or insulating regions that form functional areas of the heterostructure-based component 7.

[0075] In this embodiment, in which the heterostructure-based electronic component 7 is a HEMT, the surface structure 60 comprises a source region 61 and a drain region 62 of conductive material extending at a distance from each other along a first axis X.

[0076] The source region 61 and the drain region 62 are in electrical contact, particularly ohmic contact, with the two-dimensional gas formed at the interface between the heterostructure 50, particularly the channel layer 55 and the barrier layer 56, and form the source terminal S and the drain terminal D, respectively, of the HEMT 7.

[0077] In the embodiment of FIG. 1, source region 61 and drain region 62 extend parallel to third axis Z through insulating layers 36, 58 to top surface 21A.

[0078] However, the source region 61 and the drain region 62 may extend parallel to the third axis Z and partially through the heterostructure 50, for example through a portion of the barrier layer 56 or through the entire thickness of the barrier layer 56, to the surface 55A, depending on the particular application.

[0079] The surface structure 60 also includes a gate structure, here formed by a channel modulation region 64 and a gate contact region 65, which can be biased to electrically control the formation of a two-dimensional gas in the heterostructure 50 between the source region 61 and the drain region 62. The gate structure forms the gate terminal G of the HEMT 7.

[0080] In this embodiment, the HEMT 7 is normally off, that is, is of the enhancement type.

[0081] In particular, in this embodiment, the channel modulation region 64 is of a semiconductor material and has a different conductivity type, e.g., P-type, than that of the barrier layer 56. In particular, the channel modulation region 64 may be made of p-type gallium nitride (p-GaN).

[0082] However, the channel modulation region 64 may also be formed by an ensemble of different materials including dielectric, metallic and / or semiconducting layers used as control electrodes with suitable work functions.

[0083] The channel modulation region 64 extends along the first axis X on the top surface 21A between the source region 61 and the drain region 62 and has a top surface 64A.

[0084] The top surface 64A of the channel modulation region 64 may extend at a coordinate along a third axis Z that is the same as or different from the coordinates at which the top surfaces 40A, 41A of the insulated gate regions 40, 41 extend, depending on the particular manufacturing process used to produce the device 1.

[0085] In particular, in this embodiment, the top surface 64A of the channel modulation region 64 is disposed at a distance from the second interlayer 18 measured along the third axis Z that is less than the distance of the top surfaces 40A, 41A of the insulated gate regions 40, 41 from the second interlayer 18 measured along the third axis Z. This may enable reliable fabrication of the device 1.

[0086] A gate contact region 65 of conductive material extends in electrical contact with channel modulation region 64, and here in particular in contact with top surface 64A.

[0087] Surface region 12 of die 3 further comprises a residual separation portion 70 extending over and in direct contact with second intermediate layer 18 between first device portion 20 and second device portion 21 .

[0088] As can be seen in the schematic top view of FIG. 2, a residual isolation portion 70 surrounds the second device portion 21 .

[0089] Referring again to FIG. 1, the residual separation portion 70 has an upper surface which, in this embodiment, is continuous with and in particular aligned with the upper surface 20A of the first device portion 20 and, as a result, is indicated by the same reference number.

[0090] The residual separation portion 70 is laterally adjacent, parallel to the first axis X, to the second device portion 21 .

[0091] In particular, the residual separation portion 70 has a first sidewall 71 adjacent to the first device portion 20 and a second sidewall 72 opposite the first sidewall 71 and adjacent to the second device portion 21 .

[0092] The residual isolation portion 70 includes a defined region 75, for example comprising an oxide, in particular silicon oxide, extending over and in direct contact with the second intermediate layer 18, and a polycrystalline region 76 of the same material (silicon) as the epitaxial region 23 of the first device portion 20, extending over and in direct contact with the defined region 75.

[0093] The defined area 75 may be formed by a single layer, for example an oxide layer, in particular a silicon oxide layer, or by another multilayer film, for example comprising one or more layers of oxide and / or one or more layers of nitride.

[0094] In particular, according to one embodiment, the defined area 75 may be made of silicon oxide.

[0095] According to different embodiments, the defined area 75 may comprise an oxide layer, in particular a silicon oxide layer, and a nitride layer.

[0096] According to one embodiment, the oxide layer may be in direct contact with the semiconductor layer 18 .

[0097] The defined area 75 may have a thickness along the third axis Z, for example, comprised between 7 nm and 300 nm, in particular between 70 Å and 200 Å.

[0098] In this embodiment, polycrystalline region 76 has a polycrystalline structure.

[0099] In this embodiment, polycrystalline region 76 is monolithic with epitaxial region 23 .

[0100] The slope of the first sidewall 71 may depend on the crystalline orientation of the epitaxial region 23 and the thickness of the defined region 75 along the third axis Z. For example, if the epitaxial region 23 has a crystalline orientation <111> When oriented according to, the first sidewall 71 may form an angle of approximately 54° with a direction parallel to the first axis X.

[0101] Polycrystalline region 76 extends a distance from top surface 20A.

[0102] An insulating region 77 of insulating material, eg, oxide, extends into the die 3 from the top surface 20A between the first device portion 20 and the second device portion 21.

[0103] In particular, the insulating region 77 extends parallel to the third axis Z from the top surface 20A within the epitaxial region 23 into the first device portion 20, and within the residual isolation portion 70 between the top surface 20A and the polycrystalline region 76.

[0104] In the embodiment of FIG. 1, epitaxial multilayer 49 includes a portion that conformally extends onto second sidewall 72 of residual isolation portion 70 forming raised surface 78 .

[0105] Raised surface 78 is disposed at a coordinate along third axis Z that is greater than the coordinate of top surface 21A, and here even greater than the coordinate of top surface 58A of insulating layer 58.

[0106] The shape and structure of the residual separation portion 70 may vary depending on the particular manufacturing process used to produce the device 1 .

[0107] The presence of a polycrystalline region (region 76) between the epitaxial multilayer (21) and the epitaxial region (23) may be useful in reducing stress caused by lattice mismatch between the material forming the epitaxial multilayer (e.g., GaN) and the material forming the epitaxial region (e.g., silicon). As a result, the presence of the polycrystalline region may contribute to reducing the risk of dislocations in die 3 (and thus possible destruction of device 1).

[0108] Device 1 allows the functionality of silicon-based component 5 and heterostructure-based component 7 to be combined in a single die while maintaining smaller dimensions relative to electronic devices in which silicon-based component 5 and heterostructure-based component 7 are integrated in different dies.

[0109] Furthermore, the electrical connections between the silicon-based components 5 and the heterostructure-based components 7 can be obtained directly on the die 3. This can ensure high electrical performance of the device 1, in use, for example in terms of switching speeds of the various components, minimal resistive losses in the electrical connections between them, and minimal effects of overvoltages due to the presence of parasitic inductances.

[0110] Below, steps for manufacturing the semiconductor electronic device 1 will be described with reference to FIGS. 3A to 3N.

[0111] Figure 3A shows a cross-section of a wafer 100 of monocrystalline semiconductor material, in particular silicon, having a top surface 100A. Elements of wafer 100 that are common to those already described with reference to Figure 1 are indicated with the same reference numerals and will not be described in further detail.

[0112] Wafer 100 comprises a substrate 14 upon which epitaxial layers 15, 16, 17, and 18 have already been grown.

[0113] The fourth epitaxial layer or second intermediate layer 18 forms the top surface 100 A of the wafer 100 .

[0114] The second intermediate layer 18 comprises a first portion 101A on which the first device portion 20 is intended to be formed, i.e. on which the PMOS transistor 5A and the NMOS transistor 5B are intended to be integrated, and a second portion 101B on which the second device portion 21 is intended to be formed, i.e. on which the epitaxial multilayer 49 is grown and on which the HEMT 7 is intended to be integrated.

[0115] Next (FIG. 3B), a definition layer 102, for example comprising an oxide, in particular a silicon oxide, is formed on the upper surface 100A.

[0116] Definition layer 102 may be formed by one or more layers of different materials as described for definition region 75 in FIG.

[0117] The definition layer 102 may have a small thickness along the third axis Z, for example comprised between 7 nm and 300 nm, in particular between 70 Å and 200 Å.

[0118] Definition layer 102 is intended to form definition area 75 (FIG. 1).

[0119] The definition layer 102 can be formed via oxidation of the surface portion of the second intermediate layer 18 or via deposition on the upper surface 100A. In case of oxidation, the thickness of the second intermediate layer 18 can be reduced compared to the thickness of the layer 18 of FIG. 3A and then the oxidation can be continued. However, considering that the thickness of the definition layer 102 is much smaller compared to the thickness of the second intermediate layer 18, for the sake of simplification, it can be assumed, as a first approximation, that the thickness of the second intermediate layer 18 remains the same before and after the oxidation.

[0120] Next (FIG. 3C), the definition layer 102 is removed in a first portion 101A of the second intermediate layer 18 (on which the first device portion 20 is intended to be formed), i.e. in the portion of the second intermediate layer 18 on which the epitaxial region 23 is intended to be formed. Thus, a portion of the definition layer 102 remains, hereinafter also referred to as the growth mask 103.

[0121] In practice, the growth mask 103 exposes a first portion 101A of the second intermediate layer 18 and covers a second portion 101B of the second intermediate layer 18 .

[0122] In FIG. 3D, a surface layer 105 of semiconductor material, in particular the same material as the second intermediate layer 18 (here, silicon), is grown on the wafer 100.

[0123] The surface layer 105 has an upper surface 105A.

[0124] The surface layer 105 includes the second intermediate layer 18, in particular epitaxial portions 106 growing parallel to the third axis Z from the respective first portions 101A, and a sacrificial portion 107 growing parallel to the third axis Z on the growth mask 103.

[0125] The epitaxial portion 106 grown from the single crystal substrate is intended to maintain the single crystal structure of the second intermediate layer 18 and to form the epitaxial region 23 of the first device portion 20 .

[0126] The sacrificial portion 107 is grown from an amorphous substrate and has a polycrystalline structure.

[0127] In FIG. 3E, a doped region 28 corresponding to the body region of NMOS transistor 5B and, optionally, an insulating layer 108 are formed in surface layer 105. In FIG.

[0128] In particular, the body region 28 is formed within the epitaxial portion 106 in which the silicon-based component 5 is formed.

[0129] The body region 28 may be formed via implantation of dopant ions.

[0130] An insulating layer 108, for example of silicon oxide, forms insulating portions 33 (FIG. 1) and portions 109 intended to form insulating regions 77 (FIG. 1).

[0131] The insulating layer 108 can be obtained through forming an insulating trench, e.g., shallow-trench insulation (STI), in the surface layer 105. In this case, the thickness of the epitaxial portion 106 and the thickness of the sacrificial portion 107 can be reduced as a result of the formation of the insulating layer 108.

[0132] Further, referring again to FIG. 3E, one or more surface layers 110 may be formed on the upper surface 105A of the surface layer 105 depending on the particular silicon-based electronic components 5 intended to be integrated within the die 3 of the device 1.

[0133] In the embodiment shown, the surface layer 110 is the layer intended to form the insulated gate regions 40, 41 (FIG. 1) of the PMOS transistor 5A and the NMOS transistor 5B. In particular, of the surface layer 110, only a single gate layer of polysilicon is shown here, still designated 110. However, an oxide layer (not shown here) is formed between the upper surface 105A and the polysilicon layer 110 in a manner known per se.

[0134] Polysilicon layer 110 has an upper surface 110A.

[0135] On the surface 110A of the gate layer 110, a sacrificial mask layer 111 having an upper surface 111A is also formed, for example, of an insulating material, for example a single insulating layer or an insulating multilayer film including one or more of silicon oxide, silicon nitride, aluminum oxide, and silicon carbide.

[0136] In FIG. 3F, an opening 113 is drilled above the sacrificial portion 107.

[0137] This opening 113 is formed by selectively removing portions of layers 110 , 111 , thus exposing the underlying sacrificial portion 107 .

[0138] The remaining portion of the sacrificial layer 111 can be used as an etch mask.

[0139] Next (FIG. 3G), the insulating layer 108 and the sacrificial portion 107 are removed in the openings 113 using an etching mask 111 .

[0140] Thus, the portion of sacrificial portion 107 that was located under the etch mask remains, and will form polycrystalline region 76 of FIG.

[0141] Following the etch of FIG. 3G, the recess formed in sacrificial portion 107 is continuous with opening 113, exposing portions of growth mask 103.

[0142] In Figure 3H, the exposed portions of the growth mask 103 are removed, thus leaving only those portions of the growth mask 103 located under the polycrystalline regions 76, i.e. the defined regions 75 in Figure 1.

[0143] Etching of the exposed portions of the growth mask 103 may be carried out using a selective chemistry that does not etch the underlying second intermediate layer 18 to a first approximation.

[0144] Thus, following the etch of FIG. 3H, opening 113 also exposes second portion 101B of second intermediate layer 18.

[0145] Next (FIG. 3I), a workpiece multilayer 114, intended to form the epitaxial multilayer 49 of FIG.

[0146] In particular, a first buffer layer, which corresponds to buffer layer 52 of Figure 1 and is consequently designated by the same reference numeral, is grown on wafer 100. First buffer layer 52 extends over exposed portions of top surface 100A, over second sidewall 72, and over etch mask 111.

[0147] A second buffer layer, which corresponds to buffer layer 53 in FIG. 1 and is therefore designated by the same reference number, is grown on the first buffer layer 52 .

[0148] A channel layer, which corresponds to channel layer 55 in FIG. 1 and is therefore designated by the same reference number, is grown on the second buffer layer 53 .

[0149] A barrier layer, which corresponds to barrier layer 56 in FIG. 1 and is therefore designated by the same reference number, is grown on channel layer 55 .

[0150] The workpiece multilayer 114 includes a raised portion 115 that extends over the etching mask 111 and onto the second sidewall 72 of the remaining portion 70 , and a useful portion 116 that extends directly onto the top surface 100 A of the second intermediate layer 18 .

[0151] The useful portion 116 has an upper surface 116A that is substantially flat, in particular substantially parallel to the upper surface 100A.

[0152] The useful portion 116 grown on the second intermediate layer 18 is of single crystal type and is used to integrate the heterostructure-based device 7 .

[0153] Next (FIG. 3J), the channel modulation region 64 is formed on the upper surface 116A of the useful part 116 in a manner known per se, for example by growing and defining certain layers.

[0154] In fact, in this embodiment, the useful portion 116 of the work multilayer 114 also includes the channel modulation region 64 .

[0155] Thus, here, surface 64A of modulation region 64 forms the most elevated surface of useful portion 116, ie the surface of useful portion 116 that is furthest along third axis Z from surface 100A.

[0156] The surface 110A over which the etching mask 111 extends may be located at a distance along the third axis Z from the surface 100A that is greater than the distance of the most elevated surface of the useful portion 116 and less than the distance of the surface 110A. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus to increase the reliability of the process for manufacturing the device 1.

[0157] A protective layer 118 of insulating material, for example a single insulating layer or an insulating multilayer including one or more of silicon oxide, silicon nitride, aluminum oxide, and silicon carbide, is formed on the barrier layer 56 (FIG. 3K). The protective layer 118 has a thickness along the third axis Z that is greater than the thickness of the channel modulation region 64, for example comprised between 10 nm and 500 nm.

[0158] In other words, the protective layer 118 completely covers the channel modulation region 64 .

[0159] The protective layer 118 has an upper surface 118A in the useful portion 116 that faces the upper surface 116A of the useful portion 116.

[0160] In this embodiment, the top surface 118A of the protective layer 118 extends to a height from the surface 100A along the third axis Z that is less than the height of the top surface 111A of the etch mask 111 from the surface 100A along the third axis Z. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus to increase the reliability of the process for fabricating the device 1.

[0161] Furthermore, in this embodiment, the distance along the third axis Z between the top surface 118A of the protection layer 118 and the top surface 64A of the channel modulation region 64 is greater than the thickness of the etching mask 111 along the third axis Z. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus to increase the reliability of the process for fabricating the device 1.

[0162] In FIG. 3L, raised portion 115 of workpiece multilayer 114 has been at least partially removed down to upper surface 111A of etching mask 111, thus exposing etching mask 111. In FIG.

[0163] Removal can be accomplished via planarization, for example chemical-mechanical polishing (CMP) or other etching techniques.

[0164] In the illustrated embodiment, after removal of the raised portion 115 of the workpiece multilayer 114, only the upwardly extending portion of the second sidewall 72 remains, forming a raised surface 78 that is flush with the upper surface 111A of the etching mask 111.

[0165] A portion of the protective layer 118 remains, again designated 118 , extending over the useful portion 116 of the workpiece multilayer 114 .

[0166] Next (FIG. 3M), the wafer 100 is etched to remove the etching mask 111 and thus expose the gate layer 110.

[0167] In this embodiment, the etching of the etching mask 111 also etches the protective layer 118, thus reducing its thickness. However, because the thickness of the etching mask 111 is smaller than the distance between the top surface 64 of the channel modulation region 64 and the top surface 118A of the protective layer 118, the remaining protective layer 118 still completely covers the channel modulation region 64. As a result, the channel modulation region 64 may not be damaged by the etching operation shown in FIG. 3M.

[0168] After etching, the protective layer 118 forms the insulating layer 58 described with reference to FIG.

[0169] Depending on the materials forming the etching mask 111 and the protective layer 118, and the materials of the particular etch used to remove the etching mask 111, the etching operation of FIG. 3M may selectively remove only the etching mask 111 and may not remove the protective layer 118.

[0170] Next (FIG. 3N), the gate layer 110 is defined, thus forming the insulated gate regions 40, 41. Furthermore, (highly) doped regions 25A, 25B, 27, 29A, 29B, 31 are formed in the epitaxial portion 106 of the surface layer 105. For example, they may be defined in successive operations of masking and ion implantation.

[0171] This is followed by fabrication steps not shown here to form insulating and / or passivation layers of wafer 100 (e.g., oxide layers 35, 36 in FIG. 1) and to form metal contact regions of electronic components 5, 7 (e.g., regions 42-45 and 61, 62, 65 in FIG. 1).

[0172] Further final manufacturing steps (not shown here) follow, such as formation of a top layer of metal interconnects and dicing of the wafer, thereby forming device 1.

[0173] The present manufacturing process allows the integration of both silicon-based electronic components 5 and heterostructure-based electronic components 7 within the same die, obtaining high crystallographic quality of the heterostructure 50.

[0174] Indeed, the use of the growth mask 103 makes it possible simultaneously to both grow the (single crystal) epitaxial portion 106 on which the silicon-based electronic component 5 is formed and to ensure the surface quality of the upper surface 100A below the growth mask 103 on which the workpiece multilayer 114 is grown.

[0175] The fact that the growth mask 103 comprises an oxide, in particular silicon oxide, may allow the growth mask 103 to be etchable by a different chemical species than the chemical species that can be used to remove the second intermediate layer 18. As a result, openings or recesses 113 through the sacrificial portions 107 exposing the underlying top surface 100A may be formed without affecting, at least to a first approximation, the quality of the surface 100A on which the epitaxial workpiece multilayer 114 (FIGS. 3G-3I) is grown. In particular, the fact that the growth mask 103 comprises a layer comprising an oxide in direct contact with the semiconductor layer 18 may make it possible to further reduce the risk of damage to the surface 100A on which the epitaxial workpiece multilayer 49 is grown.

[0176] In particular, the fact that the growth mask 103 is of silicon oxide and the layer 18 is of silicon makes it possible to obtain a highly selective etching rate of the growth mask 103 with respect to the silicon of the layer 18. Furthermore, it is also possible to use a wet etch to clean the surface 100A before growing the epitaxial workpiece multilayer 114.

[0177] In fact, the growth mask 103 can be used as an etch stop layer during etching of the overlying sacrificial portion 107, thus ensuring complete removal of the overlying sacrificial portion 107. In addition, the formation of openings in the growth mask 103 does not adversely affect the quality of the underlying surface 100A, e.g., in terms of terracing and pitting.

[0178] The epitaxial multilayer 49, and therefore the heterostructure 50, can exhibit high crystallographic quality.

[0179] As a result, the corresponding electronic components 7, whose function is based on the formation of a two-dimensional gas in the heterostructure 50, can have high electrical performance when in use.

[0180] At the same time, the electronic components 5 are also integrated in a monocrystalline silicon layer (epitaxial portion 106) which may have high crystallographic quality, so that the electronic components 5 may have high electrical performance when in use.

[0181] Furthermore, the thickness of the growth mask 103 can be made thick enough to be used as a mask for forming the epitaxial multilayer 49, and at the same time thin enough to minimize non-planarity of the top surface 105A of the superficial layer 105. In fact, the top surface 105A of the superficial layer 105 can be considered to be substantially flat. This facilitates subsequent fabrication steps leading to the formation of both the silicon-based electronic components 5 and the heterostructure-based electronic components 7.

[0182] As a starting substrate for forming a semiconductor electronic device 1 <111> The possibility of using a silicon substrate 14 may allow a high epitaxial quality of the heterostructure 50 to be obtained, especially when the channel layer 55 is of GaN. As a result, the heterostructure-based electronic component 7 may have excellent electrical performance. The applicant also <111> It has also been found that the use of a silicon substrate 14 makes it possible to obtain superior electrical performance of the silicon-based electronic component 5 .

[0183] Referring to the embodiment of the manufacturing process of Figures 3A to 3N, the fact that some of the doped regions of the silicon-based device 5, in particular the doped regions having high doping levels such as the source regions, drain regions and body contact regions of the PMOS transistor 5A and the NMOS transistor 5B, can be formed after the growth of the epitaxial multilayer film 49 can further contribute to increasing the reliability of the manufacturing of the device 1.

[0184] In fact, the epitaxial multilayer 49 can be grown using a thermal budget that is larger than the thermal budget that can be sustained by the highly doped regions. In this manner, the highly doped regions of the silicon-based device 5 can be formed with high reliability.

[0185] For example, the growth of the first buffer layer 52 of AlN may be performed at a temperature of about 1100°C over a time interval comprised between about 15 and 30 minutes, and the growth of the GaN and AlGaN layers forming the second buffer layer 53, the channel layer 55, the barrier layer 56 and the channel modulation region 64 may be performed in successive growth steps at temperatures between about 1030°C and 1080°C over intervals between about 5 and 15 minutes, respectively.

[0186] However, it will be apparent to one skilled in the art that the above-described manufacturing steps and the order in which they are performed may vary from that depicted in Figures 3A-3N depending on the particular process and machinery used.

[0187] For example, the epitaxial multilayer 49 may be grown before the surface layer 105 .

[0188] For example, epitaxial multilayer 49 may be grown after formation of the heavily doped region, depending on the particular materials forming epitaxial multilayer 49 and epitaxial region 23 .

[0189] For example, the body regions of the NMOS and PMOS transistors may be formed before the formation of the insulating oxide (33, 108) or after the formation of the field isolation (STI). In particular, they are formed before the formation of the oxide that forms the gate structures of the PMOS and NMOS transistors, i.e., before the deposition of, for example, the polysilicon layer 110.

[0190] For example, multilayer 114 may be selectively grown starting only from exposed portion 101B. In this case, portion 115 is not present. As a result, the removal depicted in FIG. 3L may not be necessary.

[0191] Finally, it will be apparent that other modifications and variations can be made to the electronic device 1 described and illustrated herein and its corresponding manufacturing process without departing from the scope of the present disclosure.

[0192] The electronic device 1 may comprise other silicon-based electronic components 5, active and / or passive, integrated within the die 3 in addition to or instead of the PMOS transistor 5A and the NMOS transistor 5B.

[0193] For example, as shown in Figure 2, the silicon-based electronic component 5 may also include a bipolar transistor 5C and passive components 5D, such as diodes and resistors, in which the bipolar transistor 5C and the passive components 5D are integrated within respective device portions 120, 121 that are separate from one another and are shown diagrammatically by dashed lines.

[0194] For example, device portions 120 , 121 are formed within respective epitaxial regions of single crystal silicon grown on substrate region 10 , and in particular are monolithic with epitaxial region 23 .

[0195] Insulating regions, for example shallow or deep trenches, may be arranged, in a manner known per se, between parts 120, 121 and 20, so that the respective electronic components are, in use, electrically insulated from one another.

[0196] Device 1 may also include other silicon-based electronic components 5 integrated within die 3 in addition to or instead of those shown in Figure 2. For example, components 5 may include MOS transistors for medium voltage applications, e.g., 15V to 20V, DMOS transistors and / or drift MOS transistors for applications with operating voltages, e.g., 20V to 200V, thin film resistors, OTP or MTP memory, phase change memory, etc.

[0197] It will be clear to a person skilled in the art that the integration of different types of silicon-based electronic components 5 can be obtained via manufacturing processes known per se and therefore not further illustrated here, for example using BCD technology.

[0198] For example, the conductivity types, N or P, of the various semiconductor regions may be reversed compared to that illustrated.

[0199] For example, the epitaxial multilayer 49 may include only the heterostructure 50. In other words, the heterostructure 50 may be grown directly on the substrate region 10.

[0200] For example, layers 14-18 may include one or more diffusion regions of a dopant species (P or N), depending on the particular application.

[0201] For example, the heterostructure-based components 7 may include electronic components other than HEMTs 7 .

[0202] For example, HEMT7 may be of the normally-off type and the gate structure may be different from that described above. For example, the gate structure may be of the recessed type and / or the fabrication of the gate structure may include the use of a fluorine plasma under the gate structure. Alternatively, HEMT7 may be of the normally-on type, i.e., of the depletion type.

[0203] 1, the insulating region 77 extending between the first device portion 20 and the second device portion 21 may have a different shape and structure than that shown. For example, there may be one or more trenches extending along the third axis Z at a greater depth within the die 3.

[0204] For example, the number of epitaxial layers forming substrate region 10 may vary depending on the particular application.

[0205] For example, depending on the desired thickness of the epitaxial multilayer 49 and the epitaxial region 23 along the third axis Z, the second intermediate layer 18 may be omitted and the epitaxial multilayer 49 may be grown directly on the second deep layer 17.

[0206] For medium or low voltage applications (e.g. 7V-40V), the substrate region 10 may comprise only the substrate 14 and the first deep layer 15 (or the first intermediate layer 16). Indeed, in this case, the epitaxial multilayer 49 can be grown directly on the first deep layer 15 or on the first intermediate layer 16, if any.

[0207] For example, the electronic component 5 may be an electronic component based on a single semiconductor other than silicon, such as Ge, SiGe, etc.

[0208] A process for manufacturing a semiconductor electronic device (1) includes providing a wafer (100) including a substrate layer (18) of a semiconductor material having a first portion (101A) and a second portion (101B) different from the first portion, growing an epitaxial region (23, 106) of a single semiconductor material on the first portion (101A) of the substrate layer, growing an epitaxial multilayer (49, 114) including a heterostructure (50) on the second portion (101B) of the substrate layer, and growing a heterostructure (50) on the epitaxial region (23, 106) of the single semiconductor material on the second portion (101B). and, starting from the heterostructure, forming a second electronic component (7) based on a heterostructure; and growing an epitaxial multilayer comprises forming a growth mask (103) on the substrate layer (18), forming an opening in the growth mask (103) thereby exposing a second portion of the substrate layer, and growing an epitaxial multilayer on the second portion of the substrate layer.

[0209] A growth mask (103) is formed prior to growing the epitaxial region, the growth mask exposing a first portion (101A) of the substrate layer (18).

[0210] Growing the epitaxial region includes growing a surface layer (105) of a single semiconductor material having a first portion (106) extending above the first portion (101A) of the substrate layer (18) and a second portion (107) extending above the growth mask (103), and forming an opening in the growth mask (103) includes forming a recess in the second portion (107) of the surface layer extending to the growth mask.

[0211] The manufacturing process further includes forming an etching mask (111) extending on a first portion (106) of the surface layer (105) and having an opening (113) on a second portion (107) of the surface layer (105), and growing the epitaxial multilayer includes growing a work multilayer (114) having a first portion (116) extending on a second portion (101B) of the substrate layer (18) and a second portion (115) extending on the etching mask, and removing the second portion (115) of the work multilayer, the etching mask (111) extending along a direction (Z) from a surface (110A) that is located at a height from the substrate layer (18) along the direction (Z) that is greater than the first portion (116) of the work multilayer.

[0212] The growth mask (103) comprises an oxide layer, for example silicon oxide.

[0213] The growth mask (103) has a thickness comprised between 7 nm and 300 nm.

[0214] Forming the first electronic component (5A, 5B) includes forming one or more doped regions (25A, 25B, 29A, 29B, 27, 31) in the epitaxial region (23, 106) after the step of growing the epitaxial multilayer.

[0215] The first electronic component is a MOS transistor (5A, 5B) having an insulated gate region (40, 41), and forming the first electronic component includes forming an insulated gate region (110) over the epitaxial region (23, 106) prior to the step of growing the epitaxial multilayer film.

[0216] The single semiconductor material is silicon, and the wafer (100) is <111> It is made of silicon.

[0217] The single semiconductor material is silicon and the substrate layer 18 is a layer of single crystal silicon.

[0218] A semiconductor electronic device (1) is summarized as comprising a die (3), a first electronic component (5) based on a single semiconductor material and a second electronic component (7) based on a heterostructure, the die comprising a substrate region (10) of a semiconductor material, a first surface portion (20) comprising a monocrystalline region (23) of the single semiconductor material extending over the substrate region, and a second surface portion (21) distinct from the first surface portion and comprising an epitaxial multilayer (49) extending over the substrate region, the epitaxial multilayer comprising a heterostructure (50), the first electronic component (5) being integrated in the first surface portion of the die and the second electronic component (7) being integrated in the second surface portion of the die.

[0219] The die (3) further includes a third surface portion (70) extending over the substrate region (10) between the first surface portion and the second surface portion, the third surface portion including a polycrystalline region (76) of the single semiconductor material that is monolithic with the single crystal region (23).

[0220] The first component is one of a CMOS transistor, a DMOS transistor, a bipolar transistor, or a passive electronic component based on a single semiconductor material.

[0221] The second electronic component is a high mobility transistor (7) in which the heterostructure is based on materials from groups III and V of the periodic table, including for example GaN.

[0222] The substrate region (10) includes a monocrystalline substrate (14) having a first conductivity type (P) and at least one epitaxial layer (15, 18) having a second conductivity type (N) different from the first conductivity type and extending over the substrate.

[0223] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts from various patents, applications, and publications to provide further embodiments.

[0224] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but rather to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. 1. A process for manufacturing a semiconductor electronic device, comprising: forming an epitaxial region of a single semiconductor material on a first portion of a substrate layer; forming an epitaxial multilayer including a heterostructure on a second portion of the substrate layer different from the first portion; forming a first electronic component within the epitaxial region; forming a second electronic component within the heterostructure; The formation of the epitaxial multilayer film includes: forming a growth mask on the substrate layer; forming an opening in the growth mask thereby exposing the second portion of the substrate layer; forming the epitaxial multilayer on the second portion of the substrate layer.

2. 2. The manufacturing process of claim 1, wherein the growth mask is formed prior to growing the epitaxial region, the growth mask exposing the first portion of the substrate layer.

3. 2. The manufacturing process of claim 1 , wherein forming the epitaxial region comprises growing a superficial layer of the single semiconductor material having a first portion extending above the first portion of the substrate layer and a second portion extending above the growth mask, and forming an opening in the growth mask comprises forming a recess in the second portion of the superficial layer extending to the growth mask.

4. forming an etching mask extending over the first portion of the surface layer and having an opening over the second portion of the surface layer; Forming an epitaxial multilayer film is growing a workpiece multilayer having a first portion extending over the second portion of the substrate layer and a second portion extending over the etch mask; removing the second portion of the workpiece multilayer; 4. The manufacturing process of claim 3, wherein the etching mask extends in a direction from a surface, the surface being disposed at a height in the direction from the substrate layer that is greater than the first portion of the workpiece multilayer.

5. The manufacturing process of claim 1 , wherein the growth mask comprises an oxide layer, for example silicon oxide.

6. The manufacturing process of claim 1 , wherein the growth mask has a thickness in the range of 7 nm to 300 nm.

7. 2. The manufacturing process of claim 1, wherein forming the first electronic component comprises forming a first doped region in the epitaxial region after forming the epitaxial multilayer.

8. 2. The manufacturing process of claim 1, wherein the first electronic component is a MOS transistor having an insulated gate region, and forming the first electronic component includes forming an insulated gate region over the epitaxial region prior to forming the epitaxial multilayer.

9. The manufacturing process of claim 1 , wherein the single semiconductor material is silicon.

10. 2. The manufacturing process of claim 1, wherein the single semiconductor material is silicon and the substrate layer is a single crystal silicon layer.

11. A device, comprising: Die and a first electronic component on a single semiconductor material; a second electronic component on the heterostructure, the second electronic component including a first conductive region coupled to the channel modulation region; The die includes: a substrate region of semiconductor material; a first surface portion including a single crystal region of the single semiconductor material extending over the substrate region; a second surface portion distinct from the first surface portion and including an epitaxial multilayer extending over the substrate region, the epitaxial multilayer including the heterostructure; the first electronic component is integrated within the first surface portion of the die, the second electronic component is integrated within the second surface portion of the die, and the channel modulation region is between the epitaxial multilayer and the first conductive region.

12. 12. The device of claim 11 , wherein the die further includes a third surface portion extending over the substrate region between the first surface portion and the second surface portion, the third surface portion including a polycrystalline region of the single semiconductor material monolithically with the single crystal region.

13. 12. The device of claim 11, wherein the first electronic component is one of a CMOS transistor, a DMOS transistor, a bipolar transistor, or a passive electronic component on the single semiconductor material.

14. The device of claim 11 , wherein the second electronic component is a high mobility transistor and the heterostructure is based on materials from groups III and V of the periodic table.

15. 12. The device of claim 11 , wherein the substrate region includes a single crystal substrate having a first conductivity type and at least one epitaxial layer having a second conductivity type different from the first conductivity type and extending over the substrate.

16. A substrate; A first portion on the substrate, the first portion comprising: an epitaxial region; a first portion including a first transistor extending in the epitaxial region along a first direction; a second portion on the substrate separated from the first portion along a second direction transverse to the first direction; a third portion on the substrate between the first portion and the second portion along the second direction, the third portion comprising: A definition layer; a polycrystalline region on the definition layer; and a third portion comprising the polycrystalline region on the definition layer.

17. The device of claim 16 , wherein the definition layer is a silicon oxide layer.

18. The device of claim 16 further comprising a second transistor in the second portion.

19. The second portion is a buffer layer on the substrate; a channel layer on the buffer layer; 17. The device of claim 16, further comprising a barrier layer on the channel layer.

20. a plurality of conductive regions on the barrier layer; 20. The device of claim 19, further comprising a channel modulation region between a first conductive region of the plurality of conductive regions and the barrier layer.

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