Manufacturing process for semiconductor electronic device including integrated different electronic components and semiconductor electronic device

Abstract

To provide a manufacturing process for a semiconductor electronic device including integrated different electronic components and the semiconductor electronic device.SOLUTION: In a semiconductor electronic device 1, an epitaxial region 23 of a single semiconductor material is grown on a first portion 20 of a substrate layer 14. An epitaxial multilayer 49 having a heterostructure 50 is grown on a second portion 21 of the substrate layer. A first electronic component 5 based on the single semiconductor material is formed from the epitaxial region, and a second electronic component 7 based on the heterostructure is formed from the heterostructure. Forming the first electronic component includes forming a plurality of doped regions 25A, 25B, 27, 29A, 29B, 31 in the epitaxial region after the step of growing the epitaxial multilayer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a manufacturing process for a semiconductor electronic device integrating different electronic components, and to a semiconductor electronic device. [Background technology]

[0002] Semiconductor electronic devices are known that include silicon-based active and / or passive electronic components, such as CMOS, DMOS, BJT transistors, diodes, resistors, etc., integrated within the same silicon die and fabricated, for example, using BCD (Bipolar-CMOS-DMOS) technology.

[0003] In fact, the functionality of these electronic components is based on the electronic properties of a single semiconductor material: silicon.

[0004] These devices monolithically integrate within the same die digital, analog, and power circuits that operate at voltages that are very different from each other, for example, from a few volts for CMOS transistors used to implement logic functions, to hundreds of volts for DMOS transistors used in power applications.

[0005] Silicon-based electronic components are <100> It is integrated on a single crystal silicon region grown on a silicon wafer.

[0006] Semiconductor electronic devices including electronic components based on heterostructures, such as HEMT transistors, are also known.

[0007] In fact, the operation of these electronic components is based on the electronic properties of a heterojunction between two different semiconductor materials.

[0008] In particular, in HEMT transistors, the conductive channel is based on the formation of a layer of a high-mobility two-dimensional electron gas (2DEG) at a heterojunction, i.e., at the interface between semiconductor materials with different bandgaps. For example, HEMT devices based on a heterojunction between an aluminum gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer are known.

[0009] In particular, HEMT devices based on AlGaN / GaN heterostructures or heterojunctions offer various advantages that make them particularly suitable and widely used for different applications. For example, the high breakdown threshold of HEMT devices can be utilized for high performance power switches, the high mobility of electrons in the conductive channel allows high frequency amplifiers to be formed, and the high concentration of electrons in the 2DEG allows low on-state resistance (R ON ) can be obtained.

[0010] Furthermore, HEMT devices for radio frequency (RF) applications typically have better RF performance than similar silicon LDMOS devices.

[0011] Electronic components based on heterostructures include: <111> They are integrated into heterostructures epitaxially grown on silicon wafers or on sapphire (Al2O3) or silicon carbide (SiC) substrates.

[0012] In order to use a simple and low-cost manufacturing process, the heterostructure-based electronic components and the silicon-based electronic components are integrated into different dies starting from two different silicon wafers, in this way the manufacturing process of the silicon-based components and the manufacturing process of the heterostructure-based components do not affect each other.

[0013] For example, heterostructures can be grown using high thermal budgets without damaging silicon-based components.

[0014] However, this causes electronic devices incorporating both silicon-based and heterostructure-based components to have high area occupancy and therefore high manufacturing costs, high power consumption, and poor electrical performance due to, for example, parasitic capacitance, resistance, or inductance introduced by the electrical connections between the dies.

[0015] According to one approach, a die having silicon-based components formed therein and a die having heterostructure-based components formed therein are bonded together by die transfer techniques.

[0016] However, even this approach has drawbacks in terms of cost of use, and reliability of manufacturing and electrical performance. Summary of the Invention

[0017] Thus, according to the present disclosure, a process for manufacturing a semiconductor electronic device and a semiconductor electronic device are provided, comprising forming an epitaxial region of a single semiconductor material on a first portion of a substrate layer having a first portion and a second portion, the epitaxial region having a first surface opposite the substrate layer. The process comprises forming an epitaxial multilayer including a heterostructure on a second portion of the substrate layer, forming an isolation portion between the epitaxial region and the epitaxial multilayer, the isolation portion having a second surface coplanar with the first surface, and forming a first electronic component on the epitaxial region. The process comprises forming the second electronic component on the heterostructure, the forming the first electronic component comprising forming a plurality of doped regions in the epitaxial region after forming the epitaxial multilayer. [Brief description of the drawings]

[0018] For a better understanding of the present disclosure, embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which: [Figure 1] 1 illustrates a cross-sectional view of a semiconductor electronic device according to an embodiment. [Diagram 2] FIG. 2 shows a top view of the device of FIG. 1. [Figure 3A] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3B] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3C] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3D] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3E] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3F] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3G] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3H] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3I] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3J] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3K] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3L] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3M] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. [Figure 3N] 2 shows a cross-section of the device of FIG. 1 at a subsequent manufacturing stage. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The following description refers to the orientation illustrated in the accompanying drawings, and therefore, terms such as "upper", "lower", "bottom", "upper", "right", "left", "high", "low" and the like, are with respect to the accompanying drawings and should not be construed as limiting.

[0020] 1 and 2 show a semiconductor electronic device (hereinafter simply referred to as device) 1 in a Cartesian coordinate system XYZ having a first axis X, a second axis Y and a third axis Z.

[0021] The device 1 is formed in a die 3 and comprises one or more silicon-based electronic components 5, shown in FIG. 1 as a PMOS transistor 5A and an NMOS transistor 5B, and one or more heterostructure-based electronic components, shown in FIG. 1 as a HEMT transistor 7, all integrated on the die 3.

[0022] The die 3 comprises a substrate area 10 and a surface area 12 which extends over the substrate area 10 and in particular is in direct contact with the substrate area 10 .

[0023] Substrate region 10 comprises a substrate 14 and one or more epitaxial layers disposed on substrate 14 .

[0024] Substrate 14 is a substrate of a semiconductor material, particularly a single crystal material, and has an upper surface 14A.

[0025] In particular, in this embodiment, the substrate 14 is <111> It is of single crystal silicon oriented according to a crystal direction, and in particular the top surface 14A is oriented according to that crystal direction.

[0026] In this embodiment, the substrate region 10 comprises a first epitaxial layer or first deep layer 15 overlying the upper surface 14A of the substrate 14, a second epitaxial layer or first intermediate layer 16 overlying the first deep layer 15, a third epitaxial layer or second deep layer 17 overlying the first intermediate layer 16, and a fourth epitaxial layer or second intermediate layer 18 overlying the second intermediate layer 17.

[0027] The epitaxial layers 15-18 are of a semiconductor material, in particular a material identical to that of the substrate 14 (here silicon), and are identified by dashed lines in FIG. 1 for the sake of clarity.

[0028] The thickness along the third axis Z, conductivity type (eg, P or N), and doping profile of the substrate 14 and epitaxial layers 15-18 may be selected at the design stage depending on the particular application of the device 1.

[0029] For example, the epitaxial layers 15 to 18 may each have a thickness comprised between 0.1 μm and 7 μm.

[0030] For example, in this embodiment, the substrate 14 is of the P type, for example having a resistivity comprised between 0.1 Ω·cm and 20 Ω·cm, and the epitaxial layers 15-18 are of the N type. In this way, the first deep layer 15 can form a PN junction with the substrate 14, which can be used, in use, to isolate the devices 5, 7 integrated in the die 3 from the substrate 14.

[0031] The first deep layer 15 and the second deep layer 17 can have a doping level equal to or different from, in particular higher than, the first intermediate layer 16 and the second intermediate layer 18. For example, the doping level of the first deep layer 15 and the second deep layer 17 can be comprised between 0.1 Ω·cm and 20 Ω·cm, and the doping level of the first intermediate layer 16 and the second intermediate layer 18 can be comprised between 0.1 Ω·cm and 20 Ω·cm.

[0032] Due to the high doping level of the first deep layer 15, in use the depletion region between the first deep layer 15 and the substrate 14 extends primarily into the substrate 14, thereby improving the electrical isolation of the components 5, 7 from the substrate 14.

[0033] Furthermore, the high doping level of the first deep layer 15 may enable the first deep layer 15 to be used as a current conducting region for electronic components integrated within the die 3, for example when the silicon-based component 5 includes a BJT transistor.

[0034] If the electronic components 5, 7 are designed to operate at high voltages relative to the substrate 14, for example, 5 V applied to each end, which may be described as a positive voltage from about 20 V to the substrate 14, for example 60 V, 100 V, or 650 V, depending on the particular application and type of doping used, the presence of both the first deep layer 15 and the second deep layer 17 may be useful to simplify the manufacture of the device 1 and to obtain superior electrical performance of the device 1 during use.

[0035] The surface region 12 extends onto the second intermediate layer 18, in particular is in direct contact with said intermediate layer, and comprises a first device portion 20 in which the PMOS transistor 5A and the NMOS transistor 5B are integrated, and a second device portion 21 in which the HEMT transistor 7 is integrated.

[0036] The first device portion 20 has a top surface 20A and comprises an epitaxial region 23 of a semiconductor material, in particular the same material as the second intermediate layer 18, here monocrystalline silicon.

[0037] Epitaxial region 23 extends from second intermediate layer 18, and here in direct contact with that intermediate layer, to upper surface 20A.

[0038] The thickness along the third axis Z, the conductivity type (eg, P or N), and the doping profile of the epitaxial region 23 may be selected at the design stage depending on the particular application of the device 1.

[0039] For example, in this embodiment, epitaxial region 23 is of N-type.

[0040] The first device portion 20 extends into the epitaxial region 23 and comprises a number of doped regions which form the functional region of the silicon-based electronic component 5 .

[0041] 1, P++ type doped regions 25A, 25B extend from top surface 20A into epitaxial region 23. Doped regions 25A, 25B form the source and drain regions, respectively, of PMOS transistor 5A and define channel region 26 of PMOS transistor 5A.

[0042] Additionally, N++ type doped region 27 extends from top surface 20A into epitaxial region 23 and forms a body contact region for PMOS transistor 5A.

[0043] With further reference to the embodiment of FIG. 1, a P-type doped region 28 extends from top surface 20A into epitaxial region 23 and forms the body region of NMOS transistor 5B.

[0044] N++ type doped regions 29A, 29B extend into doped region 28 and form the source and drain regions, respectively, of NMOS transistor 5B and define a channel region 30 of NMOS transistor 5B.

[0045] Additionally, a P++ type doped region 31 extends into doped region 28 and forms the body contact region of NMOS transistor 5B.

[0046] In practice, the doped regions 25A, 25B, 27, 29A, 29B, and 31, i.e., the source and drain doped regions and the body contact region, have a peak concentration of, for example, 5·10 19 atoms / cm -3 ~5·10 20 atoms / cm -3 Conversely, the doped region 28, i.e., the body region, has a peak doping level of, for example, 1·10 16 atoms / cm -3 ~2·1018 atoms / cm -3 is a lightly doped region having a doping level included in

[0047] The number, arrangement, shape, size, and doping profile of the doped regions may be selected at the design stage depending on the particular silicon-based electronic components 5 integrated on the die 3 and the particular application of the device 1.

[0048] An insulating portion 33 of insulating material, eg, oxide, may extend from upper surface 20A into epitaxial region 23, depending on the particular application.

[0049] In particular, in FIG. 1, insulating portions 33 extend parallel to the first axis X between doped regions 27 and 25A, between 25B and 31, and between 31 and 29A.

[0050] A first insulating layer 35 of, for example, oxide or nitride, extends over the top surface 20A of the first device portion 20.

[0051] A second insulating layer 36 of, for example, oxide, extends over the first insulating layer 35 .

[0052] The surface structure 38 of the silicon-based component 5 extends over and is in direct contact with the top surface 20A of the first device region 20. The surface structure 38 forms further functional areas of the silicon-based device 5 and may include various conductive and / or insulating regions depending on the particular silicon-based electronic component 5 integrated within the die 3.

[0053] In this embodiment, the surface structure 38 comprises gate insulating regions 40, 41 extending respectively above the channel region 26 of the PMOS transistor 5A and above the channel region 30 of the NMOS transistor 5B. For simplicity, only the respective conductive regions of the gate insulating regions 40, 41, here polysilicon, again designated 40, 41, each having a respective upper surface 40A, 41A, are shown in FIG.

[0054] Although not shown in FIG. 1, gate insulating regions 40, 41 may also each include a respective insulating region disposed between a respective polysilicon region and top surface 20A, and a respective contact region of conductive material, e.g., metal, in contact with respective surface 40A, 41A to form a respective gate terminal G.

[0055] In the embodiment of FIG. 1, the surface structure 38 also includes source contact regions 42, 43 and drain contact regions 44, 45 of conductive material that extend through the first and second insulating layers 35, 36 and are in direct contact with the top surface 20A to form respective source S and drain D terminals.

[0056] In particular, source contact regions 42, 43 extend in direct contact with source region 25A of PMOS transistor 5A and source region 29A of NMOS transistor 5B, respectively.

[0057] Furthermore, in the illustrated embodiment, the source contact regions 42, 43 each also extend into direct contact with a respective body contact region 27, 31.

[0058] Drain contact regions 44, 45 extend in direct contact with drain region 25B of PMOS transistor 5A and drain region 29B of NMOS transistor 5B, respectively.

[0059] The second device portion 21 of the surface region 12 has an upper surface 21A and includes an epitaxial multilayer 49 extending onto and grown from the second intermediate layer 18.

[0060] The epitaxial multilayer 49 comprises a heterostructure 50 in which the HEMT transistor 7 is integrated.

[0061] 1, the epitaxial multilayer 49 also comprises a transition region formed therein by superimposed first and second buffer layers 52, 53 disposed between the second intermediate layer 18 and the heterostructure 50. This transition region may be useful during fabrication of the device 1 to favor epitaxial growth of the heterostructure 50 on the second intermediate layer 18.

[0062] In particular, a first buffer layer 52, for example of aluminum nitride (AlN), extends over and is in direct contact with the second intermediate layer 18, and a second buffer layer 53, for example of aluminum gallium nitride (AlGaN), extends over and is in direct contact with the first buffer layer 52.

[0063] The heterostructure 50 comprises a compound semiconductor material containing elements from groups III and V of the periodic table and forms the top surface 21A of the second device portion 21.

[0064] The top surface 21A of the second device portion 21 may extend at coordinates along a third axis Z that are equal to or different from the coordinates of the top surface 20A of the first device portion 20, depending on the particular manufacturing process used to produce the device 1.

[0065] In particular, in this embodiment, the top surface 21A of the second device portion 21 is disposed at a lower height, measured along the third axis Z, relative to the top surface 20A of the first device portion 20. This may allow for improved manufacturing of the device 1.

[0066] The heterostructure 50 comprises a channel layer 55 and a barrier layer 56 which overlie one another.

[0067] The channel layer 55 is made of a first semiconductor material, for example gallium nitride (GaN) or an alloy containing gallium nitride such as InGaN, here gallium nitride (GaN), extends over the transition region, in particular over the second buffer layer 53, and has an upper surface 55A.

[0068] The barrier layer 56 is made of a second semiconductor material, for example Al. x Ga 1-x N, AlInGaN, In x Ga 1-x N, Al x In 1-x A compound based on a ternary or quaternary alloy of gallium nitride, such as Al, AlScN, here aluminum gallium nitride (AlGaN), extends between an upper surface 55A of the channel layer 55 and an upper surface 21A of the second device portion 21.

[0069] The channel layer 55 and the barrier layer 56 may be intrinsic, P-type, or N-type, depending on the particular application. In particular, both the channel layer 55 and the barrier layer 56 may be N-type.

[0070] For example, if the barrier layer 56 is of AlGaN, the presence of aluminum atoms can make the barrier layer 56 N-type.

[0071] The heterostructure 50 is configured to accommodate a two-dimensional gas (2DEG) of (mobile) charge carriers, in particular here electrons, located at the interface between the channel layer 55 and the barrier layer 56, i.e., at the upper surface 55A of the channel layer 55.

[0072] An insulating layer 58 having an upper surface 58A of, for example, an oxide, such as, for example, silicon oxide, extends over the upper surface 21A.

[0073] The insulating layer 36 also extends over the second device portion 21, in particular over the insulating layer 58. The insulating layer 58 may have a thickness comprised, for example, between 20 nm and 1 μm.

[0074] The surface structure 60 of the heterostructure-based component 7 extends onto the upper surface 21A of the second device portion 21.

[0075] Depending on the particular heterostructure-based electronic component 7 integrated within the die 3, the surface structures 60 may be various conductive and / or insulating regions that form functional areas of the heterostructure-based component 7.

[0076] In this embodiment, in which the heterostructure-based electronic component 7 is a HEMT transistor, the surface structure 60 comprises a source region 61 and a drain region 62 of conductive material extending at a distance from each other along a first axis X.

[0077] The source region 61 and the drain region 62 are in electrical contact, in particular ohmic contact, with the heterostructure 50 and in particular with the two-dimensional gas formed at the interface between the channel layer 55 and the barrier layer 56, and form the source terminal S and the drain terminal D, respectively, of the HEMT transistor 7.

[0078] In the embodiment of FIG. 1, source region 61 and drain region 62 extend parallel to third axis Z through insulating layers 36, 58 to top surface 21A.

[0079] However, the source region 61 and the drain region 62 may extend parallel to the third axis Z and partially through the heterostructure 50, for example to a portion of the barrier layer 56 or throughout the entire thickness of the barrier layer 56 to the surface 55A, depending on the particular application.

[0080] The surface structure 60 also includes a gate structure, here formed by a channel modulation region 64 and a gate contact region 65, which can be biased to electrically control the formation of a two-dimensional gas in the heterostructure 50 between the source region 61 and the drain region 62. The gate structure forms the gate terminal G of the HEMT transistor 7.

[0081] In this embodiment, the HEMT transistor 7 is a normally-off type, that is, an enhancement type transistor.

[0082] In particular, in this embodiment, the channel modulation region 64 is of a semiconductor material and has a different conductivity type, e.g., P-type, relative to the barrier layer 56. In particular, the channel modulation region 64 may be p-type gallium nitride (p-GaN).

[0083] However, the channel modulation region 64 may be formed by a different set of materials including dielectric layers, metallic layers, and / or semiconductor layers used as control electrodes having appropriate work functions.

[0084] The channel modulation region 64 extends along the first axis X on the top surface 21A between the source region 61 and the drain region 62 and has a top surface 64A.

[0085] The upper surface 64A of the channel modulation region 64 may extend at coordinates along a third axis Z that are equal to or different from the coordinates of the upper surfaces 40A, 41A of the gate insulation regions 40, 41, depending on the particular manufacturing process used to fabricate the device 1.

[0086] In particular, in this embodiment, the top surface 64A of the channel modulation region 64 is disposed at a distance, measured along the third axis Z, from the second intermediate layer 18 that is smaller than a distance, measured along the third axis Z, of the top surfaces 40A, 41A of the gate insulating regions 40, 41 from the second intermediate layer 18. This can improve the reliability of the manufacture of the device 1.

[0087] A gate contact region 65 of conductive material extends in electrical contact with channel modulation region 64, and here in particular in contact with top surface 64A.

[0088] Surface region 12 of die 3 also includes a residual separation portion 70 extending over and in direct contact with second intermediate layer 18 between first device portion 20 and second device portion 21 .

[0089] As can be seen in the schematic top view of FIG. 2, a residual isolation portion 70 surrounds the second device portion 21 .

[0090] Referring again to FIG. 1, the residual separation portion 70 has an upper surface which, in this embodiment, is continuous with and in particular aligned with the upper surface 20A of the first device portion 20 and, as a result, is indicated by the same reference number.

[0091] The residual separation portion 70 is laterally adjacent to the second device portion 21, parallel to the first axis X.

[0092] In particular, the residual separation portion 70 has a first sidewall 71 adjacent to the first device portion 20 and a second sidewall 72 opposite the first sidewall 71 and adjacent to the second device portion 21 .

[0093] The residual isolation portion 70 includes a defined region 75, for example comprising an oxide, in particular silicon oxide, extending over and in direct contact with the second intermediate layer 18, and a polycrystalline region 76 of the same material (silicon) as the epitaxial region 23 of the first device portion 20, extending over and in direct contact with the defined region 75.

[0094] The defined area 75 may be formed, for example, by a single layer of oxide, in particular silicon oxide, or by a multilayer film, for example comprising one or more layers of oxide and / or one or more layers of nitride.

[0095] In particular, according to one embodiment, the defined area 75 may be silicon oxide.

[0096] According to different embodiments, the defined area 75 may comprise an oxide layer, in particular silicon oxide, and a nitride layer. According to one embodiment, the oxide layer may be in direct contact with the semiconductor layer 18.

[0097] The defined area 75 may have a thickness along the third axis Z, for example, comprised between 7 nm and 300 nm, in particular between 70 Å and 200 Å.

[0098] In this embodiment, polycrystalline region 76 has a polycrystalline structure.

[0099] In this embodiment, polycrystalline region 76 is monolithic with epitaxial region 23 .

[0100] The slope of the first sidewall 71 may depend on the crystal orientation of the epitaxial region 23 and the thickness of the defined region 75 along the third axis Z. For example, if the epitaxial region 23 is <111> When oriented according to the crystallographic directions, the first sidewall 71 may form an angle with a direction parallel to the first axis X of approximately 54°.

[0101] Polycrystalline region 76 extends a distance from top surface 20A.

[0102] An insulating region 77 of insulating material, eg, oxide, extends into the die 3 from the top surface 20A between the first device portion 20 and the second device portion 21.

[0103] In particular, the insulating region 77 extends parallel to the third axis Z from the top surface 20A within the epitaxial region 23 into the first device portion 20 and extends within the residual isolation portion 70 between the top surface 20A and the polycrystalline region 76.

[0104] In the embodiment of FIG. 1, epitaxial multilayer 49 includes a portion that conformally extends onto second sidewall 72 of residual isolation portion 70 forming raised surface 78 .

[0105] The raised surface 78 is disposed at a coordinate along the third axis Z that is greater than the upper surface 21A, and here even greater than the upper surface 58A of the insulating layer 58.

[0106] The shape and structure of the residual separation portion 70 may vary depending on the particular manufacturing process used to produce the device 1 .

[0107] The presence of polycrystalline region 76 between epitaxial multilayer 21 and epitaxial region 23 may be useful to reduce stress caused by lattice mismatch between the material forming the epitaxial multilayer (e.g., GaN) and the material forming the epitaxial region (e.g., silicon). As a result, the presence of the polycrystalline region may contribute to reducing the risk of dislocations in die 3 (and thus possible destruction of device 1).

[0108] Device 1 allows the functionality of silicon-based components 5 and heterostructure-based components 7 to be combined in a single die while maintaining small dimensions relative to electronic devices in which the silicon-based components 5 and heterostructure-based components 7 are integrated on different dies.

[0109] Furthermore, the electrical connections between the silicon-based components 5 and the heterostructure-based components 7 can be made directly on the die 3. This ensures high electrical performance of the device 1, in use, e.g. in terms of switching speed of the various components, minimal resistive losses associated with the electrical connections between them, and minimal overvoltage effects due to the presence of parasitic inductances.

[0110] The manufacturing process of the semiconductor electronic device 1 will be described below with reference to FIGS. 3A to 3N.

[0111] Figure 3A shows a cross-section of a wafer 100 of monocrystalline semiconductor material, in particular silicon, having a top surface 100A. Elements of wafer 100 that are common to those already described with reference to Figure 1 are indicated with the same reference numerals and will not be described in further detail.

[0112] Wafer 100 comprises a substrate 14 having epitaxial layers 15, 16, 17, and 18 already grown on the substrate 14.

[0113] The fourth epitaxial layer or second intermediate layer 18 forms the top surface 100 A of the wafer 100 .

[0114] The second intermediate layer 18 comprises a first portion 101A, on which the first device portion 20 is intended to be formed, i.e. on which the PMOS 5A and NMOS 5B transistors are intended to be integrated, and a second portion 101B, on which the second device portion 21 is intended to be formed, i.e. on which the epitaxial multilayer 49 is grown and on which the HEMT transistor 7 is intended to be integrated.

[0115] Subsequently, in FIG. 3B, a definition layer 102, for example comprising an oxide, in particular a silicon oxide, is formed on the upper surface 100A.

[0116] Definition layer 102 may be formed by one or more layers of different materials, as described for definition region 75 in FIG.

[0117] The definition layer 102 may have a small thickness along the third axis Z, for example comprised between 7 nm and 300 nm, in particular between 70 Å and 200 Å.

[0118] Definition layer 102 is intended to form definition area 75 (FIG. 1).

[0119] The definition layer 102 can be formed by oxidation of a surface portion of the second intermediate layer 18 or by deposition on the upper surface 100A. In the case of oxidation, the thickness of the second intermediate layer 18 can be reduced in response to the oxidation on the layer 18 of FIG. 3A. However, considering the much smaller thickness of the definition layer 102 relative to the thickness of the second intermediate layer 18, for simplicity, it can be assumed, as a first approximation, that the thickness of the second intermediate layer 18 remains the same before and after oxidation.

[0120] 3C, the definition layer 102 is then removed in a first portion 101A of the second intermediate layer 18 (on which the first device portion 20 is intended to be formed), i.e. in the portion of the second intermediate layer 18 on which the epitaxial region 23 is intended to be formed. Thus, a portion of the definition layer 102 remains, hereinafter also referred to as the growth mask 103.

[0121] In practice, the growth mask 103 exposes a first portion 101A of the second intermediate layer 18 and covers a second portion 101B of the second intermediate layer 18 .

[0122] In FIG. 3D, a surface layer 105 of semiconductor material, in particular the same material as the second intermediate layer 18 (here, silicon), is grown on the wafer 100.

[0123] The surface layer 105 has an upper surface 105A.

[0124] The surface layer 105 includes an epitaxial portion 106 growing parallel to the third axis Z from the second intermediate layer 18, in particular from each first portion 101A, and a sacrificial portion 107 growing parallel to the third axis Z on the growth mask 103.

[0125] The epitaxial portion 106 grown from the single crystal substrate is intended to maintain the single crystal structure of the second intermediate layer 18 and to form the epitaxial region 23 of the first device portion 20 .

[0126] The sacrificial portion 107 is grown from an amorphous substrate and has a polycrystalline structure.

[0127] In FIG. 3E, a doped region 28 corresponding to the body region of NMOS transistor 5B and, optionally, an insulating layer 108 are formed in surface layer 105. In FIG.

[0128] In particular, the body region 28 is formed within the epitaxial portion 106 in which the silicon-based component 5 is formed.

[0129] The body region 28 may be formed by doping ion implantation.

[0130] An insulating layer 108, for example of silicon oxide, forms insulating portions 33 (FIG. 1) and portions 109 intended to form insulating regions 77 (FIG. 1).

[0131] The insulating layer 108 may be formed by forming an insulating trench, e.g., Shallow Trench Isolation (STI), in the surface layer 105. In this case, the thickness of the epitaxial portion 106 and the thickness of the sacrificial portion 107 may be reduced in response to the formation of the insulating layer 108.

[0132] Additionally, referring again to FIG. 3E, one or more surface layers 110 may be formed on the top surface 105A of the surface layer 105 according to the particular silicon-based electronic components 5 desired to be integrated onto the die 3 of the device 1.

[0133] In the embodiment shown, the surface layer 110 is the layer intended to form the gate insulating regions 40, 41 (FIG. 1) of the PMOS transistor 5A and the NMOS transistor 5B. In particular, of the surface layer 110, only a single gate layer of polysilicon, still designated here by 110, is shown here. However, an oxide layer, not shown here, is formed between the upper surface 105A and the polysilicon layer 110 in a manner known per se.

[0134] Polysilicon layer 110 has an upper surface 110A.

[0135] A mask sacrificial layer 111, e.g., of an insulating material, e.g., a single layer or an insulating multilayer, including one or more of silicon oxide, silicon nitride, aluminum oxide, and silicon carbide, having an upper surface 111A, is also formed on the surface 110A of the gate layer 110.

[0136] In FIG. 3F, an opening 113 is drilled above the sacrificial portion 107.

[0137] The opening 113 is formed by selectively removing portions of layers 110 , 111 , thereby exposing the underlying sacrificial portion 107 .

[0138] The remaining portion of the sacrificial layer 111 can be used as an etch mask.

[0139] Subsequently, as shown in FIG. 3G, the insulating layer 108 and the sacrificial portion 107 are removed in the openings 113 using the etching mask 111.

[0140] Thus, the portion of sacrificial portion 107 that was located under the etch mask remains, and will form polycrystalline region 76 of FIG.

[0141] Following the etching of FIG. 3G, the recess formed in the sacrificial portion 107 is continuous with the opening 113 and exposes a portion of the growth mask 103 .

[0142] In Fig. 3H, the exposed portions of the growth mask 103 are removed, thus leaving only those portions of the growth mask 103 that are disposed under the workpiece polycrystalline region 76, i.e. the defined region 75 in Fig. 1 .

[0143] Etching of the exposed portions of the growth mask 103 may be carried out using selective chemistries that do not etch the underlying second intermediate layer 18 to a first approximation.

[0144] Thus, following the etch of FIG. 3H, opening 113 also exposes second portion 101B of second intermediate layer 18.

[0145] Next, in FIG. 3I, a workpiece multilayer 114, intended to form the epitaxial multilayer 49 of FIG.

[0146] In particular, a first buffer layer, which corresponds to buffer layer 52 of Figure 1 and is therefore designated by the same reference numeral, is grown on wafer 100. First buffer layer 52 extends over exposed portions of top surface 100A, over second sidewall 72, and over etch mask 111.

[0147] A second buffer layer, which corresponds to buffer layer 53 in FIG. 1 and is therefore designated by the same reference number, is grown on the first buffer layer 52 .

[0148] A channel layer, which corresponds to channel layer 55 in FIG. 1 and is therefore designated by the same reference number, is grown on the second buffer layer 53 .

[0149] A barrier layer, which corresponds to barrier layer 56 in FIG. 1 and is therefore designated by the same reference number, is grown on channel layer 55 .

[0150] The workpiece multilayer 114 includes an elevated portion 115 that extends over the etching mask 111 and over the second sidewall 72 of the remaining portion 70 , and a useful portion 116 that extends directly over the top surface 100 A of the second intermediate layer 18 .

[0151] The useful portion 116 has an upper surface 116A that is substantially flat, in particular substantially parallel to the upper surface 100A.

[0152] The useful portion 116 grown on the second intermediate layer 18 is of single crystal type and is used to integrate the heterostructure-based device 7 .

[0153] Next, in FIG. 3J, the channel modulation region 64 is formed on the upper surface 116A of the useful portion 116 in a manner known per se, for example by growing and defining certain layers.

[0154] In fact, in this embodiment, the useful portion 116 of the work multilayer 114 also includes the channel modulation region 64 .

[0155] Thus, here, surface 64A of modulation region 64 forms the most elevated surface of useful portion 116, ie the surface of useful portion 116 which is at the greatest distance along third axis Z from surface 100A.

[0156] The surface 110A along which the etching mask 111 extends may be located at a distance from the surface 100A along the third axis Z that is greater than the most elevated surface of the useful portion 116 and less than the surface 110A. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus to increase the reliability of the manufacturing process of the device 1.

[0157] A protective layer 118 of insulating material, e.g., a single layer or insulating multilayer, including one or more of silicon oxide, silicon nitride, aluminum oxide, and silicon carbide, is formed on the barrier layer 56, as shown in Fig. 3K. The protective layer 118 has a thickness along the third axis Z that is greater than the thickness of the channel modulation region 64, e.g., comprised between 10 nm and 500 nm.

[0158] In other words, the protective layer 118 completely covers the channel modulation region 64 .

[0159] The protective layer 118 has an upper surface 118A in the useful portion 116 that faces the upper surface 116A of the useful portion 116.

[0160] In this embodiment, the top surface 118A of the protective layer 118 extends to a height along the third axis Z from the surface 100A that is less than the height of the top surface 111A of the etch mask 111 along the third axis Z from the surface 100A. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus to increase the reliability of the manufacturing process of the device 1.

[0161] Furthermore, in this embodiment, the distance along the third axis Z between the top surface 118A of the protection layer 118 and the top surface 64A of the channel modulation region 64 is greater than the thickness of the etching mask 111 along the third axis Z. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus to enhance the reliability of the manufacturing process of the device 1.

[0162] In FIG. 3L, elevated portion 115 of workpiece multilayer 114 is at least partially removed down to upper surface 111A of etching mask 111, thereby exposing etching mask 111.

[0163] This removal may be performed by planarization, for example chemical-mechanical polishing (CMP) or other etching techniques.

[0164] In the illustrated embodiment, after removal of the elevated portion 115 of the workpiece multilayer 114, only the portion that is flush with the upper surface 111A of the etching mask 111 and extends above the second sidewall 72 forming the raised portion 78 remains.

[0165] A portion of the protective layer 118 remains, indicated by 118 , extending over the useful portion 116 of the workpiece multilayer 114 .

[0166] Next, the wafer 100 is etched to remove the etch mask 111, thus exposing the gate layer 110, as shown in FIG. 3M.

[0167] In this embodiment, the etching of the etching mask 111 also etches the protective layer 118, thus reducing its thickness. However, because the thickness of the etching mask 111 is smaller than the distance between the top surface 64 of the channel modulation region 64 and the top surface 118A of the protective layer 118, the remaining protective layer 118 still completely covers the channel modulation region 64. As a result, the channel modulation region 64 is not damaged by the etching of FIG. 3M.

[0168] After etching, the protective layer 118 forms the insulating layer 58 described with reference to FIG.

[0169] Depending on the materials forming the etching mask 111 and the protective layer 118, and the particular etch used to remove the etching mask 111, the etch of FIG. 3M may selectively remove only the etching mask 111 and not the protective layer 118.

[0170] 3N, the gate layer 110 is defined, thereby forming the gate insulating regions 40, 41. Furthermore, (highly) doped regions 25A, 25B, 27, 29A, 29B, 31 are formed in the epitaxial portion 106 of the surface layer 105. For example, they may be defined through subsequent operations of masking and ion implantation.

[0171] This is followed by fabrication steps not shown here to form insulating and / or passivation layers of wafer 100 (e.g., oxide layers 35, 36 in FIG. 1) and to form metal contact regions of electronic components 5, 7 (e.g., regions 42-45 and 61, 62, 65 in FIG. 1).

[0172] Further final manufacturing steps, not shown here, such as forming a top layer of metal interconnects and dicing the wafer, may then follow, thereby forming device 1.

[0173] In fact, in the present manufacturing process, at least some of the doped regions 25A, 25B, 27, 28, 29A, 29B, 31 of the silicon-based component 5 (here the PMOS 5A and NMOS 5B transistors) are formed after growing the epitaxial multilayer 49.

[0174] In particular, the highly doped regions of the silicon-based component 5, i.e. here the source regions 25A, 29A and drain regions 25B, 29B as well as the body contact regions 27, 31 of the transistors 5A, 5B, are formed after growing an epitaxial multilayer 49.

[0175] This allows the epitaxial multilayer 49, 114 to be grown using a high thermal budget which makes it possible to obtain good growth quality of the epitaxial multilayer 49 and at the same time not adversely affect the manufacture of the silicon-based component 5.

[0176] For example, in practice, the growth of the first buffer layer 52 of AlN may be performed at a temperature of about 1100° C. for a time interval comprised between about 15 and 30 minutes, while the growth of the GaN and AlGaN layers forming the second buffer layer 53, the channel layer 55, the barrier layer 56 and the channel modulation region 64 may be performed in subsequent growth steps at temperatures of about 1030° C. to 1080° C. for an interval between about 5 and 15 minutes, respectively. This thermal budget may cause diffusion of doping atoms in the highly doped regions of the transistors 5A, 5B and thus a decrease in the reliability of the manufacturing process.

[0177] Conversely, the present manufacturing process allows both silicon-based electronic components 5 and heterostructure-based electronic components 7 to be integrated on the same die, while at the same time allowing for both high crystallographic quality of the heterostructure 50 and high manufacturing reliability of the silicon-based components 5. As a result, the silicon-based components 5 and the heterostructure-based components 7 can have high electrical performance in use.

[0178] Furthermore, in the illustrated embodiment in which the silicon-based component 5 includes MOS transistors 5A, 5B, the manufacturing steps associated with forming the epitaxial multilayer 49 can be simplified due to the fact that the work multilayer 114 can be grown after the formation of the gate insulating layer 110 and before the definition of the gate insulating layer 110.

[0179] In practice, for example, the gate insulating layer 110 can be used as a support for the formation of the etching mask 111 .

[0180] Further, still referring to the manufacturing process embodiment of Figures 3A-3N, the use of the growth mask 103 can simultaneously allow both to grow the single crystal epitaxial portion 106 on which the silicon-based electronic component 5 is formed and to protect the surface quality of the upper surface 100A below the growth mask 103 on which the workpiece multilayer film 114 is grown.

[0181] The fact that the growth mask 103 may comprise an oxide, in particular silicon oxide, makes it etchable by a different chemical species than the chemical species that can be used to remove the second intermediate layer 18. As a result, openings or recesses 113 through the sacrificial portion 107 exposing the underlying top surface 100A can be formed without affecting, at least to a first approximation, the quality of the surface 100A on which the workpiece epitaxial multilayer 114 (FIGS. 3G-3I) is grown.

[0182] In particular, the fact that the growth mask 103 comprises an oxide-containing layer in direct contact with the semiconductor layer 18 may make it possible to further reduce the risk of damaging the surface 100A on which the epitaxial multilayer 49 is grown.

[0183] In particular, the fact that the growth mask 103 is of silicon oxide and the layer 18 is of silicon makes it possible to obtain a highly selective etching rate of the growth mask 103 with respect to the silicon of the layer 18. Furthermore, wet etching can also be used to clean the surface 100A before the growth of the workpiece epitaxial multilayer 114.

[0184] In fact, the growth mask 103 can be used as a stop layer during etching of the overlying sacrificial portion 107, thus ensuring complete removal of the overlying sacrificial portion 107. Furthermore, the formation of the openings in the growth mask 103 does not affect the quality of the underlying surface 100A, e.g., terracing and pitting.

[0185] The epitaxial multilayer 49, and thus the heterostructure 50, can have high crystallographic quality, so that the corresponding electronic component 7, functioning based on the formation of a two-dimensional gas in the heterostructure 50, can have high electrical performance in use.

[0186] At the same time, the electronic components 5 are also integrated in the monocrystalline silicon layer (epitaxial portion 106), which may have high crystallographic quality, so that the electronic components 5 may have high electrical performance during use.

[0187] Furthermore, the thickness of the growth mask 103 can be made thick enough to be used as a mask for forming the epitaxial multilayer 49, while at the same time being thin enough to minimize non-planarity of the top surface 105A of the superficial layer 105. In fact, the top surface 105A of the superficial layer 105 can be considered to be substantially flat. This can facilitate subsequent fabrication steps that result in the formation of both the silicon-based electronic components 5 and the heterostructure-based electronic components 7.

[0188] As a starting substrate for forming a semiconductor electronic device 1 <111> The possibility of using a silicon substrate 14 may allow a high epitaxial quality of the heterostructure 50 to be obtained, especially if the channel layer 55 is of GaN. As a result, the heterostructure-based electronic component 7 may have excellent electrical performance. The Applicant also <111> It has also been found that the use of a silicon substrate 14 allows the silicon-based electronic component 5 to have superior electrical performance.

[0189] However, it will be apparent to one skilled in the art that the above-described manufacturing steps and the order in which they are performed may vary from that depicted in Figures 3A-3N depending on the particular process and machinery used.

[0190] For example, the epitaxial multilayer 49 may be grown before the surface layer 105 .

[0191] For example, the body regions of the NMOS and PMOS transistors may be formed before forming the insulating oxide (33, 108) or may be implanted after forming the field isolation (STI). In particular, they are formed before forming the oxide that forms the gate structures of the PMOS and NMOS transistors, i.e., before depositing, for example, the polysilicon layer 110.

[0192] For example, multilayer 114 may be selectively grown only from exposed portion 101B. In this case, portion 115 is not present. As a result, the removal of FIG. 3L may not be necessary.

[0193] Finally, it will be apparent that other modifications and variations may be made to the electronic device 1 and manufacturing process described and illustrated herein without departing from the scope of the present disclosure as defined in the appended claims.

[0194] The electronic device 1 may comprise other silicon-based electronic components 5, active and / or passive, integrated within the die 3 in addition to or instead of the PMOS 5A and NMOS 5B transistors.

[0195] For example, as shown in Figure 2, the silicon-based electronic component 5 may also include a bipolar transistor 5C and passive components 5D, such as diodes and resistors, in which the bipolar transistor 5C and the passive components 5D are integrated in respective device portions 120, 121 that are separate from each other and are indicated diagrammatically by dashed lines.

[0196] For example, device portions 120 , 121 are formed in respective single crystal silicon epitaxial regions grown on substrate region 10 , and in particular are formed monolithically with epitaxial region 23 .

[0197] Insulating regions, for example shallow or deep trenches, may be arranged, in a manner known per se, between portions 120, 121 and 20, so that the respective electronic components are, during use, electrically isolated from one another.

[0198] Device 1 may also include other silicon-based electronic components 5 integrated within die 3 in addition to or instead of those shown in Figure 2. For example, components 5 may include MOS transistors for medium voltage applications, e.g., 15V to 20V, DMOS transistors and / or drift MOS transistors for applications with operating voltages, e.g., 20V to 200V, thin film resistors, OTP or MTP memory, phase change memory, etc.

[0199] It will be clear to a person skilled in the art that the integration of different types of silicon-based electronic components 5 can be carried out through manufacturing steps which are known per se and therefore not further shown here, for example through BCD technology.

[0200] For example, the conductivity types, n or p, of the various semiconductor regions may be reversed with respect to those described.

[0201] For example, the epitaxial multilayer 49 may include only the heterostructure 50. In other words, the heterostructure 50 may be grown directly on the substrate region 10.

[0202] For example, layers 14-18 may include one or more diffusion regions of a doping species (P or N), depending on the particular application.

[0203] For example, the heterostructure-based components 7 may include electronic components other than HEMT transistors 7 .

[0204] For example, the HEMT transistor 7 may be of the normally-off type and the gate structure may be different from that described above. For example, the gate structure may be recessed and / or the fabrication of the gate structure may include the use of a fluorine plasma under the gate structure. Alternatively, the HEMT transistor 7 may be of the normally-on type, i.e., depletion type.

[0205] 1, the insulating region 77 extending between the first device portion 20 and the second device portion 21 may have a different shape and structure than that shown, for example, it may be one or more trenches that extend along the third axis Z to a greater depth within the die 3.

[0206] For example, the number of epitaxial layers forming substrate region 10 may vary depending on the particular application.

[0207] For example, depending on the desired thickness of the epitaxial multilayer 49 and the epitaxial region 23 along the third axis Z, the second intermediate layer 18 may be omitted and the epitaxial multilayer 49 may be grown directly on the second deep layer 17.

[0208] For medium or low voltage (e.g. 7V-40V) applications, the substrate region 10 may comprise only the substrate 14 and the first deep layer 15 (or the first intermediate layer 16). Indeed, in this case, the epitaxial multilayer 49 can be grown directly on the first deep layer 15 or on the first intermediate layer 16, if any.

[0209] For example, the electronic component 5 may be an electronic component based on a single semiconductor other than silicon, such as Ge, SiGe, etc.

[0210] A process for manufacturing a semiconductor electronic device includes providing a wafer (100) including a substrate layer (18) of a semiconductor material having a first portion (101A) and a second portion (101B) different from the first portion, growing an epitaxial region (23, 106) of a single semiconductor material on the first portion (101A) of the substrate layer, growing an epitaxial multilayer (49, 114) including a heterostructure (50) on the second portion (101B) of the substrate layer, and The method of the present invention is summarized as comprising forming a first electronic component (5A, 5B, 5C, 5D) based on a single semiconductor material from the epitaxial region (23, 106) and forming a second electronic component (7) based on a heterostructure from the heterostructure, the forming of the first electronic component comprising, after the step of growing the epitaxial multilayer, forming a plurality of doped regions (25A, 25B, 27, 29A, 29B, 31) in the epitaxial region (23).

[0211] The first electronic component is a MOS transistor (5A, 5B), and forming the plurality of doped regions includes forming one or more of a source region (25A, 29A), a drain region (25B, 29B), and a body contact region (27, 31) of the MOS transistor within the epitaxial region.

[0212] The first electronic component is a MOS transistor (5A, 5B) having a gate insulating region (40, 41), and forming the first electronic component further includes forming a gate insulating layer (110), e.g. of polysilicon, on the epitaxial region (106) prior to growing the epitaxial multilayer (114, 49), and defining the gate insulating layer, thereby forming the gate insulating region, after the step of growing the epitaxial multilayer.

[0213] The doped region is 1·10 16 atoms / cm 3 ~4·10 21 atoms / cm 3 The doping levels are included in

[0214] Growing the epitaxial multilayer includes forming a growth mask (103) on the substrate layer (18) and forming an opening in the growth mask (103) thereby exposing a second portion of the substrate layer.

[0215] A growth mask (103) is formed prior to growing the epitaxial region, the growth mask exposing a first portion (101A) of the substrate layer (18).

[0216] Growing the epitaxial region includes growing a surface layer (105) of a single semiconductor material having a first portion (106) extending over the first portion (101A) of the substrate layer (18) and a second portion (107) extending over the growth mask (103), and forming an opening in the growth mask (103) includes forming a recess in the second portion (107) of the surface layer extending to the growth mask.

[0217] The manufacturing process further includes forming an etching mask (111) extending above a first portion (106) of the surface layer (105) and having an opening (113) above a second portion (107) of the surface layer (105), and growing the epitaxial multilayer includes growing a work multilayer (114) having a first portion (116) extending onto a second portion (101B) of the substrate layer (18) and a second portion (115) extending onto the etching mask, and removing the second portion (115) of the work multilayer, the etching mask (111) extending along a direction (Z) from a surface (110A) that is located higher than the first portion (116) of the work multilayer from the substrate layer (18) along the direction (Z).

[0218] The growth mask (103) comprises an oxide layer, for example silicon oxide.

[0219] The growth mask (103) has a thickness comprised between 7 nm and 300 nm.

[0220] The second electronic component is a HEMT transistor (7), the heterostructure being based on materials from groups III and V of the periodic table, including for example GaN.

[0221] The HEMT transistor includes a channel modulation region (64) of semiconductor material having a top surface (64A), and forming the second electronic component includes growing the channel modulation region on the heterostructure (50) such that the top surface (64A) of the channel modulation region (64) is positioned at a distance from the substrate layer (18) along the direction (Z) that is less than a distance along the direction (Z) between the top surface (110A) of the gate insulation layer (110) and the substrate layer.

[0222] The wafer includes a substrate (14) having a first conductivity type (P) and a substrate layer (15, 16, 17, 18) having a second conductivity type (N) different from the first conductivity type and extending above the substrate.

[0223] The single semiconductor material is silicon, and the wafer (100) is made of single crystal silicon, particularly <111> It is made of silicon.

[0224] A semiconductor electronic device (1) is summarized as comprising a die (3), a first electronic component (5) based on a single semiconductor material and a second electronic component (7) based on a heterostructure, the die comprising a substrate region (10) of a semiconductor material, a first surface portion (20) comprising a monocrystalline region (23) of the single semiconductor material extending over the substrate region, and a second surface portion (21) distinct from the first surface portion and comprising an epitaxial multilayer (49) extending over the substrate region, the epitaxial multilayer comprising a heterostructure (50), the first electronic component (5) being integrated on the first surface portion of the die and the second electronic component (7) being integrated on the second surface portion of the die.

[0225] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts from various patents, applications, and publications to provide further embodiments.

[0226] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but rather to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. 1. A process for manufacturing a semiconductor electronic device, comprising: forming an epitaxial region of a single semiconductor material on a first portion of a substrate layer having a first portion and a second portion, the epitaxial region having a first surface opposite the substrate layer; forming an epitaxial multilayer including a heterostructure on the second portion of the substrate layer; forming an isolation portion between the epitaxial region and the epitaxial multilayer, the isolation portion having a second surface coplanar with the first surface; forming a first electronic component on the epitaxial region; forming a second electronic component on the heterostructure; A manufacturing process, wherein said forming said first electronic component includes forming a plurality of doped regions within said epitaxial region after said forming said epitaxial multilayer.

2. 2. The manufacturing process of claim 1, wherein the first electronic component is a MOS transistor, and forming the plurality of doped regions includes forming a source region, a drain region, and a body contact region of the MOS transistor in the epitaxial region.

3. The first electronic component is a MOS transistor having a gate insulating region, and forming the first electronic component includes: forming a gate insulating layer on the epitaxial region prior to forming the epitaxial multilayer; 2. The manufacturing process of claim 1, further comprising: after forming the epitaxial multilayer, defining the gate insulating layer, thereby forming the gate insulating region.

4. The doped region is 1.10 １６ atoms / cm ３ ~4.10 ２１ atoms / cm ３ 2. The manufacturing process of claim 1 having a doping level in the range of:

5. Growing the epitaxial multilayer film comprises: forming a growth mask on the substrate layer; 2. The manufacturing process of claim 1 including forming an opening in the growth mask to expose the second portion of the substrate layer.

6. 6. The manufacturing process of claim 5, wherein the growth mask is formed prior to forming the epitaxial region, the growth mask exposing the first portion of the substrate layer.

7. 6. The manufacturing process of claim 5, wherein the forming the epitaxial region comprises growing a superficial layer of the single semiconductor material having a first portion extending over the first portion of the substrate layer and a second portion extending over the growth mask, and wherein forming the opening in the growth mask comprises forming a recess in the second portion of the superficial layer extending to the growth mask.

8. forming an etch mask extending over the first portion of the surface layer and having an opening over the second portion of the surface layer; The formation of the epitaxial multilayer film includes: growing a workpiece multilayer having a first portion extending over the second portion of the substrate layer and a second portion extending over the etch mask; removing the second portion of the workpiece multilayer; 8. The manufacturing process of claim 7, wherein the etching mask is spaced a first distance from the substrate layer along a first direction, the first distance being greater than a second distance along the first direction between the first portion of the work multilayer and the substrate layer.

9. The manufacturing process of claim 5 , wherein the growth mask comprises an oxide layer.

10. The manufacturing process of claim 5, wherein the growth mask has a thickness in the range of 7 nm to 300 nm.

11. 4. The manufacturing process of claim 3, wherein the second electronic component is a HEMT transistor and the heterostructure is based on materials from groups III and V of the periodic table.

12. 12. The manufacturing process of claim 11, wherein the HEMT transistor includes a channel modulation region of semiconductor material having a top surface, and wherein the forming of the second electronic component includes growing the channel modulation region on the heterostructure such that the top surface of the channel modulation region is positioned at a first distance from the substrate layer along the first direction that is less than a second distance along the first direction between a top surface of the gate insulation layer and the substrate layer.

13. 13. The manufacturing process of claim 12, further comprising a substrate coupled to the substrate layer and having a first conductivity type, the substrate layer having a second conductivity type different from the first conductivity type and extending above the substrate.

14. The manufacturing process of claim 13 , wherein the single semiconductor material is silicon.

15. 1. An electronic device comprising: Die and A first electronic component; a second electronic component coupled to the first electronic component; The die includes: a substrate region of semiconductor material; a first surface portion including a single crystal region of a single semiconductor material extending over the substrate region; a second surface portion distinct from the first surface portion and including an epitaxial multilayer extending over the substrate region, the epitaxial multilayer including a heterostructure; An electronic device, wherein the first electronic component is integrated within the first surface portion of the die and the second electronic component is integrated within the second surface portion of the die.

16. The second electronic component includes: a gate contact region; 16. The electronic device of claim 15, further comprising a channel modulation region between the heterostructure and the gate contact region.

17. 16. The electronic device of claim 15, further comprising a buffer layer between the substrate region and the epitaxial multilayer.

18. 1. A method comprising: forming a definition layer on a wafer, the definition layer having a first portion on a first portion of the wafer and a second portion on a second portion of the wafer; removing the first portion of the definition layer to expose the first portion of the wafer; forming a surface layer having a first portion on the first portion of the wafer and a second portion on the definition layer; forming a mask on the first portion of the surface layer; removing the second portion of the surface layer to expose the definition layer; forming a workpiece multilayer having a first portion above the mask and a second portion above the second portion of the wafer.

19. 20. The method of claim 18, further comprising, after forming the surface layer, forming a doped region and a plurality of insulating portions within the first portion of the surface layer.

20. The work multilayer film is A buffer layer; a channel layer on the buffer layer; a barrier layer on the channel layer.

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