Semiconductor electronic device that reduces mechanical stress by integrating electronic components based on heterostructure

Abstract

To provide: a semiconductor electronic device that integrates electronic components based on a heterostructure; and reduces mechanical stress.SOLUTION: A semiconductor electronic device 1 has a substrate area 10 of a semiconductor material, a first electronic component 21 based on a heterostructure having an epitaxial multilayer film 49 that extends over the substrate area and includes a heterostructure 50, and a separation area 70 that extends over the substrate area. The separation area includes a polycrystalline area 73A of a polycrystalline semiconductor material, which is arranged alongside the epitaxial multilayer film along a first direction. The device also has an epitaxial area 23 of single-crystal, single-semiconductor material that extends over the substrate area. The polycrystalline area extends between the epitaxial multilayer film and the epitaxial area along the first direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to semiconductor electronic devices that integrate heterostructure-based electronic components to reduce mechanical stress. The present disclosure also relates to a manufacturing process for the semiconductor electronic devices. [Background technology]

[0002] 2. Description of Related Art Semiconductor electronic devices are known that include silicon-based active and / or passive electronic components, such as CMOS transistors, DMOS transistors, BJT transistors, diodes, resistors, etc., integrated within the same silicon die, e.g., fabricated using BCD (Bipolar-CMOS-DMOS) technology.

[0003] In fact, the functionality of these electronic components is based on the electronic properties of a single semiconductor material: silicon.

[0004] These devices monolithically integrate within the same die digital, analog, and power circuits that operate at voltages that are very different from each other, for example, from a few volts for CMOS transistors used to implement logic functions, to hundreds of volts for DMOS transistors used in power applications.

[0005] Silicon-based electronic components <100> It is integrated on a single crystal silicon region grown on a silicon wafer.

[0006] Semiconductor electronic devices comprising heterostructure-based electronic components, such as HEMT transistors, are also known.

[0007] In fact, the functionality of these electronic components is based on the electronic properties of the heterojunction between two different semiconductor materials.

[0008] In particular, in HEMT transistors, the conductive channel is based on the formation of a layer of a high-mobility two-dimensional electron gas (2DEG) at a heterojunction, i.e., at the interface between semiconductor materials with different bandgaps. For example, HEMT devices based on a heterojunction between an aluminum gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer are known.

[0009] In particular, HEMT devices based on AlGaN / GaN heterostructures or heterojunctions offer various advantages that make them particularly suitable and widely used for different applications. For example, the high breakdown threshold of HEMT devices can be utilized for high performance power switches, the high mobility of electrons in the conductive channel allows high frequency amplifiers to be formed, and the high concentration of electrons in the 2DEG allows low on-state resistance (R ON ) can be obtained.

[0010] Furthermore, HEMT devices for radio frequency (RF) applications typically have better RF performance than similar silicon LDMOS devices.

[0011] Heterostructure-based electronic components include: <111> They are integrated into heterostructures epitaxially grown on silicon wafers or on sapphire (Al2O3) or silicon carbide (SiC) substrates.

[0012] Applicants have observed that growth of heterostructures on silicon wafers can induce high mechanical stresses in the silicon wafer due to the different lattice pitches between the growth substrate (silicon) and the materials forming the heterostructure (e.g., GaN / AlGaN).

[0013] This high mechanical stress can cause dislocations in the silicon wafer.

[0014] These dislocations can compromise the mechanical stability of the silicon wafers on which the heterostructure-based electronic components are formed, causing the heterostructure-based electronic components to be subject to dielectric breakdown during fabrication and use.

[0015] Furthermore, in the presence of electronic components based on silicon and integrated within silicon wafers, high mechanical stresses and dislocations can impair the mechanical stability and performance of the silicon-based components.

[0016] As a result, the heterostructure-based electronic components and the silicon-based electronic components are integrated into separate dies starting from two different silicon wafers.

[0017] However, this causes electronic devices incorporating both silicon-based and heterostructure-based components to have high area occupancy and therefore high manufacturing costs, high power consumption, and poor electrical performance due to, for example, parasitic capacitance or inductance introduced by the electrical connections between the dies.

[0018] According to one approach, a die having silicon-based components formed therein and a die having heterostructure-based components formed therein are bonded together by die transfer techniques.

[0019] However, even this approach has drawbacks in terms of cost of use, and reliability of manufacturing and electrical performance. Summary of the Invention

[0020] Thus, in accordance with the present disclosure, there is provided a semiconductor electronic device and a manufacturing process for the semiconductor electronic device. The system includes a semiconductor substrate and a first electronic device on the semiconductor substrate. The first electronic device includes a heterostructure and an epitaxial multilayer. An isolation region isolates the first electronic device. The isolation region includes a trench region, a polycrystalline portion, and an epitaxial region on the semiconductor substrate. [Brief description of the drawings]

[0021] For a better understanding of the present disclosure, embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which: [Figure 1] 1 illustrates a cross-sectional view of a semiconductor electronic device according to an embodiment. [Diagram 2] FIG. 2 shows a top view of the device of FIG. 1. [Figure 3A] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3B] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3C] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3D] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3E] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3F] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3G] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3H] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3I] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3J] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3K] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3L] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3M] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3N] 2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 3O]2 illustrates steps in a manufacturing process for the device of FIG. 1 according to one embodiment. [Figure 4] 3 shows a top view of a portion of the device of FIG. 2 according to another embodiment. [Diagram 5] 3 shows a top view of a portion of the device of FIG. 2 according to another embodiment. [Figure 6A] 1 illustrates steps in a manufacturing process for a semiconductor electronic device according to different embodiments. [Figure 6B] 1 illustrates steps in a manufacturing process for a semiconductor electronic device according to different embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The following description refers to the orientation illustrated in the accompanying drawings, and therefore, terms such as "upper", "lower", "bottom", "upper", "right", "left", "high", "low" and the like, are with respect to the accompanying drawings and should not be construed as limiting.

[0023] 1 and 2 show a semiconductor electronic device (hereinafter simply referred to as device) 1 in a Cartesian coordinate system XYZ having a first axis X, a second axis Y and a third axis Z.

[0024] The device 1 is formed in a die 3 and comprises one or more silicon-based electronic components 5, shown in FIG. 1 as a PMOS transistor 5A and an NMOS transistor 5B, and one or more heterostructure-based electronic components, shown in FIG. 1 as a HEMT transistor 7, all integrated within the die 3.

[0025] The die 3 comprises a substrate area 10 and a surface area 12 which extends over the substrate area 10 and in particular is in direct contact with the substrate area 10 .

[0026] Substrate region 10 comprises a substrate 14 and one or more epitaxial layers disposed on substrate 14 .

[0027] Substrate 14 is of a semiconductor material, particularly single crystal, and has an upper surface 14A.

[0028] Specifically, in this embodiment, the substrate 14 is of single crystal silicon, and in particular the upper surface 14A is <111> It is oriented according to the crystal directions.

[0029] In this embodiment, the substrate region 10 comprises a first epitaxial layer or first deep layer 15 overlying the upper surface 14A of the substrate 14, a second epitaxial layer or first intermediate layer 16 overlying the first deep layer 15, a third epitaxial layer or second deep layer 17 overlying the first intermediate layer 16, and a fourth epitaxial layer or second intermediate layer 18 overlying the second intermediate layer 17.

[0030] The epitaxial layers 15-18 are of semiconductor material, in particular the same material as the substrate 14 (here silicon), and are identified by dashed lines in FIG. 1 for the sake of clarity.

[0031] The thickness along the third axis Z, conductivity type (eg, P or N), and doping profile of the substrate 14 and epitaxial layers 15-18 may be selected at the design stage depending on the particular application of the device 1.

[0032] For example, the epitaxial layers 15 to 18 may each have a thickness comprised between 0.1 μm and 7 μm.

[0033] For example, in this embodiment, the substrate 14 is of the P type, for example with a resistivity comprised between 0.1 Ωcm and 20 Ωcm, and the epitaxial layers 15-18 are of the N type. In this way, the first deep layer 15 can form a PN junction with the substrate 14, which can be used, in use, to isolate the devices 5, 7 integrated in the die 3 from the substrate 14.

[0034] The first deep layer 15 and the second deep layer 17 may have different, in particular higher, doping levels with respect to the first intermediate layer 16 and the second intermediate layer 18. For example, the doping levels of the layers 15 to 18 may be such as to provide a resistivity comprised, for example, between 0.1 Ωcm and 20 Ωcm.

[0035] Due to the high doping level of the first deep layer 15, in use the depletion region between the first deep layer 15 and the substrate 14 extends primarily into the substrate 14, thereby improving the electrical isolation of the components 5, 7 from the substrate 14.

[0036] Furthermore, the high doping level of the first deep layer 15 may enable the first deep layer 15 to be used as a current conducting region for electronic components integrated within the die 3, for example when the silicon-based component 5 includes a BJT transistor.

[0037] The presence of both the first deep layer 15 and the second deep layer 17 can be useful to simplify the manufacture of the device 1 and to obtain superior electrical performance of the device 1 during use when the electronic components 5, 7 are designed to operate at high voltages relative to the substrate 14, for example, starting from about 60 V and up to about 650 V or even higher.

[0038] The surface region 12 extends onto the second intermediate layer 18, in particular in direct contact with said intermediate layer, and comprises a first device portion 20 in which the PMOS transistor 5A and the NMOS transistor 5B are integrated, and a second device portion 21 in which the HEMT transistor 7 is integrated.

[0039] The first device portion 20 has an upper surface 20A and comprises an epitaxial region 23 of monocrystalline semiconductor material, in particular the same material as the second intermediate layer 18, here monocrystalline silicon.

[0040] Epitaxial region 23 extends from second intermediate layer 18, and here in direct contact with that intermediate layer, to upper surface 20A.

[0041] The thickness along the third axis Z, the conductivity type (eg, P or N), and the doping profile of the epitaxial region 23 may be selected at the design stage depending on the particular application of the device 1.

[0042] For example, in this embodiment, epitaxial region 23 is of N-type.

[0043] The first device portion 20 extends into the epitaxial region 23 and comprises a number of doped regions which form the functional region of the silicon-based electronic component 5 .

[0044] In practice, silicon-based electronic components 5, here a PMOS transistor 5A and an NMOS transistor 5B, are integrated in an epitaxial region 23.

[0045] 1, P++ type doped regions 25A, 25B extend from top surface 20A into epitaxial region 23. Doped regions 25A, 25B form the source and drain regions, respectively, of PMOS transistor 5A and define channel region 26 of PMOS transistor 5A.

[0046] Additionally, N++ type doped region 27 extends from top surface 20A into epitaxial region 23 and forms a body contact region for PMOS transistor 5A.

[0047] With further reference to the embodiment of FIG. 1, a P-type doped region 28 extends from top surface 20A into epitaxial region 23 and forms the body region of NMOS transistor 5B.

[0048] N++ type doped regions 29A, 29B extend into doped region 28 and form the source and drain regions, respectively, of NMOS transistor 5B and define a channel region 30 of NMOS transistor 5B.

[0049] Additionally, a P++ type doped region 31 extends into doped region 28 and forms the body contact region of NMOS transistor 5B.

[0050] In practice, the doped regions 25A, 25B, 27, 29A, 29B, and 31, i.e., the source doped regions, the drain doped regions, and the body contact regions, are doped with, for example, 5-10 19 atoms / cm -3 ~5·10 20 atoms / cm -3 Conversely, the doped region 28, i.e., the body region, is a highly doped region having a peak doping level included in, for example, 1·10 16 atoms / cm -3 ~2·10 18 atoms / cm -3 is a lightly doped region having a doping level included in

[0051] The number, arrangement, shape, size, and doping profile of the doped regions may be selected at the design stage depending on the particular silicon-based electronic components 5 integrated within the die 3 and the particular application of the device 1.

[0052] An insulating portion 33 of insulating material, for example an oxide, may begin at upper surface 20A and extend into epitaxial region 23, depending on the particular application.

[0053] In particular, in FIG. 1, insulating portions 33 extend parallel to the first axis X between doped regions 27 and 25A, between 25B and 31, and between 31 and 29A.

[0054] A first insulating layer 35 of, for example, oxide or nitride, extends over the top surface 20A of the first device portion 20.

[0055] A second insulating layer 36 of, for example, oxide, extends over the first insulating layer 35 .

[0056] The surface structure 38 of the silicon-based component 5 extends over and is in direct contact with the top surface 20A of the first device region 20. The surface structure 38 forms further functional areas of the silicon-based device 5 and may include various conductive and / or insulating regions depending on the particular silicon-based electronic component 5 integrated within the die 3.

[0057] In this embodiment, the surface structure 38 comprises gate insulating regions 40, 41 extending respectively above the channel region 26 of the PMOS transistor 5A and above the channel region 30 of the NMOS transistor 5B. For simplicity, only the respective conductive regions of the gate insulating regions 40, 41, here of polysilicon and again designated 40, 41, are shown in Figure 1, each having a respective upper surface 40A, 41A.

[0058] Although not shown in FIG. 1, gate insulating regions 40, 41 may also each include a respective insulating region disposed between a respective polysilicon region and top surface 20A, and a respective contact region of conductive material, e.g., metal, in contact with respective surface 40A, 41A to form a respective gate terminal G.

[0059] In the embodiment of FIG. 1, the surface structure 38 also includes source contact regions 42, 43 and drain contact regions 44, 45 of conductive material that extend through the first and second insulating layers 35, 36 and are in direct contact with the top surface 20A to form respective source S and drain D terminals.

[0060] In particular, source contact regions 42, 43 extend in direct contact with source region 25A of PMOS transistor 5A and source region 29A of NMOS transistor 5B, respectively.

[0061] Furthermore, in the illustrated embodiment, the source contact regions 42, 43 also each extend into direct contact with a respective body contact region 27, 31.

[0062] Drain contact regions 44, 45 extend in direct contact with drain region 25B of PMOS transistor 5A and drain region 29B of NMOS transistor 5B, respectively.

[0063] The second device portion 21 of the surface region 12 has an upper surface 21A and includes an epitaxial multilayer 49 extending onto and grown from the second intermediate layer 18.

[0064] The epitaxial multilayer 49 comprises a heterostructure 50 in which the HEMT transistor 7 is integrated.

[0065] 1, epitaxial multilayer 49 also comprises a transition region formed therein by overlapping first and second buffer layers 52, 53 disposed between second intermediate layer 18 and heterostructure 50. This transition region may be useful during fabrication of device 1 to favor epitaxial growth of heterostructure 50 on second intermediate layer 18.

[0066] In particular, a first buffer layer 52, for example of aluminum nitride (AlN), extends over and is in direct contact with the second intermediate layer 18, and a second buffer layer 53, for example of aluminum gallium nitride (AlGaN), extends over and is in direct contact with the first buffer layer 52.

[0067] The heterostructure 50 comprises a compound semiconductor material containing elements from groups III and V of the periodic table and forms the top surface 21A of the second device portion 21.

[0068] The top surface 21A of the second device portion 21 may extend at coordinates along a third axis Z that are the same as or different from the coordinates of the top surface 20A of the first device portion 20, depending on the particular manufacturing process used to produce the device 1.

[0069] In particular, in this embodiment, the top surface 21A of the second device portion 21 is disposed at a lower height, measured along the third axis Z, relative to the top surface 20A of the first device portion 20. This may allow for improved manufacturing of the device 1.

[0070] The heterostructure 50 comprises a channel layer 55 and a barrier layer 56 which overlie one another.

[0071] The channel layer 55 is made of a first semiconductor material, for example gallium nitride (GaN) or an alloy containing gallium nitride such as InGaN, here gallium nitride (GaN), extends over the transition region, in particular over the second buffer layer 53, and has an upper surface 55A.

[0072] The barrier layer 56 is made of a second semiconductor material, for example Al. x Ga 1-x N, AlInGaN, In x Ga 1-x N, Al x In 1-x A compound based on a ternary or quaternary gallium nitride alloy such as Al, AlScN, here aluminum gallium nitride (AlGaN), extends between an upper surface 55A of the channel layer 55 and an upper surface 21A of the second device portion 21.

[0073] The channel layer 55 and the barrier layer 56 may be intrinsic, P-type, or N-type, depending on the particular application. In particular, both the channel layer 55 and the barrier layer 56 may be N-type.

[0074] For example, if the barrier layer 56 is of AlGaN, the presence of aluminum atoms can make the barrier layer 56 N-type.

[0075] The heterostructure 50 is configured to accommodate a two-dimensional gas (2DEG) of (mobile) charge carriers, in particular here electrons, located at the interface between the channel layer 55 and the barrier layer 56, i.e., at the upper surface 55A of the channel layer 55.

[0076] An insulating layer 58 having an upper surface 58A of oxide, for example silicon oxide, extends on the upper surface 21A with a thickness, for example, comprised between 20 nm and 1 μm.

[0077] Insulating layer 36 also extends over second device portion 21 , in particular over insulating layer 58 .

[0078] The surface structure 60 of the heterostructure-based component 7 extends onto the upper surface 21A of the second device portion 21.

[0079] Depending on the particular heterostructure-based electronic component 7 integrated within the die 3, the surface structures 60 may be various conductive and / or insulating regions that form functional areas of the heterostructure-based component 7.

[0080] In this embodiment, in which the heterostructure-based electronic component 7 is a HEMT transistor, the surface structure 60 comprises a source region 61 and a drain region 62 of conductive material extending at a distance from each other along a first axis X.

[0081] The source region 61 and the drain region 62 are in electrical contact, in particular ohmic contact, with the heterostructure 50 and in particular with the two-dimensional gas formed at the interface between the channel layer 55 and the barrier layer 56, and form the source terminal S and the drain terminal D, respectively, of the HEMT transistor 7.

[0082] In the embodiment of FIG. 1, source region 61 and drain region 62 extend parallel to third axis Z through insulating layers 36, 58 to top surface 21A.

[0083] However, the source region 61 and the drain region 62 may extend parallel to the third axis Z and partially through the heterostructure 50, for example to a portion of the barrier layer 56 or throughout the entire thickness of the barrier layer 56 to the surface 55A, depending on the particular application.

[0084] The surface structure 60 also includes a gate structure, here formed by a channel modulation region 64 and a gate contact region 65, which can be biased to electrically control the formation of a two-dimensional gas in the heterostructure 50 between the source region 61 and the drain region 62. The gate structure forms the gate terminal G of the HEMT transistor 7.

[0085] In this embodiment, the HEMT transistor 7 is of the normally-off type, that is, the enhancement type.

[0086] In particular, in this embodiment, the channel modulation region 64 is of a semiconductor material and has a different conductivity type, e.g., P-type, relative to the barrier layer 56. In particular, the channel modulation region 64 may be of P-type gallium nitride (p-GaN).

[0087] However, the channel modulation region 64 may be of a different material, for example a dielectric material, to obtain an insulated gate structure.

[0088] The channel modulation region 64 extends along the first axis X on the top surface 21A between the source region 61 and the drain region 62 and has a top surface 64A.

[0089] The upper surface 64A of the channel modulation region 64 may extend at coordinates along a third axis Z that are equal to or different from the coordinates of the upper surfaces 40A, 41A of the gate insulation regions 40, 41, depending on the particular manufacturing process used to fabricate the device 1.

[0090] In particular, in this embodiment, the top surface 64A of the channel modulation region 64 is disposed at a distance from the second interlayer 18 measured along the third axis Z that is less than the distance of the top surfaces 40A, 41A of the gate insulating regions 40, 41 from the second interlayer 18 measured along the third axis Z. This can increase the reliability of the fabrication of the device 1.

[0091] A gate contact region 65 of conductive material extends in electrical contact with channel modulation region 64, and here in particular in contact with top surface 64A.

[0092] The device 1 also comprises an isolation region 70 which extends in the surface region 12 of the die 3 alongside the epitaxial multilayer 49 and onto the substrate region 10 , in particular onto and in direct contact with the second intermediate layer 18 .

[0093] 1 and 2, the isolation region 70 extends parallel to the first axis X between the epitaxial multilayer 49 and the epitaxial region 23. As shown in FIG.

[0094] In this embodiment, as seen in FIG. 2, isolation region 70 surrounds epitaxial multilayer 49 .

[0095] In particular, the separation region 70 comprises a defined area 72 of a material different from the material of the second intermediate layer 18 and a polycrystalline region formed here by two polycrystalline portions 73A, 73B of a polycrystalline semiconductor material, in particular polycrystalline silicon.

[0096] The defined area 72 may be formed by a single layer, for example an oxide, in particular a silicon oxide, or by a multilayer film, for example comprising one or more layers of an oxide and / or one or more layers of a nitride.

[0097] In particular, according to one embodiment, the defined area 72 may be of silicon oxide.

[0098] According to different embodiments, the demarcation area 72 may comprise an oxide layer, in particular silicon oxide, and a nitride layer. According to one embodiment, the oxide layer may be in direct contact with the second intermediate layer 18.

[0099] The defined area 72 extends in direct contact with the second intermediate layer 18 .

[0100] The defined area 72 may have a thickness along the third axis Z, for example, comprised between 7 nm and 300 nm, in particular between 70 Å and 200 Å.

[0101] Polycrystalline portions 73 A, 73 B extend over defined area 72 and surround epitaxial multilayer 49 .

[0102] The isolation region 70 further comprises a trench 75 extending within the polycrystalline region, specifically here between the two polycrystalline portions 73A, 73B.

[0103] In particular, a trench 75 separates the two polycrystalline portions 73A, 73B from each other. Indeed, in this embodiment, the two polycrystalline portions 73A, 73B are separate from each other and extend at a certain distance from each other.

[0104] The trench 75 has a width W measured between the two polycrystalline portions 73A, 73B, which may be comprised between 0.2 μm and 3 μm (their boundaries may or may not be included).

[0105] Polycrystalline portion 73A extends outside trench 75 and, in this embodiment, is continuous (monolithic) with epitaxial region 23. In effect, polycrystalline portion 73A forms an outer sidewall 76 of isolation region 70.

[0106] The slope of the outer sidewall 76 may depend on the crystal orientation of the epitaxial region 23 and the thickness of the defined region 75 along the third axis Z. For example, if the epitaxial region 23 is <111> When oriented according to the crystallographic directions, the outer sidewall 76 may form an angle with a direction parallel to the first axis X of approximately 54°.

[0107] Polycrystalline portion 73B extends inside trench 75 where it is in contact with epitaxial multilayer 49. In effect, polycrystalline portion 73B forms inner sidewall 77 of isolation region 70.

[0108] The slope of the inner sidewall 77 may depend on the particular manufacturing process used to produce the epitaxial multilayer 49 .

[0109] The trenches 75 may be partially or completely filled, or may be empty, depending on the particular manufacturing process used to fabricate the device 1 .

[0110] Referring to FIG. 1, trench 75 comprises a peripheral portion 79 formed by one or more of the materials forming epitaxial multilayer 49, and a central portion 80 which may be empty or may be filled wholly or partially with an insulating material, for example the same material that forms insulating layer 36.

[0111] In this embodiment, polycrystalline portions 73A, 73B extend a distance from top surface 20A. In particular, insulating region 82 of insulating material, e.g., oxide, extends from top surface 20A inwardly of epitaxial region 23 and isolation region 70 into die 3.

[0112] In the embodiment of FIG. 1, epitaxial multilayer 49 includes a peripheral portion 84 that conformally extends onto inner sidewall 77 of isolation region 70 and forms a raised surface 84A.

[0113] Raised surface 84A is disposed at a coordinate along third axis Z that is greater than top surface 21A, and here even greater than top surface 58A of insulating layer 58.

[0114] Moreover, in this embodiment, trench 75 extends along third axis Z through insulating region 82 to a coordinate along third axis Z that is greater than top surface 20A that is specifically aligned with raised surface 84A, although the shape and configuration of trench 75 will depend on the particular manufacturing process used.

[0115] The polycrystalline region of isolation region 70 formed here by polycrystalline portions 73A, 73B along with epitaxial multilayer 49 serves as a spacing region between epitaxial multilayer 49 and epitaxial region 23.

[0116] In fact, the presence of polycrystalline regions makes it possible to absorb the mechanical stresses caused by the different lattice pitches between the material forming the epitaxial region 23 (here, silicon) and the materials forming the heterostructure 50 (here, AlN, GaN and AlGaN).

[0117] As a result, the heterostructure 50 is subjected to low mechanical stress in the lateral direction and therefore may have good crystallographic quality, such that the HEMT transistor 7, in use, may have good electrical performance.

[0118] The presence of the isolation region 70 also reduces the mechanical stress experienced by the epitaxial region 23, lowering the risk of dislocations. Silicon-based electronic components 5 can then be integrated into the epitaxial region 23.

[0119] Moreover, applicants have determined that the presence of trenches 75, along with epitaxial multilayer 49, contributes to further reducing mechanical stress.

[0120] In fact, device 1 may enable the functionality of silicon-based component 5 and heterostructure-based component 7 to be combined within a single die while maintaining small dimensions relative to electronic devices in which silicon-based component 5 and heterostructure-based component 7 are integrated on different dies.

[0121] Furthermore, electrical connections between the silicon-based components 5 and the heterostructure-based components 7 can be made directly on the die 3, thereby ensuring high electrical performance of the device 1 when in use.

[0122] The manufacturing process of the semiconductor electronic device 1 will be described below with reference to FIGS. 3A to 3O.

[0123] Figure 3A shows a cross-section of a wafer 100 of monocrystalline semiconductor material, in particular silicon, having a top surface 100A. Elements of wafer 100 that are common to those already described with reference to Figure 1 are indicated with the same reference numerals and will not be described in further detail.

[0124] Wafer 100 comprises a substrate 14 on which epitaxial layers 15, 16, 17, and 18 have already been grown.

[0125] The fourth epitaxial layer or second intermediate layer 18 forms the top surface 100 A of the wafer 100 .

[0126] The second intermediate layer 18 comprises a first portion 101A in which the epitaxial region 23 is intended to be formed, a second portion 101B in which the epitaxial multilayer film 49 is intended to be formed, and a third portion 101C in which the isolation region 70 is intended to be formed.

[0127] Subsequently, in FIG. 3B, a definition layer 102, for example comprising an oxide of silicon dioxide, is formed on the upper surface 100A.

[0128] Definition layer 102 may be a single layer or a multi-layer film, as described for definition region 72 .

[0129] The definition layer 102 may have a small thickness along the third axis Z, for example comprised between 7 nm and 300 nm, in particular between 70 Å and 200 Å.

[0130] Definition layer 102 is intended to form definition area 72 (FIG. 1).

[0131] The definition layer 102 can be formed by oxidation of a surface portion of the second intermediate layer 18 or by deposition on the upper surface 100A. In case of oxidation, the thickness of the second intermediate layer 18 can be reduced after oxidation with respect to the layer 18 of FIG. 3A. However, considering the much smaller thickness of the definition layer 102 with respect to the thickness of the second intermediate layer 18, for the sake of simplicity, it can be assumed, as a first approximation, that the thickness of the second intermediate layer 18 remains the same before and after oxidation.

[0132] 3C, the definition layer 102 is then removed in a first portion 101A of the second intermediate layer 18, i.e. in the portion of the second intermediate layer 18 on which the epitaxial region 23 is intended to be formed. Thus, a portion of the definition layer 102 remains, also referred to below as growth mask 103.

[0133] In practice, the growth mask 103 exposes a first portion 101A of the second intermediate layer 18 and covers a second portion 101B and a third portion 101C of the second intermediate layer 18.

[0134] In FIG. 3D, a surface layer 105 of semiconductor material, in particular the same material as the second intermediate layer 18 (here, silicon), is grown on the wafer 100.

[0135] The surface layer 105 has an upper surface 105A.

[0136] The surface layer 105 includes an epitaxial portion 106 growing parallel to the third axis Z from the second intermediate layer 18, in particular from each first portion 101A, and a sacrificial portion 107 growing parallel to the third axis Z on the growth mask 103.

[0137] The epitaxial portion 106 growing from the single crystal substrate is intended to maintain the single crystal structure of the second intermediate layer 18 and form the epitaxial region 23 .

[0138] The sacrificial portion 107 is grown from an amorphous substrate and has a polycrystalline structure.

[0139] In FIG. 3E, a doped region 28 corresponding to the body region of NMOS transistor 5B and, optionally, an insulating layer 108 are formed in surface layer 105. In FIG.

[0140] In particular, the body region 28 is formed within the epitaxial portion 106 in which the silicon-based component 5 is formed.

[0141] The body region 28 may be formed by implantation of doping ions.

[0142] For example, insulating layer 108 of silicon oxide forms insulating portions 33 (FIG. 1) and portions 109 intended to form insulating regions 82 (FIG. 1).

[0143] The insulating layer 108 may be formed by forming an insulating trench, e.g., Shallow Trench Isolation (STI), in the surface layer 105. In this case, the thickness of the epitaxial portion 106 and the thickness of the sacrificial portion 107 may be reduced in response to the formation of the insulating layer 108. The portion 109 may be continuous or may be formed by a number of structures separated from one another, e.g., by alternating dielectric zones having different thicknesses.

[0144] Further, and referring to FIG. 3E, one or more surface layers 110 may be formed on the upper surface 105A of the surface layer 105 depending on the particular silicon-based electronic components 5 desired to be integrated within the die 3 of the device 1.

[0145] In the embodiment shown, the surface layer 110 is the layer intended to form the gate insulating regions 40, 41 (FIG. 1) of the PMOS transistor 5A and the NMOS transistor 5B. In particular, of the surface layer 110, only a single gate layer of polysilicon, still designated here by 110, is shown here. However, an oxide layer, not shown here, is formed between the upper surface 105A and the polysilicon layer 110 in a manner known per se.

[0146] Polysilicon layer 110 has an upper surface 110A.

[0147] A mask sacrificial layer 111 having a top surface 111A, for example of an insulating material, is also formed on the surface 110A of the gate layer 110. This mask sacrificial layer 111 may be a single layer or a multi-layer film including, for example, silicon oxide, silicon nitride, aluminum oxide, and silicon carbide, or combinations thereof.

[0148] In FIG. 3F, an opening 113 is drilled above the sacrificial portion 107.

[0149] The opening 113 is formed by selectively removing portions of the layers 110, 111, thus exposing the underlying sacrificial portion 107, in particular the portion of the second intermediate layer 18 facing the second portion 101B.

[0150] The remaining portion of the sacrificial layer 111 can be used as an etch mask.

[0151] Subsequently, as shown in FIG. 3G, the insulating layer 108 and the sacrificial portion 107 are removed in the openings 113 using the etching mask 111.

[0152] Thus, only a portion of the sacrificial portion 107 remains that is located below the etching mask, faces the third portion 101C of the second intermediate layer 18, and will form the polycrystalline portions 73A, 73B of FIG. 1 (here shown as work polycrystalline region 114).

[0153] Following the etching of FIG. 3G, the recess formed in the sacrificial portion 107 is continuous with the opening 113 and exposes a portion of the growth mask 103 facing the second portion 101B of the second intermediate layer 18.

[0154] 3H, the exposed portions of the growth mask 103 are removed, thus leaving only those portions of the growth mask 103 that are located below the workpiece polycrystalline region 114, i.e. the defined regions 72 in FIG.

[0155] Etching of the exposed portions of the growth mask 103 may be performed using a selective chemistry that does not, to a first approximation, etch the underlying second intermediate layer 18 .

[0156] Thus, following the etch of FIG. 3H, opening 113 also exposes second portion 101B of second intermediate layer 18.

[0157] 3I, trenches 75 of FIG. 1 are formed by opening respective windows in etching mask 111 and removing exposed portions of workpiece polycrystalline region 114. Thus, polycrystalline portions 73A and 73B of workpiece polycrystalline region 114 remain.

[0158] In this embodiment, forming trench 75 also includes removing a portion of insulating layer 109 .

[0159] Removal of the exposed portions of workpiece polycrystalline region 114 may be performed using the same chemistry used to form recess 113 of FIG. 3G.

[0160] Next, in FIG. 3J, a workpiece multilayer 117, intended to form the epitaxial multilayer 49 of FIG.

[0161] In particular, a first buffer layer, which corresponds to buffer layer 52 of Figure 1 and is therefore designated by the same reference numeral, is grown on wafer 100. First buffer layer 52 extends over exposed portions of top surface 100A, over inner sidewalls 77, and over etch mask 111.

[0162] A second buffer layer, which corresponds to buffer layer 53 in FIG. 1 and is therefore designated by the same reference number, is grown on the first buffer layer 52 .

[0163] A channel layer, which corresponds to channel layer 55 in FIG. 1 and is therefore designated by the same reference number, is grown on the second buffer layer 53 .

[0164] A barrier layer, which corresponds to barrier layer 56 in FIG. 1 and is therefore designated by the same reference number, is grown on channel layer 55 .

[0165] In the illustrated embodiment, a portion of the work epitaxial multilayer 117 also grows conformally within the trench 75, and in particular here on the walls of the trench 75, forming a fill portion 118 and leaving a central portion 119 of the trench 75 empty.

[0166] Without loss of generality, the filler portion 118 may be formed from one or more of the materials forming the work multilayer 117 (e.g., AlN, AlGaN, and / or GaN) or other materials, such as, for example, a dielectric or insulator, such as, for example, an oxide or silicon nitride, aluminum oxide, etc., and the particular shape of the filler portion 118 may differ from that illustrated depending on the particular growth conditions used to grow the work multilayer 117.

[0167] In practice, the work multilayer 117 comprises, in addition to the filling portion 118, an elevated portion 120 extending over the etching mask 111 and onto the inner sidewall 77 of the isolation region 70, and a useful portion 121 extending directly onto the upper surface 100A of the second intermediate layer 18.

[0168] The useful portion 121 has an upper surface 121A that is substantially flat, in particular substantially parallel to the upper surface 100A.

[0169] The useful portion 121 grown on the second intermediate layer 18 is of single crystal type and is used to integrate a heterostructure-based device 7 .

[0170] Next, in FIG. 3K, a channel modulation region 64 is formed on the upper surface 121A of the useful part 121 in a manner known per se, for example by growing and defining certain layers.

[0171] In fact, in this embodiment, the useful portion 121 of the work multilayer 117 also comprises a channel modulation region 64 .

[0172] Thus, here, the surface 64A of the modulation region 64 forms the most elevated surface of the useful portion 121, ie the surface of the useful portion 121 at the greatest distance along the third axis Z from the surface 100A.

[0173] The surface 110A along which the etching mask 111 extends may be located at a distance from the surface 100A along the third axis Z that is greater than the most elevated surface of the useful portion 121. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus to increase the reliability of the manufacturing process of the device 1.

[0174] A protective layer 124 of insulating material, e.g., a single layer or multilayer film including, e.g., silicon oxide, silicon nitride, aluminum oxide, silicon carbide, or a combination thereof, is formed on the barrier layer 56, as shown in FIG. 3L. The protective layer 124 has a thickness along the third axis Z that is greater than the thickness of the channel modulation region 64, e.g., comprised between 10 nm and 500 nm.

[0175] In other words, the protective layer 124 completely covers the channel modulation region 64 .

[0176] The protective layer 124 has an upper surface 124A in the useful portion 121 that faces the upper surface 121A of the useful portion 121.

[0177] In this embodiment, the top surface 124A of the protective layer 124 extends at a height from the surface 100A along the third axis Z, which is less than the height of the top surface 111A of the etching mask 111 from the surface 100A along the third axis Z. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus to increase the reliability of the manufacturing process of the device 1.

[0178] Furthermore, in this embodiment, the distance along the third axis Z between the top surface 124A of the protection layer 124 and the top surface 64A of the channel modulation region 64 is greater than the thickness of the etching mask 111 along the third axis Z. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus enhance the reliability of the manufacturing process of the device 1.

[0179] In FIG. 3M, elevated portion 120 of workpiece multilayer 117 has been at least partially removed down to upper surface 111A of etch mask 111, thereby exposing etch mask 111. In FIG.

[0180] This removal can be performed by planarization, for example chemical-mechanical polishing (CMP) or other etching techniques.

[0181] In the illustrated embodiment, after removal of the elevated portion 120 of the workpiece multilayer 117, only a portion remains extending onto the inner sidewall 77 forming a peripheral portion 84 (FIG. 1) of the multilayer 49 whose surface 84A is flush with the upper surface 111A of the etching mask 111.

[0182] A portion of the protective layer 124 still remains, designated by 124 , extending over the useful portion 121 of the workpiece multilayer 117 .

[0183] Next, FIG. 3N, the wafer 100 is etched to remove the etch mask 111, thus exposing the gate layer 110.

[0184] In this embodiment, the etching of the etching mask 111 also etches the protective layer 124, thus reducing its thickness. However, because the thickness of the etching mask 111 is smaller than the distance between the top surface 64 of the channel modulation region 64 and the top surface 124A of the protective layer 124, the remaining protective layer 124 still completely covers the channel modulation region 64. As a result, the channel modulation region 64 is not damaged by the etching of FIG. 3N.

[0185] After etching, the protective layer 124 forms the insulating layer 58 described with reference to FIG.

[0186] Depending on the materials forming the etching mask 111 and the protective layer 118, and the particular etch used to remove the etching mask 111, the etch of FIG. 3N may selectively remove only the etching mask 111 and not the protective layer 124.

[0187] 3O, the gate layer 110 is defined, thereby forming the gate insulating regions 40, 41. Furthermore, (highly) doped regions 25A, 25B, 27, 29A, 29B, 31 are formed in the epitaxial portion 106 of the surface layer 105, for example through subsequent masking and ion implantation steps, depending on the particular application.

[0188] This is followed by fabrication steps not shown here to form insulating and / or passivation layers of wafer 100 (e.g., oxide layers 35, 36 in FIG. 1) and to form metal contact regions of electronic components 5, 7 (e.g., regions 42-45 and 61, 62, 65 in FIG. 1).

[0189] Further final manufacturing steps, not shown here, such as forming a top layer of metal interconnects and dicing the wafer, may then follow, thereby forming device 1.

[0190] In fact, the growth mask 103 can be used to form the isolation region 70 in FIG. 1. Therefore, the growth of the epitaxial multilayer 49 produces low mechanical stress, and therefore reduces the probability of dislocation. Therefore, the manufacturing process has high reliability.

[0191] Furthermore, the use of the growth mask 103 can simultaneously allow for both growing a single crystal epitaxial portion 106 onto which silicon-based electronic components 5 can be integrated, and protecting the surface quality of the upper surface 100A below the growth mask 103, onto which the work multilayer film 114 is grown.

[0192] The manufacturing process therefore makes it possible to integrate both silicon-based electronic components 5 and heterostructure-based electronic components 7 within the same die, while obtaining high crystallographic quality of the heterostructure 50 .

[0193] The fact that the growth mask 103 may be made of a different material (here, for example, silicon oxide) relative to the second intermediate layer 18 (here, for example, silicon) and in particular may be etchable by a different chemical species relative to the chemical species that can be used to remove the second intermediate layer 18, makes it possible to form openings or recesses 113 through the sacrificial portions 107 exposing the underlying top surface 100A without, at least to a first approximation, affecting the quality of the surface 100A on which the work epitaxial multilayer 117 (Figures 3G to 3J) is grown.

[0194] In fact, the growth mask 103 can be used as a stop layer during etching of the overlying sacrificial portion 107, thus ensuring complete removal of the overlying sacrificial portion 107. Furthermore, the formation of the openings in the growth mask 103 does not affect the quality of the underlying surface 100A, e.g., terracing and pitting.

[0195] The epitaxial multilayer 49, and therefore the heterostructure 50, can have high crystallographic quality.

[0196] As a result, the corresponding electronic components 7, whose function is based on the formation of a two-dimensional gas in the heterostructure 50, can have high electrical performance when in use.

[0197] At the same time, the electronic components 5 are also integrated in the monocrystalline silicon layer (epitaxial portion 106), which may have high crystallographic quality, so that the electronic components 5 may have high electrical performance during use.

[0198] Furthermore, the thickness of the growth mask 103 can be made thick enough to be used as a mask for forming the epitaxial multilayer 49, while at the same time being thin enough to minimize non-planarity of the top surface 105A of the superficial layer 105. In fact, the top surface 105A of the superficial layer 105 can be considered to be substantially flat. This can facilitate subsequent fabrication steps that result in the formation of both the silicon-based electronic components 5 and the heterostructure-based electronic components 7.

[0199] As a starting substrate for forming a semiconductor electronic device 1 <111> The possibility of using a silicon substrate 14 of any orientation may enable a high epitaxial quality of the heterostructure 50 to be obtained, especially if the channel layer 55 is of or includes GaN. As a result, the heterostructure-based electronic component 7 may have excellent electrical performance. The applicant also <111> It has also been found that the use of a silicon substrate 14 allows the silicon-based electronic component 5 to have superior electrical performance.

[0200] With reference to the embodiment of the manufacturing process of Figures 3A to 3O, the fact that some of the doped regions of the silicon-based device 5, particularly the highly doped regions such as the source, drain and body contact regions of the PMOS transistor 5A and the NMOS transistor 5B, can be formed after the growth of the epitaxial multilayer film 49, may further contribute to increasing the reliability of the manufacturing of the device 1.

[0201] In fact, the epitaxial multilayer 49 can be grown using a higher thermal budget than the highly doped regions can withstand, and in this manner, the highly doped regions of the silicon-based device 5 can be formed with high reliability.

[0202] For example, the growth of the first buffer layer 52 of AlN may be performed at a temperature of about 1100° C. for a time interval comprised between about 15 and 30 minutes, and the growth of the GaN and AlGaN layers forming the second buffer layer 53, the channel layer 55, the barrier layer 56 and the channel modulation region 64 may be performed in subsequent growth steps at temperatures between about 1030° C. and 1080° C. for an interval between about 5 and 15 minutes, respectively.

[0203] However, it will be apparent to one skilled in the art that the above-described manufacturing steps and the order in which they are performed may vary from that depicted in Figures 3A-3O depending on the particular process and machinery used.

[0204] For example, epitaxial multilayer 49 may be grown after formation of the highly doped region, depending on the particular materials forming epitaxial multilayer 49 and epitaxial region 23 .

[0205] For example, surface 105A may not be flat, depending on, for example, the growth mode used to grow layer 105, the thickness of layer 102, and surface treatments (e.g., chemical-mechanical polishing) performed following epitaxial growth.

[0206] 4 shows a different embodiment of an isolation region, here indicated by 170. This isolation region 170 here comprises a polycrystalline region formed by three polycrystalline portions 173A, 173B, 173C and two trenches 175A, 175B extending through the polycrystalline region along a third axis Z.

[0207] Also, in this embodiment, polycrystalline portions 173A, 173B, 173C are separated from one another by trenches 175A, 175B.

[0208] The trenches 175A, 175B are substantially concentric with each other and completely surround the epitaxial multilayer 49 in which the HEMT transistor 7 is integrated.

[0209] The trenches 175A, 175B may each have a width, measured between two adjacent polycrystalline portions, comprised for example in the range 0.2 μm to 3 μm. The trenches 175A, 175B may extend from each other at a distance comprised for example in the range 0.5 μm to 5 μm.

[0210] The greater the number of trenches, the greater the contribution they can make to reducing the mechanical stress between the epitaxial multilayer 49 and the epitaxial region 23 .

[0211] FIG. 5 shows a further embodiment of an isolation region, here indicated by 190, comprising a polycrystalline region formed here by a plurality of polycrystalline portions 195 and a trench, here indicated by 193, which extends through the polycrystalline region and is defined internally by an epitaxial multilayer film 49 and externally by an epitaxial region 23 (not shown here).

[0212] In particular, the polycrystalline portions 195 are arranged at a distance from each other within the trench 193. In effect, the polycrystalline portions 195 each form a polycrystalline pillar starting from the defined region 72 and extending along the third axis Z.

[0213] The pillars 195 may each have a width along the first axis X and / or the second axis Y comprised, for example, between 0.5 μm and 5 μm. The pillars 195 may extend from one another at a distance comprised, for example, between 0.2 μm and 3 μm.

[0214] The pillars 195 may have a constant or variable cross-section along the third axis Z, for example polygonal or circular (regular or irregular).

[0215] The pillars 195 may be distributed around the multilayer film 49 according to a regular or irregular distribution, depending on the particular design layout.

[0216] In effect, pillars 195 form distinct portions of polycrystalline regions that extend alongside and especially around epitaxial multilayer 49 .

[0217] Finally, it will be apparent that other modifications and variations may be made to the electronic device 1 and its manufacturing process described and illustrated herein without departing from the scope of the present disclosure.

[0218] The isolation region 70 may have a structure different from that shown and described with reference to FIGS.

[0219] The trenches 75, 175A, 175B, 190 may only partially surround the epitaxial multilayer 49.

[0220] The trenches 75, 175A, 175B, 190 may extend along the third axis Z only partially through the polycrystalline region, i.e., so as not to contact the defined region 72. Indeed, in this case, the polycrystalline portions 73A, 73B of Figure 1, the polycrystalline portions 173A, 173B, 173C of Figure 4, and the polycrystalline portion 195 of Figure 5 are continuous with one another and form a monolithic polycrystalline region.

[0221] In practice, the polycrystalline regions of the isolation regions 70, 170, 190 may be formed by one or more polycrystalline portions that are continuous or separate from one another, in other words, the polycrystalline regions may be single monolithic regions or may be discontinuous regions.

[0222] Trenches 175A, 175B, 190 may be empty or filled (partially or completely) similar to that discussed for trench 75 of Figure 1. Furthermore, possible filling of trenches 175A, 175B, 190 may be uniform or non-uniform around epitaxial multilayer 49, depending on the particular fabrication process used.

[0223] The electronic device 1 may comprise only heterostructure-based electronic components 7 and not silicon-based electronic components 5. The presence of the isolation regions, in particular the respective polycrystalline regions, contributes to a reduction of the mechanical stresses caused by the growth of the epitaxial multilayer 49 and thus allows a good crystallographic quality of the heterostructure 50.

[0224] The electronic device 1 may comprise other silicon-based electronic components 5, active and / or passive, integrated within the die 3 in addition to or instead of the PMOS transistor 5A and the NMOS transistor 5B.

[0225] For example, as shown in Figure 2, the silicon-based electronic component 5 may also include a bipolar transistor 5C and passive components 5D, such as diodes and resistors, in which the bipolar transistor 5C and the passive components 5D are integrated in respective device portions 120, 121 that are separate from each other and are indicated diagrammatically by dashed lines.

[0226] For example, device portions 120 , 121 are formed in respective single crystal silicon epitaxial regions grown on substrate region 10 , and in particular are formed monolithically with epitaxial region 23 .

[0227] Insulating regions, for example shallow or deep trenches, may be arranged, in a manner known per se, between portions 120, 121 and 20, so that the respective electronic components are, during use, electrically isolated from one another.

[0228] 1, the insulating region 82 extending between the first device portion 20 and the second device portion 21 may have a shape and structure different from that shown. For example, it may comprise one or more trenches extending in the epitaxial region 23 to a greater depth in the die 3 along the third axis Z so as to mutually electrically insulate the portion of the substrate region 10 located below the device portion 21 in which the HEMT transistor 7 is integrated from the portion of the substrate region 10 located below the device portion 20 in which the PMOS transistor 5A and the NMOS transistor 5B are integrated.

[0229] The formation of such deep isolation trenches may be integrated into the manufacturing process described with reference to Figures 3A-30. For example, Figure 6A shows a cross-section of wafer 100 after the manufacturing step of Figure 3H.

[0230] In the wafer 100 of FIG. 6A, a deep isolation trench 210 has been formed in the wafer 100, particularly in the epitaxial portion 106 of the surface layer 105, and partially in the substrate region 10.

[0231] In this embodiment, the deep isolation trench 210 is formed simultaneously with the trench 75, thus optimizing the number of lithography and etching steps.

[0232] The deep isolation trench 210 and the trench 75 can be formed simultaneously even though the deep isolation trench 210 and the trench 75 have different depths in the wafer 100 along the third axis Z. In fact, the definition region 72 serves as a stop layer during the etching of the workpiece polycrystalline region 114. As a result, it is possible to adjust the depth of the deep isolation trench 210 by adjusting the etching time without compromising the formation of the trench 75.

[0233] However, deep isolation trench 210 may be formed through a dedicated lithography and etching process, ie, through a process separate (either above or subsequent) from that used to form trench 75 .

[0234] 6B, here 212. In this embodiment, the workpiece epitaxial multilayer 212 is grown conformally both in the trench 75 and in the deep isolation trench 210.

[0235] Device 1 may also comprise other silicon-based electronic components 5 integrated within die 3 in addition to or instead of those shown in Figure 2. For example, components 5 may include MOS transistors for medium voltage applications, e.g., 15V to 20V, DMOS transistors and / or drift MOS transistors for applications with operating voltages, e.g., 20V to 200V, thin film resistors, OTP or MTP memory, phase change memory, etc.

[0236] It will be clear to a person skilled in the art that the integration of different types of silicon-based electronic components 5 can be carried out through manufacturing steps which are known per se and therefore not further shown here, for example through the BCD technique.

[0237] For example, the conductivity types, n or p, of the various semiconductor regions may be reversed with respect to those described.

[0238] Epitaxial multilayer 49 may include a different number of layers than shown and described.

[0239] For example, the epitaxial multilayer 49 may include only the heterostructure 50. In other words, the heterostructure 50 may be grown directly on the substrate region 10.

[0240] Heterostructure 50 may include other semiconducting and / or insulating layers, for example between channel layer 55 and barrier layer 56, depending on the particular application.

[0241] For example, the heterostructure-based components 7 may include electronic components other than HEMT transistors 7 .

[0242] For example, the HEMT transistor 7 may be of the normally-off type and the gate structure may be different from that described above. For example, the gate structure may be recessed and / or the fabrication of the gate structure may include the use of a fluorine plasma under the gate structure. Alternatively, the HEMT transistor 7 may be of the normally-on type, i.e., of the depletion type.

[0243] For example, the number of epitaxial layers forming substrate region 10 may vary depending on the particular application.

[0244] For example, the growth of the workpiece multilayer 114, 212 may vary from that described with reference to Figures 3J and 6B, depending on the particular growth parameters used.

[0245] As a result, the shape of epitaxial multilayer 49 may differ from that shown in Figure 1. For example, peripheral portion 84 may not be conformal with inner sidewall 77.

[0246] For example, the multilayer film 114 may be selectively grown starting only from the exposed portion 101B of the second intermediate layer 18. In this case, the removal step described with reference to Figure 3M may be omitted.

[0247] For example, depending on the desired thickness of the epitaxial multilayer 49 and the epitaxial region 23 along the third axis Z, the second intermediate layer 18 may be omitted and the epitaxial multilayer 49 may be grown directly on the second deep layer 17.

[0248] For medium or low voltage (e.g. 7V-40V) applications, the substrate region 10 may comprise only the substrate 14 and the first deep layer 15 (or the first intermediate layer 16). Indeed, in this case, the epitaxial multilayer 49 can be grown directly on the first deep layer 15 or on the first intermediate layer 16, if any.

[0249] In practice, in summary, in the present semiconductor electronic device, the substrate region 10 can comprise a monocrystalline substrate 14 having a first conductivity type (e.g., P) and at least one epitaxial layer (15-18) extending over the substrate and having a conductivity type different from that of the substrate (e.g., N).

[0250] For example, the electronic component 5 may be an electronic component based on a single semiconductor other than silicon, such as Ge, SiGe, etc.

[0251] The above described embodiments can be combined to provide further solutions.

[0252] The semiconductor electronic device (1) comprises a substrate region (10) of a semiconductor material, a first electronic component (7) based on a heterostructure comprising an epitaxial multilayer (49) extending on the substrate region and comprising a heterostructure (50), an isolation region (70, 170, 190) extending on the substrate region and comprising polycrystalline regions (73A, 73B, 173A, 173B, 173C) of a semiconductor material of polycrystalline type arranged alongside the epitaxial multilayer along a first direction (X, Y), and an epitaxial region (23) of a single semiconductor material of monocrystalline type extending on the substrate region (10), the polycrystalline regions (73A, 73B, 173A, 173B, 173C, 195) extending along the first direction (X) between the epitaxial multilayer (49) and the epitaxial region (23).

[0253] The semiconductor electronic device further includes a second electronic component (5) based on a single semiconductor material and integrated in the epitaxial region (23), the second electronic component being, for example, one of a CMOS transistor, a DMOS transistor, a bipolar transistor, or a passive electronic component based on a single semiconductor material.

[0254] The isolation region (70, 170, 190) includes at least one trench (75, 175A, 175B, 195) that extends into the polycrystalline region.

[0255] The polycrystalline region includes multiple portions (73A, 73B, 173A, 173B, 173C, 195) that are different from one another and separated by at least one trench.

[0256] Two adjacent parts of the polycrystalline region (73A, 73B, 173A, 173B, 173C, 195) extend at a mutual distance of 0.2 μm to 3 μm.

[0257] The polycrystalline region portions (195) are each pillars having a width of 0.5 μm to 5 μm.

[0258] The isolation region further includes a definition region (72) that includes an oxide and extends between the substrate region (10) and the polycrystalline region.

[0259] The defined region (72) has a thickness of 7 nm to 300 nm.

[0260] The isolation region (70, 170, 190) at least partially surrounds the epitaxial multilayer (49).

[0261] The epitaxial region (23) is of a first semiconductor material, for example silicon, and the heterostructure (50) includes a second semiconductor material, for example GaN, that is different from the first semiconductor material.

[0262] The process for manufacturing a semiconductor electronic device (1) comprises providing a wafer (100) including a substrate layer (18) of a semiconductor material having a first growth portion (101B) and a second growth portion (101C) different from the first growth portion, growing on the first growth portion an epitaxial multilayer (49) including a heterostructure (50), starting from the heterostructure to form a first electronic component (7) based on the heterostructure, and growing on the second growth portion along a first direction (X, Y) an epitaxial multilayer (49) including a heterostructure (50). forming an isolation region (70, 170, 190) including a polycrystalline region (73A, 73B, 173A, 173B, 173C, 195) of a semiconductor material of a polycrystalline type arranged alongside the multilayer film; and forming an epitaxial region (23) of a single semiconductor material of a monocrystalline type extending on the substrate layer (18), the polycrystalline region (73A, 73B, 173A, 173B, 173C, 195) extending along a first direction (X) between the epitaxial multilayer film (49) and the epitaxial region (23).

[0263] The substrate layer includes a third growth portion (101A) different from the first and second growth portions, and the method further comprises forming on the substrate layer a growth mask (103) covering the first growth portion (101B) and the second growth portion (101C) of the substrate layer, growing a surface layer (105) of a single semiconductor material having a monocrystalline portion (106) extending on the third growth portion (101A) of the substrate layer and a polycrystalline portion (107) extending on the growth mask, wherein the polycrystalline region of the separation region is formed starting from the polycrystalline portion of the surface layer and the epitaxial region is formed starting from the monocrystalline portion of the surface layer, and forming an opening (113) in the polycrystalline portion (107) of the surface layer (105) and in the growth mask (103) exposing the first growth portion (101B) of the substrate layer before growing the epitaxial multilayer film (117, 212).

[0264] The manufacturing process further comprises forming a second electronic component (5) based on a single semiconductor material integrated within the monocrystalline portion (106) of the surface layer (105).

[0265] Forming the isolation region (70, 170, 190) includes forming at least one trench (75, 175A, 175B, 195) through the polycrystalline portion (107) of the surface layer (105) and above the third growth portion (101C) of the substrate layer (18).

[0266] The trench (75) is formed prior to growing the epitaxial multilayer.

[0267] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts from various patents, applications, and publications to provide further embodiments.

[0268] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but rather to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. a substrate region of semiconductor material; a first electronic component based on a heterostructure, the first electronic component comprising an epitaxial multilayer extending over the substrate region and including a heterostructure; an isolation region extending over the substrate region and including a polycrystalline region of a polycrystalline type semiconductor material aligned alongside the epitaxial multilayer along a first direction; an epitaxial region of a single semiconductor material of monocrystalline type extending over said substrate region, said polycrystalline region extending along said first direction between said epitaxial multilayer and said epitaxial region; a first trench in the isolation region, the trench separating the polycrystalline region into a first portion and a second portion different from the first portion.

2. 2. The semiconductor electronic device of claim 1, further comprising a second electronic component based on the single semiconductor material and integrated in the epitaxial region, the second electronic component being one of a CMOS transistor, a DMOS transistor, a bipolar transistor, or a passive electronic component based on a single semiconductor material.

3. 2. The semiconductor electronic device of claim 1, further comprising a second trench in said isolation region, said second trench further separating said polycrystalline region into a third portion different from said first portion and said second portion.

4. 4. The semiconductor device of claim 3, wherein the first electronic component is surrounded by the first trench, and the first trench is surrounded by the second trench.

5. 5. The semiconductor electronic device according to claim 4, wherein two adjacent portions of said polycrystalline region extend at a mutual distance comprised between 0.2 μm and 3 μm.

6. 5. The semiconductor electronic device of claim 4, wherein said portions of said polycrystalline regions are each pillars having a width comprised between 0.5 μm and 5 μm.

7. 2. The semiconductor electronic device of claim 1, wherein said isolation region further comprises a definition region comprising an oxide and extending between said substrate region and said polycrystalline region.

8. The semiconductor electronic device according to claim 7, wherein said defined region has a thickness comprised between 7 nm and 300 nm.

9. The semiconductor electronic device of claim 1 , wherein the isolation region at least partially surrounds the epitaxial multilayer.

10. 10. The semiconductor electronic device of claim 1, wherein the epitaxial region is of a first semiconductor material and the heterostructure comprises a second semiconductor material that is different from the first semiconductor material.

11. 1. A process for manufacturing a semiconductor electronic device, comprising: providing a wafer comprising a substrate layer of semiconductor material having a first growth portion and a second growth portion different from the first growth portion; growing an epitaxial multilayer film having a heterostructure on the first growth portion; Starting from a heterostructure, forming a first electronic component based on said heterostructure; forming an isolation region on the second growth portion, the isolation region including a polycrystalline region of a polycrystalline type semiconductor material disposed alongside the epitaxial multilayer along a first direction; forming an epitaxial region of a single semiconductor material of a single crystal type extending over the substrate layer; the polycrystalline region extends along the first direction between the epitaxial multilayer and the epitaxial region.

12. the substrate layer includes a third growth portion different from the first growth portion and the second growth portion; forming a growth mask on the substrate layer covering the first growth portion and the second growth portion of the substrate layer; growing a surface layer of a single semiconductor material having a monocrystalline portion extending on the third growth portion of the substrate layer and a polycrystalline portion extending on the growth mask, the polycrystalline portion of the isolation region being formed starting from the polycrystalline portion of the surface layer and the epitaxial region being formed starting from the monocrystalline portion of the surface layer; 12. The manufacturing process of claim 11, further comprising, prior to growing the epitaxial multilayer, forming openings in the polycrystalline portion of the surface layer and in the growth mask exposing the first growth portion of the substrate layer.

13. 13. The manufacturing process according to claim 12, further comprising forming a second electronic component based on a single semiconductor material integrated within the single crystal portion of the surface layer.

14. 12. The manufacturing process of claim 11, wherein forming the isolation region comprises forming at least one trench through the polycrystalline portion of the surface layer above the third growth portion of the substrate layer.

15. 15. The manufacturing process of claim 14, wherein the trench is formed prior to growing the epitaxial multilayer.

16. forming the isolation region forming a trench through the polycrystalline region; and forming a plurality of polycrystalline portions within the trench.

17. The process of claim 16 , wherein the plurality of polycrystalline portions are a plurality of polycrystalline pillars.

18. A semiconductor substrate; a first electronic device on the semiconductor substrate, the first electronic device comprising: A heterostructure; a first electronic device including an epitaxial multilayer; a trench region on the semiconductor substrate surrounding the first electronic device; a plurality of polycrystalline pillars in the trench; an epitaxial region on the semiconductor substrate surrounding the trench.

19. 20. The system of claim 18, wherein the epitaxial region is of a first semiconductor material and the heterostructure includes a second semiconductor material that is different from the first semiconductor material.

20. 20. The system of claim 18, further comprising a second electronic device on the semiconductor substrate, the second electronic device being one of a CMOS transistor, a DMOS transistor, a bipolar transistor, or a single semiconductor material passive electronic component.

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