Input-output device

Abstract

To reduce the number of transistors for a photoelectric conversion element.SOLUTION: A display circuit that becomes a display state according to data of a display data signal, and a plurality of light detection circuits that generate light data according to the illuminance of incident light are included. The light detection circuit includes X (X is a natural number of 2 or more) photoelectric conversion elements, X charge accumulation control transistors in each of which one of a source and a drain is electrically connected to a second current terminal of one of the X photoelectric conversion elements and one of X charge accumulation control signals is input in a gate from a light detection circuit control unit, and an amplification transistor whose gate is electrically connected to one of the source and the drain of each of the X charge accumulation control transistors.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to an input / output device. [Background technology]

[0002] In recent years, devices that have the function of outputting information and the function of inputting information by the incidence of light have become Technological development of input / output devices (also known as input / output devices) is progressing.

[0003] The input / output device is composed of a number of display circuits and a number of light detection circuits (optical sensors) arranged in a row and column direction. The pixel section is equipped with an optical sensor (also called an optical sensor) that detects the illuminance of light incident on the optical sensor. A function to detect the coordinates of the object to be read that is superimposed on the base part (also called a coordinate detection function) and An example is an input / output device that has a function to generate image data of the object (reading function). For example, Patent Document 1. The input / output device shown in Patent Document 1 includes a photodiode, an amplifier transistor, and a The photodetector circuit is made up of a photodiode, a photodiode, a photodiode, a photodiode, a photodiode, and a photodiode. It has been made. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2010-182064 A Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional input / output devices, an amplifier transistor and a first A photodetector reset transistor and a selection transistor are provided. There was a problem with the number of transistors per conversion element. If the size of the pixel is too small, it will be difficult to reduce the size of the pixel, and the leakage current of the transistor will be affected. The sound also gets louder.

[0006] One embodiment of the present invention is to reduce the number of transistors for one photoelectric conversion element and One of the objectives is to reduce the effect of leakage current of a transistor. do. [Means for solving the problem]

[0007] One embodiment of the present invention is a photoelectric conversion element, a charge storage control transistor, and an amplifying transistor. and a photodetection circuit including at least an amplification transistor shared by a plurality of photoelectric conversion elements. This allows the number of transistors in the pixel section to be reduced. We aim to reduce this.

[0008] Further, one embodiment of the present invention is a photoelectric conversion element, a charge storage control transistor, and an amplifying transistor. and an output selection transistor, and an output selection transistor are shared by a plurality of photoelectric conversion elements to form a photodetection circuit. This makes it possible to reduce the number of transistors in a pixel portion.

[0009] Further, one embodiment of the present invention is a photoelectric conversion element, a charge storage control transistor, and an amplifying transistor. a photodetection circuit including an output select transistor and a photodetection reset transistor; At least an amplifying transistor, an output selection transistor, and a photodetector reset transistor The photodetection circuit is configured by sharing the same signal between multiple photoelectric conversion elements. The number of transistors in a pixel portion is reduced.

[0010] In addition, according to one embodiment of the present invention, a charge storage control transistor having a small off-state current is provided for each photoelectric conversion element. The photoelectric conversion element is provided with a photodiode that stores an amount of charge for a certain period of time according to the illuminance of light incident on the photoelectric conversion element. This reduces the effect of leakage current of the transistor. Effect of the Invention

[0011] According to one embodiment of the present invention, the number of transistors relative to the number of photoelectric conversion elements can be reduced. Therefore, the number of transistors in the pixel portion can be reduced. [Brief description of the drawings]

[0012] [Figure 1] 1 is a diagram for explaining an input / output device according to Embodiment 1. [Diagram 2] 10A to 10C illustrate an example of a photodetector circuit in Embodiment 2. [Diagram 3] 13A to 13C are diagrams illustrating examples of photodetection circuits in Embodiment 3. [Figure 4] 13A to 13C illustrate an example of a display circuit in Embodiment 4. [Diagram 5] 13A to 13C illustrate examples of transistors in Embodiment 5. [Figure 6] 5A to 5C are schematic cross-sectional views illustrating an example of a method for manufacturing the transistor shown in FIG. [Figure 7] FIG. 1 is a diagram for explaining a characteristic evaluation circuit. [Figure 8] FIG. 13 is a graph showing the relationship between the elapsed time Time in measurements in SMP4, SMP5, and SMP6, and the output voltage Vout and leakage current calculated by the measurements. [Figure 9] FIG. 13 is a graph showing the relationship between the voltage and leakage current at node A estimated by measurement. [Figure 10] FIG. 13 is a graph showing the relationship between the voltage and leakage current at node A estimated by measurement. [Figure 11] FIG. 13 is a graph showing the relationship between the voltage and leakage current at node A estimated by measurement. [Figure 12] FIG. 13 is a graph showing the relationship between the voltage and leakage current at node A estimated by measurement. [Figure 13] 13A and 13B are diagrams illustrating a structural example of an active matrix substrate in an input / output device of Embodiment 6. [Figure 14] 13A and 13B are diagrams illustrating a structural example of an active matrix substrate in an input / output device of Embodiment 6. [Figure 15] 13 is a diagram illustrating a structural example of an input / output device in embodiment 6. [Figure 16] 13 is a diagram illustrating a structural example of an input / output device in embodiment 6. [Figure 17] FIG. 23 is a schematic diagram showing a configuration example of an electronic device according to a seventh embodiment. [Figure 18] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 19] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 20] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 21] FIG. 13 is a diagram illustrating the gate voltage dependence of mobility obtained by calculation. [Figure 22] FIG. 13 is a diagram illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Diagram 23] FIG. 13 is a diagram illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 24] FIG. 13 is a diagram illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Diagram 25] FIG. 13 illustrates a cross-sectional structure of a transistor used in calculation. [Figure 26] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 27] 1A and 1B are top views and cross-sectional views illustrating structures of transistors corresponding to Samples 1 to 6. [Figure 28]13 shows the Vg-Id characteristics and field-effect mobility of the transistors of Sample 3 and Sample 4. [Figure 29] 13 shows Vg-Id characteristics and field-effect mobility of a transistor of Sample 1 before and after a BT test. [Diagram 30] 13 shows Vg-Id characteristics and field-effect mobility of a transistor of Sample 4 before and after a BT test. [Diagram 31] 13 shows Vg-Id characteristics and field-effect mobility as a function of measurement temperature of the transistor of Sample 4. [Diagram 32] 13 shows temperature characteristics of threshold voltage and field-effect mobility of a transistor which is Sample 4. [Diagram 33] FIG. 1 shows an XRD spectrum of an In—Sn—Zn—O film. [Diagram 34] FIG. 13 shows the off-state current of a transistor including an In-Sn-Zn-O film. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] An embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the following description, and any modifications and variations are possible without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the form and details of the present invention. The invention should not be construed as being limited to the description of the embodiments shown below.

[0014] The contents of each embodiment can be appropriately combined with each other. The contents of can be substituted for each other.

[0015] In addition, terms using ordinal numbers such as 1st and 2nd are added to avoid confusion of components. and each component is not limited to an ordinal number.

[0016] (Embodiment 1) In this embodiment, it is possible to output information by displaying an image, and the incident light An example of an input / output device that allows information to be input via a keyboard will now be described.

[0017] An example of an input / output device according to the present embodiment will be described with reference to FIG. FIG. 13 is a diagram for explaining an example of an input / output device in the embodiment.

[0018] First, a configuration example of an input / output device in this embodiment will be described with reference to FIG. Fig. 1(A) is a schematic diagram showing a configuration example of an input / output device according to the present embodiment.

[0019] The input / output device shown in FIG. 1A includes a display circuit control unit 101a and a light detection circuit control unit 101b. , a light source section 101c, and a pixel section 101d.

[0020] The display circuit control unit 101a includes a display drive circuit (also called DISPDRV) 111 and a display device. and a data signal output circuit (also called DDOUT) 112.

[0021] The photodetection circuit control unit 101b is connected to a photodetection drive circuit (also called PSDRV) 113 and a readout and a detection circuit 116.

[0022] The light source section 101c includes a light unit (also called LIGHT) 114.

[0023] The pixel unit 101d includes a plurality of display circuits (also called DISPs) 115d and a plurality of light detection circuits. In addition, one or more display circuits 115d may be used to display one A pixel is formed. The pixel may include one or more photodetection circuits 115p. The display circuits 115d are arranged in rows and columns in the pixel section 101d. The multiple photodetection circuits 115p are arranged in rows and columns in the pixel section 101d.

[0024] The display driver circuit 111 outputs a plurality of display selection signals (also called signals DSEL) which are pulse signals. It has the function of outputting.

[0025] The display drive circuit 111 includes, for example, a shift register. A display selection signal can be output by outputting a pulse signal from the register. .

[0026] An image signal is input to the display data signal output circuit 112. 12 is a display data signal (also called a signal DD) which is a voltage signal based on the input image signal. and outputs the generated display data signal.

[0027] The display data signal output circuit 112 includes, for example, a switching transistor.

[0028] In an input / output device, a transistor has two terminals and a voltage applied to the two terminals. and a current control terminal for controlling the current flowing between the two terminals. In an element, the terminals between which the current flowing between them is controlled are also called current terminals. The two current terminals are also referred to as a first current terminal and a second current terminal, respectively.

[0029] In the input / output device, a field effect transistor is used as a transistor. In the case of a field effect transistor, the first current terminals may be the source and drain. the first current terminal is the other of the source and the drain, and the current control terminal is It is a gate.

[0030] In general, voltage refers to the difference in electric potential (also called potential difference) between two points. However, voltage and potential values ​​are often expressed in volts (V) in circuit diagrams, etc. Therefore, in this specification, unless otherwise specified, The potential difference between the potential at a point and the reference potential (also called the reference potential) is called the voltage at that point. It may be used.

[0031] The display data signal output circuit 112 outputs an image signal when the switching transistor is in an on state. The switching transistor can output the data of the signal as a display data signal. The current can be controlled by inputting a control signal, which is a pulse signal, to the current control terminal. In addition, when the number of the display circuits 115d is plural, a plurality of switching transistors By selectively turning on or off the image signal data, a plurality of display data are obtained. The signal may be output as a timer signal.

[0032] The photodetection drive circuit 113 outputs a photodetection reset signal (also called a signal PRST) which is a pulse signal. ), and a storage control signal (also called signal TX), which is a pulse signal. If necessary, the photodetector driver circuit 113 outputs a pulse signal, which is an output selection signal (signal OSEL and The configuration may have a function of outputting a signal (also referred to as a signal).

[0033] The light detection drive circuit 113 includes, for example, a shift register. 13 outputs a pulse signal from the shift register to generate a light detection reset signal and and an accumulation control signal, or a light detection reset signal, an accumulation control signal, and an output selection signal. It is possible.

[0034] The light unit 114 is a light emitting unit equipped with a light source.

[0035] The light source may be, for example, a cold cathode fluorescent lamp or a light emitting diode. The laser has a wavelength in the visible light region (for example, a region in which the wavelength of light is 360 nm to 830 nm). The light emitting diode is a light emitting diode that emits light that emits light. The number of light emitting diodes of each color may be more than one. In addition, examples of light emitting diodes include red light emitting diodes, green light emitting diodes, and A blue light emitting diode may be used. A red light emitting diode, a green light emitting diode, and a blue By using color light emitting diodes, for example, the display can be switched according to the display selection signal during one frame period. Thus, one or more of a red light emitting diode, a green light emitting diode, and a blue light emitting diode are used. A driving method that displays full-color images by sequentially switching the number of LEDs to emit light (filter). It is possible to use a full-color sequential drive method and to read objects in full color. It is possible to read the following.

[0036] For example, a control circuit for controlling the lighting of a light emitting diode is provided, and the control signal is a pulse signal. It is also possible to control the lighting of the light emitting diode in accordance with a control signal input to the control circuit.

[0037] The display circuit 115d is superimposed on the light unit 114. The display circuit 115d includes a light Light is incident from the unit 114. A display circuit 115d receives a display signal, which is a pulse signal. A selection signal is input, and a display data signal is input according to the input display selection signal. The display circuit 115d has a function of changing the display state according to the data of the input display data signal. has.

[0038] The display circuit 115d includes, for example, a display selection transistor and a display element.

[0039] The display selection transistor selects whether or not to input data of the display data signal to the display element. It has the function of

[0040] The display element is configured such that data of a display data signal is inputted according to the display selection transistor. As a result, the display state corresponds to the data of the display data signal.

[0041] As the display element, for example, a liquid crystal element can be used.

[0042] In addition, the display method of the input / output device equipped with the liquid crystal element is TN (Twisted Nem atic) mode, IPS (In Plane Switching) mode, STN ( Super Twisted Nematic) mode, VA(Vertical Al ignment) mode, ASM(Axially Symmetric aligne) d Micro-cell mode, OCB (Optically Compensated ed Birefringence mode, FLC (Ferroelectric L iquid Crystal mode, AFLC (AntiFerroelectric) Liquid Crystal mode, MVA (Multi-Domain Ver tical Alignment) mode, PVA(Patterned Vertic) mode Alignment) mode, ASV (Advanced Super View ) mode, or FFS (Fringe Field Switching) mode, etc. It may be used.

[0043] The light detection circuit 115p is overlapped with the light unit 114. For example, When there is an object to be read, the light emitted from the light unit 114 is reflected by the object. The reflected light is incident on the photodetection circuit 115p. A set signal and a charge accumulation control signal are input. A detection circuit 115p may also be provided. For example, red, green, and blue color filters may be provided. A photodetector is provided for each color through red, green, and blue color filters. Generate light data using 115p, and synthesize multiple light data to generate image data. By doing so, full-color image data can also be generated.

[0044] The photodetection circuit 115p includes X (X is a natural number of 2 or more) photoelectric conversion elements (also called PCEs). The charge storage control transistor includes at least X charge storage control transistors and an amplifying transistor.

[0045] Each of the X photoelectric conversion elements has a first current terminal and a second current terminal. Each of the first current terminals of the electrochemical conversion element is connected to a unit voltage or X number of photodetection reset signals. Among them, different light detection reset signals are input. By doing so, a current (also called a photocurrent) flows according to the illuminance of the incident light. When a unit voltage is input to the first current terminal of the photoelectric conversion element, The value of the unit voltage input to the first current terminal is set appropriately.

[0046] The first current terminals of the X charge storage control transistors are connected to the X photoelectric conversion elements. Among them, X charge storage capacitors are electrically connected to the second current terminals of the different photoelectric conversion elements. Each of the current control terminals of the control transistors is connected to one of the X charge storage control signals. Different charge accumulation control signals are input to the

[0047] A unit voltage is input to one of the first current terminal and the second current terminal of the amplifying transistor. The optical data is outputted to the optical detector via the other of the first current terminal and the second current terminal of the amplifying transistor. The current control terminal of the amplifying transistor is connected to X charge storage control transistors. The X charge storage control transistors are electrically connected to the second current terminals of the X charge storage control transistors. The control transistor shares one amplifier transistor. The value is set appropriately.

[0048] In addition, the photodetection circuit 115p is connected to the first current terminal or the second current terminal of the amplification transistor. The optical data is output as an optical data signal via the optical fiber.

[0049] The read circuit 116 selects the photodetection circuit 115p from which the optical data is to be read, and The output circuit 115p has a function of reading out optical data.

[0050] The read circuit 116 is configured using, for example, a selection circuit. A photodetection circuit 115p is provided with a switching transistor. By inputting an optical data signal from the optical fiber 10, optical data can be read out.

[0051] Further, a configuration example of the photodetection circuit 115p will be described with reference to FIG. 1A is a circuit diagram showing a configuration example of a photodetection circuit in the input / output device shown in FIG.

[0052] The photodetection circuit shown in FIG. 1B includes photoelectric conversion elements 131_1 to 131_Z ( Z photoelectric conversion elements (Z is a natural number of 3 or more), a transistor 132, and a transistor 1 33 and Z transistors 134_1 to 134_Z. 4 and is equipped with.

[0053] A first current terminal of the photoelectric conversion element 131_K (K is a natural number from 1 to Z) is connected to a photodetection reset terminal. A reset signal PRST_K is input.

[0054] Each of the photoelectric conversion elements 131_1 to 131_Z may be, for example, a photodiode. A diode or a phototransistor can be used. In the case of a photodiode One of the anode and the cathode of the photodiode is connected to a first current terminal of the photoelectric conversion element. In this case, the other of the anode and the cathode of the photodiode is a second current terminal of the photoelectric conversion element. In the case of a phototransistor, the source and drain of the phototransistor are One of the terminals corresponds to the first current terminal of the photoelectric conversion element, and the other corresponds to the source and drain of the phototransistor. The other of the rains corresponds to a second current terminal of the photoelectric conversion element.

[0055] One of the source and drain of the transistor 134_K is connected to the second The gate of the transistor 134_K is connected to the current terminal of the transistor 134_K. The gate of the transistor 134_K is connected to the charge storage control signal TX_ K is input to the transistor 134_K. The connection point with element 131_K is also referred to as node N11_K.

[0056] Each of the transistors 134_1 to 134_Z is a charge storage control transistor. It functions as a register.

[0057] Each of the transistors 134_1 to 134_Z may be, for example, a channel A transistor including an oxide semiconductor layer in which a gate electrode is formed can be used. The conductor layer is an intrinsic (also called I-type) or substantially intrinsic semiconductor layer, and the carrier The number is extremely small, and the carrier concentration is 1×10 14 / cm 3 Less than 1 x 10 1 2 / cm 3 less than 1×10 11 / cm 3 is less than.

[0058] The off-state current of the transistor including the oxide semiconductor layer is 1 μm per 1 μm of channel width. 0aA(1×10 -17 A) or less, preferably 1aA (1×10 -18 A) The following: is preferably 10zA (1×10 -20 A) or less, more preferably 1zA (1×10 - 21 A) or less, and more preferably 100yA (1×10 -22 A) The following:

[0059] In addition, since the oxide semiconductor layer has a low carrier concentration, a transistor including the oxide semiconductor layer Even when the temperature of a transistor changes, the off-state current is low. Even at a temperature of 150° C., the off-state current is 100 zA / μm or less.

[0060] A voltage V0 is input to one of the source and drain of the transistor 132. The gate of the transistor 132 is connected to the sources of the transistors 134_1 through 134_Z and The gate of the transistor 132 and the drain of the transistor 133 are connected to each other. The other of the sources and drains of the transistors 134_1 to 134_Z The connection point of these is also referred to as a node N12. The value of the voltage V0 is set appropriately.

[0061] The transistor 132 functions as an amplifying transistor.

[0062] One of the source and drain of the transistor 133 is connected to the source and drain of the transistor 132. The signal OSEL is input to the gate of the transistor 133. .

[0063] The transistors 132 and 133 are, for example, transistors in which a channel is formed. A semiconductor layer or channel containing a semiconductor of Group 14 of the periodic table (such as silicon) In the present invention, a transistor including an oxide semiconductor layer in which a gate insulating film is formed can be used. The transistors including the layer include transistors 134_1 to 134_Z. A transistor including an applicable oxide semiconductor layer can be used.

[0064] In addition, the transistors 134_1 to 134_Z and the transistor 133 The transistor 132 is formed using an oxide semiconductor layer in which a channel is formed. A panel is formed, which produces semiconductors containing semiconductors from Group 14 of the periodic table (such as silicon). A layer of the material may also be used.

[0065] Next, an example of a method for driving the photodetector circuit shown in FIG. 1B will be described with reference to FIG. FIG. 1C is a timing chart for explaining an example of a method for driving the photodetector circuit shown in FIG. 1 is a chart showing signals PRST_1 to PRST_Z, signals TX_1 to TX_ The respective states of the photoelectric conversion element, Z, and the signal OSEL are shown here as an example. Each of the photoelectric conversion elements 131_1 to 131_Z is a photodiode, and a voltage V A case where the value of 0 is the same as the reference potential will be described.

[0066] In the example of the method for driving the photodetection circuit illustrated in FIG. 1B, in the period T11, A pulse (also called pls) of the signal TX_1 and a pulse of the signal TX_2 are input, and further, during a period T12 A pulse of the signal PRST_2 and a pulse of the signal TX_2 are input. Then, Different pulses of the signal PRST and the signal TX are input in sequence for each period. Then, a pulse of the signal PRST_Z and a pulse of the signal TX_Z are input.

[0067] While the pulses of the signals PRST_K and TX_K are being input, the photoelectric conversion element 131_ K is in a state where a current flows in the forward direction, and transistor 134_K is in an on state. This resets the voltages of the nodes N11_K and N12 to a constant value. Therefore, the voltages of the nodes N11_1 to N11_Z are reset in sequence. The voltage on board N12 is also reset.

[0068] In the period T11 to the period T13, the pulse width of the signal PRST_K is It is preferable that the pulse width of the signal TX_K is longer than that of the signal TX_K. It is preferable that the pulse of the signal PRST_K is still being input.

[0069] Furthermore, during periods T11 to T13, after the pulse of the signal PRST_K is input, Until the pulse of the signal TX_K is input again, the photoelectric conversion element 131_K receives the first current A voltage is applied between the first terminal and the second current terminal in the direction opposite to the forward direction. At this time, a current flows through the photoelectric conversion element 131_K in accordance with the illuminance of the incident light. The voltage value of the node N11_K changes in response to the current flowing through the node 131_K. During periods T11 to T13, after the pulse of the signal PRST_K is input, the signal TX The period until the K pulse is input is also called the accumulation period.

[0070] Furthermore, in a period T14, a pulse of the signal TX_1 is input, and in a period T15, A pulse of the signal OSEL is input. Furthermore, in a period T16, a pulse of the signal TX_2 is input. In a period T17, a pulse of the signal OSEL is input. The pulses of the signal PRST are input in sequence, and during the period after the pulses of the signal PRST are input, In period T18, a pulse of the signal OSEL is input, and in period T19, a pulse of the signal TX_Z is is input, and in a period T19, a pulse of the signal OSEL is input.

[0071] During the period T14 to the period T19, while the pulse of the signal TX_K is being input, the The resistor 134_K is turned on, and the voltages of the nodes N11_K and N12 are At this time, the voltage of the node N11_K and the voltage of the node N12 are respectively When the voltage at node N12 changes, the transistor 13 The value of the channel resistance between the source and drain of MOSFET 2 changes.

[0072] Also, while the signal OSEL is being pulsed, the transistor 133 is in an on state. , the source and drain of transistor 132, and the source and drain of transistor 133 The current flows through the source and drain of transistor 132 and the The current flowing through the source and drain of the transistor 133 is equal to the voltage at the node N12, i.e. That is, it depends on the value of the voltage at the gate of the transistor 132. current flowing through the source and drain of transistor 133 is a value according to the illuminance of light incident on the photoelectric conversion element 131_K during the accumulation period. For example, The higher the illuminance of the light incident on the photoelectric conversion element 131_K, the lower the voltage of the optical data. However, the present invention is not limited to this, and the higher the illuminance of the light, the higher the voltage of the optical data can be. In the photodetection circuit shown in FIG. The other output of the optical signal is an optical data signal.

[0073] In the period T14 to the period T19, after the pulse of the signal OSEL is input, Before a pulse of a signal TX_M (M is a natural number from 2 to Z) is input, signals TX_M-1 and Then, node N12 may be put into the reset state again by inputting a pulse on signal PRST_M-1. In this manner, during the period T14 to the period T19, a pulse of the signal OSEL is input. Then, before the next pulse of the signal TX_M (M is a natural number from 2 to Z) is input, the signal TX By inputting the pulses of _M-1 and PRST_M-1, the reset operation is performed again. Since there is no need to perform the above steps, the reading (also called imaging) cycle can be shortened. 1B is a driving method example of the photodetector circuit shown in FIG.

[0074] Next, as an example of a method for driving the input / output device in this embodiment, the input / output device shown in FIG. An example of a method for driving the device will now be described.

[0075] In the example of the driving method of the input / output device shown in FIG. 1A, the display circuit A display data signal is input to the display circuit 115d, and the display circuit 115d converts the input display data signal The pixel section 101d is brought into a display state according to the data, and displays an image.

[0076] In addition, in the example of the driving method of the input / output device shown in FIG. 1(A), the optical detector described with reference to FIG. A driving method of the output circuit is used to drive the light detection circuits 115p in response to the illuminance of light incident on each of the light detection circuits 115p. The optical data is generated based on the received signal and output sequentially as an optical data signal.

[0077] Furthermore, the optical data output from the multiple optical detection circuits 115p is read by the read circuit 116. The read optical data is used for, for example, detecting the coordinates of the object to be read or for detecting image data. It is used for specific processing such as generation.

[0078] An image signal is generated from the generated optical data, and a display data signal is generated using the image signal. This allows the display image to be changed in response to the optical data.

[0079] As described with reference to FIG. 1, an example of the input / output device in this embodiment is a photodetector circuit. In the above, one amplifier transistor and one output selection transistor are controlled by a plurality of charge storage circuits. The above-mentioned structure is shared by a transistor and a plurality of photoelectric conversion elements. This makes it possible to reduce the number of transistors in the pixel portion. By reducing the number of transistors, the size of each pixel can be reduced or the number of photoelectric conversion elements can be reduced. For example, the larger the size of the photoelectric conversion element, the larger the input power. The sensitivity to incoming light is improved.

[0080] In addition, an example of the input / output device in this embodiment includes at least a charge storage control transistor As a result, a transistor having a low off-state current and including an oxide semiconductor layer in which a channel is formed is provided. By using the above-mentioned configuration, the leakage current of the charge storage control transistor Since the fluctuation of the optical data due to the interference can be suppressed, the signal-to-noise ratio can be improved. In addition, in the past, multiple charge storage control transistors were connected to the gate of one amplification transistor. When the other of the source and drain is connected, the leakage current of the charge storage control transistor However, the above configuration results in a large fluctuation in the gate voltage of the amplifier transistor. This makes it possible to suppress fluctuations in optical data caused by leakage current from the charge storage control transistor. This allows multiple charge storage control transistors to be connected to the gate of one amplification transistor. Even if the other of the source and drain is connected, the voltage of the gate of the amplifier transistor Therefore, it is possible to suppress the fluctuation of one amplifier transistor. In the case where the charge storage control transistor is used in common with the transistor and the photoelectric conversion element, As a transistor, a transistor including an oxide semiconductor layer in which a channel is formed and in which an off-current is small is used. It is preferable to use a resistor.

[0081] (Embodiment 2) In this embodiment mode, another example of the photodetector circuit in the input / output device of the above embodiment mode will be described. In the example of the photodetector circuit in this embodiment, the input / output The same parts as the photodetection circuits in the input / output device of the above embodiment are the same as those in the input / output device of the above embodiment. The description of the detection circuit will be used as appropriate.

[0082] An example of a photodetection circuit according to the present embodiment will be described with reference to FIG. 1 is a diagram for explaining a light detection circuit in the embodiment. FIG.

[0083] First, a configuration example of a photodetector circuit in this embodiment will be described with reference to FIG. 2A is a circuit diagram showing a configuration example of a photodetection circuit according to this embodiment.

[0084] The photodetection circuit shown in FIG. 2A includes a photoelectric conversion element 13 similarly to the photodetection circuit shown in FIG. Z photoelectric conversion elements 131_1 to 131_Z, a transistor 132, A transistor 133 and Z transistors 134_1 to 134_Z Further, the photodetection circuit shown in FIG. Prepare.

[0085] In the photodetection circuit shown in FIG. 2A, the first current terminal of the photoelectric conversion element 131_K is A voltage Vb is input.

[0086] One of the source and drain of the transistor 134_K is connected to the second The gate of the transistor 134_K is connected to the current terminal of the transistor 134_K. The gate of the transistor 134_K is connected to the charge storage control signal TX_ K is entered.

[0087] A voltage V0 is input to one of the source and drain of the transistor 132. The gate of the transistor 132 is connected to the sources of the transistors 134_1 through 134_Z and The drains are connected to the other respective ones of the drains.

[0088] One of the source and drain of the transistor 133 is connected to the source and drain of the transistor 132. The signal OSEL is input to the gate of the transistor 133. .

[0089] A voltage Va is input to one of the source and drain of the transistor 135. The other of the source and drain of the transistor 135 is connected to the gate of the transistor 132. The gate of the transistor 135 receives the light detection reset signal PRST.

[0090] Transistor 135 resets the voltage at the gate of transistor 132 (node ​​N12). The transistor functions as a photodetector reset transistor.

[0091] One of the voltages Va and Vb is a high power supply voltage Vdd, and the other of the voltages Va and Vb is a high power supply voltage Vdd. The other is a low power supply voltage Vss. The values ​​of the voltages Va and Vb are determined by, for example, the transistor These may be interchanged depending on the polarity of the

[0092] Next, an example of a method for driving the photodetector circuit shown in FIG. 2A will be described with reference to FIG. FIG. 2B is a timing chart for explaining an example of a method for driving the photodetector circuit shown in FIG. 1 is a chart showing the operation of the signal PRST, the signals TX_1 to TX_Z, and the signal OSEL. In this example, the photoelectric conversion elements 131_1 to 131_2 are shown in the respective states. Each of the elements 131_Z is a photodiode, the voltage Va is a high power supply voltage, and The case where the voltage Vb is a low power supply voltage and the value of the voltage V0 is the same as the reference potential will be described. do.

[0093] In the example of the method for driving the photodetector circuit illustrated in FIG. 2A, the power of the signal TX_1 is In the period T21, a pulse of the signal TX_2 is input. After that, a pulse of a different signal TX is input in each period, and in the period T23, the signal T A pulse of X_Z is input. Also, one pulse of the signal PRST is input from the period T21 to the period It is entered through T23.

[0094] While the pulses of the signals PRST and TX_K are being input, the transistor 135 is on. In this state, the photoelectric conversion element 131_K is in a state in which a current flows in the forward direction, and the transistor This causes the transistor 134_K to turn on. The voltages of the nodes N11_1 to N11_Z are reset to a constant value. The voltages are reset in sequence.

[0095] Furthermore, during the period T21 to T23, after the pulse of the signal TX_K is input, Until a pulse of the optical signal TX_K is input, the optical transducer 131_K is connected to the first current terminal A voltage is applied between the first current terminal and the second current terminal in a direction opposite to the forward direction. A current flows through the photoelectric conversion element 131_K in accordance with the illuminance of the incident light. The voltage value of the node N11_K changes according to the current flowing through the node N31_K. In the period T23, after the pulse of the signal TX_K is input, the pulse of the signal TX_K is input again. The period until the pulse is input is also called the accumulation period.

[0096] Furthermore, in a period T24, a pulse of the signal PRST is input, and in a period T25, A pulse of the signal TX_1 is input, and in a period T26, a pulse of the signal OSEL is input. Furthermore, in a period T27, a pulse of the signal PRST is input, and in a period T28, During a period T29, a pulse of the signal OSEL is input. After that, the signal PRST is pulsed several times. Each time a pulse of a different signal TX is input, a different pulse of the signal TX is input in the following period. In the period after the pulse is input, a pulse of the signal OSEL is input, and in the period T30 In period T31, a pulse of the signal PRST is input, and in period T32, a pulse of the signal TX_Z is input. In period T32, a pulse of the signal OSEL is input.

[0097] During the period T24 to T32, while the pulse of the signal PRST is being input, the node The voltage at N12 is reset.

[0098] During the period T24 to the period T32, while the pulse of the signal TX_K is being input, The transistor 134_K is turned on, and the voltage of the node N11_K and the voltage of the node N12 At this time, the voltages of the nodes N11_K and N12 are respectively When the voltage at node N12 changes, the transistor The value of the channel resistance between the source and drain of the transistor 132 changes.

[0099] During the period T24 to the period T32, while the pulse of the signal OSEL is being input, The transistor 133 is turned on, and the source and drain of the transistor 132 and A current flows through the source and drain of the transistor 133. and the source and drain of transistor 133. The current depends on the voltage at node N12, i.e., the value of the voltage at the gate of transistor 132. Therefore, the source and drain of the transistor 132 and the source and drain of the transistor 133 The current flowing through the source and drain is incident on the photoelectric conversion element 131_K during the accumulation period. The value corresponds to the illuminance of the light. For example, when the illuminance of the light incident on the photoelectric conversion element 131_K is high, The voltage of the optical data can be lowered as the photoelectric conversion element The higher the illuminance of the light incident on 131_K, the higher the voltage of the optical data can be. The photodetection circuit shown in FIG. 2(A) is a photodiode that is connected to the other of the source and drain of the transistor 133. The data is output as an optical data signal.

[0100] In the period T24 to the period T32, after the pulse of the signal OSEL is input, Before a pulse of a signal TX_M (M is a natural number from 2 to Z) is input, signals TX_M-1 and Then, node N12 may be put into the reset state again by inputting a pulse on signal PRST_M-1. In this manner, during the period T24 to the period T32, a pulse of the signal OSEL is input. Then, before the next pulse of the signal TX_M (M is a natural number from 2 to Z) is input, the signal TX By inputting the pulses of _M-1 and PRST_M-1, the reset operation is performed again. Since there is no need to perform the above steps, the reading (also called imaging) cycle can be shortened. 2A is a diagram illustrating an example of a method for driving the photodetector circuit shown in FIG.

[0101] As described with reference to FIG. 2, an example of the photodetection circuit according to the present embodiment includes one amplifier transistor. A transistor and one output selection transistor are connected to a plurality of charge storage control transistors and a plurality of By using the above-mentioned configuration, the pixel portion is The number of transistors in the pixel area can be reduced. By reducing the number of pixels, the size of one pixel can be reduced or the size of a photoelectric conversion element can be increased. For example, the larger the size of the photoelectric conversion element, the higher the sensitivity to incident light. do.

[0102] Furthermore, in one example of the photodetection circuit according to the present embodiment, the gate voltage of the amplification transistor is The configuration includes a photodetection reset transistor that selects whether or not to reset. By configuring it this way, the accuracy of the optical data according to the illuminance of the light incident on the optical detection circuit is improved. It is possible to do so.

[0103] (Embodiment 3) Another example of the photodetector circuit in the input / output device of the above embodiment will be described. In the example of the light detection circuit in the embodiment, the light detection For the same parts as the circuits, the description of the photodetection circuit in the input / output device of the above embodiment will be applied. Please use as appropriate.

[0104] An example of a photodetection circuit according to the present embodiment will be described with reference to FIG. 1 is a diagram for explaining a light detection circuit in the embodiment. FIG.

[0105] First, a configuration example of a photodetector circuit in this embodiment will be described with reference to FIG. 3A is a circuit diagram showing a configuration example of a photodetection circuit according to this embodiment.

[0106] The photodetection circuit shown in FIG. 3A includes a photoelectric conversion element 13 similarly to the photodetection circuit shown in FIG. Z photoelectric conversion elements 131_1 to 131_Z, a transistor 132, Z transistors, ie, transistors 134_1 to 134_Z, The photodetector circuit shown in FIG. 3(A) and the photodetector circuit shown in FIG. In comparison, the photodetection circuit shown in FIG. 3A does not include the transistor 133. .

[0107] In the photodetection circuit shown in FIG. 3A, the first current terminal of the photoelectric conversion element 131_K is A voltage Vb is input.

[0108] One of the source and drain of the transistor 134_K is connected to the second The gate of the transistor 134_K is connected to the current terminal of the transistor 134_K. The gate of the transistor 134_K is connected to the charge storage control signal TX_ K is entered.

[0109] A voltage V0 is input to one of the source and drain of the transistor 132. The gate of the transistor 132 is connected to the sources of the transistors 134_1 through 134_Z and The drains are connected to the other respective ones of the drains.

[0110] A reset voltage signal (signal VRS) is applied to one of the source and drain of the transistor 135. The other of the source and drain of the transistor 135 is connected to a transistor 132 and the gate of the transistor 135 is connected to the light detection reset signal PR ST is entered.

[0111] Next, an example of a method for driving the photodetector circuit shown in FIG. 3A will be described with reference to FIG. FIG. 3B is a timing chart for explaining an example of a method for driving the photodetection circuit shown in FIG. 1 is a chart showing the operation of the signal PRST, the signals TX_1 to TX_Z, and the signal OSEL. In this example, the photoelectric conversion elements 131_1 to 131_2 are shown in the respective states. Each of the elements 131_Z is a photodiode, the voltage Va is a high power supply voltage, and A case will be described where voltage Vb is a low power supply voltage and the value of voltage V0 is the same as the reference potential.

[0112] In the example of the method for driving the photodetection circuit shown in FIG. 3A, the power of the signal PRST is Also, one pulse of the signal VRS is input from the period T41 to the period T45. The input is

[0113] While the signals PRST and VRS are being pulsed, the transistor 135 is in an on state. The voltage at node N12 is reset to a constant value.

[0114] Furthermore, a pulse of the signal TX_1 is input during the period T42. While the TX_1 pulse is being input, the signal PRST pulse is input. During the period T43, a pulse of the signal TX_2 is input. While the pulse of the signal PRST is being input, a pulse of the signal PRST is input. Then, a different signal The TX pulses are input sequentially, and while the TX pulse is being input, the PRST signal is A pulse of the signal TX_Z is input during a period T44. While a pulse of the signal TX_Z is being input, a pulse of the signal PRST is input.

[0115] During the period T42 to T44, before the pulse of the signal PRST_K is input, the signal T While the X_K pulse is being input, the transistor 134_K is in the on state, and the node The voltage of node N11_K and the voltage of node N12 change. The voltage at node N1 and the voltage at node N12 change according to the ratio of capacitance added to each of them. When the voltage at 2 changes, the value of the channel resistance between the source and drain of transistor 132 changes. changes.

[0116] In addition, current flows through the source and drain of transistor 132. The current flowing through the source and drain of 132 is proportional to the voltage of node N12, i.e., the transistor It depends on the value of the voltage at the gate of the transistor 132.

[0117] During the period T42 to T44, the pulses of the signal TX_K and the signal VRS are input. During this time, the voltage at node N12 is reset to a value equal to voltage Va.

[0118] Furthermore, during the period T42 to T44, after the pulse of the signal PRST_K is input, , until a pulse of the signal TX_K is input again (for example, the signal T Until the pulse of X_K is input), the photoelectric conversion element 131_K is connected to the first current terminal and A voltage is applied between the current terminals of the photodiode and the photodiode in the reverse direction. A current flows through the conversion element 131_K in accordance with the illuminance of the incident light, and the photoelectric conversion element 131_ The value of the node N11_K changes depending on the current flowing through the node N11_K. At 44, after the pulse of the signal PRST_K is input, the pulse of the signal TX_K is input again. The period until input is also called the accumulation period.

[0119] The current flowing through the source and drain of the transistor 132 is The value corresponds to the illuminance of the light incident on the conversion element 131_K. For example, The higher the illuminance of the light incident on the _K, the lower the voltage of the optical data can be. The photodetection circuit shown in FIG. 1 receives optical data from the other of the source and drain of the transistor 132. The optical data signal representing the

[0120] Furthermore, during a period T45, after the pulse of the signal VRS is input, the pulse of the signal PRST is The address is entered.

[0121] During a period T45, while the pulse of the signal PRST is being input, the transistor 135 At this time, the voltage of node N12 is reset, and the voltage of node N12 becomes This voltage becomes equal to the voltage of the signal VRS, and the transistor 132 is turned off. 13 is an example of a method for driving the photodetection circuit shown in (A).

[0122] As described with reference to FIG. 3, an example of the photodetection circuit according to the present embodiment includes one amplifier transistor. A transistor is shared by a plurality of charge storage control transistors and a plurality of photoelectric conversion elements. By adopting the above-mentioned structure, the number of transistors in the pixel portion can be reduced. By reducing the number of transistors in the pixel area, It is possible to reduce the size of the element or to increase the size of the photoelectric conversion element. The larger the size of the element, the greater the sensitivity to incident light.

[0123] Furthermore, in one example of the photodetection circuit according to the present embodiment, the gate voltage of the amplification transistor is The configuration includes a photodetection reset transistor that selects whether or not to reset. By configuring it this way, the accuracy of the optical data according to the illuminance of the light incident on the optical detection circuit is improved. It is possible to do so.

[0124] As described with reference to FIG. 3, an example of the photodetection circuit in this embodiment is a photoelectric conversion element a charge storage control transistor, an amplifying transistor, and a gate voltage of the amplifying transistor The configuration includes a light detection reset transistor that selects whether or not to reset the voltage. By adopting the above configuration, the accuracy of generating optical data according to the illuminance of light incident on the optical detection circuit is improved. This improves the efficiency while reducing the number of transistors by eliminating the output selection transistor. Cut.

[0125] (Embodiment 4) In this embodiment mode, an example of a display circuit in the input / output device of the above embodiment mode will be described. .

[0126] An example of a display circuit in this embodiment will be described with reference to FIG. 1A and 1B are diagrams illustrating an example of a display circuit in the embodiment.

[0127] First, a configuration example of a display circuit in this embodiment will be described with reference to FIGS. 4A and 4B. 4A and 4B show a configuration example of a display circuit in this embodiment. FIG.

[0128] The display circuit shown in FIG. 4A includes a transistor 161a, a liquid crystal element 162a, and a capacitor. 163a.

[0129] Note that in the display circuit illustrated in FIG. 4A, the transistor 161a is a field-effect transistor. It is Sta.

[0130] In the input / output device, the liquid crystal element includes a first display electrode, a second display electrode, and a liquid crystal layer. The liquid crystal layer is configured by applying a voltage between the first display electrode and the second display electrode. The light transmittance changes depending on the

[0131] In the input / output device, the capacitance element includes a first capacitance electrode, a second capacitance electrode, and a first The capacitance element includes a dielectric layer overlapping the first capacitance electrode and the second capacitance electrode. A charge is accumulated between the first and second capacitive electrodes in response to a voltage applied therebetween.

[0132] A signal DD is input to one of the source and drain of the transistor 161a. The signal DSEL is input to the gate of the first transistor 161a.

[0133] The first display electrode of the liquid crystal element 162a is connected to the source and drain of the transistor 161a. A voltage Vc is input to the second display electrode of the liquid crystal element 162a. The value of the voltage Vc can be set appropriately.

[0134] The first capacitor electrode of the capacitor 163a is connected to the source and drain of the transistor 161a. A voltage Vc is input to the second capacitance electrode of the capacitance element 163a. .

[0135] The display circuit shown in FIG. 4B includes a transistor 161b, a liquid crystal element 162b, and a capacitor. 163b, a capacitance element 164, a transistor 165, and a transistor 166. do.

[0136] Note that in the display circuit shown in FIG. 4B, the transistor 161b and the transistor 165 , and transistor 166 are field effect transistors.

[0137] A signal DD is input to one of the source and drain of the transistor 165. A write selection signal (also called a signal WSEL) which is a pulse signal is input to the gate of the transistor 165. is entered.

[0138] A first capacitor electrode of the capacitor 164 is connected to the other of the source and drain of the transistor 165. A voltage Vc is input to the second capacitive electrode of the capacitive element 164 which is electrically connected to the first capacitive electrode.

[0139] One of the source and drain of the transistor 161b is connected to the source and drain of the transistor 165. The gate of the transistor 161b is electrically connected to the other drain of the transistor 161b. is entered.

[0140] The first display electrode of the liquid crystal element 162b is connected to the source and drain of the transistor 161b. A voltage Vc is input to the second display electrode of the liquid crystal element 162b. .

[0141] The first capacitor electrode of the capacitor 163b is connected to the source and drain of the transistor 161b. A voltage Vc is input to the second capacitance electrode of the capacitance element 163b. The value of the voltage Vc is set appropriately according to the specifications of the display circuit.

[0142] A reference voltage is input to one of the source and drain of the transistor 166. The other of the source and drain of the transistor 166 is connected to the source and drain of the transistor 161b. The gate of the transistor 166 is electrically connected to the other input of the A display reset signal (also called a signal DRST) is input.

[0143] Furthermore, each component of the display circuit shown in FIG. 4(A) and FIG. 4(B) will be described.

[0144] The transistors 161a and 161b function as display selection transistors. has.

[0145] The liquid crystal layer in the liquid crystal element 162a and the liquid crystal element 162b includes a first display electrode and A liquid crystal layer that transmits light when the voltage applied to the display electrode of 2 is 0 V can be used. For example, electrically controlled birefringent liquid crystal (also called ECB type liquid crystal), liquid crystal with added dichroic dye (G It uses a liquid crystal layer containing polymer dispersed liquid crystal or discotic liquid crystal. The liquid crystal layer may be a liquid crystal layer exhibiting a blue phase. The liquid crystal layer exhibiting a blue phase is composed of a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. Liquid crystals that exhibit a blue phase have a short response time of less than 1 msec and are optically isotropic. Therefore, no alignment treatment is required and the viewing angle dependency is small. By using it, the operation speed can be improved.

[0146] The capacitor 163a and the capacitor 163b are connected to the transistor 161a or the transistor 16 1b, a voltage corresponding to the signal DD is applied between the first capacitive electrode and the second capacitive electrode. The capacitor 163a and the capacitor 163b function as a storage capacitor. However, by providing the capacitance elements 163a and 163b, Suppresses fluctuations in voltage applied to liquid crystal elements caused by leakage currents in display selection transistors It is possible.

[0147] The capacitance element 164 is connected between the first capacitance electrode and the second capacitance electrode through the transistor 165. The capacitor has a function as a storage capacitor to which a voltage corresponding to the signal DD is applied.

[0148] The transistor 165 is a write transistor that selects whether or not to input the signal DD to the capacitance element 164. It functions as a select transistor.

[0149] The transistor 166 selects whether or not to reset the voltage applied to the liquid crystal element 162b. It has a function as a display reset selection transistor that selects

[0150] The transistors 161a, 161b, 165, and The transistor 166 is, for example, a semiconductor of group 14 in the periodic table, in which a channel is formed. A transistor including a semiconductor layer containing a material (such as silicon) or an oxide semiconductor layer is used. It is possible.

[0151] Next, an example of a method for driving the display circuit shown in FIGS. 4A and 4B will be described.

[0152] First, an example of a method for driving the display circuit shown in FIG. 4A will be described with reference to FIG. FIG. 4C is a timing chart for explaining an example of a method for driving the display circuit shown in FIG. 13 shows the respective states of the signals DD and DSEL.

[0153] In the example of the driving method of the display circuit shown in FIG. 4A, when a pulse of the signal DSEL is input, The transistor 161a is turned on.

[0154] When the transistor 161a is turned on, a signal DD is input to the display circuit, and the liquid crystal element 1 The voltage of the first display electrode of the capacitor element 62a and the first capacitance electrode of the capacitor element 163a is the voltage of the signal DD. will be equivalent to

[0155] At this time, the liquid crystal element 162a is in a write state (also called state wt), and the signal DD As a result, the display circuit receives the data of the signal DD (data D1 to The display state will be according to each of the data DQ (Q is a natural number equal to or greater than 2).

[0156] After that, the transistor 161a is turned off, and the liquid crystal element 162a is in the holding state (state hld), and the voltage applied between the first display electrode and the second display electrode is The amount of variation from the initial value becomes greater than the reference value until the next pulse of the DSEL signal is input. When the liquid crystal element 162a is in the holding state, the input of the above embodiment is held. The light unit in the output device is turned on.

[0157] Next, an example of a method for driving the display circuit shown in FIG. 4B will be described with reference to FIG. FIG. 4D is a timing chart for explaining an example of a method for driving the display circuit shown in FIG. 4B. It is.

[0158] In the example of a method for driving a display circuit shown in FIG. 4B, when a pulse of a signal DRST is input, The transistor 166 is turned on, and the first display electrode of the liquid crystal element 162b and the capacitance element 1 The voltage of the first capacitive electrode of 63b is reset to a reference voltage.

[0159] When a pulse of the signal WSEL is input, the transistor 165 is turned on. A signal DD is input to the display circuit, and the first capacitance electrode of the capacitance element 164 has a voltage equal to the voltage of the signal DD. The value becomes

[0160] After that, when a pulse of the signal DSEL is input, the transistor 161b is turned on. The voltage of the first display electrode of the liquid crystal element 162b and the voltage of the first capacitance electrode of the capacitance element 163b are The voltage at the first capacitive electrode of the capacitance element 164 becomes equal to the voltage at the first capacitive electrode of the capacitance element 164 .

[0161] At this time, the liquid crystal element 162b is in a writing state, and the light transmittance corresponds to the signal DD. As a result, the display circuit receives the data of the signal DD (data D1 to data DQ). ) will be displayed according to the

[0162] After that, the transistor 161b is turned off, and the liquid crystal element 162b is in a holding state. Then, the voltage applied between the first display electrode and the second display electrode is changed to the pulse of the signal DSEL. The amount of variation from the initial value is kept so as not to exceed the reference value until a new value is input. When the liquid crystal element 162b is in the holding state, the light in the input / output device of the above embodiment The unit will turn on.

[0163] As described with reference to FIGS. 4A and 4B, one of the display circuits in this embodiment An example is a configuration including a display selection transistor and a liquid crystal element. This allows the display circuit to be put into a display state according to the display data signal.

[0164] As described with reference to FIG. 4B, an example of the display circuit in this embodiment is a display In addition to the display selection transistor and the liquid crystal element, the display device is provided with a write selection transistor and a capacitance element. By adopting the above-mentioned configuration, the liquid crystal element is caused to respond to the data of a certain display data signal. While the display state is being set to the same state, the data of the next display data signal is written to the capacitance element. Therefore, the operation speed of the display circuit can be improved.

[0165] (Embodiment 5) In this embodiment mode, a transistor in the input / output device described in the above embodiment mode will be Applicable transistors will now be described.

[0166] In the input / output device described in the above embodiment, the transistor is, for example, A channel is formed, and the semiconductor containing the semiconductor of group 14 of the periodic table (such as silicon) A transistor including a conductor layer or an oxide semiconductor layer can be used. The layer formed is also called a channel forming layer.

[0167] The semiconductor layer may be a single crystal semiconductor layer, a polycrystalline semiconductor layer, a microcrystalline semiconductor layer, or an amorphous semiconductor layer. It may be a semiconductor layer.

[0168] Furthermore, in the input / output device described in the above embodiment, As a possible example of a transistor including an oxide semiconductor layer, A transistor having an oxide semiconductor layer that is made substantially intrinsic (also called an intrinsic type) or substantially intrinsic (i-type) It can be used.

[0169] An example of a structure of a transistor including an oxide semiconductor layer will be described with reference to FIG. 1 is a schematic cross-sectional view illustrating a structural example of a transistor according to this embodiment.

[0170] The transistor shown in FIG. 5A is one of bottom-gate transistors. It is also called a tag transistor.

[0171] The transistor illustrated in FIG. 5A includes a conductive layer 401a, an insulating layer 402a, and an oxide semiconductor Layer 403a, conductive layer 405a, and conductive layer 406a.

[0172] A conductive layer 401a is provided on the substrate 400a.

[0173] An insulating layer 402a is provided on the conductive layer 401a.

[0174] The oxide semiconductor layer 403a overlaps with the conductive layer 401a with the insulating layer 402a interposed therebetween.

[0175] The conductive layer 405a and the conductive layer 406a are each formed on a part of the oxide semiconductor layer 403a. It will be established.

[0176] In addition, in FIG. 5A, part of the top surface of the oxide semiconductor layer 403a of the transistor The area where the conductive layer 405a and the conductive layer 406a are not provided is covered with the insulating layer 407a. Contact.

[0177] The insulating layer 407a is formed between the conductive layer 405a, the conductive layer 406a, and the oxide semiconductor layer 403. The insulating layer 402a is in contact with the insulating layer 402 at a location where the insulating layer a is not provided.

[0178] The transistor shown in FIG. 5B includes a conductive layer 408a in addition to the structure shown in FIG. .

[0179] The conductive layer 408a overlaps with the oxide semiconductor layer 403a with the insulating layer 407a interposed therebetween.

[0180] The transistor shown in FIG. 5C is one of bottom-gate transistors.

[0181] The transistor illustrated in FIG. 5C includes a conductive layer 401b, an insulating layer 402b, and an oxide semiconductor Layer 403b, conductive layer 405b, and conductive layer 406b.

[0182] A conductive layer 401b is provided on the substrate 400b.

[0183] An insulating layer 402b is provided on the conductive layer 401b.

[0184] The conductive layer 405b and the conductive layer 406b are provided on a portion of the insulating layer 402b.

[0185] The oxide semiconductor layer 403b overlaps with the conductive layer 401b with the insulating layer 402b interposed therebetween.

[0186] In addition, in FIG. 5C, a top surface of the oxide semiconductor layer 403b in the transistor and The side surface is in contact with the insulating layer 407b.

[0187] The insulating layer 407b is formed between the conductive layer 405b, the conductive layer 406b, and the oxide semiconductor layer 403. In the area where b is not provided, the insulating layer 402b is in contact with the insulating layer 402b.

[0188] In addition, in FIG. 5(A) and FIG. 5(C), a protective insulating layer may be provided on the insulating layer.

[0189] The transistor shown in FIG. 5D includes a conductive layer 408b in addition to the structure shown in FIG. .

[0190] The conductive layer 408b overlaps with the oxide semiconductor layer 403b with the insulating layer 407b interposed therebetween.

[0191] The transistor shown in FIG. 5E is one of top-gate transistors.

[0192] The transistor illustrated in FIG. 5E includes a conductive layer 401c, an insulating layer 402c, and an oxide semiconductor The conductive layer 403c includes a conductive layer 405c and a conductive layer 406c.

[0193] The oxide semiconductor layer 403c is provided over a substrate 400c with an insulating layer 447 interposed therebetween.

[0194] The conductive layer 405c and the conductive layer 406c are provided over the oxide semiconductor layer 403c. do.

[0195] The insulating layer 402c is formed over the oxide semiconductor layer 403c, the conductive layer 405c, and the conductive layer 406c. It will be established.

[0196] The conductive layer 401c overlaps with the oxide semiconductor layer 403c with the insulating layer 402c interposed therebetween.

[0197] Furthermore, each of the components shown in FIG. 5(A) to FIG. 5(E) will be described.

[0198] For example, a light-transmitting substrate can be used as the substrates 400a to 400c. As the light-transmitting substrate, for example, a glass substrate or a plastic substrate can be used. can.

[0199] Each of the conductive layers 401a to 401c functions as a gate of a transistor. Note that the conductive layer having a function as the gate of a transistor is called a gate electrode or a gate This is also called wiring.

[0200] The conductive layers 401a to 401c can be formed of, for example, molybdenum, titanium, chromium, or titanium. Metallic materials such as tantalum, tungsten, aluminum, copper, neodymium, or scandium A layer of a conductive material or an alloy material containing such a material as a main component can be used. The conductive layers 401a to 401c are formed by stacking layers of materials applicable to the formation of the conductive layers 401a to 401c. A conductive layer 401c may also be formed.

[0201] Each of the insulating layers 402a to 402c serves as a gate insulating layer of a transistor. It has functions.

[0202] Examples of the insulating layers 402a to 402c include a silicon oxide layer, a silicon nitride layer, A silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, Using an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer In addition, layers of materials applicable to the insulating layers 402a to 402c can be stacked. Insulating layers 402a to 402c can also be formed.

[0203] The insulating layers 402a to 402c can be formed using, for example, an element belonging to Group 13 of the periodic table. Alternatively, an insulating layer made of a material containing an element and an oxygen element can be used. When the oxide semiconductor layer 403c contains a Group 13 element, the oxide semiconductor layers 403a to By using an insulating layer containing a Group 13 element as the insulating layer in contact with the compound semiconductor layer 403c, This can improve the state of the interface between the insulating layer and the oxide semiconductor layer.

[0204] Examples of materials containing Group 13 elements include gallium oxide, aluminum oxide, and aluminum oxide. Examples of the gallium oxide include gallium gallium oxide and aluminum gallium oxide. Gallium has a higher aluminum content (atomic %) than gallium content (atomic %). Gallium aluminum oxide is a substance with a gallium content (atomic percent) of aluminum. This refers to a substance that contains more than 100% minium (atomic percent).

[0205] For example, insulating layers containing gallium oxide are used as the insulating layers 402a to 402c. As a result, the insulating layers 402a to 402c and the oxide semiconductor layers 403a to 403c are Accumulation of hydrogen or hydrogen ions at the interface with the semiconductor layer 403c can be reduced.

[0206] For example, the insulating layers 402a to 402c may be formed using an insulating material containing aluminum oxide. By using the insulating layers 402a to 402c, the oxide semiconductor layer 403a To reduce accumulation of hydrogen or hydrogen ions at the interface with the oxide semiconductor layer 403c In addition, since the insulation layer containing aluminum oxide is difficult for water to pass through, By using an insulating layer containing silicon, it is possible to prevent water from entering the oxide semiconductor layer through the insulating layer. It can be suppressed.

[0207] The insulating layers 402a to 402c are made of, for example, AlO x (x=3+α, α is a value greater than 0 and less than 1), Ga2O x (x=3+α, α is greater than 0 and less than 1 smallest value), or Ga x Al 2-x O 3+α (x is a value greater than 0 and less than 2, and α is a value greater than 0. A material having a dielectric constant greater than 1 and smaller than 1 can also be used. The insulating layers 402a to 402c can be formed by stacking layers of materials applicable to the insulating layers 402a to 402c. 2c can also be constructed. For example, multiple GaO x Contains gallium oxide, represented by The insulating layers 402a to 402c may be formed by stacking layers containing GaO x The insulating layer contains gallium oxide, and AlO x Aluminum oxide, represented as The insulating layers 402a to 402c may be formed by stacking insulating layers including the above.

[0208] The insulating layer 447 functions as a base layer that prevents diffusion of impurity elements from the substrate 400c. Note that the insulating layer 447 is provided in the transistors having the structures shown in FIGS. It is okay.

[0209] The insulating layer 447 is, for example, a layer of a material applicable to the insulating layers 402a to 402c. In addition, a layer of a material applicable to the insulating layers 402a to 402c can be used. The insulating layer 447 may be formed by stacking the above.

[0210] Each of the oxide semiconductor layers 403a to 403c is a channel of a transistor. The layer functions as a layer in which the channel of the transistor is formed. The layer having a function as a channel formation layer is also referred to as a channel formation layer. As an oxide semiconductor applicable to the oxide semiconductor layer 403c, at least indium (In) It is preferable to use an oxide semiconductor containing In and zinc (Zn). It is preferable to use an oxide semiconductor. In addition, as the oxide semiconductor, for example, a Sn-based metal In addition, the electric properties of a transistor using the above oxide semiconductor can be improved. Gallium (G) is added to the oxide semiconductor as a stabilizer to reduce the variation in characteristics. It is preferable that the oxide semiconductor contains tin (S It is preferable that the oxide semiconductor contains hafnium as a stabilizer. It is preferable that the oxide semiconductor contains arsenic (Hf) as a stabilizer. It is preferred to have aluminum (Al).

[0211] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The oxide semiconductor may contain one or more kinds of tetraethene (Lu).

[0212] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. The metal oxide that can be used as the oxide semiconductor is silicon oxide. The present invention may also include

[0213] In this case, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than a and Zn may be present.

[0214] In the case of using an In-Zn based metal oxide, for example, In:Zn=50:1 or In:Zn= 1:2 (converted to a molar ratio of In2O3:ZnO=25:1 or In2O3:ZnO= 1:4), preferably In:Zn=20:1 to In:Zn=1:1 (in terms of molar ratio) In2O3:ZnO=10:1 to In2O3:ZnO=1:2), more preferably In:Zn=15:1 to In:Zn=1.5:1 (converted to molar ratio In2O3 Oxide target with a composition ratio of In2O3:ZnO=15:2 to In2O3:ZnO=3:4 For example, a semiconductor layer of In-Zn metal oxide can be formed using In-Z The target used for forming the n-type oxide semiconductor has an atomic ratio of In:Zn:O=P:U:R. In this case, R>1.5P+U. By increasing the amount of In, the transistor movement The mobility (also called field effect mobility) can be improved.

[0215] In addition, as an oxide semiconductor, InMO3(ZnO)m (m is a number greater than 0) Materials that can be used include InMO3(ZnO) m M is Ga, Al, Mn, and and Co.

[0216] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:Ga In-Ga-Zn oxide with an atomic ratio of Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) The composition of the oxide may be In:Sn:Zn=1:1. :1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6 :1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having a composition similar to that of the above-mentioned oxide.

[0217] However, the present invention is not limited to these, and may be applied to any semiconductor properties (mobility, threshold voltage, and other electrical properties) required. In addition, the appropriate composition can be selected according to the required semiconductor In order to obtain the desired characteristics, the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, It is preferable to make the interatomic bond distance, density, etc. appropriate.

[0218] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. In addition, it has been reported that the mobility can be improved by reducing the defect density in the bulk of In-Ga-Zn oxides. It can be done.

[0219] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C =1) is close to the oxide composition, a, b, and c are (a-A) 2 +(b-B) 2 + (c-C) 2 ≦r 2 It means that the following condition is satisfied. For example, r can be set to 0.05. The same is true for other oxides.

[0220] The oxide semiconductor may be single-crystalline or non-single-crystalline. In the latter case, it may be amorphous or polycrystalline. In addition, the structure may include a portion having crystallinity in the amorphous state, or a non-amorphous structure. That's fine too.

[0221] Since it is relatively easy to obtain a flat surface for an amorphous oxide semiconductor, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high quality. Therefore, high mobility can be obtained.

[0222] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility equal to or higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form the surface on a thickness of 0.1 nm or less.

[0223] For Ra, the centerline average roughness defined in JIS B0601 can be applied to the surface. It is a value expanded into three dimensions so that it can be used as a reference. It is the average of the absolute value of the deviation from the reference surface to the specified surface. This can be expressed as a "value" and is defined by the following formula:

[0224]

number

[0225] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 )(x2,y2) is the rectangular area bounded by the four points, and Z0 is It refers to the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). The measurement surface is the surface shown by all the measurement data. It consists of three parameters (X, Y, Z) and is expressed as Z = F(X, Y). Note that the range of X (and Y) is 0 to XMAX (and YMAX), and the range of Z is is ZMIN to ZMAX.

[0226] In addition, the oxide semiconductor is preferably a semiconductor having a c-axis orientation and ab-plane, a three-dimensional structure as viewed from the surface or interface direction. It has a square or hexagonal atomic arrangement, and the metal atoms are arranged in layers or in a combination of metal atoms and acids on the c axis. The atoms are arranged in layers, and the a-axis and b-axis directions are different on the ab plane (the c-axis C-Axis Aligned Crystal (CAAC) Next, an oxide containing CAAC will be described.

[0227] In a broad sense, oxides containing CAAC are non-single crystals that are not crystalline when viewed from a direction perpendicular to the ab plane. The atomic arrangement is a triangle, a hexagon, a regular triangle, or a regular hexagon, and the direction perpendicular to the c-axis direction is When viewed from the opposite direction, it is an oxide containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. This refers to.

[0228] CAAC is not single crystal, nor is it entirely amorphous. The crystals contain small crystals, but the boundary between one crystal and another cannot be clearly distinguished. It also says:

[0229] When oxygen is contained in CAAC, a part of the oxygen may be replaced with nitrogen. The c-axes of the individual crystal parts that make up the CAAC are aligned in a certain direction (e.g., the substrate surface on which the CAAC is formed, The CAAC may be aligned in a direction perpendicular to the surface of the CAAC. The normal to the ab plane of the crystal part of the CAAC is in a certain direction (for example, the substrate plane supporting the CAAC, The direction may be perpendicular to the surface of the substrate.

[0230] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Also, depending on the composition, it may be transparent or opaque to visible light. To do.

[0231] An example of such a CAAC is a film-like CAAC that is formed in a direction perpendicular to the film surface or the supporting substrate surface. When observed from the side, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, List crystals in which layered arrangements of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) are observed. It is also possible.

[0232] Next, an example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. 18 to 20. In addition, unless otherwise specified, the upward direction in Fig. 18 to Fig. 20 is the c-axis direction, The plane perpendicular to the ab plane is called the ab plane. Note that when simply referring to the upper and lower halves, the ab plane is used as the boundary. This refers to the upper and lower halves of the case.

[0233] In Figure 18(A), one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereafter referred to as 4) adjacent to the In atom are shown. The structure shown here has a metal atom and a valence atom (O) with a valence atom (O) with a valence atom (O). The structure in Figure 18(A) shows an octahedral structure. For simplicity, the upper and lower halves of FIG. Each group has three 4-coordinate O atoms. The small group shown in Figure 18(A) has a zero charge.

[0234] In Figure 18(B), one pentagonal Ga atom and three trigonal oxygen atoms (hereafter referred to as 3) adjacent to the Ga atom are shown. The structure shows a structure having a 4-coordinated O atom and two 4-coordinated O atoms adjacent to Ga. The 3-coordinated O atom is Both exist on the ab plane. The upper and lower halves of Figure 18(B) each have one quaternary arrangement. In addition, since In also has a 5-coordinate, the structure shown in FIG. 18(B) can be formed. The small group shown in 18(B) has a charge of zero.

[0235] FIG. 18(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 18(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. Or, in the upper half of Figure 18(C), there are three 4-coordinate Os, and in the lower half, there is one There may be 4-coordinated O. The small group shown in Figure 18(C) has a zero charge.

[0236] FIG. 18(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The upper half of Figure 18(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 18(D) has a charge of +1.

[0237] Figure 18(E) shows a small group containing two Zn atoms. The upper half of Figure 18(E) shows one Zn atom. The small group shown in Figure 18(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0238] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a This is called a large group (also called a unit cell).

[0239] Here, we will explain the rules for combining these small groups. The upper three O's of the 6-coordinate In have three adjacent In's downward, and the lower three Each O has three In neighbors in the upward direction. One O in the upper half of the five-coordinate Ga is It has one adjacent Ga in the downward direction, and one O in the lower half has one adjacent Ga in the upward direction. One O in the upper half of the 4-coordinated Zn has one neighboring Zn below it, and the three O in the lower half There are three neighboring Zn atoms in the upward direction. Thus, the four-coordinate O atoms in the upward direction of the metal atom The number of adjacent metal atoms below the O is equal to the number of adjacent metal atoms below the O. The number of coordinated O atoms is equal to the number of adjacent metal atoms above the O atoms. Since O atoms are 4-coordinated, The sum of the number of adjacent metal atoms in the downward direction and the number of adjacent metal atoms in the upward direction is 4. Therefore, The number of 4-coordinated O atoms above a metal atom and the number of 4-coordinated O atoms below another metal atom are When the sum of the number of metal atoms is 4, the two small groups containing metal atoms can bond together. For example, a hexacoordinated metal atom (In or Sn) is bonded via a tetracoordinated oxygen atom in the lower half. In this case, there are three tetracoordinated O atoms, so there are five-coordinated metal atoms (Ga or In) or four-coordinated gold atoms. It will bond to one of the group atoms (Zn).

[0240] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinate oxygen atoms. In addition, multiple small groups are bonded to form a middle layer so that the total charge of the layer structure is zero. Configure groups.

[0241] Figure 19(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 19(B) shows a large group consisting of three medium groups. FIG. 19C shows the atomic arrangement when the layer structure of FIG. 19B is observed from the c-axis direction.

[0242] In FIG. 19(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three tetrahedral O atoms, as shown in the circle. Similarly, in FIG. 19(A), the upper and lower halves of In are Each has one 4-coordinate O, which is shown as 1 in a circle. ) in which the lower half has one tetracoordinate O and the upper half has three tetracoordinate O. n and Zn, which has one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. It shows.

[0243] In FIG. 19(A), the middle group, which is composed of an In-Sn-Zn-O layer structure, is Sn has three tetracoordinate O atoms in the upper half and one in the lower half, and The In bonds to the Zn with three tetracoordinate O in the upper half. The Zn is bonded to the upper half and the lower half of the Zn via one tetracoordinate O. It bonds to In in the lower half, and the In is transferred to two Zn atoms with one tetrahedral O in the upper half. The small group is bonded to a tetracoordinate O atom via one tetracoordinate O atom in the lower half of the small group. The structure is such that three O are bonded to Sn in the upper half and three Sn in the lower half. Multiple units are combined to form larger groups.

[0244] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.66. 7, -0.5. For example, In (6 or 5 coordinates), Zn (4 coordinates ), Sn (5- or 6-coordinate) have charges of +3, +2, and +4, respectively. Therefore, S The small group containing n has a charge of +1. Therefore, to form a layer structure containing Sn, A charge of -1 is required to cancel the charge of +1. The structure that takes the charge of -1 is shown in Figure 18 (E As shown in Fig. 1, there are two small groups containing Zn. For example, there are small groups containing Sn. If there is one small group containing two Zn atoms for each group, the charges are cancelled out. , the total charge of the layer structure can be zero.

[0245] Specifically, the large group shown in FIG. 19(B) is repeated to form an In-Sn- It is possible to obtain Zn-O crystals (In2SnZn3O8). The layered structure of the Sn-Zn-O system is In2SnZn2O7(ZnO). m (m is 0 or a natural number) This can be expressed by the composition formula:

[0246] In addition, there are oxides of four-component metals, such as In-Sn-Ga-Zn oxides and ternary metal oxides. In-Ga-Zn oxide (also written as IGZO), which is an oxide of In-Ga l-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce -Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Z n-type oxide, In-Dy-Zn-type oxide, In-Ho-Zn-type oxide, In-Er-Zn In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide Oxides and oxides of binary metals such as In-Zn oxides, Sn-Zn oxides, and Al- Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and In The same applies when -Ga-based oxides are used.

[0247] For example, Figure 20(A) shows a model of the middle group consisting of an In-Ga-Zn-O layer structure. A diagram of the rule is shown.

[0248] In FIG. 20(A), the middle group, which is made up of an In-Ga-Zn-O-based layer structure, is In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to a certain Zn, and one of the four-coordinate O atoms is connected to the lower half of the Zn via the three four-coordinate O atoms. It bonds to Ga in the upper and lower halves of the two, and through one tetracoordinate O in the lower half of the Ga. In this structure, three tetracoordinate O atoms are bonded to In atoms in the upper and lower halves. Multiple groups combine to form larger groups.

[0249] Figure 20(B) shows a large group consisting of three medium groups. 20(B) shows the atomic arrangement when the layer structure of FIG. 20(B) is observed from the c-axis direction.

[0250] Here, the charges of In (6 or 5 coordinates), Zn (4 coordinates), and Ga (5 coordinates) are respectively Since the charge levels are +3, +2, and +3, the small group containing In, Zn, and Ga is Therefore, if these small groups are combined, the total of the medium groups will be The charge is always 0.

[0251] The middle group, which is made up of an In-Ga-Zn-O-based layer structure, is shown in FIG. Not limited to the middle group, large-scale combination of middle groups with different arrangements of In, Ga, and Zn Groups are also possible.

[0252] The above is an explanation of one example of the crystal structure contained in CAAC.

[0253] Further, the conductive layers 405a to 405c and the conductive layers 406a to 406c shown in FIG. Each of 06c functions as a source or drain of a transistor. The conductive layer functioning as the source of a transistor is also called a source electrode or a source wiring. The conductive layer having a function as the drain of the transistor is formed as a drain electrode or a drain wiring. It is also called.

[0254] Examples of the conductive layers 405a to 405c and the conductive layers 406a to 406c include For example, aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten. A layer of a metal material such as ZnO or an alloy material mainly composed of such a metal material can be used. In addition, the conductive layers 405a to 405c and the conductive layers 406a to 406c The conductive layers 405a to 405c and the conductive layer 404 are stacked by using a stack of layers of a material suitable for the above-mentioned method. The conductive layers 406a to 406c may also be formed.

[0255] In addition, the conductive layers 405a to 405c and the conductive layers 406a to 406c Alternatively, a layer containing a conductive metal oxide may be used. For example, indium oxide, tin oxide, zinc oxide, indium oxide tin oxide alloy, or indium oxide An indium-zinc oxide alloy can be used. The conductive metal oxide applicable to the conductive layers 406a to 406c is silicon oxide. The present invention may also include

[0256] The insulating layers 407a and 407b are the same as the insulating layers 402a to 402c. For example, an insulating layer made of a material containing an element of Group 13 of the periodic table and oxygen may be used. The insulating layer 407a and the insulating layer 407b may be made of, for example, AlO x , GaO x , or Ga x Al 2-x O 3+α It is also possible to use a material represented by the formula:

[0257] For example, the insulating layers 402a to 402c and the insulating layers 407a and 407b are , GaO x The insulating layer may be made of an insulating material containing gallium oxide, which is represented by the formula: The insulating layer 402a to the insulating layer 402c and the insulating layer 407a and the insulating layer 407b are each formed of a G a2O x The insulating layers 402a to 402b are each formed of an insulating layer containing gallium oxide. The layer 402c and the other of the insulating layers 407a and 407b are made of AlO x It is written as Alternatively, the insulating layer may be made of aluminum oxide.

[0258] Each of the conductive layers 408a and 408b functions as a gate of a transistor. Note that when the transistor has a structure including the conductive layer 408a and the conductive layer 408b, In this case, one of the conductive layer 401a and the conductive layer 408a, or the conductive layer 401b and the conductive layer 408b One of the gate electrodes is called a back gate, a back gate electrode, or a back gate wiring. By providing a plurality of layers having the function of the channel forming layer, a transistor The threshold voltage of the transistor can be controlled.

[0259] The conductive layer 408a and the conductive layer 408b may be made of, for example, aluminum, chromium, copper, or tantalum. Metallic materials such as titanium, molybdenum, or tungsten, or these metallic materials In addition, the conductive layer 408a and the conductive layer 408b may be formed of an alloy material having a main component of Conductive layer 408a and conductive layer 408b are formed by stacking layers of a material applicable to It is also possible to configure

[0260] As the conductive layer 408a and the conductive layer 408b, a layer containing a conductive metal oxide is used. Examples of conductive metal oxides include indium oxide, tin oxide, and Zinc, indium oxide, tin oxide, or indium oxide zinc oxide alloy can be used. Note that a conductive metal oxide that can be used for the conductive layers 408a and 408b is an oxide. The silicon oxide may also be included.

[0261] Note that the transistor of this embodiment is formed by using an oxide semiconductor having a function as a channel formation layer. The insulating layer is provided on a portion of the semiconductor layer, and the insulating layer is disposed on the oxide semiconductor layer. A structure including a conductive layer having a function as a source or a drain may be used. In this case, the insulating layer is a layer that protects the channel formation layer of the transistor (also called a channel protection layer). The insulating layer having the function of a channel protection layer is, for example, A layer of a material applicable to the insulating layers 402a to 402c can be used. The insulating layers 402a to 402c are formed by stacking layers of a material suitable for the insulating layers 402a to 402c, and are used as a channel protection layer. Alternatively, the insulating layer may have a function as the insulating layer.

[0262] As shown in FIG. 5(A) to FIG. 5(E), the transistor of this embodiment is not necessarily In addition, the entire oxide semiconductor layer must overlap with the conductive layer having a function as a gate electrode. However, the entire oxide semiconductor layer does not necessarily overlap with the conductive layer having a function as a gate electrode. With this structure, incidence of light into the oxide semiconductor layer can be suppressed.

[0263] In addition, the field effect transition of insulated gate transistors that are actually measured is not limited to oxide semiconductors. Mobility can be lower than the original mobility for various reasons. There are defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. Using this method, it is possible to theoretically derive the field effect mobility assuming that there are no defects inside the semiconductor. I can.

[0264] The inherent mobility of the semiconductor is μ0, and the measured field-effect mobility is μ. If we assume the existence of potential barriers (such as grain boundaries), this can be expressed by the following equation.

[0265]

number

[0266] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. In addition, if we assume that the potential barrier originates from defects, then in the Levinson model, In this case, E is expressed by the following formula:

[0267]

number

[0268] Here, e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the is the dielectric constant, n is the number of carriers contained in the channel per unit area, and Cox is the where V is the gate voltage, and t is the channel thickness. In the case of a semiconductor layer, the thickness of the channel may be the same as the thickness of the semiconductor layer. The drain current Id in the region is expressed by the following equation.

[0269]

number

[0270] Here, L is the channel length and W is the channel width, where L=W=10 μm. Also, Vd is the drain voltage. Dividing both sides of the above equation by Vg and then taking the logarithm of both sides gives us the following equation:

[0271]

number

[0272] The right-hand side of equation 5 (the rightmost part) is a function of Vg. As can be seen from this equation, the vertical axis is ln (Id / Vg), the slope of the line on the graph obtained by plotting the actual measured values ​​with 1 / Vg on the horizontal axis The defect density N can be calculated from the Id-Vg characteristics of the transistor. The oxide semiconductors are indium (In), tin (Sn), and zinc (Z). n) ratio is In:Sn:Zn=1:1:1, the defect density N is 1×10 12 / c m2 That's about it.

[0273] Based on the defect density thus obtained, equations 2 and 3 are used to calculate μ0 = 120 cm 2 / Vs The mobility measured in the defective In-Sn-Zn oxide is 40 cm 2 / V However, oxide semiconductors without defects inside the semiconductor or at the interface between the semiconductor and the insulating film Body mobility μ0 is 120cm 2 It can be expected that / Vs.

[0274] However, even if there are no defects inside the semiconductor, the electrons may be scattered at the interface between the channel and the gate insulating layer. The transport properties of the transistor are affected by the interface between the channel and the gate insulating layer. The mobility μ1 at a distance x from the target is expressed by the following equation:

[0275]

number

[0276] Here, D is the electric field in the gate direction, and B and l are constants. B and l are determined from actual measurement results. From the above measurement results, B = 4.75 × 10 7 cm / s, l=10n m (depth of interface scattering). As D increases (i.e., gate voltage increases), It can be seen that the mobility μ1 decreases because the second term of Equation 6 increases.

[0277] Mobility of a transistor using an ideal oxide semiconductor channel with no internal defects The results of calculating μ2 are shown in Figure 21. The calculation was performed using a Synopsys device simulator. Sentaurus Device is a software that can be used to measure the bandgap of oxide semiconductors. The top, electron affinity, dielectric constant, and thickness are 2.8 eV, 4.7 eV, and These values ​​were measured for thin films formed by sputtering. This was obtained by

[0278] In addition, the work functions of the gate, source, and drain are set to 5.5 eV and 4.6 eV, respectively. The gate insulating layer had a thickness of 100 nm and a dielectric constant of 4.6 eV. was set to 4.1. The channel length and width were both 10 μm, and the drain voltage Vd was 0. It is 1V.

[0279] As shown in Figure 21, the mobility is 100 cm at a gate voltage of 1 V. 2 / Vs or more, but the gate If the voltage is further increased, the interface scattering increases and the mobility decreases. In order to reduce this, it is necessary to flatten the semiconductor layer surface at the atomic level (Atomic Lay er Flatness) is desirable.

[0280] The characteristics of a miniaturized transistor manufactured using an oxide semiconductor having such mobility are as follows: The results of the calculation of the characteristics are shown in Figs. 22 to 24. The structure of the transistor shown in FIG. + Conductivity type The semiconductor region 703a and the semiconductor region 703c are The resistivity of region 703c is 2×10 -3 Let it be Ωcm.

[0281] The transistor shown in FIG. 25A includes a base insulating layer 701 and a semiconductor layer embedded in the base insulating layer 701. A buried insulating material 702 made of aluminum oxide is formed so as to be The transistor is sandwiched between a semiconductor region 703a and a semiconductor region 703c. The gate electrode 705 is formed on the intrinsic semiconductor region 703b. The width of 705 is 33 nm.

[0282] Between the gate electrode 705 and the semiconductor region 703b, a gate insulating layer 704 is provided. On both sides of the gate electrode 705, there are sidewall insulators 706a and 706b, and a gate electrode 706c. An insulator 707 is provided on the top of the gate electrode 705 to prevent short circuits between the gate electrode 705 and other wiring. The width of the sidewall insulator is set to 5 nm. 3c, a source electrode 708a and a drain electrode 708b are provided. The channel width of the transistor shown in A is 40 nm.

[0283] The transistor shown in FIG. 25B includes a base insulating layer 701 and a buried insulating film made of aluminum oxide. A semiconductor region 703a and a semiconductor region 703c are formed on the insulator 702. The intrinsic semiconductor region 703b sandwiched between the gate electrode 703 and the gate insulator 704 has a width of 33 nm. The edge layer 704, the sidewall insulators 706a and 706b, the insulator 707, and the source 25A in that it includes a drain electrode 708a and a drain electrode 708b. is the same as:

[0284] The transistor shown in FIG. 25(A) and the transistor shown in FIG. 25(B) differ in that the sidewall insulation The conductivity type of the semiconductor region under the insulator 706a and the sidewall insulator 706b. In the illustrated transistor, the semiconductor regions under the sidewall insulators 706a and 706b are n +The semiconductor region 703a and the semiconductor region 703c have the conductivity type of In the transistor shown in FIG. 25B, the intrinsic semiconductor region 703b is an intrinsic semiconductor region. In the semiconductor layer shown in FIG. 1, the semiconductor region 703a (semiconductor region 703c) and the gate electrode 70 5 does not overlap by Loff. This area is called the offset area, and The width Loff is called the offset length. As is clear from the figure, the offset length is determined by the sidewall insulator. It is the same as the width of 706a (sidewall insulator 706b).

[0285] The other parameters used in the calculation are as described above. We used the Sentaurus Device simulation software. The drain current (Id, solid line) and mobility (μ, The gate voltage (Vg) dependence of the drain current Id is shown. and the mobility μ was calculated assuming a drain voltage of +0.1V.

[0286] FIG. 22(A) shows the case where the thickness of the gate insulating layer is 15 nm, and FIG. 22(B) shows the case where the thickness of the gate insulating layer is 15 nm. FIG. 22(C) is a diagram showing the case where the thickness of the gate insulating layer is set to 10 nm, and FIG. 22(D) is a diagram showing the case where the thickness of the gate insulating layer is set to 10 nm. The figure shows the case where the gate insulating layer is 5 nm. As the gate insulating layer becomes thinner, the drain On the other hand, the peak value of the mobility μ and the on-state current Id (off-state current) are significantly decreased. There is no noticeable change in the drain current Id (on-state current). At a gate voltage of around 1V, the drain The current was shown to be greater than 10 μA.

[0287] FIG. 23 shows a transistor having the structure shown in FIG. 25(B), with the offset length Loff set to 5n Dependence of drain current Id (solid line) and mobility μ (dotted line) on gate voltage Vg when m is set In addition, the drain current Id is calculated with the drain voltage set to +1V. The mobility μ was calculated with the gate voltage set to +0.1 V. FIG. 23(B) shows the case where the gate insulating layer thickness is 10 nm. FIG. 23(C) is a diagram when the thickness of the gate insulating layer is set to 5 nm.

[0288] FIG. 24 shows a transistor having the structure shown in FIG. 25B with an offset length Loff of 1 Drain current Id (solid line) and mobility μ (dotted line) dependence on gate voltage when the thickness is 5 nm In addition, the drain current Id is calculated with the drain voltage set to +1V. The mobility μ was calculated with the gate voltage set to +0.1 V. FIG. 24(B) shows the case where the gate insulating layer is 10 nm thick. FIG. 24(C) is a diagram when the thickness of the gate insulating layer is set to 5 nm.

[0289] In both cases, the thinner the gate insulating layer, the more significantly the off-state current decreases, while the peak of the mobility μ There is no noticeable change in the on-state current or the on-state voltage.

[0290] In addition, the peak of the mobility μ is 80 cm in FIG. 2 / Vs, but in Figure 23, it is 60 cm 2 / Vs, 40 cm in Figure 24 2 / Vs, the offset length Loff increases. The mobility μ decreases as the number of ions increases. The off-state current also tends to decrease. The current decreases with increasing offset length Loff, but this is not as large as the decrease in the off-state current. In both cases, the drain current was 10 μA at a gate voltage of about 1 V. has been shown to exceed

[0291] In addition, a transistor having a channel formation region made of an oxide semiconductor mainly composed of In, Sn, and Zn was developed. In the case of the oxide semiconductor, the substrate is heated during the formation of the oxide semiconductor. By performing a heat treatment after forming the conductor layer, good characteristics can be obtained. A component refers to an element that is contained at 5 atomic % or more in terms of composition.

[0292] Intentionally heating the substrate after deposition of an oxide semiconductor layer mainly composed of In, Sn, and Zn This makes it possible to improve the field effect mobility of the transistor. This makes it possible to positively shift the threshold voltage of the transistor and make it normally off.

[0293] For example, FIG. 28 shows a MOSFET with In, Sn, and Zn as the main components, a channel length L of 3 μm, and a channel width A transistor using an oxide semiconductor layer with W of 10 μm and a gate insulating layer with a thickness of 100 nm. 13 is a diagram showing the characteristics of a MOS transistor, where Vd is set to 10 V.

[0294] FIG. 28(A) shows a case where In, Sn, and Zn were mainly formed by sputtering without intentionally heating the substrate. 13 is a diagram showing transistor characteristics when an oxide semiconductor layer is formed as a component. The field effect mobility is 18.8 cm 2 On the other hand, the substrate is intentionally heated to I Forming an oxide semiconductor layer containing n, Sn, and Zn as its main components improves the field effect mobility. FIG. 28(B) shows the structure of the substrate heated to 200° C. to form a thin film of In, Sn, and Zn as the main components. 13 is a diagram showing transistor characteristics when an oxide semiconductor layer is formed as a component. The field effect mobility is 32.2 cm 2 / Vsec.

[0295] The field effect mobility was measured by forming an oxide semiconductor layer mainly composed of In, Sn, and Zn and then annealing it. Fig. 28(C) shows the results of the experiment using In, Sn, and Zn. The oxide semiconductor layer, which is mainly composed of , is formed by sputtering at 200°C, and then heat-treated at 650°C. This figure shows the transistor characteristics when the device is treated with a ZnO-type GaN-GaN ... 5cm 2 / Vsec.

[0296] By intentionally heating the substrate, moisture is absorbed into the oxide semiconductor layer during sputtering. In addition, by performing a heat treatment after the film formation, the amount of oxidation can be reduced. Hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor layer, as described above. Such an improvement in the field effect mobility can be achieved by dehydration. Not only does hydrogenation and dehydrogenation remove impurities, but the interatomic distances become shorter due to the increased density. It is also estimated that the crystal structure can be improved by removing impurities from the oxide semiconductor and purifying it. Such a highly purified non-single-crystal oxide semiconductor can be ideally 100cm 2 It is estimated that it will be possible to achieve a field effect mobility of more than 1000 times the capacitance of the semiconductor. do.

[0297] Oxygen ions are implanted into an oxide semiconductor whose main components are In, Sn, and Zn, and the oxide is then converted into The hydrogen, hydroxyl groups, or moisture contained in the oxide semiconductor is released, and the heat treatment is performed simultaneously or in conjunction with the heat treatment. The oxide semiconductor may be crystallized by a heat treatment thereafter. By the crystallization treatment, a non-single-crystal oxide semiconductor with good crystallinity can be obtained.

[0298] The effect of intentionally heating the substrate during film formation and / or heat treatment after film formation is that the electric field This not only improves the effective mobility but also contributes to making the transistor normally off. The oxide semiconductor, which is mainly composed of In, Sn, and Zn, was formed without intentionally heating the substrate. A transistor that uses a conductor layer as a channel formation region exhibits a negative shift in threshold voltage. However, when an oxide semiconductor layer formed by intentionally heating a substrate is used, This negative shift in threshold voltage is eliminated. This tendency is evident from the comparison of Figure 28(A) and Figure 28(B). can also be confirmed.

[0299] The threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. By setting the composition ratio to In:Sn:Zn=2:1:3, a transistor can be formed. In addition, the composition ratio of the target is In:Sn: When Zn=2:1:3, an oxide semiconductor layer with high crystallinity can be obtained.

[0300] The intentional substrate heating temperature or heat treatment temperature is 150° C. or higher, preferably 200° C. or higher. The temperature is more preferably 400° C. or higher. By forming the film or performing heat treatment at a higher temperature, the transistor can be easily formed. This makes it possible to achieve a normally-off transistor.

[0301] In addition, the substrate may be intentionally heated during deposition and / or after deposition to reduce the gate Stability against bias stress can be improved. For example, 2MV / cm, 15 At 0°C and 1 hour application, the threshold voltage drift is less than ±1.5V, Preferably, less than 1.0 V can be obtained.

[0302] In fact, Sample 1 was not subjected to heat treatment after the oxide semiconductor layer was formed, and Sample 2 was subjected to heat treatment at 650° C. The BT test was performed on the transistor of sample 2 that had been subjected to the above.

[0303] First, the substrate temperature was set to 25°C, Vd was set to 10V, and the Vg-Id characteristics of the transistor were measured. Next, the substrate temperature was set to 150°C, and Vd (voltage between the drain and source) was set to 0.1 Next, the electric field strength applied to the gate insulating layer 608 was set to 2 MV / cm. A voltage of 20 V was applied to Vg (voltage between the gate and source) and held for 1 hour. Vg was set to 0 V. Next, the substrate temperature was set to 25° C., Vd was set to 10 V, and the Vg -Id measurement was performed. This is called the Plus BT test.

[0304] Similarly, first, set the substrate temperature to 25°C, Vd to 10V, and measure the Vg-Id characteristics of the transistor. Next, the substrate temperature was set to 150°C and Vd was set to 0.1V. Next, the gate Apply −20 V to Vg so that the electric field strength applied to the insulating layer 608 is −2 MV / cm. Then, Vg was set to 0 V. Next, the substrate temperature was set to 25° C., and V d was set to 10V and the Vg-Id of the transistor was measured. This is called the negative BT test. cormorant.

[0305] The results of the positive BT test of sample 1 are shown in FIG. 29(A), and the results of the negative BT test are shown in FIG. The results of the positive BT test of sample 2 are shown in FIG. 30(A), and the results of the negative BT test are shown in FIG. The results are shown in Figure 30(B).

[0306] The threshold voltage shifts of sample 1 due to the positive BT test and the negative BT test were 1.8 and 1.8, respectively. The positive and negative BT tests for sample 2 were 0V and -0.42V. The resulting threshold voltage shifts were 0.79 V and 0.76 V, respectively. In both samples 1 and 2, the change in threshold voltage before and after the BT test was small, and the reliability was high. I know it's expensive.

[0307] The heat treatment can be carried out in an oxygen atmosphere, but it is first carried out in a nitrogen or inert gas atmosphere, or under reduced pressure. Alternatively, heat treatment may be performed in an atmosphere containing oxygen after heat treatment in the atmosphere containing oxygen. By adding oxygen to the oxide semiconductor after oxidation, the effect of the heat treatment can be further enhanced. To add oxygen later, oxygen ions can be accelerated by an electric field to form a A method of implanting the layer may also be applied.

[0308] Defects due to oxygen vacancies occur in the oxide semiconductor and in the interface with a film stacked on the oxide semiconductor. However, when the oxide semiconductor contains excess oxygen by the heat treatment, In this way, the oxygen deficiency that is constantly generated can be compensated for by excess oxygen. The oxygen atoms are mainly present between the lattices, and the oxygen concentration is 1×10 16 / cm 3 2×1 or more 0 20 / cm 3 If the above condition is satisfied, the crystal can be included in the oxide semiconductor without causing distortion. It is possible.

[0309] In addition, by making the oxide semiconductor contain crystals at least in part through the heat treatment, For example, a composition ratio of In:Sn:Zn=1 can be obtained. The oxide film was sputtered using a 1:1 target without intentionally heating the substrate. The semiconductor layer was analyzed by X-ray diffraction (XRD) to find a halo pattern. The oxide semiconductor layer thus formed is crystallized by heat treatment. The heat treatment temperature can be selected arbitrarily. For example, by performing heat treatment at 650° C., Clear diffraction peaks can be observed by X-ray diffraction.

[0310] In fact, we performed XRD analysis of the In-Sn-Zn-O film. Using the AXS X-ray diffraction device D8 ADVANCE, the out-of-plane method was used. Measured.

[0311] Samples A and B were prepared for XRD analysis. A method for producing the above will be described.

[0312] First, an In-Sn-Zn-O film was formed to a thickness of 100 nm on a dehydrogenated quartz substrate. The membrane was

[0313] The In-Sn-Zn-O film was formed by sputtering in an oxygen atmosphere at a power of 100 W ( The target was In:Sn:Zn=1:1:1 [atomic ratio]. An n-Sn-Zn-O target was used. The substrate heating temperature during film formation was 200°C. The sample thus prepared was designated as sample A.

[0314] Next, a sample prepared in the same manner as sample A was subjected to a heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen atmosphere for one hour, and then in an oxygen atmosphere without lowering the temperature. The sample was then subjected to an additional heat treatment for 1 hour.

[0315] Figure 33 shows the XRD spectra of sample A and sample B. In sample A, the peaks derived from crystals In sample B, 2θ was observed at around 35 deg and 37 deg to 38 deg. A peak derived from crystals was observed.

[0316] In this way, oxide semiconductors mainly composed of In, Sn, and Zn are formed by intentionally heating the substrate. The characteristics of the transistor can be improved by heating and / or by heat treatment after film formation. This can be done.

[0317] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. In other words, it has the effect of preventing the oxide semiconductor from being included in the film or removing it from the film. High purification can be achieved by removing hydrogen, which becomes a donor impurity in the conductor. This allows the transistor to be normally off, and the oxide semiconductor is highly purified. By this, the off-current can be reduced to 1 aA / μm or less. The unit of the value indicates the current value per 1 μm of channel width.

[0318] Specifically, as shown in FIG. 34, when the substrate temperature is 125° C., the current is 1 aA / μm (1×1 0 -18 A / μm) or less, and at 85°C it is 100zA / μm (1×10 -19 A / μm ) or less, and at room temperature (27°C), it is 1zA / μm (1×10 -21 A / μm or less Preferably, the resistance is 100 zA / μm (1×10 -19 A / μ m) or less at 85°C, -20 A / μm) at room temperature At 0.1zA / μm (1×10 -22 It is possible to achieve a value of less than 100 A / μm.

[0319] However, in order to prevent hydrogen and moisture from being mixed into the film during the formation of the oxide semiconductor layer, The leakage from the deposition chamber and the outgassing from the inner walls of the deposition chamber are sufficiently suppressed, and the sputtering gas is highly purified. For example, it is preferable that the sputtering gas has a dew point of -70°C or lower so that moisture is not included in the film. It is preferable to use a gas that is within the range of 1000 to 2000 nm. It is preferable to use a target that has been highly purified so that it does not contain any impurities. Oxide semiconductors that are mainly composed of In, Sn, and Zn can be heat-treated to remove moisture from the film. However, the temperature at which moisture is released is higher than that of oxide semiconductors whose main components are In, Ga, and Zn. Therefore, it is preferable to form a film that does not contain moisture from the beginning.

[0320] In addition, a sample that was subjected to heat treatment at 650° C. after the oxide semiconductor layer was formed was used for the transistor. The relationship between the substrate temperature and the electrical characteristics was evaluated.

[0321] The transistor used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, and Lov is 3 μm on each side (total 6 μm), and dW is 0 μm. Vd is 10 V. The substrate temperatures were −40° C., −25° C., 25° C., 75° C., 125° C., and 150° C. In a transistor, the overlap width between the gate electrode and a pair of electrodes is called Lov, and The protrusion of the pair of electrodes from the semiconductor layer is called dW.

[0322] FIG. 31 shows the Vg dependence of Id (solid line) and field effect mobility (dotted line). Figure 32(A) shows the relationship between the substrate temperature and the threshold voltage, and Figure 32(B) shows the relationship between the substrate temperature and the field-effect mobility. Shows.

[0323] From FIG. 32(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The range was 0.38V to -1.08V at -40℃ to 150℃.

[0324] Moreover, from FIG. 32(B), it can be seen that the higher the substrate temperature, the lower the field effect mobility. The range is -40℃ to 150℃ and is 37.4cm 2 / Vs~33.4cm 2 / Vs Therefore, it is understood that the fluctuation of the electrical characteristics is small within the above-mentioned temperature range.

[0325] The above-mentioned oxide semiconductor mainly composed of In, Sn, and Zn is used as a channel forming region. According to the transistor, the field effect mobility is increased to 30c while keeping the off-current below 1aA / μm. m 2 / Vsec or more, preferably 40cm 2 / Vsec or more, preferably 60cm 2 / Vsec or more, and the on-current value required by the LSI can be satisfied. For example, A FET with L / W=33nm / 40nm, gate voltage 2.7V, drain voltage 1.0V When the on-state current is 12μA or more, the on-state current required for the transistor to operate is 12μA or more. Even in a wide temperature range, sufficient electrical characteristics can be ensured. For example, a transistor made of oxide semiconductor is embedded in an integrated circuit made of silicon semiconductor. Even if the chip is used in a large number of chips, it is possible to realize an integrated circuit with new functions without sacrificing the operating speed. Cut.

[0326] Next, an example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor layer will be described. This will be explained using Figure 26 etc.

[0327] Figure 26 shows the top of a coplanar top-gate top-contact transistor. FIG. 26(A) shows a top view of a transistor. FIG. 26(B) shows a top view of a transistor. 26(A) shows a cross section AB corresponding to the dashed line AB in FIG. 26(A).

[0328] The transistor shown in FIG. 26B includes a substrate 750 and a base insulating film provided over the substrate 750. A protective insulating layer 754 provided around the base insulating layer 752 and a base insulating layer 75 2 and a protective insulating layer 754. a gate insulating layer 758 provided over the oxide semiconductor layer 756; a gate electrode overlapping with the oxide semiconductor layer 756 with a gate insulating layer 758 interposed therebetween; 760, a sidewall insulator 762 provided in contact with the side surface of the gate electrode 760, and at least A pair of electrodes 764 provided in contact with the low-resistance region 756b and at least an oxide semiconductor layer 756, an interlayer insulating layer 766 provided to cover the gate electrode 760 and the pair of electrodes 764; 766 is connected to at least one of the pair of electrodes 764 through an opening provided in the interlayer insulating layer 766. and a wiring 768 provided continuously thereto.

[0329] Although not shown, a protective film is provided to cover the interlayer insulating layer 766 and the wiring 768. By providing the protective film, the surface conduction of the interlayer insulating layer 766 can be prevented. The minute leakage current caused by the semiconductor device can be reduced, and the off-current of the transistor can be reduced. can be done.

[0330] Next, we investigated the structure of a transistor using an In-Sn-Zn-O film as the oxide semiconductor layer, which is different from the above. Another example will be described.

[0331] FIG. 27 is a top view and a cross-sectional view illustrating a structure of a transistor manufactured in this embodiment mode. FIG. 27(A) is a top view of a transistor. FIG. 27(B) is a cross-sectional view of a portion of FIG. 27(A). FIG. 2 is a cross-sectional view corresponding to the dashed line AB.

[0332] The transistor shown in FIG. 27B includes a substrate 600 and a base insulating film provided over the substrate 600. a base insulating layer 602, an oxide semiconductor layer 606 provided over the base insulating layer 602, and an oxide semiconductor layer A pair of electrodes 614 in contact with the oxide semiconductor layer 606 and a pair of electrodes 614 provided on the oxide semiconductor layer 606 and the pair of electrodes 614 The gate insulating layer 608 is overlapped with the oxide semiconductor layer 606 via the gate insulating layer 608. A gate electrode 610 is provided so as to overlap with the gate insulating layer 608 and the gate electrode 610. An interlayer insulating layer 616 is provided between the first and second electrodes 611 and 612, and a pair of insulating layers 616 are provided through openings in the interlayer insulating layer 616. A wiring 618 connected to the electrode 614 and a metal insulating layer 616 and a metal insulating layer 618 are provided to cover the wiring 618. and a protective film 620.

[0333] The substrate 600 is a glass substrate, the base insulating layer 602 is a silicon oxide film, and the oxide The semiconductor layer 606 is an In-Sn-Zn-O film, and the pair of electrodes 614 is a tungsten The gate insulating layer 608 is a silicon oxide film, and the gate electrode 610 is a nitride film. The interlayer insulating layer 616 is a silicon oxynitride layer. The laminated structure is made of a composite film and a polyimide film. The wiring 618 is made of a titanium film, an aluminum film, The laminated structure in which the titanium film is formed in this order is a polyimide film as a protective film 620, Each was used.

[0334] In the transistor having the structure shown in FIG. 27A, the gate electrode 610 and the pair of electrodes The width of the overlap with the oxide semiconductor layer 606 is referred to as Lov. The protrusion of pole 614 is called dW.

[0335] As an example of a method for manufacturing a transistor in this embodiment, a transistor shown in FIG. An example of a method for manufacturing a transistor will be described with reference to FIGS. 6A to 6E are cross-sectional views illustrating an example of a manufacturing method of the transistor shown in FIG. FIG.

[0336] First, as shown in FIG. 6A, a substrate 400a is prepared, and a first conductive layer is formed on the substrate 400a. A conductive layer 401a is formed by forming a film on the first conductive film and etching a part of the first conductive film. .

[0337] For example, a film of a material applicable to the conductive layer 401a is formed by a sputtering method. The first conductive film can be formed by the above-mentioned method. The first conductive film can also be formed by stacking films.

[0338] The sputtering gas may contain impurities such as hydrogen, water, hydroxyl groups, or hydrides. By using a high-purity gas from which impurities have been removed, the impurity concentration in the film formed is reduced. It is possible.

[0339] Before forming a film by sputtering, a preheating chamber of the sputtering device is By carrying out the above-mentioned preheating treatment, hydrogen, moisture, etc. can be removed. Impurities can be desorbed.

[0340] In addition, before forming a film by sputtering, for example, argon, nitrogen, helium, Alternatively, in an oxygen atmosphere, no voltage is applied to the target side, and a voltage is applied to the substrate side using an RF power source. A process is then performed to modify the surface to be treated by applying a plasma (also called reverse sputtering). By performing reverse sputtering, powdery substances (particles) adhering to the surface to be formed can be removed. , also called garbage) can be removed.

[0341] In addition, when forming a film using a sputtering method, a suction type vacuum pump or the like is used. It is possible to remove residual moisture in the film forming chamber. For example, a cryopump, an ion pump, or a titanium sublimation pump may be used. In addition, a turbo molecular pump equipped with a cold trap is used to evaporate the gas in the deposition chamber. Residual moisture can also be removed.

[0342] In addition, the method for forming the conductive layer 401a may be used in the fabrication of the transistor of this embodiment. In the example of the manufacturing method, when a layer is formed by etching a part of a film, for example, photolithography A resist mask is formed on a part of the film by a roughening process, and the film is then exposed using the resist mask. By etching, the layer can be formed. In this case, after the layer is formed, The resist mask is removed.

[0343] Alternatively, the resist mask may be formed by using an inkjet method. By using this method, a photomask is no longer necessary, which reduces manufacturing costs. In addition, an exposure mask having multiple regions with different transmittance (also called a multi-tone mask) is used. A resist mask may be formed by using a multi-tone mask. A resist mask having a region can be formed, and the resist used for manufacturing a transistor can be The number of masks can be reduced.

[0344] Next, as shown in FIG. 6(B), a first insulating film is formed on the conductive layer 401a. This forms an insulating layer 402a.

[0345] For example, a method applicable to the insulating layer 402a can be formed by using a sputtering method or a plasma CVD method. By forming a film of the material, the first insulating film can be formed. The first insulating film can also be formed by stacking films of materials applicable to 2a. In addition, high density plasma CVD (e.g., microwave (e.g., microwave with a frequency of 2.45 GHz) A film of a material suitable for the insulating layer 402a is formed using a high-density plasma CVD method using This makes it possible to make the insulating layer 402a dense, and the withstand voltage of the insulating layer 402a can be increased. It can be improved.

[0346] Next, as shown in FIG. 6C, an oxide semiconductor layer is formed over the insulating layer 402a, and then The oxide semiconductor layer is partly etched to form the oxide semiconductor layer 403a.

[0347] For example, an oxide semiconductor material applicable to the oxide semiconductor layer 403a can be formed by a sputtering method. By forming a film of the material, an oxide semiconductor layer can be formed. The oxide semiconductor layer may be formed in an atmosphere of oxygen, or in a mixed atmosphere of a rare gas and oxygen. stomach.

[0348] In addition, the sputtering target was In2O3:Ga2O3:ZnO=1:1:1. An oxide semiconductor layer is formed using an oxide target having a composition ratio of [molar ratio]. For example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] The oxide semiconductor layer may be formed using an oxide target having the above composition ratio.

[0349] In addition, when using an In-Sn-Zn-O-based material as an oxide semiconductor, the target The composition ratio of In:Sn:Zn is 1:2:2, 2:1:3, 1:1:1, Or, use an oxide target with a ratio of 20:45:35. The oxide can be referred to as ITZO.

[0350] In addition, when the oxide semiconductor layer is formed by sputtering, the substrate 400a is placed in a reduced pressure state. The substrate 400a is heated to a temperature of 100° C. to 600° C., preferably 200° C. to 400° C. By heating the substrate 400a, the impurities in the oxide semiconductor layer can be removed. The concentration can be reduced, and damage to the oxide semiconductor layer caused by sputtering can be reduced. It is possible.

[0351] Next, as shown in FIG. 6D, a second The second conductive film is then partially etched to form the conductive layers 405a and A conductive layer 406a is formed.

[0352] For example, a method applicable to the conductive layers 405a and 406a can be used by a sputtering method or the like. The second conductive film can be formed by forming a film of the material. A second conductive film is formed by stacking a film of a material applicable to the conductive layer 406a and the conductive layer 406b. It can also be done.

[0353] Next, as shown in FIG. 6E, the insulating layer 407a is formed in contact with the oxide semiconductor layer 403a. Form.

[0354] For example, in a rare gas (typically argon) atmosphere, in an oxygen atmosphere, or in a mixture of rare gas and oxygen, A film applicable to the insulating layer 407a is formed by sputtering in a mixed atmosphere. The insulating layer 407a can be formed by a sputtering method. By forming 7a, an oxide having a function as a back channel of a transistor is formed. The decrease in resistance of the semiconductor layer 403a can be suppressed. The substrate temperature during the formation is preferably from room temperature to 300° C. inclusive.

[0355] In addition, before forming the insulating layer 407a, a plasma treatment using a gas such as N2O, N2, or Ar was performed. Then, adsorbed water and the like attached to the exposed surface of the oxide semiconductor layer 403a are removed by a rubbing treatment. In the case where the plasma treatment is performed, the insulating layer 407 may be removed without being exposed to the air. It is preferred to form a.

[0356] In addition, in the example of the method for manufacturing the transistor shown in FIG. Heat treatment is performed at a temperature below 0°C or above 400°C but below the distortion point of the substrate. For example, After forming a semiconductor layer, a part of the oxide semiconductor layer is etched, and then a second conductive film is formed. After that, a part of the second conductive film is etched or an insulating layer 407a is formed. The above heat treatment is carried out.

[0357] The heat treatment device for the above-mentioned heat treatment may be an electric furnace or a heating element such as a resistance heating element. A device that heats the workpiece by thermal conduction or thermal radiation from a GR TA (Gas Rapid Thermal Annealing) equipment or LRTA ( RTA (Ra Lamp Rapid Thermal Annealing) equipment pid Thermal Annealing (LRTA) equipment can be used. The lamps are, for example, halogen lamps, metal halide lamps, xenon arc lamps, carbon Light emitted from lamps such as arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps ( The GRTA device is a device that heats the workpiece by radiating high-temperature electromagnetic waves. This is a device that performs heat treatment using gas. The high-temperature gas is, for example, a rare gas or a heating An inert gas (eg, nitrogen) that does not react with the workpiece during the treatment can be used.

[0358] After the above heat treatment, the heating temperature is maintained or cooled from the heating temperature. In the process of this, high-purity oxygen gas, high-purity N2O gas, Or by introducing ultra-dry air (an atmosphere with a dew point of -40°C or less, preferably -60°C or less), In this case, it is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or N2O gas introduced into the heat treatment device is set to 6N or more, preferably 7N or more, that is, the impurity concentration in the oxygen gas or N2O gas is 1 ppm or less, preferably It is preferable that the concentration of the oxidized gas is 0.1 ppm or less. Oxygen is supplied to the oxide semiconductor layer 403a, and oxygen deficiency in the oxide semiconductor layer 403a causes Defects can be reduced.

[0359] In addition to the above heat treatment, after the insulating layer 407a is formed, Alternatively, heat treatment in an oxygen gas atmosphere (preferably at 200° C. or higher and 400° C. or lower, for example, 250 ℃ or more and 350 ℃ or less) may be performed.

[0360] After the insulating layer 402a is formed, an oxide semiconductor layer is formed. After forming a conductive layer, forming an insulating layer, or performing a heat treatment, oxygen doping treatment using oxygen plasma is performed. For example, oxygen doping may be performed using high-density plasma at 2.45 GHz. Alternatively, oxygen doping may be performed using ion implantation or ion doping. By performing oxygen doping treatment, the electrical characteristics of the manufactured transistor can be improved. For example, the insulating layer 40 can be doped with oxygen to reduce the variation in the properties. 2a and / or the insulating layer 407a are made to have a higher oxygen content than the stoichiometric composition ratio. This allows excess oxygen in the insulating layer to be easily supplied to the oxide semiconductor layer 403a. Therefore, in the oxide semiconductor layer 403a, or in one of the insulating layers 402a and 407a, Since oxygen defects at the interface between the oxide semiconductor layer 403a and both of the oxide semiconductor layers 403a and the oxide semiconductor layer 403b can be reduced, In this case, the carrier concentration in the oxide semiconductor layer 403a can be further reduced.

[0361] For example, one or both of the insulating layers 402a and 407a may contain gallium oxide. When forming an insulating layer, oxygen is supplied to the insulating layer to change the composition of gallium oxide to GaO x Nissu It is possible.

[0362] In addition, one or both of the insulating layers 402a and 407a may contain aluminum oxide. When forming an insulating layer containing aluminum oxide, oxygen is supplied to the insulating layer to change the composition of aluminum oxide to AlO. x It can be.

[0363] In addition, one or both of the insulating layers 402a and 407a may be made of gallium aluminum oxide. When an insulating layer containing aluminum or aluminum gallium oxide is formed, oxygen is supplied to the insulating layer. The composition of gallium aluminum oxide or aluminum gallium oxide is Ga x Al 2-x O 3+α It can be said that:

[0364] Through the above steps, hydrogen, water, a hydroxyl group, or hydride (hydride) is removed from the oxide semiconductor layer 403a. impurities such as fluorine-containing compounds (also referred to as fluorine compounds) are removed and oxygen is supplied to the oxide semiconductor layer 403a. This allows the oxide semiconductor layer to be highly purified.

[0365] Note that although an example of a method for manufacturing the transistor illustrated in FIG. 5A has been described, the present invention is not limited to this example. For example, among the components shown in FIG. 5B to FIG. 5E, the names of the components shown in FIG. 5A may be the same as those of the components shown in FIG. If the elements are the same as those shown in FIG. 5(A) and at least a part of the functions are the same as those shown in FIG. For example, the description of the example of the method for manufacturing the transistor in FIG. 5A can be referred to as appropriate.

[0366] As described with reference to FIGS. 5 and 6, an example of a transistor in this embodiment is a gate A conductive layer having a function as a gate, an insulating layer having a function as a gate insulating layer, and a gate A conductive layer having a function as a gate is overlapped with an insulating layer having a function as a gate insulating layer. The oxide semiconductor layer in which a channel is formed and the source A conductive layer that functions as one of a source and a drain and a and a conductive layer having a function as the other of the source and drain.

[0367] In addition, an example of a transistor in this embodiment includes an oxide semiconductor layer, a source and a drain A conductive layer having a function as one of the gates and a function as the other of the source and drain. The insulating layer in contact with the oxide semiconductor layer in a portion where the conductive layer having the gate insulating layer is not provided is a gate insulating layer. The structure is such that the oxide layer is in contact with the insulating layer that functions as an insulating layer. a semiconductor layer, a conductive layer having a function as one of a source and a drain, and a source and The conductive layer having the other function of the drain is in contact with the oxide semiconductor layer. Since the oxide semiconductor layer, the source and drain are surrounded by an insulating layer having an insulating function, A conductive layer having a function as one of the gates and a function as the other of the source and drain. It is possible to suppress the intrusion of impurities into the conductive layer.

[0368] In addition, the concentration of alkali metal in the oxide semiconductor layer in which the channel is formed is low. For example, when sodium is contained in the oxide semiconductor layer in which the channel is formed, The concentration of sodium in the oxide semiconductor layer in which the channel is formed is 5×10 16 / cm 3 Below, and further, 1×10 16 / cm 3 Below, and even 1×10 15 / cm 3 Below For example, it is preferable that the oxide semiconductor layer in which the channel is formed contains lithium. In this case, the lithium concentration in the oxide semiconductor layer in which the channel is formed is 5×10 15 / cm 3 Below, and further, 1×10 15 / cm 3 It is preferable that the following is true: For example, when potassium is contained in the oxide semiconductor layer in which the channel is formed, the channel is formed. The concentration of potassium in the oxide semiconductor layer is 5×10 15 / cm 3 Further details are below. is 1 x 10 15 / cm 3 For example, sodium is an oxide semiconductor. When the insulating layer adjacent to the conductor layer is an oxide, the oxide penetrates into the insulating layer and the transistor characteristics In addition, degradation of the transistors (e.g., threshold voltage shift, mobility reduction, etc.) occurs. This also causes variations in characteristics between transistors. By reducing the concentration of alkali metals in the semiconductor layer, the This makes it possible to suppress deterioration of the characteristics of the transistor.

[0369] As described above, the oxide semiconductor layer in which the channel is formed can be highly purified to form an i-type Alternatively, the oxide semiconductor layer is substantially i-type. The carrier concentration of the oxide semiconductor layer is increased to 1×10 14 / cm 3 Less than 1x1 0 12 / cm3 less than 1×10 11 / cm 3 It can be less than In addition, the above structure can suppress the change in characteristics due to the temperature change. The off-current per 1 μm of panel width is 10 aA (1 × 10 -17 A) The following: is the off-current per 1 μm of channel width of 1 aA (1 × 10 -18 A) The following, and further The off-state current per 1 μm of panel width is 10 zA (1 × 10 -20 A) Below, further channels The off-current per 1 μm of width is 1 zA (1 × 10 -21 A) or less, even channel width 1μ The off-state current per m is 100 yA (1×10 -22 A) It can be done as follows. The lower the off-state current of the transistor, the better. The lower limit of the current is about 10 -30 It is estimated to be A / μm.

[0370] The transistor including the oxide semiconductor layer of this embodiment may be, for example, Display circuit of output device, display selection signal output circuit, display data signal output circuit, light detection circuit, light A transistor in one or more of the detection reset signal output circuits and the output selection signal output circuits By using this in a memory, the reliability of the input / output device can be improved.

[0371] Furthermore, the oxide semiconductor of this embodiment was evaluated by measuring the leakage current using a characteristic evaluation circuit. A calculation example of the off-state current value in an example of a transistor including a conductor layer will be described below. .

[0372] The leakage current measurement using the characteristic evaluation circuit will be explained with reference to FIG. FIG. 13 is a diagram for explaining a value circuit.

[0373] First, the circuit configuration of the characteristic evaluation circuit will be described with reference to FIG. FIG. 2 is a circuit diagram showing a circuit configuration of a characteristic evaluation circuit.

[0374] The characteristic evaluation circuit shown in FIG. 7A includes a plurality of measurement systems 801. In this example, eight measurement systems 801 are connected in parallel. By using multiple measurement systems 801, multiple measurements can be performed simultaneously. can be done.

[0375] The measurement system 801 includes a transistor 811, a transistor 812, a capacitance element 813, and a The transistor 814 and the transistor 815 .

[0376] Transistor 811, transistor 812, transistor 814, and transistor 81 5 is an N-type field effect transistor.

[0377] A voltage V1 is input to one of the source and drain of the transistor 811. A voltage Vext_a is input to the gate of the transistor 811. The transistor 811 is a charge injection transistor. This is a necessary transistor.

[0378] One of the source and drain of the transistor 812 is connected to the source and drain of the transistor 811. The other of the source and drain of the transistor 812 is connected to a voltage V A voltage Vext_b is input to the gate of the transistor 812. The transistor 812 is a transistor for evaluating leakage current. is a leakage current including an off-state current of a transistor.

[0379] A first capacitor electrode of the capacitor 813 is connected to the other of the source and drain of the transistor 811. A voltage V2 is input to the second capacitance electrode of the capacitance element 813. In this case, the voltage V2 is 0V.

[0380] A voltage V3 is input to one of the source and drain of the transistor 814. The gate of the transistor 814 is connected to the other of the source and drain of the transistor 811. The gate of the transistor 814 and the other of the source and drain of the transistor 811 One of the source and the drain of the transistor 812 and the first electrode of the capacitor 813 The connection point is also referred to as node A. Here, voltage V3 is 5V.

[0381] One of the source and drain of the transistor 815 is connected to the source and drain of the transistor 814. The other of the source and drain of the transistor 815 is connected to a voltage V 4 is input to the gate of the transistor 815, and the voltage Vext_c is input to the gate of the transistor 816. , where the voltage Vext_c is 0.5V.

[0382] Furthermore, the measurement system 801 is connected to the other of the source and drain of the transistor 814 and The voltage at the connection point between the source and drain of the transistor 815 is output as the output voltage Vout. To exert effort.

[0383] Here, as an example of the transistor 811, a transistor including an oxide semiconductor layer and having a channel length L=1 A transistor with a gate length of 0 μm and a channel width of W=10 μm is used.

[0384] An example of the transistor 814 and the transistor 815 is a transistor including an oxide semiconductor layer. A transistor with a channel length L=3 μm and a channel width W=100 μm is used.

[0385] The structure of the transistor 812 is shown in FIG. FIG. 2 is a schematic cross-sectional view showing the structure of a star.

[0386] As shown in FIG. 7B, the transistor 812 has a conductive layer 9 01, an insulating layer 902 having a function as a gate insulating layer, and a conductive layer an oxide semiconductor layer 903 having a function as a channel formation layer provided over the layer 901; a conductive layer which is in contact with the oxide semiconductor layer 903 and serves as one of a source and a drain; 905 and a conductive layer 906 having the function of the other of the source and drain. The transistor 812 further includes an oxide semiconductor layer 903, a conductive layer 905, and a conductive layer 906. An insulating layer 907 and a planarizing layer 908 are laminated on the insulating layer 907, and a metal layer 908 is formed on the planarizing layer 908 through an opening. A conductive layer 909 contacts the conductive layer 905 through an opening, and a conductive layer 906 contacts the conductive layer 906 through an opening. 910 is provided, and the conductive layer 905 and the conductive layer 906 do not overlap with the conductive layer 901, and the conductive layer 905 and the conductive layer 906 are provided with a width of 1 The offset region is 1.5 μm. By providing the offset region, the parasitic capacitance is reduced. Further, the transistor 812 can be formed by a channel length L and a channel width W We use six transistor samples (also called SMPs) with different lattice sizes (see Table 1).

[0387] [Table 1]

[0388] Next, a method for manufacturing the transistor 812 will be described below.

[0389] First, a glass substrate that will become the substrate 900 is prepared, and an insulating layer 927 is formed on the substrate 900. Here, a silicon nitride film having a thickness of 100 nm is formed on a substrate 900. A 150 nm thick silicon oxynitride film is formed on the silicon film to form an insulating layer 927. Form.

[0390] Next, a conductive layer 901 is formed on the substrate 900 via an insulating layer 927. A 100 nm thick tin film was deposited on the substrate 900 via the layer 927 by sputtering. A tungsten film is formed, and a part of the tungsten film is etched to form a conductive layer 901. Form.

[0391] Next, an insulating layer 902 is formed over the conductive layer 901 and the insulating layer 927. On the insulating layer 927 and the insulating layer 901, a silicon oxynitride layer having a thickness of 100 nm is formed by a CVD method. By forming a film, an insulating layer 902 is formed.

[0392] Next, an oxide semiconductor layer 903 is formed over the conductive layer 901 with the insulating layer 902 interposed therebetween. In the example, an oxide semiconductor film is formed on a conductive layer 901 by a sputtering method with an insulating layer 902 interposed therebetween. Then, a part of the oxide semiconductor layer is etched to form an oxide semiconductor layer 903 In the process of forming the oxide semiconductor layer, the following structure is formed: In2O3:Ga2O3:ZnO= A metal oxide target of 1:1:2 [mol] was used, the substrate temperature was set to 200°C, and the sputtering was performed. The pressure in the chamber of the sputtering device was set to 0.6 Pa. The DC power supply was set to 5 kV, and the deposition atmosphere was a mixture of oxygen and argon (oxygen flow rate 50 s The oxide semiconductor layer is formed with a nitrogen flow rate of 50 sccm and an argon flow rate of 50 sccm.

[0393] Next, the specimen was heated at 450°C for 1 hour in a mixed atmosphere of nitrogen and oxygen (80% nitrogen, 20% oxygen). Perform processing.

[0394] Next, a part of the insulating layer 902 is etched to form an opening penetrating the conductive layer 901 .

[0395] Next, a conductive layer 905 and a conductive layer 906 are formed over the oxide semiconductor layer 903. A titanium film having a thickness of 100 nm was formed on the oxide semiconductor layer 903 by a sputtering method. A 200 nm thick aluminum film is formed on the titanium film. A titanium film having a thickness of 100 nm was formed on the aluminum film, and the titanium film, the aluminum film, and the titanium film were A conductive layer 905 and a conductive layer 906 are formed by etching a part of the laminated layer of the titanium film. do.

[0396] Next, a heat treatment is performed at 300° C. for 1 hour in a nitrogen atmosphere.

[0397] Next, over the insulating layer 902, the oxide semiconductor layer 903, the conductive layer 905, and the conductive layer 906, An insulating layer 907 is formed. Here, the insulating layer 902, the oxide semiconductor layer 903, and the conductive layer 90 5 and the conductive layer 906, a silicon oxide film having a thickness of 300 nm is formed on the conductive layer 906. An insulating layer 907 is formed.

[0398] Next, a part of the insulating layer 907 is etched to form an opening penetrating the conductive layer 905. An opening penetrating the conductive layer 906 is formed.

[0399] Next, a planarization layer 908 is formed on the insulating layer 907. A planarizing layer 908 is formed by applying an acrylic layer and exposing a portion of the acrylic layer. .

[0400] Further, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0401] Next, a conductive layer 909 in contact with the conductive layer 905 and a conductive layer 906 in contact with the conductive layer 906 are formed on the planarization layer 908. A conductive layer 910 is formed on the planarization layer 908 by a sputtering method. A titanium film having a thickness of 200 nm was formed on the substrate, and a part of the titanium film was etched. A conductive layer 909 and a conductive layer 910 are formed.

[0402] Next, a heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour. This is the manufacturing method.

[0403] As shown in Fig. 7(A), a transistor for charge injection and a transistor for leakage current evaluation are By providing the transistor for leak current evaluation separately, the transistor for leak current evaluation can be always can be kept in the off state.

[0404] In addition, a transistor for charge injection and a transistor for leakage current evaluation are provided separately. This allows each transistor to be sized appropriately. The channel width W of the transistor for current evaluation is set to be smaller than the channel width W of the transistor for charge injection. By making the value larger than the leakage current evaluation transistor, it is possible to evaluate characteristics other than the leakage current of the transistor. The leakage current component of the circuit can be made relatively small. As a result, The leakage current of the transistor can be measured with high accuracy. At the same time, Since it is not necessary to turn on the transistor for leak current evaluation, the leak current evaluation A part of the charge in the channel formation region of the transistor flows into node A. There is no effect of voltage fluctuations at A.

[0405] Next, the leakage current measurement method for the characteristic evaluation circuit shown in Figure 7(A) is explained using Figure 7(C). FIG. 7C shows a leakage current measurement method using the characteristic evaluation circuit shown in FIG. 1 is a timing chart for explaining the above.

[0406] The leakage current measurement method using the characteristic evaluation circuit shown in FIG. The operation during each period is described below.

[0407] During the write period, the voltage Vext_b is set so that the transistor 812 is in an off state. Input the voltage VL (-3V) as the write voltage Vw as the voltage V1. Then, the voltage Vext_a is set to a voltage that keeps the transistor 811 in an on state for a certain period of time. Input VH (5V). This causes charge to accumulate at node A, and the voltage at node A becomes Then, the voltage Vext_a is set to a value equivalent to the write voltage Vw. Input a voltage VL that will turn off 811. Then, set the voltage V1 to the voltage VS Input S(0V).

[0408] During the hold period, the voltage at node A changes due to the change in the amount of charge held by node A. The amount of change in the voltage is measured. The current flowing between the electrodes can be calculated. and the amount of change in the voltage at node A can be measured.

[0409] At this time, the charge of node A is stored and the amount of change in the voltage of node A is measured (storage and measurement operations First, the first accumulation and measurement operation is repeated 15 times. In the accumulation and measurement operation, a voltage of 5 V is input as the write voltage Vw during the write period. The retention period is one hour. Next, the second accumulation and measurement operation is repeated twice. In the accumulation and measurement operation of 2, a voltage of 3.5 V was input as the write voltage Vw during the write period. Then, the third accumulation and measurement operation is performed once. In the accumulation and measurement operation of 3, a voltage of 4.5 V was input as the write voltage Vw during the write period. The data is input and held for 10 hours. By repeating the accumulation and measurement operations, It can be confirmed that the measured current value is a value in a steady state. and the current I flowing through node A A Of these, the transient current (which decreases over time from the start of measurement) As a result, the leakage current can be measured with higher accuracy. It is possible.

[0410] In general, the voltage at node A, V A is expressed as a function of the output voltage Vout as follows: .

[0411]

number

[0412] Also, the charge Q at node A A is the voltage at node A, V A , capacitance C connected to node A A , fixed Using a number (const), it is expressed as follows:

[0413]

number

[0414] Here, the capacitance C connected to node A A is the capacitance of the capacitor 813 and the capacitance of the capacitor other than the capacitor 813. is the sum of the capacitive components of

[0415] Current I at node A A is the charge flowing into (or out of) node A. Since it is a differential between the current and the current A is expressed as follows:

[0416]

number

[0417] In this example, Δt is set to about 54000 sec. Capacitance C connected to A The leakage current I A Therefore, the leakage current of the characteristic evaluation circuit can be obtained.

[0418] Next, the output voltage measurement results by the measurement method using the above characteristic evaluation circuit and the The calculated leakage current value of the characteristic evaluation circuit will be explained with reference to FIG.

[0419] FIG. 8A shows an example of the transistors in SMP4, SMP5, and SMP6. The elapsed time Time related to the above measurement (first accumulation and measurement operation) and the output voltage Vout FIG. 8(B) shows the relationship between the elapsed time Time and the calculated value obtained by the measurement. The current I A The output voltage Vout fluctuates after the measurement starts, and It is clear that it takes more than 10 hours to reach this state.

[0420] FIG. 9 shows the estimated values ​​of SMP1 to SMP6 from the values ​​obtained by the above measurements. In Fig. 9, the relationship between the voltage and leakage current of node A in an SMP4 is shown. When the voltage at the input is 3.0V, the leakage current is 28yA / μm. Since the off-current of the transistor 812 is also included, the off-current of the transistor 812 is also 28 yA / It can be considered to be less than μm.

[0421] 10, 11, and 12 show the results of the above measurements at 85°C, 125°C, and 150°C. Relationship between the voltage and leakage current at node A in SMP1 to SMP6 estimated by the As shown in Figs. 10 to 12, even at 150°C, the leakage current is 1 It can be seen that the value is less than 0.00zA / μm.

[0422] As described above, the present invention can be implemented by using a semiconductor device that includes a highly purified oxide semiconductor layer having a function as a channel formation layer. In the characteristic evaluation circuit using a transistor including It can be seen that the off-state current of the transistor is sufficiently small. , it can be seen that the temperature is sufficiently low even when the temperature increases.

[0423] (Embodiment 6) In this embodiment mode, a structural example of the input / output device in the above embodiment mode will be described.

[0424] The input / output device in this embodiment includes a first Between the substrate (active matrix substrate), the second substrate, and the first substrate and the second substrate and a liquid crystal layer provided thereon.

[0425] First, a structural example of an active matrix substrate in an input / output device according to the present embodiment will be described. The following description will be given with reference to Figs. 13 and 14. Figs. 13 and 14 show the input / output device of the present embodiment. 13A is a schematic plan view showing an example of the structure of an active matrix substrate in the FIG. 13B is a schematic cross-sectional view taken along line AB in FIG. 13A. FIG. FIG. 14(A) is a schematic plan view, and FIG. 14(B) is a cross-section taken along line segment CD in FIG. 14(A). In addition, in FIG. 14, as an example of a photodetection circuit, the photodetection circuit having the configuration shown in FIG. This shows a case where a detection circuit is used. As an example, two photoelectric conversion elements and two charge accumulation control transistors are used. 13 and 14 show the transistors, the amplifier transistor, and the output selection transistor. In the fourth embodiment, a transistor having the structure described with reference to FIG. This indicates that

[0426] The active matrix substrate shown in FIGS. 13 and 14 includes a substrate 500 and a conductive layer 501a. A conductive layer 501k, an insulating layer 502, semiconductor layers 503a to 503e, and a conductive The layers 504a to 504n, the insulating layer 505, the semiconductor layer 506a, and the semiconductor layer 50 6b, a semiconductor layer 507a, a semiconductor layer 507b, a semiconductor layer 508a, and a semiconductor layer 50 8b, an insulating layer 509, and conductive layers 510a to 510c.

[0427] Each of the conductive layers 501 a to 501 k is provided on one surface of the substrate 500 .

[0428] The conductive layer 501a functions as the gate of a display selection transistor in the display circuit. do.

[0429] The conductive layer 501b functions as a first capacitor electrode of a storage capacitor in the display circuit. The layer having the function of the first capacitance electrode of the capacitance element (storage capacitance) is called the first capacitance electrode. It is also called.

[0430] The conductive layer 501c functions as a wiring to which a first photodetection reset signal is input. Note that a layer having a function as a wiring is also called a wiring.

[0431] The conductive layer 501d functions as a wiring to which a second photodetection reset signal is input.

[0432] The conductive layer 501e serves as the gate of a first charge storage control transistor in the light detection circuit. It has the following functions.

[0433] The conductive layer 501f serves as the gate of a second charge storage control transistor in the light detection circuit. It has the following functions.

[0434] The conductive layer 501g functions as a signal line to which a first charge accumulation control signal is input. Note that a layer having a function as a signal line is also called a signal line.

[0435] The conductive layer 501h functions as a signal line to which a second charge accumulation control signal is input.

[0436] The conductive layer 501i functions as the gate of the output selection transistor in the photodetection circuit. do.

[0437] The conductive layer 501j functions as the gate of the amplification transistor in the photodetection circuit. .

[0438] The conductive layer 501k functions as a wiring to which the voltage V0 is input.

[0439] The insulating layer 502 is provided on one surface of the substrate 500 with the conductive layers 501a to 501k interposed therebetween. can be done.

[0440] The insulating layer 502 is a gate insulating layer for a display selection transistor in the display circuit. the dielectric layer of the storage capacitor in the photodetector circuit, and each of the X charge storage control transistors in the photodetector circuit. the gate insulating layer of the amplifying transistor in the photodetection circuit, and the gate insulating layer of the amplifying transistor in the photodetection circuit It functions as a gate insulating layer for the output selection transistor in the circuit.

[0441] The semiconductor layer 503a overlaps with the conductive layer 501a with the insulating layer 502 interposed therebetween. The layer a functions as a channel formation layer of a display selection transistor in a display circuit.

[0442] The semiconductor layer 503b overlaps with the conductive layer 501d with the insulating layer 502 interposed therebetween. b functions as a channel forming layer of the first charge storage control transistor in the photodetection circuit; Possesses the ability.

[0443] The semiconductor layer 503c overlaps with the conductive layer 501f with the insulating layer 502 interposed therebetween. c functions as a channel forming layer of the second charge storage control transistor in the photodetection circuit. Possesses the ability.

[0444] The semiconductor layer 503d overlaps with the conductive layer 501i with the insulating layer 502 interposed therebetween. d has a function as a channel forming layer of the output selection transistor in the photodetection circuit. .

[0445] The semiconductor layer 503e overlaps with the conductive layer 501j with the insulating layer 502 interposed therebetween. j has a function as a channel formation layer of the amplifying transistor in the photodetector circuit.

[0446] The conductive layer 504a is electrically connected to the semiconductor layer 503a. The gate serves as one of the source and drain of a display selection transistor in the path.

[0447] The conductive layer 504b is electrically connected to the conductive layer 501b and the semiconductor layer 503a. 504b is the other of the source and drain of the display selection transistor in the display circuit It has the following functions.

[0448] The conductive layer 504c overlaps with the conductive layer 501b with the insulating layer 502 interposed therebetween. , and serves as a second capacitor electrode of a storage capacitor in the display circuit.

[0449] The conductive layer 504d is electrically connected to the conductive layer 501c at an opening that penetrates the insulating layer 502. The conductive layer 504d is connected to the first current terminal of the first photoelectric conversion element in the photodetection circuit. and serves as one of the second current terminals.

[0450] The conductive layer 504e is electrically connected to the conductive layer 501d at an opening that penetrates the insulating layer 502. The conductive layer 504e is connected to the first current terminal of the second photoelectric conversion element in the photodetection circuit. and serves as one of the second current terminals.

[0451] The conductive layer 504f is electrically connected to the semiconductor layer 503b. Functioning as one of the source and drain of a first charge storage control transistor in the circuit has.

[0452] The conductive layer 504g is electrically connected to the semiconductor layer 503c. Functioning as one of the source and drain of a second charge storage control transistor in the circuit has.

[0453] The conductive layer 504h is connected to the conductive layer 501e and the conductive layer 501c at an opening penetrating the insulating layer 502. The conductive layer 504h is electrically connected to the first charge accumulation control signal. It functions as a signal line.

[0454] The conductive layer 504i is connected to the conductive layer 501f and the conductive layer 501c at an opening penetrating the insulating layer 502. The conductive layer 504i is electrically connected to the second charge accumulation control signal. It functions as a signal line.

[0455] The conductive layer 504j is electrically connected to the semiconductor layer 503b and the semiconductor layer 503c and is an insulating layer. The conductive layer 501j is electrically connected to the conductive layer 501j at an opening through the edge layer 502. 4j is a first charge storage control transistor and a second charge storage control transistor in the photodetection circuit; It functions as the other of the source and drain of the transistor.

[0456] The conductive layer 504k is electrically connected to the semiconductor layer 503d. It functions as one of the source and drain of the output selection transistor in the circuit.

[0457] The conductive layer 504l is electrically connected to the semiconductor layer 503d and the semiconductor layer 503e. Layer 504l is the other of the source and drain of the output selection transistor in the photodetection circuit. and functioning as one of the source and drain of an amplifying transistor in a photodetector circuit. Yes.

[0458] The conductive layer 504m is electrically connected to the semiconductor layer 503e and has an opening penetrating the insulating layer 502. The conductive layer 504m is electrically connected to the conductive layer 501k at the portion of the light detection circuit. The amplifier transistor has a function as the other of the source and drain of the amplifier transistor.

[0459] The conductive layer 504n is electrically connected to the conductive layer 501k at an opening that penetrates the insulating layer 502. The conductive layer 504n functions as a wiring to which a voltage V0 is input.

[0460] The insulating layer 505 is formed by insulating the semiconductor layers 503a to 504k with the conductive layers 504a to 504k interposed therebetween. It contacts layer 503d.

[0461] The semiconductor layer 506a is formed by arranging the conductive layer 504d in an opening formed through the insulating layer 505. is electrically connected to

[0462] The semiconductor layer 506b is formed by arranging the conductive layer 504e in an opening formed through the insulating layer 505. is electrically connected to

[0463] The semiconductor layer 507a is in contact with the semiconductor layer 506a.

[0464] The semiconductor layer 507b is in contact with the semiconductor layer 506b.

[0465] The semiconductor layer 508a is in contact with the semiconductor layer 507a.

[0466] The semiconductor layer 508b is in contact with the semiconductor layer 507b.

[0467] The insulating layer 509 is made up of the insulating layer 505, the semiconductor layer 506a, the semiconductor layer 506b, and the semiconductor layer 507. The insulating layer 5 overlaps with the semiconductor layer 507b, the semiconductor layer 508a, and the semiconductor layer 508b. 09 functions as a planarization insulating layer in the display circuit and the photodetector circuit. The insulating layer 509 does not necessarily have to be provided.

[0468] The conductive layer 510a is formed by bonding the conductive layer 50 to the insulating layer 505 at an opening penetrating the insulating layer 509. 4b. In addition, the conductive layer 510a is overlapped with the conductive layer 501a. The conductive layer 510a is a layer for a display element in a display circuit. The layer having the function of a pixel electrode is called a pixel electrode. Also called.

[0469] The conductive layer 510b is formed by bonding the conductive layer 50 to the insulating layer 505 at an opening penetrating the insulating layer 509. 4f, and a semiconductor is formed in an opening penetrating the insulating layer 505 and the insulating layer 509. The insulating layer 508a is electrically connected to the insulating layer 508b.

[0470] The conductive layer 510c is formed by bonding the conductive layer 50 to the insulating layer 505 at an opening penetrating the insulating layer 509. 4g, and a semiconductor device is provided at an opening penetrating the insulating layer 505 and the insulating layer 509. The insulating layer 508b is electrically connected to the insulating layer 508c.

[0471] Further, a structural example of the input / output device in this embodiment will be described with reference to FIGS. 15 and 16. 15 and 16 show a liquid crystal display device using the active matrix substrate shown in FIG. 13 and FIG. 15A is a schematic plan view of an input / output device according to an embodiment of the present invention; FIG. 15B is a schematic plan view of an input / output device according to an embodiment of the present invention; FIG. 15B) is a schematic cross-sectional view taken along line AB in FIG. 15A, and FIG. 16A is a schematic plan view. FIG. 16(B) is a schematic cross-sectional view taken along line segment CD in FIG. 16(A). As an example, the photoelectric conversion element is a photodiode, and the display element is a liquid crystal element.

[0472] The input / output device shown in FIGS. 15 and 16 is an active matrix type device shown in FIGS. In addition to the plate, a substrate 512, a light-shielding layer 513, an insulating layer 516, a conductive layer 517, and a liquid crystal layer 5 15A and 16A, the conductive layer 517 is not shown for the sake of convenience. is omitted.

[0473] The light-shielding layer 513 is provided on a part of one plane of the substrate 512. For example, the light-shielding layer 513 is a photoelectric conversion layer. It is provided on one surface of the substrate 512 except for the portion where the conversion elements are formed.

[0474] The insulating layer 516 is provided on one surface of the substrate 512 with the light-shielding layer 513 interposed therebetween.

[0475] The conductive layer 517 is provided on one surface of the substrate 512. It has a function as a common electrode. Note that the conductive layer 517 is not necessarily provided in the light detection circuit. It doesn't have to be.

[0476] The liquid crystal layer 518 is provided between the conductive layer 510a and the conductive layer 517 and is connected to the insulating layer 509. 508.

[0477] The conductive layer 510a, the liquid crystal layer 518, and the conductive layer 517 are a display element in a display circuit. It has the function as follows.

[0478] Furthermore, each component of the input / output device shown in FIG. 15 and FIG. 16 will be described.

[0479] The substrate 500 and the substrate 512 are applicable to the substrate 400a in FIG. can be used.

[0480] The conductive layers 501a to 501k may be formed by applying the same composition as that of the conductive layer 401a in FIG. A layer of a material applicable to the conductive layer 401a can be used. The conductive layers 501a to 501k may be formed by layering the conductive layers 501a to 501k.

[0481] The insulating layer 502 is made of a material that can be used for the insulating layer 402a in FIG. Also, the insulating layer 502 can be formed by stacking layers of a material applicable to the insulating layer 402a. It may be configured.

[0482] The semiconductor layers 503a to 503e are the oxide semiconductor layer 40 shown in FIG. A layer of material applicable to 3a may be used.

[0483] The conductive layers 504a to 504n may be the conductive layer 405a or A layer of a material applicable to the conductive layer 406a can be used. Conductive layers 504a to 504n are formed by stacking layers of a material applicable to conductive layer 406a. You may do so.

[0484] The insulating layer 505 is made of a material that can be used for the insulating layer 407a in FIG. In addition, the insulating layer 505 can be formed by stacking layers applicable to the insulating layer 407a. This is also fine.

[0485] The semiconductor layer 506a and the semiconductor layer 506b are semiconductor layers of one conductivity type (either P type or N type). The semiconductor layer 506a and the semiconductor layer 506b are, for example, a semiconductor containing silicon. A conductive layer may be used.

[0486] The semiconductor layer 507a and the semiconductor layer 507b have a higher resistance than the semiconductor layer 506. The semiconductor layer 507a and the semiconductor layer 507b are made of, for example, a semiconductor containing silicon. A layer may be used.

[0487] The semiconductor layer 508a and the semiconductor layer 508b have a conductivity type different from that of the semiconductor layer 506 (P type and The semiconductor layer 508a and the semiconductor layer 508b are, for example, For example, a semiconductor layer containing silicon can be used.

[0488] The insulating layer 509 and the insulating layer 516 may be made of, for example, polyimide, acrylic, benzocyclobutene, or the like. The insulating layer 509 may be a layer of an organic material such as tungsten. A layer of material (also called low-k material) can also be used.

[0489] The conductive layers 510 to 510c and the conductive layer 517 can be formed, for example, using a light-transmitting conductive film. A layer of conductive material can be used. An example of a conductive material that has light-transmitting properties is indium tin. Oxide, a metal oxide made by mixing indium oxide and zinc oxide (IZO: indium zi nc oxide), a conductive material made by mixing indium oxide with silicon oxide (SiO2) Indium oxides including organo-indium, organo-tin, tungsten oxide, tungsten oxide Indium zinc oxide containing tin, indium oxide containing titanium oxide, or titanium oxide For example, indium tin oxide containing indium can be used.

[0490] In addition, the conductive layer 51 is formed using a conductive composition containing a conductive macromolecule (also called a conductive polymer). The conductive layers 510a to 510c and the conductive layer 517 can also be formed using a conductive composition. The conductive layer formed by this method has a sheet resistance of 10,000 Ω / □ or less and a transparency at a wavelength of 550 nm. It is preferable that the light efficiency is 70% or more. The resistivity is preferably 0.1 Ω·cm or less.

[0491] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples of the dopant-conjugated conductive polymer include polyaniline or its derivatives, and polypyrrole. or derivatives thereof, polythiophene or derivatives thereof, or aniline, pyrrole and Examples of the copolymer include a copolymer of two or more kinds of thiophene and a derivative thereof.

[0492] In addition, the conductive layers 510a to 510c and the conductive layer 517 are formed using graphene. It is also possible.

[0493] The light blocking layer 513 may be, for example, a layer made of a metal material.

[0494] The liquid crystal layer 518 may be, for example, a TN liquid crystal, an OCB liquid crystal, an STN liquid crystal, a VA liquid crystal, or an ECB type. Use of a layer containing liquid crystal, GH liquid crystal, polymer dispersed liquid crystal, discotic liquid crystal, or the like Note that the liquid crystal layer 518 can be formed by applying a voltage to the conductive layer 510c and the conductive layer 517. It is preferable to use a liquid crystal that transmits light when the voltage is 0V.

[0495] As described with reference to FIGS. 13 to 16, the structure of the input / output device in this embodiment is an active matrix substrate including a transistor, a pixel electrode, and a photoelectric conversion element; A structure including a substrate, an active matrix substrate, and a liquid crystal layer having liquid crystal between an opposing substrate. By adopting the above structure, the display circuit and the light detection circuit can be formed on the same substrate in the same process. Since a circuit can be fabricated, manufacturing costs can be reduced.

[0496] As described with reference to FIGS. 13 to 16, the configuration of the input / output device in this embodiment The example has a structure in which a light-shielding layer is provided except for the portion through which light is transmitted. This suppresses the incidence of light on transistors provided on an active matrix substrate, for example. This allows the electrical characteristics of the transistor (such as the threshold voltage) to be controlled by light. Fluctuations can be suppressed.

[0497] In the input / output device according to this embodiment, the display circuit and the light detection circuit are provided on the same substrate. In this case, the display driver circuit may be provided with a display driver circuit and a light detection driver circuit. The transistor structure of the circuits such as the display circuit and the photodetection circuit is The structure of the transistor may be the same as that of the transistor in the semiconductor device.

[0498] (Embodiment 7) In this embodiment mode, an example of an electronic device including the input / output device in the above embodiment mode will be described. Reveal.

[0499] Configuration examples of electronic devices in this embodiment will be described with reference to FIGS. 17A to 17D. 17A to 17D are configuration examples of electronic devices in this embodiment. FIG.

[0500] The electronic device shown in FIG. 17(A) is an example of a portable information terminal. The terminal includes a housing 1001a and a display unit 1002a provided in the housing 1001a. .

[0501] A connection terminal for connecting to an external device is provided on a side surface 1003a of the housing 1001a, and One or more buttons for operating the portable information terminal shown in 17(A) may be provided. .

[0502] The portable information terminal shown in FIG. 17(A) includes a CPU and a main memory in a housing 1001a. an interface for transmitting and receiving signals between an external device and the CPU and main memory; An antenna for transmitting and receiving signals to and from external devices is provided. There may be one or more integrated circuits having a specific functionality.

[0503] The portable information terminal shown in FIG. 17(A) is, for example, a telephone, an electronic book, a personal computer, etc. The device has the functions of one or more of a game machine and a game controller.

[0504] The electronic device shown in FIG. 17B is an example of a folding portable information terminal. The portable information terminal shown in FIG. 1 includes a housing 1001b and a display unit 100 provided in the housing 1001b. 2b, a housing 1004, a display unit 1005 provided on the housing 1004, and a housing 1001b. and a shaft portion 1006 that connects the housing 1004.

[0505] In the portable information terminal shown in FIG. 17B, the shaft portion 1006 is connected to the housing 1001b or By moving the housing 1004, the housing 1001b can be superimposed on the housing 1004. Cut.

[0506] In addition, a side surface 1003b of the housing 1001b or a side surface 1007 of the housing 1004 is connected to an external device. 17B shows a connection terminal for connecting the portable information terminal to the One or more of the above may be provided.

[0507] Also, the display unit 1002b and the display unit 1005 may display different images or a series of images. The display unit 1005 is not necessarily provided. Alternatively, a keyboard may be provided as an input device.

[0508] The portable information terminal shown in FIG. 17B includes a CPU in the housing 1001b or the housing 1004. and a main memory, and an interface for transmitting and receiving signals between an external device and the CPU and main memory. In addition, a specific function is provided in the housing 1001b or the housing 1004. In addition, a portable information terminal shown in FIG. An antenna for transmitting and receiving signals to and from the outside may be provided.

[0509] The portable information terminal shown in FIG. 17(B) is, for example, a telephone, an electronic book, a personal computer, etc. The device has the functions of one or more of a game machine and a game controller.

[0510] The electronic device shown in FIG. 17(C) is an example of a stationary information terminal. The information terminal includes a housing 1001c and a display unit 1002c provided in the housing 1001c. Prepare.

[0511] The display unit 1002c may be provided on the deck portion 1008 of the housing 1001c. do.

[0512] Also, the stationary information terminal shown in FIG. 17(C) has a CPU and a main An interface that transmits and receives signals between memory, external devices, the CPU, and main memory In addition, the housing 1001c includes one or more integrated circuits having a specific function. In addition, the stationary information terminal shown in FIG. 17(C) may be provided with a function for transmitting and receiving signals to and from the outside. An antenna may be provided to perform the same.

[0513] Furthermore, on a side surface 1003c of a housing 1001c of a stationary information terminal shown in FIG. One or more of a ticket output unit for outputting tickets, a coin input unit, and a bill input unit may be provided. .

[0514] The stationary information terminal shown in FIG. 17(C) is, for example, an automatic teller machine, a device for ordering tickets, etc. Functions as an information and communication terminal (also called a multimedia station) for playing games or as a gaming machine has.

[0515] FIG. 17(D) is an example of a stationary information terminal. The stationary information terminal shown in FIG. 17(D) is a housing. The device includes a body 1001d and a display unit 1002d provided on the housing 1001d. A support stand may be provided to support the housing 1001d.

[0516] A connection terminal for connecting to an external device is provided on a side surface 1003d of the housing 1001d, and One or more buttons for operating the stationary information terminal shown in 17(D) may be provided. .

[0517] Also, the stationary information terminal shown in FIG. 17(D) has a CPU and a main An interface that transmits and receives signals between memory, external devices, the CPU, and main memory In addition, an integrated circuit having a specific function may be installed in the housing 1001d. Alternatively, a plurality of units may be provided. In addition, the stationary information terminal shown in FIG. 17(D) may be provided with a signal transmission unit for transmitting signals to the outside. An antenna for receiving may be provided.

[0518] The stationary information terminal shown in FIG. 17(D) is, for example, a digital photo frame, an input / output monitor, Or it has the function of a television device.

[0519] The input / output device according to the above embodiment is used as, for example, a display unit of an electronic device. The display units 1002a to 1002d shown in FIGS. In addition, the input / output device of the above embodiment is used as the display unit 1005 shown in FIG. Good too.

[0520] As described with reference to FIG. 17, an example of the electronic device according to the present embodiment is The input / output unit is configured to include the input / output device in the above-described embodiment. This allows, for example, a finger or a pen to be used to operate an electronic device or input information into the electronic device. This can be done.

[0521] In addition, in one example of the electronic device according to the present embodiment, the housing is provided with a power supply voltage control circuit in response to the illuminance incident thereon. The device is provided with one or more of a photoelectric conversion unit that generates a voltage and an operation unit that operates an input / output device. For example, by providing a photoelectric conversion unit, an external power supply is not required. The electronic device can be used for a long time even in places without a power source. [Explanation of symbols]

[0522] 101a Display circuit control unit 101b Photodetection circuit control section 101c Light source section 101d Pixel section 111 Display driver circuit 112 Display data signal output circuit 113 Photodetector driver circuit 114 Light Unit 115d display circuit 115p Photodetector circuit 116 Readout circuit 131 Photoelectric conversion element 132 Transistor 133 Transistor 134 Transistor 135 Transistor 161a Transistor 161b Transistor 162a Liquid crystal element 162b Liquid crystal element 163a Capacitive element 163b Capacitive element 164 Capacitive element 165 Transistors 166 Transistor 400a board 400b board 400c board 401a Conductive layer 401b Conductive layer 401c conductive layer 402a Insulating layer 402b Insulating layer 402c Insulating layer 403a Oxide semiconductor layer 403b Oxide semiconductor layer 403c Oxide semiconductor layer 405a Conductive layer 405b Conductive layer 405c conductive layer 406a conductive layer 406b Conductive layer 406c conductive layer 407a Insulating layer 407b Insulating layer 408a conductive layer 408b Conductive layer 447 Insulating Layer 500 boards 501a conductive layer 501b conductive layer 501c conductive layer 501d conductive layer 501e conductive layer 501f conductive layer 501g conductive layer 501h conductive layer 501i conductive layer 501j conductive layer 501k conductive layer 502 Insulating layer 503a Semiconductor layer 503b Semiconductor layer 503c Semiconductor layer 503d Semiconductor layer 503e Semiconductor layer 503j Semiconductor layer 504a Conductive layer 504b conductive layer 504c conductive layer 504d Conductive layer 504e conductive layer 504f conductive layer 504g conductive layer 504h conductive layer 504i conductive layer 504j conductive layer 504k conductive layer 504l Conductive layer 504m Conductive Layer 504n conductive layer 505 Insulation Layer 506 Semiconductor Layer 506a Semiconductor layer 506b Semiconductor layer 507a Semiconductor layer 507b Semiconductor layer 508 Semiconductor layer 508a Semiconductor layer 508b Semiconductor layer 509 Insulating layer 510 Conductive layer 510a Conductive layer 510b Conductive layer 510c conductive layer 512 Substrate 513 Light blocking layer 516 Insulating Layer 517 Conductive Layer 518 Liquid crystal layer 600 Substrates 602 Undercoat insulation layer 606 Oxide semiconductor layer 608 Gate Insulation Layer 610 Gate electrode 614 Electrode 616 Interlayer Insulation Layer 618 Wiring 620 Protective film 701 Undercoat insulation layer 702 Insulation 703a Semiconductor area 703b Semiconductor area 703c Semiconductor field 704 Gate insulation layer 705 Gate electrode 706a Sidewall insulation 706b Sidewall insulation 707 Insulation 708a Source electrode 708b Drain electrode 750 Board 752 Undercoat insulation layer 754 Protective insulation layer 756 Oxide semiconductor layer 756a High resistance area 756b Low resistance region 758 Gate Insulation Layer 760 Gate electrode 762 Sidewall Insulation 764 Electrode 766 Interlayer Insulation Layer 768 Wiring 801 Measurement System 811 Transistor 812 Transistor 813 Capacitive element 814 Transistor 815 Transistor 900 Substrate 901 Conductive layer 902 Insulation layer 903 Oxide semiconductor layer 905 Conductive layer 906 Conductive layer 907 Insulation Layer 908 Planarization layer 909 Conductive layer 910 Conductive layer 927 Insulation Layer 1001a Case 1001b Case 1001c Case 1001d case 1002a Display section 1002b Display section 1002c Display section 1002d Display section 1003a side 1003b Side 1003c side 1003d side 1004 Case 1005 Display section 1006 Shaft 1007 Side 1008 Deck section

Claims

[Claim 1] a first photoelectric conversion element having silicon; a second photoelectric conversion element having silicon; a first transistor, one of a source and a drain of which is electrically connected to a cathode of the first photoelectric conversion element; a second transistor, one of a source and a drain of which is electrically connected to the cathode of the second photoelectric conversion element; a third transistor, the gate of which is electrically connected to the other of the source or the drain of the first transistor and the other of the source or the drain of the second transistor via a first conductive layer; a fourth transistor, one of a source and a drain of which is electrically connected to one of a source and a drain of the third transistor; having the anode of the first photoelectric conversion element is electrically connected to the third conductive layer via the second conductive layer; the other of the source and the drain of the third transistor is electrically connected to a fourth conductive layer; the other of the source and the drain of the fourth transistor is electrically connected to a fifth conductive layer functioning as a wiring for outputting a signal; the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer comprise copper; the first conductive layer and the second conductive layer are disposed in contact with a first insulating layer; the second conductive layer and the third conductive layer are disposed on a side opposite to a light receiving surface side of the first photoelectric conversion element, a second insulating layer disposed on the light receiving surface side of the first photoelectric conversion element has a region covering a side surface of the first photoelectric conversion element, In a plan view, the first conductive layer overlaps with the third conductive layer via the first insulating layer; A semiconductor device, wherein, in a planar view, a contact hole provided in the first insulating layer and electrically connecting the second conductive layer and the third conductive layer overlaps with a light-shielding layer arranged on the light-receiving surface side of the first photoelectric conversion element.

Images