Signal generating circuit and semiconductor device
Patent Information
- Application Number
- JP2023128327
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-08-07
- Publication Date
- 2025-02-20
Smart Images
Figure 2025024305000001_ABST
Abstract
Description
[Technical field]
[0001] The present disclosure relates to a signal generating circuit and a semiconductor device. [Background technology]
[0002] A circuit that receives an input control signal generates one or more signals required by a downstream circuit in response to the input control signal. Examples of input control signals include a power-down control signal, an enable control signal, and various setting signals. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] JP 2020-108189 A
[0004] [overview] It is sometimes necessary to generate a plurality of signal systems with different reference levels according to an input control signal, and it would be beneficial if such generation could be realized with a simple configuration.
[0005] A signal generation circuit according to one embodiment of the present disclosure includes an input circuit having a first FET that receives an input control signal at its gate and configured to generate a first signal depending on a state of the first FET, an intermediate circuit having a second FET that receives the first signal at its gate and configured to generate a second signal depending on a state of the second FET, and an output circuit having a third FET that receives the second signal at its gate and configured to generate a third signal depending on a state of the third FET, wherein the input control signal, the first signal, the second signal, and the third signal have a low level or a high level, the input circuit has a first clamp diode connected in parallel to the first FET and configured to set a high level of the first signal to a predetermined first clamp voltage, the intermediate circuit has a second clamp diode connected in parallel to the second FET and configured to set a high level of the second signal to a predetermined second clamp voltage, and the output circuit has an output resistor that is provided between an application node of a power supply voltage and an output node at which the third signal is generated and is connected in series with the third FET, and a third clamp diode that is connected in parallel to the output resistor and configured to set a low level of the third signal to a voltage lower than the power supply voltage by a predetermined third clamp voltage. [Brief description of the drawings]
[0006] [Figure 1] FIG. 1 is a schematic configuration diagram of a semiconductor device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is an external perspective view of the semiconductor device according to the embodiment of the present disclosure. [Diagram 3] FIG. 3 is a diagram for explaining the voltage ranges of two systems of signals handled by the semiconductor device according to the embodiment of the present disclosure. [Figure 4] FIG. 4 is a configuration diagram of a signal generating circuit according to a reference example. [Diagram 5] FIG. 5 is a configuration diagram of a signal generating circuit according to a reference example. [Figure 6] FIG. 6 is a configuration diagram of a signal generating circuit according to a first example of an embodiment of the present disclosure. [Figure 7]FIG. 7 is a diagram illustrating the operation of a signal generating circuit according to a first example of an embodiment of the present disclosure. [Figure 8] FIG. 8 is a configuration diagram of an internal power supply circuit and peripheral circuits according to a second embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram illustrating the operation of an internal power supply circuit and peripheral circuits according to a second example of the embodiment of the present disclosure. [Figure 10] FIG. 10 is a configuration diagram of an amplifier device according to a third example of an embodiment of the present disclosure.
[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are generally omitted. In this specification, for the sake of simplicity, by writing a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, the name of the information, signal, physical quantity, functional part, circuit, element, or part corresponding to the symbol or code may be omitted or abbreviated.
[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductive part may be formed using a conductor such as a metal. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage shown without a particular reference represents a potential seen from the ground. Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.
[0009] For any transistor configured as a FET (field effect transistor) such as a MOSFET, the on-state refers to the state where conduction exists between the drain and source of the transistor, and the off-state refers to the state where non-conduction (blocking state) exists between the drain and source of the transistor. The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-mode MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered short-circuited to the source.
[0010] Hereinafter, for any transistor, the on-state and off-state may also be simply expressed as on and off. Also, for any transistor, the period during which the transistor is in the on-state is referred to as the on-period, and the period during which the transistor is in the off-state is referred to as the off-period.
[0011] For any signal taking a high-level or low-level signal level, the period during which the level of the signal is high is referred to as the high-level period, and the period during which the level of the signal is low is referred to as the low-level period. The same applies to any voltage taking a high-level or low-level voltage level.
[0012] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection.
[0013] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, and "v1<v2" represents that voltage v1 is lower than voltage v2. The same applies to other expressions including physical quantities other than voltage.
[0014] FIG. 1 shows a schematic configuration of a semiconductor device 10 according to an embodiment of the present disclosure. FIG. 2 is an external perspective view of the semiconductor device 10. The semiconductor device 10 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a case (package) for accommodating the semiconductor chip, and a plurality of external terminals exposed from the case to the outside of the semiconductor device 10. The semiconductor device 10 is formed by sealing the semiconductor chip in a case (package) made of resin. Note that the number of external terminals of the semiconductor device 10 and the type of case of the semiconductor device 10 shown in FIG. 2 are merely examples, and can be designed arbitrarily. FIG. 1 shows a power input terminal IN, a ground terminal GND, and a control terminal CNT included in the plurality of external terminals. Other external terminals are also provided in the semiconductor device 10. The ground terminal GND is connected to ground.
[0015] A control signal Scnt is input to the control terminal CNT from an external circuit (not shown). The external circuit is, for example, an arithmetic processing circuit such as a microcomputer. The control signal Scnt is a binary signal having a high level or a low level. The high level of the control signal Scnt is determined by the operating power supply voltage of the external circuit. The operating power supply voltage of the external circuit is, for example, 3.3V or 1.8V. It is often required to make the operating power supply voltage of the external circuit as low as possible, and here the operating power supply voltage of the external circuit is assumed to be 1.8V. For this reason, the high level control signal Scnt also has 1.8V (however, there may be some error). The low level control signal Scnt has 0V (however, there may be some error).
[0016] A power supply voltage VCC is input to the power supply input terminal IN from a voltage source not shown. In this embodiment, it is assumed that the semiconductor device 10 is mounted on a vehicle such as an automobile. In this case, the output voltage of a battery mounted on the vehicle is input to the power supply input terminal IN as the power supply voltage VCC. The power supply voltage VCC depends on the output voltage of the battery and is, for example, 12V or 14.4V. The power supply voltage VCC has a potential at least higher than that of the high-level control signal Scnt. For the sake of concrete explanation, the design value of the power supply voltage VCC is assumed to be 12V, and in many situations the power supply voltage VCC is approximately 12V.
[0017] However, due to the effects of a load dump, the power supply voltage VCC may temporarily have a voltage higher than 12 V. For this reason, the power supply input terminal IN is required to withstand a voltage of 40 V. In other words, the semiconductor device 10 needs to be able to withstand without any problems a situation in which a power supply voltage VCC of 40 V is applied to the power supply input terminal IN.
[0018] The semiconductor device 10 includes a signal generating circuit 20, a functional circuit 30L, and a functional circuit 30H. The signal generating circuit 20 is connected to a control terminal CNT and generates signals PD_LV and PD_HV in response to a control signal Scnt. The control signal Scnt can be referred to as an external control signal, and the signals PD_LV and PD_HV can be referred to as internal control signals.
[0019] A signal PD_LV is input to the functional circuit 30L. The signal PD_LV is a binary signal having an assert level or a negate level. The functional circuit 30L is a circuit that performs a predetermined functional operation F_L. However, the functional circuit 30L operates or does not operate depending on the level of the signal PD_LV. The functional circuit 30L is in an operating state during a period when the signal PD_LV has an assert level, and executes the functional operation F_L. The functional circuit 30L is in an inactive state during a period when the signal PD_LV has a negate level, and does not execute the functional operation F_L.
[0020] A signal PD_HV is input to the functional circuit 30H. The signal PD_HV is a binary signal having an assert level or a negate level. The functional circuit 30H is a circuit that performs a predetermined functional operation F_H. However, the functional circuit 30H operates or does not operate depending on the level of the signal PD_HV. The functional circuit 30H is in an operating state during a period when the signal PD_HV has an assert level, and executes the functional operation F_H. The functional circuit 30H is in an inactive state during a period when the signal PD_HV has a negate level, and does not execute the functional operation F_H.
[0021] In this way, the functional circuit 30L is controlled to be activated or deactivated according to the level of the signal PD_LV, and the functional circuit 30H is controlled to be activated or deactivated according to the level of the signal PD_HV (these controls are performed by the signal generation circuit 20). The control signal Scnt functions as a power-down control signal, and the signal generation circuit 20 can also be called a power-down control circuit. Note that the signal PD_LV may be input to the functional circuit 30H in addition to the signal PD_HV. The functional circuit 30H may realize a functional operation F_H in the active state according to the signals PD_HV and PD_LV.
[0022] Of the assertion level and negation level of the signal PD_LV, one is a high level and the other is a low level. Of the assertion level and negation level of the signal PD_HV, one is a high level and the other is a low level.
[0023] Here, the signal PD_LV has a level referenced to ground. That is, the low level of the signal PD_LV has the level of ground, while the high level of the signal PD_LV has a level higher than ground. However, the high level of the signal PD_LV is set to a level lower than the power supply voltage VCC.
[0024] On the one hand, the signal PD_HV has a level referenced to the power supply voltage VCC. That is, the high level of the signal PD_HV has the level of the power supply voltage VCC, while the low level of the signal PD_HV has a level lower when viewed from the power supply voltage VCC. However, the low level of the signal PD_HV is set to a level higher than the ground.
[0025] Referring to FIG. 3, the functional circuit 30L is a circuit designed to operate or not operate by receiving a signal within a predetermined voltage range RNG1 as the signal PD_LV, and the functional circuit 30H is a circuit designed to operate or not operate by receiving a signal within a predetermined voltage range RNG2 as the signal PD_HV. For this reason, the signal generation circuit 20 confines the low level and the high level of the signal PD_LV within the voltage range RNG1, and confines the low level and the high level of the signal PD_HV within the voltage range RNG2.
[0026] The voltage range RNG1 is a range of 0V or more and a predetermined voltage VL or less, and the voltage range RNG2 is a range of a predetermined voltage VH or more and the power supply voltage VCC or less. "0 < VL < VCC" and "0 < VH < VCC" are satisfied. As shown in FIG. 3, "VL < VH" may hold. However, "VL = VH" or "VL > VH" may also be possible. When "VL > VH", the voltage range RNG1 and the voltage range RNG2 partially overlap.
[0027] [Reference Example] FIG. 4 shows a signal generation circuit 920_A according to a first reference example. The signal generation circuit 920_A includes transistors 921 and 924 formed of N-channel MOSFETs, clamp diodes 922 and 925 formed of Zener diodes, pull-up resistors 923 and 926, and a current limiting resistor 927.
[0028] A control signal Scnt is input to the gate of a transistor 921. The drain of the transistor 921 is connected to an application node of a power supply voltage VCC via a resistor 923. The source of the transistor 921 is connected to ground. The anode of a clamp diode 922 is connected to ground, and the cathode of the clamp diode 922 is connected to the drain of the transistor 921 at a node NDa.
[0029] A control signal Scnt is also input to the gate of transistor 924. The drain of transistor 924 is connected to node NDb via resistor 927. Node NDb is connected to a node to which a power supply voltage VCC is applied via resistor 926. The anode of clamp diode 925 is connected to node NDb, and the cathode of clamp diode 925 is connected to the node to which the power supply voltage VCC is applied.
[0030] In the signal generating circuit 920_A, the signals at the nodes NDa and NDb are used as the signals PD_LV and PD_HV, respectively. In the signal generating circuit 920_A, a clamp diode 922 clamps the high level of the signal PD_LV to a Zener voltage V 922 (for example, 5.5 V), and the clamp diode 925 clamps the low level of the signal PD_HV to the Zener voltage V 925 (e.g. 5.5V) lower.
[0031] That is, in the signal generating circuit 920_A, during a high-level period of the control signal Scnt, the transistor 921 is turned on, so that the signal PD_LV has the ground level, and during a low-level period of the control signal Scnt, the transistor 921 is turned off, so that the signal PD_LV has the Zener voltage V 922 On the other hand, in the signal generating circuit 920_A, during the high-level period of the control signal Scnt, the transistor 924 is turned on, so that the signal PD_HV becomes higher than the power supply voltage VCC by the Zener voltage V 925(for example, 5.5 V) during the low-level period of the control signal Scnt, the transistor 924 is turned off, causing the signal PD_HV to have the level of the power supply voltage VCC.
[0032] In this way, in the signal generating circuit 920_A, the signal PD_LV is a voltage (0 V or 922 ), and the signal PD_HV is a voltage (VCC or (VCC-V 925 1, when the control signal Scnt has a high level, the functional circuits 30L and 30H are in an operating state. That is, in the signal generating circuit 920_A, the low level of the signal PD_LV corresponds to the assert level, and the low level of the signal PD_HV corresponds to the assert level.
[0033] In order to meet the requirements shown in FIG. 3, the clamp voltage (i.e., the Zener voltage V 922 ) and the clamp voltage at the clamp diode 925 (i.e., the Zener voltage V 925 ) is designed.
[0034] Incidentally, in the signal generating circuit 920_A, when the transistor 924 is off, a potential difference of the power supply voltage VCC is added to the drain-source voltage of the transistor 924. As described above, the power supply voltage VCC can rise to 40 V, so the transistor 924 needs to be a high-voltage transistor that can withstand a voltage of 40 V (the rectangular frame surrounding the transistor 924 in FIG. 4 indicates that the transistor 924 is a high-voltage transistor). However, since the gate threshold voltage of a high-voltage transistor is generally high, it is difficult to turn on the transistor 924 with a control signal Scnt of about 1.8 V.
[0035] As a countermeasure, a first countermeasure method is considered, in which a transistor having a high withstand voltage but a correspondingly low gate threshold voltage is used as the transistor 924. The first countermeasure method requires a dedicated manufacturing process for forming a transistor having a high withstand voltage and a low gate threshold voltage. Also, depending on the level of the control signal Scnt and the magnitude of the required withstand voltage, it may not be possible to manufacture a corresponding transistor. Therefore, the first countermeasure method is difficult to realize or is not practical.
[0036] A second countermeasure method may be considered in which a level shifter 928 is introduced to increase the gate drive voltage of the transistor 924, as in the signal generating circuit 920_B shown in Fig. 5. In the second countermeasure method, the high level of the gate voltage of the transistor 924 is set to an intermediate power supply voltage VDD (e.g., 5V) higher than the high level of the control signal Scnt. However, in the second countermeasure method, a separate circuit for generating the intermediate power supply voltage VDD is required, which increases the circuit size. The increase in circuit size leads to increased costs.
[0037] Several examples taking these circumstances into consideration are shown below. The matters described above in this embodiment are applied to each of the following examples (excluding matters related to the Reference Example) unless otherwise specified and unless there is a contradiction. In each example, if there is a matter that contradicts the matters described above, the description in each example may take precedence. Furthermore, unless there is a contradiction, matters described in any of the multiple examples shown below can also be applied to any of the other examples (i.e., any two or more of the multiple examples can also be combined).
[0038] <<First Example>> A first embodiment will now be described. Fig. 6 shows a circuit diagram of a signal generating circuit 20 according to the first embodiment. The signal generating circuit 20 includes transistors M1 to M3, clamp diodes D1 to D3, and resistors R1 to R4. The transistors M1 to M3 are N-channel MOSFETs.
[0039] The transistor M1, the clamp diode D1 and the resistor R1 form an input circuit 21. The transistor M2, the clamp diode D2 and the resistor R2 form an intermediate circuit 22. The transistor M3, the clamp diode D3 and the resistors R3 and R4 form an output circuit 23.
[0040] The gate of the transistor M1 is connected to the control terminal CNT and receives a control signal Scnt. The drain of the transistor M1 is connected to the node ND1, and the source of the transistor M1 is connected to the ground. The clamp diode D1 is connected in parallel to the transistor M1 so that the forward direction is from the ground to the node ND1. That is, the anode of the clamp diode D1 is connected to the ground, and the cathode of the clamp diode D1 is connected to the node ND1. The resistor R1 is a first pull-up resistor that is provided in series between the application node of the power supply voltage VCC and the transistor M1. Specifically, the first end of the resistor R1 is connected to the application node of the power supply voltage VCC to receive the power supply voltage VCC, and the second end of the resistor R1 is connected to the node ND1. The application node of the power supply voltage VCC refers to the node to which the power supply voltage VCC is applied.
[0041] Node ND1 is a connection node between resistor R1 and transistor M1, and the signal at node ND1 is signal PD_LV. The level of signal PD_LV changes depending on whether transistor M1 is in an on state or an off state. That is, input circuit 21 generates signal PD_LV at node ND1 according to the state of transistor M1. Signal PD_LV is a binary signal having a high level or a low level.
[0042] The gate of the transistor M2 is connected to the node ND1 and receives the signal PD_LV. The drain of the transistor M2 is connected to the node ND2, and the source of the transistor M2 is connected to the ground. The clamp diode D2 is connected in parallel to the transistor M2 so that the forward direction is from the ground to the node ND2. That is, the anode of the clamp diode D2 is connected to the ground, and the cathode of the clamp diode D2 is connected to the node ND2. The resistor R2 is a second pull-up resistor provided in series between the application node of the power supply voltage VCC and the transistor M2. Specifically, a first end of the resistor R2 is connected to the application node of the power supply voltage VCC to receive the power supply voltage VCC, and a second end of the resistor R2 is connected to the node ND2.
[0043] Node ND2 is a connection node between resistor R2 and transistor M2, and the signal at node ND2 is an intermediate signal MID. The level of intermediate signal MID changes depending on whether transistor M2 is in an on state or an off state. That is, intermediate circuit 22 generates intermediate signal MID according to the state of transistor M2 at node ND2, which is a connection node between resistor R2 and transistor M2. Intermediate signal MID is a binary signal having a high level or a low level.
[0044] The gate of the transistor M3 is connected to the node ND2 and receives the intermediate signal MID. The drain of the transistor M3 is connected to the node ND3 via the resistor R4. That is, a first end of the resistor R4 is connected to the node ND3, and a second end of the resistor R4 is connected to the drain of the transistor M3. The source of the transistor M3 is connected to the ground. The resistor R3 is an output resistor (in other words, a third pull-up resistor) that is provided in series between the application node of the power supply voltage VCC and the node ND3 and is connected in series to the transistor M3. Specifically, the first end of the resistor R3 is connected to the application node of the power supply voltage VCC to receive the power supply voltage VCC, and the second end of the resistor R3 is connected to the node ND3. The clamp diode D3 is connected in parallel to the resistor R3 so that the forward direction is from the node ND3 to the application node of the power supply voltage VCC. That is, the anode of the clamp diode D3 is connected to the node ND3, and the cathode of the clamp diode D3 is connected to the application node of the power supply voltage VCC.
[0045] The signal at node ND3 is a signal PD_HV. The level of the signal PD_HV changes depending on whether the state of transistor M3 is on or off. That is, the output circuit 23 generates the signal PD_HV at node ND3 according to the state of transistor M3. The signal PD_HV is a binary signal having a high level or a low level.
[0046] The operation of the signal generating circuit 20 will be described with reference to Fig. 7. Fig. 7 is a diagram in which the level of each signal of the signal generating circuit 20 and the state of each transistor are added to Fig. 6. In Fig. 7, "H" written in parentheses indicates that the corresponding signal is at a high level, and "L" written in parentheses indicates that the corresponding signal is at a low level. In Fig. 7, "ON" written in parentheses indicates that the corresponding transistor is in an on state, and "OFF" written in parentheses indicates that the corresponding transistor is in an off state.
[0047] In the input circuit 21, the clamp diode D1 is a Zener diode. The Zener voltage of the clamp diode D1 is smaller than the power supply voltage VCC, for example, 5.5 V. When the control signal Scnt has a low level, the transistor M1 is in an off state, and when the control signal Scnt has a high level, the transistor M1 is in an on state.
[0048] When the transistor M1 is in an off state, the signal PD_LV has a high level. The clamp diode D1 clamps the high level of the signal PD_LV to a predetermined clamp voltage V CLMP1 Set the clamp voltage V CLMP1 is equal to the Zener voltage of the clamp diode D1 (hence, for example, 5.5V). That is, during the off-period of the transistor M1, a current flows from the application node of the power supply voltage VCC through the resistor R1 and the clamp diode D1, so that the signal PD_LV has the Zener voltage of the clamp diode D1. When the transistor M1 is in the on-state, the node ND1 is connected to ground through the channel of the transistor M1, so that the signal PD_LV has a low level. The low level of the signal PD_LV has the level of ground. In this way, the signal PD_LV is equal to 0V or the clamp voltage V CLMP1 has.
[0049] In the intermediate circuit 22, the clamp diode D2 is a Zener diode. The Zener voltage of the clamp diode D2 is smaller than the power supply voltage VCC, for example, 5.5 V. When the signal PD_LV has a low level, the transistor M2 is in an off state, and when the signal PD_LV has a high level, the transistor M2 is in an on state.
[0050] When the transistor M2 is in an off state, the intermediate signal MID has a high level. The clamp diode D2 clamps the high level of the intermediate signal MID to a predetermined clamp voltage V CLMP2 Set the clamp voltage V CLMP2is equal to the Zener voltage of the clamp diode D2 (hence, for example, 5.5V). That is, during the off-period of the transistor M2, a current flows from the application node of the power supply voltage VCC through the resistor R2 and the clamp diode D2, so that the intermediate signal MID has the Zener voltage of the clamp diode D2. When the transistor M2 is in the on-state, the node ND2 is connected to ground through the channel of the transistor M2, so that the intermediate signal MID has a low level. The low level of the intermediate signal MID has the level of ground. In this way, the intermediate signal MID is equal to 0V or the clamp voltage V CLMP2 has.
[0051] In the output circuit 23, the clamp diode D3 is a Zener diode. The Zener voltage of the clamp diode D3 is smaller than the power supply voltage VCC, for example, 5.5 V. When the intermediate signal MID has a low level, the transistor M3 is in an off state, and when the intermediate signal MID has a high level, the transistor M3 is in an on state.
[0052] When the transistor M3 is in an off state, the signal PD_HV has a high level. During the off period of the transistor M3, no current flows through the resistor R3, and therefore the high level of the signal PD_HV has the level of the power supply voltage VCC. When the transistor M3 is in an on state, the signal PD_HV has a low level. The clamp diode D3 clamps the low level of the signal PD_HV by a predetermined clamp voltage V below the power supply voltage VCC. CLMP3 Set the clamp voltage V CLMP3 is equal to the Zener voltage of the clamp diode D3 (for example, 5.5 V). In other words, during the on-period of the transistor M3, a current flows from the application node of the power supply voltage VCC through the resistor R3 and the clamp diode D3, so that the signal PD_HV is lower than the power supply voltage VCC by the clamp voltage V CLMP3 In this way, the signal PD_HV has a voltage lower than the power supply voltage VCC or the clamp voltage V CLMP3 The resistor R4 is a current limiting resistor for limiting the current flowing through the transistor M3 during the ON period of the transistor M3.
[0053] To meet the requirements shown in Figure 3, the clamp voltage V CLMP1 and V CLMP3 That is, the clamp voltage V CLMP1 is less than or equal to the voltage VL, and the voltage (VCC-V CLMP3 ) is equal to or greater than the voltage VH.
[0054] 6 is used, the functional circuits 30L and 30H are in an operating state when the control signal Scnt has a high level. During the high level period of the control signal Scnt, the signals PD_LV and PD_HV have a low level, so that the low level of the signal PD_LV corresponds to the assert level, and the low level of the signal PD_HV corresponds to the assert level. Conversely, the high level of the signal PD_LV corresponds to the negate level, and the high level of the signal PD_HV corresponds to the negate level.
[0055] When the transistor M3 is off, a potential difference of the power supply voltage VCC is applied to the drain-source voltage of the transistor M3. As described above, the power supply voltage VCC can rise to 40V, so the transistor M3 needs to be a high-voltage transistor with a withstand voltage of 40V (the square frame surrounding the transistor M3 in FIG. 6 and FIG. 7 indicates that the transistor M3 is a high-voltage transistor). Since the gate threshold voltage of a high-voltage transistor is generally high, it is difficult to turn on the transistor M3 with a control signal Scnt of about 1.8V. However, in the signal generating circuit 20 in FIG. 6, an intermediate signal MID is supplied to the gate of the transistor M3, and the gate of the transistor M3 is driven using the intermediate signal MID.
[0056] And the clamp voltage V CLMP2is set higher than the high-level control signal Scnt (i.e., has a higher potential than the high-level control signal Scnt). Therefore, the high-level intermediate signal MID has a higher voltage than the high-level control signal Scnt. Specifically, for example, the high-level control signal Scnt has a voltage of 1.8V, whereas the high-level intermediate signal MID has a clamp voltage V CLMP2 Therefore, during the high-level period of the control signal Scnt, the transistor M3 can be reliably turned on with a sufficiently high gate voltage (high-level intermediate signal MID).
[0057] Furthermore, the intermediate circuit 22 may be a circuit having the same configuration as the input circuit 21. That is, the signal generation circuit 20 in Fig. 6 can be obtained by simply adding a circuit that is the same as the input circuit 21 as the intermediate circuit 22, based on a signal generation circuit corresponding to the signal generation circuit 920_A in Fig. 4. Therefore, the signal generation circuit 20 that can reliably turn on the transistor M3 can be easily realized, and the number of additional components required for this purpose can be reduced.
[0058] <<Second Example>> A second embodiment will now be described. Fig. 8 shows a circuit diagram of an internal power supply circuit 60 that can be included in a functional circuit 30H. The internal power supply circuit 60 includes transistors M4 and M5 and a clamp diode D4. The transistor M4 is a P-channel MOSFET, and the transistor M5 is an N-channel MOSFET. The transistors M4 and M5 are formed as high-voltage transistors having the same withstand voltage as the transistor M3 (the rectangular frames surrounding the transistors M4 and M5 in Fig. 8 indicate that the transistors M4 and M5 are high-voltage transistors; the same applies to Fig. 9 described below).
[0059] The gate of the transistor M4 is connected to the node ND3 in Fig. 6 and receives the signal PD_HV generated at the node ND3. The source of the transistor M4 is connected to the node to which the power supply voltage VCC is applied. The drain of the transistor M4 is connected to the node ND4. The anode of the clamp diode D4 is connected to ground and the cathode is connected to the node ND4. The gate of the transistor M5 is connected to the node ND4 and receives the signal generated at the node ND4. The drain of the transistor M5 is connected to the node to which the power supply voltage VCC is applied and the source of the transistor M5 is connected to the node ND5.
[0060] The voltage at the node ND5 is referred to as the internal power supply voltage Vreg1. The internal power supply circuit 60 can generate the internal power supply voltage Vreg1 lower than the power supply voltage VCC based on the power supply voltage VCC. However, the internal power supply circuit 60 executes or does not execute the operation of generating the internal power supply voltage Vreg1 according to the signal PD_HV. When the signal PD_HV is at a low level, the internal power supply circuit 60 performs the operation of generating the internal power supply voltage Vreg1, and at this time, the voltage of the node ND5 becomes, for example, about 3V. When the signal PD_HV is at a high level, the internal power supply circuit 60 does not perform the operation of generating the internal power supply voltage Vreg1, and at this time, the voltage of the node ND5 becomes 0V (however, a transient state is ignored). The operation of generating the internal power supply voltage Vreg1 is included in the functional operation F_H in the functional circuit 30H of FIG. 1. A transistor (not shown) may be provided in the internal power supply voltage 60, which is an N-channel MOSFET having a drain connected to node ND5, a source connected to ground, and a gate receiving signal PD_LV, and which turns on during the high-level period of signal PD_LV to set the voltage of node ND5 to 0 V.
[0061] The node ND5 is connected to a load 70. The load 70 is a load within the semiconductor device 10. The load 70 is any load that operates based on the internal power supply voltage Vreg1 when the internal power supply voltage Vreg1 is generated. The load 70 is provided with an LDO (Low Dropout) regulator 71. When the internal power supply voltage Vreg1 is generated, the LDO regulator 71 generates an internal power supply voltage Vreg2 that is a lower voltage than the internal power supply voltage Vreg1 and has high accuracy based on the internal power supply voltage Vreg1. Any circuit that operates based on the internal power supply voltage Vreg2 may be provided in the load 70. A part of the load 70 may be a component of the functional circuit 30H, and another part of the load 70 may be a component of the functional circuit 30L.
[0062] The operation of the internal power supply circuit 60 will be described with reference to Fig. 9. Fig. 9 is a diagram in which the level of each signal and the state of each transistor of the internal power supply circuit 60 are added to Fig. 8. In Fig. 9, "H" written in parentheses indicates that the corresponding signal is at a high level, and "L" written in parentheses indicates that the corresponding signal is at a low level. In Fig. 9, "ON" written in parentheses indicates that the corresponding transistor is in an on state, and "OFF" written in parentheses indicates that the corresponding transistor is in an off state.
[0063] The clamp diode D4 is a Zener diode. The Zener voltage of the clamp diode D4 is smaller than the power supply voltage VCC, for example, 5.5 V. When the signal PD_HV has a high level, the transistor M4 is in an off state, and when the signal PD_HV has a low level, the transistor M4 is in an on state.
[0064] When the transistor M4 is off, the signal at the node ND4 has a low level. The low level of the signal at the node ND4 has a ground level. In order to reliably and quickly set the signal at the node ND4 to 0 V when the transistor M4 is off, a pull-down resistor (not shown) may be provided in parallel with the diode D4.
[0065] When the transistor M4 is in an on state, the signal at the node ND4 has a high level. The clamp diode D4 clamps the high level of the signal at the node ND4 to a predetermined clamp voltage V CLMP4 Set the clamp voltage V CLMP4 is equal to the Zener voltage of the clamp diode D4 (for example, 5.5V). That is, during the on-period of the transistor M4, a current flows from the node to which the power supply voltage VCC is applied through the transistor M4 and the clamp diode D4, so that the signal at the node ND4 has the Zener voltage of the clamp diode D4. In this way, the signal at the node ND4 has a Zener voltage of 0V or the clamp voltage V CLMP4 has.
[0066] When the signal at the node ND4 is at a low level, the transistor M5 is in an off state. During the off period of the transistor M5, the operation of generating the internal power supply voltage Vreg1 is not performed, and the voltage at the node ND5 becomes 0V.
[0067] When the signal at the node ND4 has a high level, the transistor M5 is in an on state. When the signal at the node ND4 has a high level, a voltage that is lower than the voltage at the node ND4 by the gate threshold voltage of the transistor M5 is generated at the node ND5 as the internal power supply voltage Vreg1. Therefore, for example, the clamp voltage V CLMP4 If the gate threshold voltage of the transistor M5 is 5.5V and the gate threshold voltage of the transistor M5 is 2.5V, when the signal at the node ND4 has a high level, an internal power supply voltage Vreg1 of 3.0V is generated at the node ND5. CLMP4 is greater than the gate threshold voltage of the transistor M5. The clamp voltage V CLMP4 is designed.
[0068] <<Third Example>> A third embodiment will now be described. Fig. 10 shows the configuration of an amplifier device AMP according to the third embodiment. The amplifier device AMP is a class-D amplifier including a semiconductor device 10, a coil L1, and a capacitor C1. The semiconductor device 10 constituting the amplifier device AMP includes a signal input terminal A_IN and a signal output terminal A_OUT as a plurality of external terminals in addition to the above-mentioned power supply input terminal IN, ground terminal GND, and control terminal CNT.
[0069] The amplifier device AMP is incorporated in an audio device. The audio device may be an in-vehicle audio device mounted in a vehicle such as an automobile. In the audio device, an analog audio input signal Sin supplied from an arbitrary sound source is input to a signal input terminal A_IN.
[0070] The semiconductor device 10 according to the third embodiment includes the signal generating circuit 20 described above, as well as a functional circuit 100 and transistors MH and ML. The transistor MH is a high-side transistor configured with a P-channel MOSFET, and the transistor ML is a low-side transistor configured with an N-channel MOSFET. The source of the transistor MH is connected to a power supply input terminal IN and receives a power supply voltage VCC. The drains of the transistors MH and ML are commonly connected to a signal output terminal A_OUT. The source of the transistor ML is connected to a ground terminal GND (and is therefore connected to ground).
[0071] The signal generating circuit 20 supplies signals PD_LV and PD_HV to the functional circuit 100. The functional circuit 100 is an integration of the functional circuits 30L and 30H of FIG. 1, and among the functional circuit 100, the circuit forming the functional circuit 30L operates when the signal PD_LV has an assert level, and the circuit forming the functional circuit 30H operates when the signal PD_HV has an assert level. The third embodiment can be implemented in combination with the second embodiment, and although not particularly shown, the internal power supply circuit 60 shown in FIG. 8 is also provided in the functional circuit 100. It may be understood that the modulation circuit 110 and the drive circuit 120 are included in the components of the load 70 shown in FIG. 8.
[0072] The functional circuit 100 includes a modulation circuit 110 and a drive circuit 120. The modulation circuit 110 and the drive circuit 120 operate only when the signals PD_LV and PD_HV have asserted levels. The modulation circuit 110 and the drive circuit 120 may be circuits that are driven based on an internal power supply voltage Vreg2. Hereinafter, the operations of the modulation circuit 110 and the drive circuit 120 will be described assuming that the signals PD_LV and PD_HV have asserted levels.
[0073] The modulation circuit 110 is connected to a signal input terminal A_IN and receives an analog audio input signal Sin through the signal input terminal A_IN. The modulation circuit 110 generates a pulse-width modulated signal Spwm by pulse-width modulating the analog audio input signal Sin. The signal Spwm is a rectangular wave signal having a predetermined frequency and alternately has a high level and a low level. The length of the period during which the signal Spwm has a high level is determined according to the signal value of the audio input signal Sin. The high level of the signal Spwm has the potential of the internal power supply voltage Vreg2, and the low level of the signal Spwm has the ground potential.
[0074] The drive circuit 120 is connected to the gates of the transistors MH and ML, and drives the gates of the transistors MH and ML in response to the signal Spwm to alternately turn the transistors MH and ML on and off. The drive circuit 120 controls the gate potentials of the transistors MH and ML so that the transistor MH is on and the transistor ML is off during a high-level period of the signal Spwm, and so that the transistor MH is off and the transistor ML is on during a low-level period of the signal Spwm.
[0075] As a result, a square wave signal Sout1 having a waveform similar to that of the signal Spwm appears at the signal output terminal A_OUT. The high level of the square wave signal Sout1 has the potential of the power supply voltage VCC, and the low level of the square wave signal Sout1 has the ground potential (although there is a slight error). A first end of the coil L1 is connected to the signal output terminal A_OUT. A second end of the coil L1 and a first end of the capacitor C1 are connected to the output node OUT. A second end of the capacitor C1 is connected to the ground. The signal at the output node OUT is an analog audio output signal Sout2. The audio output signal Sout2 corresponds to an amplified signal of the audio input signal Sin. The coil L1 and the capacitor C1 form a rectifying and smoothing circuit that rectifies and smoothes the square wave signal Sout1, and generates the audio output signal Sout2 by rectifying and smoothing the square wave signal Sout1. The audio output signal Sout2 is supplied to a speaker (not shown) to be reproduced and output as a sound wave.
[0076] <<Fourth Example>> A fourth embodiment will be described. In the fourth embodiment, modified techniques or supplementary matters to the above items will be described.
[0077] In each of the above-mentioned embodiments, the control signal Scnt corresponds to a power-down control signal, but the control signal Scnt may be any control signal for controlling the operation of the semiconductor device 10. For example, the control signal Scnt may be a signal for specifying ON / OFF of the mute function. That is, in the semiconductor device 10 shown in the third embodiment, when the control signal Scnt has a high level, a square wave signal Sout1 corresponding to the audio input signal Sin is generated as shown in the third embodiment, while when the control signal Scnt has a low level, the mute function may be turned on and the transistors MH and ML may be fixed to OFF regardless of the audio input signal Sin. At this time, the third embodiment differs from the third embodiment in that the internal power supply voltages Vreg1 and Vreg2 are generated based on the power supply voltage VCC even when the mute function is turned on. When the transistors MH and ML are fixed to OFF, no signal waveform similar to the audio input signal Sin is generated at the output node OUT, and no sound waves are generated from the speaker.
[0078] Although the third embodiment has been described as an example of constructing a class-D amplifier using the semiconductor device 10, the scope of application of the semiconductor device 10 is not limited to class-D amplifiers. For example, the semiconductor device 10 may be a power supply control device that controls the operation of a DC / DC converter, a motor driver device that drives and controls a motor, or an LED driver device that drives and controls an LED (light-emitting diode). The functional circuits 30L and 30H are designed according to the functions that the semiconductor device 10 should realize.
[0079] In the above description, it is assumed that the semiconductor device 10 is mounted on a vehicle such as an automobile, but it is not essential that the semiconductor device 10 is mounted on a vehicle. For example, the semiconductor device 10 may be mounted on a home appliance, a portable electronic device, or a personal computer.
[0080] For any signal or voltage, the relationship between the high level and the low level may be reversed without departing from the spirit of the above, so that, for example, the assert level may correspond to the high level and the negate level may correspond to the low level.
[0081] The channel types of FETs (field effect transistors) shown in each embodiment are merely examples, and the channel type of any FET may be changed between P-channel and N-channel without departing from the spirit of the above.
[0082] Any of the transistors described above may be any type of transistor, provided that no disadvantage occurs. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage occurs. Any of the transistors has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.
[0083] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and can be changed to various numerical values as a matter of course.
[0084] <<Additional Notes>> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.
[0085] A signal generating circuit (20) according to one aspect of the present disclosure includes an input circuit (21) having a first FET (M1) that receives an input control signal (Scnt) at its gate and configured to generate a first signal (PD_LV) corresponding to a state of the first FET, an intermediate circuit (22) having a second FET (M2) that receives the first signal at its gate and configured to generate a second signal (MID) corresponding to a state of the second FET, and an output circuit (23) having a third FET (M3) that receives the second signal at its gate and configured to generate a third signal (PD_HV) corresponding to a state of the third FET, wherein the input control signal, the first signal, the second signal, and the third signal have a low level or a high level, and the input circuit is configured to output a first signal (PD_LV) corresponding to a state of the first FET in parallel with the first FET. the intermediate circuit has a first clamp diode (D1) connected in series with the second FET and configured to set the high level of the first signal to a predetermined first clamp voltage, the intermediate circuit has a second clamp diode (D2) connected in parallel with the second FET and configured to set the high level of the second signal to a predetermined second clamp voltage, and the output circuit has an output resistor (R3) provided between an application node of a power supply voltage (VCC) and an output node (ND3) at which the third signal is generated and connected in series with the third FET, and a third clamp diode (D3) connected in parallel with the output resistor and configured to set the low level of the third signal to a voltage lower than the power supply voltage by a predetermined third clamp voltage (first configuration).
[0086] This makes it possible to generate multiple systems of signals with different reference levels according to the input control signal, and to realize such generation with a simple configuration. One of the multiple systems of signals is a first signal, and the first signal can be generated based on the ground according to the input control signal. The other of the multiple systems of signals is a third signal, and the third signal can be generated based on the power supply voltage according to the input control signal.
[0087] In the signal generating circuit of the first configuration described above, the input circuit may have a first pull-up resistor (R1) arranged in series between the node to which the power supply voltage is applied and the first FET, and generate the first signal at a first connection node (ND1) between the first FET and the first pull-up resistor, and the intermediate circuit may have a second pull-up resistor (R2) arranged in series between the node to which the power supply voltage is applied and the second FET, and generate the second signal at a second connection node (ND2) between the second FET and the second pull-up resistor (second configuration).
[0088] In the signal generating circuit of the second configuration, in the input circuit, when the input control signal has a first level, the first FET is turned off to generate the first signal of a high level at the first connection node, and when the input control signal has a second level, the first FET is turned on to generate the first signal of a low level at the first connection node; in the intermediate circuit, when the first signal has a low level, the second FET is turned off to generate the second signal of a high level at the second connection node, and when the first signal has a high level, the second FET is turned on to generate the second signal of a low level at the second connection node; and in the output circuit, when the second signal has a low level, the third FET is turned off to generate the third signal of a high level at the output node, and when the second signal has a high level, the third FET is turned on to generate the third signal of a low level at the output node (third configuration).
[0089] In the signal generating circuit according to any one of the first to third configurations, the second clamp voltage may be set higher than the input control signal at a high level (fourth configuration).
[0090] This allows the gate of the third FET to be driven with a voltage higher than the input control signal, making it possible to reliably turn on the third FET even when the gate threshold voltage of the third FET is high.
[0091] In the signal generating circuit according to any one of the first to fourth configurations, a configuration (fifth configuration) may be employed in which a current limiting resistor (R4) is provided in series between the third FET and the output node.
[0092] In the signal generating circuit according to any one of the first to fifth configurations, the first FET, the second FET, and the third FET may each be of an N-channel type (sixth configuration).
[0093] A semiconductor device according to one aspect of the present disclosure has a configuration (seventh configuration) including a signal generating circuit (20) according to any of the first to sixth configurations described above, a first functional circuit (30L) configured to be controlled to be activated or deactivated in response to the level of the first signal, and a second functional circuit (30H) configured to be controlled to be activated or deactivated in response to the level of the third signal.
[0094] This makes it possible to control the operation and non-operation of the first function circuit and the second function circuit in response to the input control signal.
[0095] In the semiconductor device of the seventh configuration above, the second functional circuit may include an internal power supply circuit (60) configured to generate an internal power supply voltage (Vreg1) based on the power supply voltage, and the internal power supply circuit may be configured to perform or not perform the generation operation of the internal power supply voltage depending on the level of the third signal (eighth configuration).
[0096] In the semiconductor device according to the eighth configuration, the internal power supply circuit may include a fourth FET (M4) which is a P-channel FET having a gate which receives the third signal, a source which receives the power supply voltage, and a drain which generates a fourth signal, a fourth clamp diode (D4) which is connected to the drain of the fourth FET and is configured to set a high level of the fourth signal to a predetermined fourth clamp voltage, and a fifth FET (M5) which is an N-channel FET which is provided between a node to which the power supply voltage is applied and a node to which the internal power supply voltage is applied and receives the fourth signal at its gate, and when the third signal has a low level, the fourth FET is turned on to generate the fourth signal at a high level, and the fifth FET is turned on in response to the fourth signal at a high level, thereby generating the internal power supply voltage (ninth configuration). [Explanation of symbols]
[0097] 10 Semiconductor device 20 Signal generation circuit 30L, 30H Functional circuit VCC Power supply voltage IN Power input terminal CNT control terminal GND Ground terminal Scnt control signal (external control signal) PD_LV, PD_HV signals (internal control signals) RNG1, RNG2 voltage range VH, VL voltage 920_A, 920_B signal generation circuit 921, 924 Transistors 922, 925 Clamp Diodes 923, 926, 927 Resistance 928 Level Shifter NDa, NDb nodes 21 Input circuit 22 Intermediate circuit 23 Output circuit M1~M5 Transistors D1~D4 Clamp diodes R1~R4 resistance ND1~ND5 nodes 60 Internal power circuit 70 Load 71 LDO Regulator Vreg1, Vreg2 internal power supply voltage AMP Amplifier device 100 Functional Circuit 110 Modulation circuit 120 Drive circuit A_IN Signal input terminal A_OUT Signal output terminal Sin Audio input signal SPMW signal (Pulse Width Modulation signal) MH, ML transistors Sout1 Square wave signal Sout2 Audio output signal L1 coil C1 Capacitor Sout output node
Claims
1. an input circuit having a first FET having a gate receiving an input control signal, the input circuit being configured to generate a first signal in response to a state of the first FET; an intermediate circuit having a second FET receiving the first signal at its gate and configured to generate a second signal responsive to a state of the second FET; an output circuit having a third FET that receives the second signal at a gate thereof and configured to generate a third signal according to a state of the third FET; the input control signal, the first signal, the second signal, and the third signal have a low level or a high level; the input circuit includes a first clamp diode connected in parallel with the first FET and configured to set a high level of the first signal to a predetermined first clamp voltage; the intermediate circuit includes a second clamp diode connected in parallel with the second FET and configured to set a high level of the second signal to a predetermined second clamp voltage; The output circuit includes an output resistor that is provided between a node to which a power supply voltage is applied and an output node to which the third signal is generated and that is connected in series to the third FET, and a third clamp diode that is connected in parallel to the output resistor and that is configured to set a low level of the third signal to a voltage that is lower than the power supply voltage by a predetermined third clamp voltage. , signal generation circuit.
2. the input circuit has a first pull-up resistor connected in series between an application node of the power supply voltage and the first FET, and generates the first signal at a first connection node between the first FET and the first pull-up resistor; The intermediate circuit has a second pull-up resistor connected in series between the node to which the power supply voltage is applied and the second FET, and generates the second signal at a second connection node between the second FET and the second pull-up resistor.
2. The signal generating circuit according to claim 1.
3. in the input circuit, when the input control signal has a first level, the first FET is turned off to generate the first signal of a high level at the first connection node, and when the input control signal has a second level, the first FET is turned on to generate the first signal of a low level at the first connection node; in the intermediate circuit, when the first signal has a low level, the second FET is turned off to generate the second signal of a high level at the second connection node, and when the first signal has a high level, the second FET is turned on to generate the second signal of a low level at the second connection node; In the output circuit, when the second signal has a low level, the third FET is turned off to generate the third signal of a high level at the output node, and when the second signal has a high level, the third FET is turned on to generate the third signal of a low level at the output node.
3. The signal generating circuit according to claim 2.
4. The second clamp voltage is set higher than the high level of the input control signal.
2. The signal generating circuit according to claim 1.
5. A current limiting resistor is provided in series between the third FET and the output node.
2. The signal generating circuit according to claim 1.
6. The first FET, the second FET, and the third FET each have an N-channel type.
2. The signal generating circuit according to claim 1.
7. A signal generating circuit according to any one of claims 1 to 6; a first function circuit configured to be controlled to be activated or deactivated in response to a level of the first signal; a second function circuit configured to be controlled to be activated or deactivated in response to a level of the third signal; , semiconductor device.
8. the second functional circuit includes an internal power supply circuit configured to generate an internal power supply voltage based on the power supply voltage; The internal power supply circuit performs or does not perform an operation of generating the internal power supply voltage in response to a level of the third signal. The semiconductor device according to claim 7 .
9. the internal power supply circuit comprises: a fourth FET which is a P-channel FET having a gate which receives the third signal, a source which receives the power supply voltage, and a drain which generates a fourth signal; a fourth clamp diode which is connected to the drain of the fourth FET and which is configured to set a high level of the fourth signal to a predetermined fourth clamp voltage; and a fifth FET which is an N-channel FET which is provided between an application node of the power supply voltage and an application node of the internal power supply voltage, and which receives the fourth signal at its gate; When the third signal has a low level, the fourth FET is turned on to generate the fourth signal at a high level, and in response to the fourth signal at a high level, the fifth FET is turned on to generate the internal power supply voltage. The semiconductor device according to claim 8 .
Citation Information
Patent Citations
Switching power supply device and semiconductor device
JP2020108189A