Display device and manufacturing method of the same

Abstract

To suppress deterioration of reliability.SOLUTION: According to an embodiment, a manufacturing method of a display device, includes steps of: forming a lower electrode; forming an inorganic insulation layer; sequentially forming a lower layer and an upper layer; forming a first resist to be patterned; performing an etching while using the first resist as a mask; sequentially removing the upper layer and the lower layer exposed from the first resist; forming a second resist exposing the inorganic insulation layer while covering the lower layer and the upper layer after the removing of the first resist; performing the etching while using the second resist as a mask; forming an opening overlapped to the lower electrode to the inorganic insulation layer; performing the etching of the lower layer after the removing of the second resist; forming a partition wall having a lower part positioned on the inorganic insulation layer and an upper part that is positioned to an upper side of the lower apart and is projected from a side surface of the lower part; performing a vapor deposition while using the partition wall as a mask; and forming a lamination film containing an organic layer and the upper electrode onto the lower electrode in the opening.SELECTED DRAWING: Figure 4H

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. This display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer that covers the lower electrode, and an upper electrode that covers the organic layer. In the process of manufacturing such display elements, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability and a manufacturing method thereof. [Means for solving the problem]

[0005] According to one embodiment, a method for manufacturing a display device includes the steps of: a lower electrode is formed on a substrate, an inorganic insulating layer is formed to cover the lower electrode, a lower layer and an upper layer are sequentially formed on the inorganic insulating layer, a patterned first resist is formed on the upper layer, etching is performed using the first resist as a mask, the upper layer and the lower layer exposed from the first resist are sequentially removed, after the first resist is removed, a second resist is formed to cover the lower layer and the upper layer and to expose the inorganic insulating layer, etching is performed using the second resist as a mask, an opening is formed in the inorganic insulating layer to overlap the lower electrode, after the second resist is removed, etching is performed on the lower layer, a partition wall is formed having a lower portion located on the inorganic insulating layer and an upper portion located on the lower portion and protruding from a side surface of the lower portion, deposition is performed using the partition wall as a mask, and a laminated film including an organic layer and an upper electrode is formed on the lower electrode in the opening.

[0006] According to one embodiment, a method for manufacturing a display device includes the steps of: a lower electrode is formed on a substrate, an inorganic insulating layer covering the lower electrode is formed, a lower layer and an upper layer are sequentially formed on the inorganic insulating layer, a patterned first resist is formed on the upper layer, etching is performed using the first resist as a mask, the upper layer, the lower layer, and the inorganic insulating layer exposed from the first resist are sequentially removed, an opening overlapping the lower electrode is formed in the inorganic insulating layer, after the first resist is removed, the lower layer is etched, a partition wall is formed having a lower portion located on the inorganic insulating layer and an upper portion located on the lower portion and protruding from a side surface of the lower portion, deposition is performed using the partition wall as a mask, and a laminated film including an organic layer and an upper electrode is formed on the lower electrode in the opening.

[0007] According to one embodiment, the display device comprises: The device comprises a substrate, a lower electrode disposed above the substrate, an inorganic insulating layer covering a peripheral portion of the lower electrode, a partition having a lower portion disposed on the inorganic insulating layer and an upper portion disposed on the lower portion, an organic layer disposed on the lower electrode and including an emitting layer, and an upper electrode disposed on the organic layer and in contact with the lower portion, wherein the lower portion has a first conductive layer covering an upper surface of the inorganic insulating layer and a second conductive layer disposed on the first conductive layer, and the first conductive layer and the upper portion protrude from a side surface of the second conductive layer. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing an example of the configuration of a display device DSP. [Diagram 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG. [Figure 4A] FIG. 4A is a diagram for explaining a manufacturing method of the display device. [Figure 4B] FIG. 4B is a diagram for explaining a manufacturing method of the display device. [Figure 4C] FIG. 4C is a diagram for explaining a manufacturing method of the display device. [Figure 4D] FIG. 4D is a diagram for explaining a manufacturing method of the display device. [Figure 4E] FIG. 4E is a diagram for explaining a manufacturing method of the display device. [Figure 4F] FIG. 4F is a diagram for explaining a manufacturing method of the display device. [Figure 4G] FIG. 4G is a diagram for explaining a manufacturing method of the display device. [Figure 4H] FIG. 4H is a diagram for explaining a manufacturing method of the display device. [Figure 4I] FIG. 4I is a diagram for explaining a manufacturing method of the display device. [Diagram 5] FIG. 5 is a diagram for explaining a manufacturing method of the display device. [Figure 6] FIG. 6 is a diagram for explaining a manufacturing method of the display device. [Figure 7] FIG. 7 is a diagram for explaining a manufacturing method of the display device. [Figure 8] FIG. 8 is a diagram for explaining a manufacturing method of the display device. [Figure 9] FIG. 9 is a diagram for explaining a manufacturing method of the display device. [Figure 10] FIG. 10 is a diagram for explaining a manufacturing method of the display device. [Figure 11A] FIG. 11A is a view for explaining another manufacturing method. [Figure 11B] FIG. 11B is a view for explaining another manufacturing method. [Figure 12A] FIG. 12A is a view for explaining another manufacturing method. [Figure 12B] FIG. 12B is a view for explaining another manufacturing method. [Figure 12C] FIG. 12C is a view for explaining another manufacturing method. [Figure 13] FIG. 13 is a cross-sectional view showing display elements DE1, DE2, and DE3 formed through the manufacturing method shown in FIGS. 12A to 12C. [Figure 14] FIG. 14 is an enlarged cross-sectional view of the display element DE1 and the display element DE2 shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiment will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0010] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view.

[0011] The display device according to this embodiment is an organic electroluminescence display device having an organic light emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] FIG. 1 is a plan view showing an example of the configuration of a display device DSP.

[0013] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 may be a glass substrate or a flexible resin substrate.

[0014] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0015] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixels PX include a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, the second color, and the third color are different from each other. The pixel PX may include a subpixel SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0016] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0018] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] The display element DE is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0020] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along a first direction X. Each of the terminals TE extends in a second direction Y, but this is not limited thereto. For example, some of the plurality of terminals TE may extend in an oblique direction. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit board or an IC chip.

[0021] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3.

[0022] In the illustrated example, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0023] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0024] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0025] An insulating layer 5 and partition walls 6 are disposed in the display area DA. The insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0026] The partition wall 6 overlaps with the insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the subpixels SP1, SP2, and SP3, similar to the insulating layer 5. The partition wall 6 is conductive and is electrically connected to the terminal TE of the common potential among the multiple terminals TE shown in FIG. 1.

[0027] The sub-pixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0028] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the aperture AP1. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 overlap with the insulating layer 5 in a planar view.

[0029] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the lower electrode LE2, the organic layer OR2, and the upper electrode UE2 overlap with the insulating layer 5 in a planar view.

[0030] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the aperture AP3. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 overlap with the insulating layer 5 in a planar view.

[0031] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dashed lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes illustrated in the drawings do not necessarily reflect the exact shapes.

[0032] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or a common electrode, and are in contact with the partition walls 6.

[0033] In the illustrated example, the areas of the openings AP1, AP2, and AP3 are different from one another. The area of ​​the openings AP1 is larger than the area of ​​the openings AP2, and the area of ​​the openings AP2 is larger than the area of ​​the openings AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0034] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0035] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Fig. 1, and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens unevenness caused by the circuit layer 11.

[0036] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and are spaced apart from each other. The insulating layer 5 is an inorganic insulating layer and is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. An opening AP1 in the insulating layer 5 overlaps the lower electrode LE1, an opening AP2 overlaps the lower electrode LE2, and an opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3 through contact holes provided in the insulating layer 12. The contact holes in the insulating layer 12 are omitted in FIG. 3.

[0037] The partition 6 includes a conductive lower portion 61 disposed on the insulating layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. Both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition 6 is called an overhang shape.

[0038] In the illustrated example, the lower portion 61 has a first conductive layer 63 disposed on the insulating layer 5 and a second conductive layer 64 disposed on the first conductive layer 63. For example, the first conductive layer 63 is formed to be thinner than the second conductive layer 64. In addition, in the illustrated example, both ends of the first conductive layer 63 protrude from the side surfaces of the second conductive layer 64. The upper portion 62 has a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. Both end portions of the first thin film 65 and the second thin film 66 protrude from the side surfaces of the second conductive layer 64.

[0039] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has a peripheral portion located on the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower portion 61.

[0040] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has a peripheral portion located on the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower portion 61.

[0041] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has a peripheral portion located on the insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower portion 61.

[0042] In the illustrated example, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. The cap layers CP1, CP2, and CP3 may be omitted.

[0043] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0044] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3.

[0045] In the illustrated example, parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are located on the partition wall 6 around the subpixel SP1. These parts are separated from parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located in the aperture AP1 (parts constituting the display element DE1). Similarly, portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 are located on the partition 6 surrounding the subpixel SP2, and these portions are spaced apart from portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 that are located in the opening AP2 (portions that constitute the display element DE2). Similarly, portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 are located on the partition 6 surrounding the subpixel SP3, and these portions are spaced apart from portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 that are located in the opening AP3 (portions that constitute the display element DE3).

[0046] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 is referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 is referred to as a laminate film FL3.

[0047] Ends of the sealing layers SE1, SE2, and SE3 and ends of the stacked films FL1, FL2, and FL3 are located on the partition wall 6. In the illustrated example, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE3 on the partition wall 6.

[0048] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0049] The insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0050] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The first conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0051] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may be formed of an insulating material. The first thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The second thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0052] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent layer made of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer made of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers. The lower transparent layer functions as an adhesive layer that adheres to the insulating layer 12.

[0053] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in a blue wavelength range, the emitting layer EM2 is formed of a material that emits light in a green wavelength range, and the emitting layer EM3 is formed of a material that emits light in a red wavelength range. In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers, such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0054] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0055] The cap layers CP1, CP2, and CP3 are multilayer structures made up of a plurality of thin films, all of which are transparent and have different refractive indices.

[0056] The illustrated circuit layer 11, insulating layer 12, insulating layer 5, resin layer 13, resin layer 15, and sealing layer 14 are disposed across the display area DA and the peripheral area SA.

[0057] Next, a method for manufacturing the display device DSP will be described. Note that in each drawing for explaining the manufacturing method, illustration of the part below the insulating layer 12 is omitted.

[0058] First, on the substrate 10, the circuit layer 11 and the insulating layer 12 are formed across the display area DA and the peripheral area SA, and then, as shown in FIG. 4A, the lower electrode LE1 of the subpixel SP1, the lower electrode LE2 of the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 are formed on the insulating layer 12. The process of forming the lower electrodes LE1, LE2, and LE3 includes, for example, the following processes. That is, the process of forming the lower electrodes includes a process of forming an adhesion layer LEA on the insulating layer 12, a process of forming a reflective layer LEB on the adhesion layer LEA, a process of forming a transparent layer LEC on the reflective layer LEB, and a process of patterning the adhesion layer LEA, the reflective layer LEB, and the transparent layer LEC. As a result, a multilayer body of the adhesion layer LEA, the reflective layer LEB, and the transparent layer LEC is formed in an island shape. These multilayer bodies correspond to the lower electrodes LE1, LE2, and LE3, respectively. The adhesion layer LEA is formed of, for example, ITO. The reflective layer LEB is formed of, for example, silver. The transparent layer LEC is made of, for example, ITO.

[0059] Subsequently, as shown in FIG. 4B, an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride is deposited to form an insulating layer 5 that covers the insulating layer 12 and the lower electrodes LE1, LE2, and LE3.

[0060] Next, as shown in FIG. 4C, a lower layer for forming the lower portion 61 of the partition wall 6 is formed on the insulating layer 5, and then an upper layer for forming the upper portion 62 of the partition wall 6 is formed on the lower layer. The step of forming the lower layer includes a step of forming a first conductive layer 63 made of a titanium-based material on the insulating layer 5, and a step of forming a second conductive layer 64 made of an aluminum-based material on the first conductive layer 63. In other words, the lower layer is a multilayer body of the first conductive layer 63 and the second conductive layer 64. The step of forming the upper layer includes a step of forming a first thin film 65 made of a titanium-based material on the second conductive layer 64, and a step of forming a second thin film 66 made of ITO on the first thin film 65. In other words, the upper layer is a multilayer body of the first thin film 65 and the second thin film 66.

[0061] Subsequently, as shown in FIG. 4D, a first resist R1 patterned into a predetermined shape is formed on the second thin film 66 of the upper layer.

[0062] 4E, etching is performed using the first resist R1 as a mask, and the upper layer exposed from the first resist R1 is removed, followed by the lower layer. Specifically, the second thin film 66 is first removed by wet etching. Then, the first thin film 65 is removed by dry etching, followed by the second conductive layer 64, and then the first conductive layer 63, exposing the insulating layer 5 directly above the lower electrodes LE1, LE2, and LE3.

[0063] Next, as shown in FIG. 4F, the first resist R1 is removed.

[0064] 4G, a second resist R2 is formed to cover the first conductive layer 63 and the second conductive layer 64, which are the lower layers, and the first thin film 65 and the second thin film 66, which are the upper layers. The second resist R2 covers the upper surface of the second thin film 66, and also covers the side surfaces of the lower layer and the upper layer, and is in contact with the insulating layer 5 around the first conductive layer 63. The second resist R2 exposes the insulating layer 5 directly above the lower electrodes LE1, LE2, and LE3.

[0065] 4H, etching is performed using the second resist R2 as a mask. Specifically, the insulating layer 5 exposed from the second resist R2 is removed by dry etching to form openings AP1, AP2, and AP3. The opening AP1 overlaps the lower electrode LE1 of the subpixel SP1, the opening AP2 overlaps the lower electrode LE2 of the subpixel SP2, and the opening AP3 overlaps the lower electrode LE3 of the subpixel SP3.

[0066] Then, as shown in FIG. 4I, the second resist R2 is removed.

[0067] 5, the second conductive layer 64 of the lower layer is etched. Specifically, the second conductive layer 64 is recessed from the ends of the first conductive layer 63 and the upper layer by wet etching. As a result, the partition wall 6 is formed, which has a lower portion 61 located on the insulating layer 5 and an upper portion 62 located on the lower portion 61 and protruding from the side surface of the second conductive layer 64.

[0068] Next, the display element DE1 is formed.

[0069] First, as shown in FIG. 6, a laminated film FL1 including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The process of forming the laminated film FL1 includes a process of forming an organic layer OR1 that contacts the lower electrode LE1 at the opening AP1, a process of forming an upper electrode UE1 that covers the organic layer OR1 and contacts the lower portion 61 of the partition wall 6, and a process of forming a cap layer CP1 located on the upper electrode UE1. The organic layer OR1 includes a hole injection layer, a hole transport layer, an electron blocking layer, an emitting layer EM1, a hole blocking layer, an electron transport layer, an electron injection layer, and the like. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by deposition using the partition wall 6 as a mask. The laminated film FL1 is divided into a plurality of parts by the overhanging partition wall 6. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are continuously formed while maintaining a vacuum environment.

[0070] Then, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminated film FL1. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each of the divided portions of the laminated film FL1 and the partition walls 6.

[0071] 7, a third resist R3 patterned into a predetermined shape is formed on the sealing layer SE1. The third resist R3 overlaps the subpixel SP1 and a part of the partition wall 6 around it.

[0072] 8, etching is performed using the third resist R3 as a mask to remove the sealing layer SE1 and stacked film FL1 exposed from the third resist R3. In this etching, after removing the sealing layer SE1 exposed from the third resist R3, the cap layer CP1 exposed from the sealing layer SE1 is removed, and further, after removing the upper electrode UE1 exposed from the cap layer CP1, the organic layer OR1 exposed from the upper electrode UE1 is removed. As a result, the lower electrode LE2 of the subpixel SP2 and the lower electrode LE3 of the subpixel SP3 are exposed. Thereafter, the third resist R3 is removed, thereby forming a display element DE1 in the subpixel SP1.

[0073] Next, as shown in FIG. 9, a display element DE2 is formed. The procedure for forming the display element DE2 is the same as that for forming the display element DE1. That is, an organic layer OR2 including an emitting layer EM2, an upper electrode UE2, and a cap layer CP2 are formed in this order on the lower electrode LE2 to form a laminated film FL2. Then, a sealing layer SE2 is formed on the laminated film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. As a result, a display element DE2 is formed in the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 is exposed.

[0074] Next, as shown in FIG. 10, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as that for forming the display element DE1. That is, an organic layer OR3 including an emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are formed in this order on the lower electrode LE3 to form a laminated film FL3. Then, a sealing layer SE3 is formed on the laminated film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. As a result, a display element DE3 is formed in the subpixel SP3.

[0075] Thereafter, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in Fig. 3 etc. are formed in this order, thereby completing the display device DSP.

[0076] In the above manufacturing process, it is assumed that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed, but the order of formation of display elements DE1, DE2, and DE3 is not limited to this example.

[0077] Here, as Comparative Example 1, a case where openings AP1, AP2, and AP3 are formed in the insulating layer 5 before the partition wall 6 is formed will be described. In such Comparative Example 1, a first conductive layer is formed by sputtering on the lower electrodes LE1, LE2, and LE3 exposed from the openings AP1, AP2, and AP3, respectively. Furthermore, the first conductive layer is dry-etched when forming the partition wall 6. Such sputtering and dry etching may damage the transparent layers on the surfaces of the lower electrodes LE1, LE2, and LE3.

[0078] On the other hand, according to the manufacturing method of this embodiment, the sputtering and dry etching of the first conductive layer are performed before forming the openings AP1, AP2, and AP3. This suppresses damage to the lower electrodes LE1, LE2, and LE3. This makes it possible to achieve the desired display performance in each of the display elements DE1, DE2, and DE3, and suppresses deterioration in reliability.

[0079] As Comparative Example 2, a case in which the partition wall 6 is formed, then covered with a resist, and the openings AP1, AP2, and AP3 are formed in the insulating layer 5 will be described. In such Comparative Example 2, when the overhanging partition 6 is covered with resist, cavities in the resist tend to occur below the upper portion 62 that serves as an overhang. Such cavities may expand and burst when the resist is dried under reduced pressure. In this case, a part of the necessary resist may be missing, causing a pattern defect, and it may become difficult to form the desired openings AP1, AP2, and AP3 in the insulating layer 5. Furthermore, if the application speed of the resist is reduced in order to suppress the occurrence of cavities, this may lead to a decrease in productivity.

[0080] On the other hand, according to the manufacturing method of this embodiment, as described with reference to Fig. 4G, before forming the overhanging partition wall 6, the multilayer body of the first conductive layer 63, the second conductive layer 64, the first thin film 65, and the second thin film 66 is covered with the second resist R2. This prevents the generation of cavities in the second resist R2 without reducing the resist application speed. This allows the desired openings AP1, AP2, and AP3 to be formed in the insulating layer 5 without reducing productivity.

[0081] Next, another method for manufacturing the display device DSP will be described.

[0082] First, the lower electrodes LE1, LE2, and LE3 are formed in the same manner as in the above manufacturing method (FIG. 4A). Then, the insulating layer 5 is formed (FIG. 4B). Then, the first conductive layer 63, the second conductive layer 64, the first thin film 65, and the second thin film 66 are formed (FIG. 4C). Then, the first resist R1 is formed (FIG. 4D). Then, the first conductive layer 63, the second conductive layer 64, the first thin film 65, and the second thin film 66 are patterned (FIG. 4E). Then, the first resist R1 is removed (FIG. 4F). Then, the second resist R2 is formed (FIG. 4G). Then, the openings AP1, AP2, and AP3 are formed in the insulating layer 5 (FIG. 4H). Then, the second resist R2 is removed (FIG. 4I).

[0083] 11A, a protective film PR is formed to cover the openings AP1, AP2, and AP3. That is, the protective film PR covers the lower electrodes LE1, LE2, and LE3. The protective film PR may be formed of a general resist material or a resin such as polyimide.

[0084] 11B, the second conductive layer 64 of the lower layer is etched. Specifically, the second conductive layer 64 is recessed from the ends of the first conductive layer 63 and the upper layer by wet etching. As a result, the partition wall 6 is formed, which has a lower portion 61 located on the insulating layer 5 and an upper portion 62 located on the lower portion 61 and protruding from the side surface of the second conductive layer 64. Thereafter, the protective film PR is removed.

[0085] Next, in the same manner as in the above-mentioned manufacturing method, a display element DE1 is formed (FIGS. 6 to 8), a display element DE2 is formed (FIG. 9), and a display element DE3 is formed (FIG. 10).

[0086] This manufacturing method also provides the same effects as the above manufacturing method. In addition, damage to the lower electrodes LE1, LE2, and LE3 caused by the etching solution used in wet etching the second conductive layer 64 can be suppressed. For example, if the transparent layer of the lower electrodes LE1, LE2, and LE3 has a defect, the defect may become a path for the etching solution to penetrate and corrode the silver reflective layer. Therefore, by covering the lower electrodes LE1, LE2, and LE3 with a protective film PR prior to wet etching the second conductive layer 64, even if the transparent layer has a defect, the penetration of the etching solution into the reflective layer can be suppressed, and the erosion of the reflective layer can be suppressed.

[0087] Next, another method for manufacturing the display device DSP will be described.

[0088] First, similarly to the above manufacturing method, the lower electrodes LE1, LE2, and LE3 are formed (FIG. 4A). Then, the insulating layer 5 is formed (FIG. 4B). Then, the first conductive layer 63, the second conductive layer 64, the first thin film 65, and the second thin film 66 are formed (FIG. 4C). Then, the first resist R1 is formed (FIG. 4D).

[0089] 12A, etching is performed using the first resist R1 as a mask to remove the upper layer exposed from the first resist R1, and then the lower layer is removed, and the insulating layer 5 is then removed. As a result, openings AP1, AP2, and AP3 are formed in the insulating layer 5. The opening AP1 overlaps the lower electrode LE1 of the subpixel SP1, the opening AP2 overlaps the lower electrode LE2 of the subpixel SP2, and the opening AP3 overlaps the lower electrode LE3 of the subpixel SP3. Specifically, first, the second thin film 66 is removed by wet etching. Then, the first thin film 65 is removed by dry etching, the second conductive layer 64 is removed, and further the first conductive layer 63 is removed, and then the insulating layer 5 is removed.

[0090] Next, as shown in FIG. 12B, the first resist R1 is removed.

[0091] 12C, the second conductive layer 64 of the lower layer is etched. Specifically, the second conductive layer 64 is recessed from the ends of the first conductive layer 63 and the upper layer by wet etching. As a result, the partition wall 6 is formed, which has a lower portion 61 located on the insulating layer 5 and an upper portion 62 located on the lower portion 61 and protruding from the side surface of the second conductive layer 64.

[0092] Next, in the same manner as in the above-mentioned manufacturing method, a display element DE1 is formed (FIGS. 6 to 8), a display element DE2 is formed (FIG. 9), and a display element DE3 is formed (FIG. 10). The display elements DE1, DE2, and DE3 formed through such steps are shown in FIG.

[0093] This manufacturing method also provides the same effects as the above manufacturing method. In addition, compared to the above manufacturing method, the second resist is not necessary, which makes it possible to reduce manufacturing costs and simplify the manufacturing process. In addition, it is no longer necessary to consider misalignment when forming the second resist. This makes it possible to reduce the width of the insulating layer 5 and the partition wall 6, or to enlarge the openings AP1, AP2, and AP3 (enlarge the light-emitting area).

[0094] In the manufacturing method described here, the lower electrodes LE1, LE2, and LE3 exposed from the openings AP1, AP2, and AP3, respectively, may be covered with a protective film PR as described with reference to Fig. 11A before etching the second conductive layer 64 shown in Fig. 12C. This makes it possible to suppress damage to the lower electrodes LE1, LE2, and LE3 caused by the etching solution used in wet etching the second conductive layer 64.

[0095] Fig. 14 is an enlarged cross-sectional view of the display element DE1 and the display element DE2 shown in Fig. 13. Note that in Fig. 14, the resin layer 13, the sealing layer 14, and the resin layer 15 below the insulating layer 12 are not shown.

[0096] The display element DE1 includes a lower electrode LE1 disposed on the insulating layer 12, an organic layer OR1 disposed on the lower electrode LE1 and including an emitting layer EM1, and an upper electrode UE1 disposed on the organic layer OR1 and in contact with the lower portion 61. Like the display element DE1, the display element DE2 also includes a lower electrode LE2, an organic layer OR2 including an emitting layer EM2, and an upper electrode UE2.

[0097] The lower electrodes LE1 and LE2 are multilayer bodies having an adhesive layer LEA made of, for example, ITO, a reflective layer LEB made of, for example, silver, and a transparent layer LEC made of, for example, ITO.

[0098] Each of the organic layers OR1 and OR2 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Among these functional layers, at least the hole injection layer HIL is separated from the first conductive layer 63. This suppresses undesired carrier leakage through the hole injection layer HIL.

[0099] The insulating layer 5 is disposed on the insulating layer 12 and covers the periphery of the lower electrodes LE1 and LE2. The insulating layer 5 is made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0100] The partition wall 6 has a lower portion 61 disposed on the insulating layer 5, and an upper portion 62 disposed on the lower portion 61. The lower portion 61 has a first conductive layer 63 covering the upper surface 5A of the insulating layer 5, and a second conductive layer 64 disposed on the first conductive layer. According to the above manufacturing method, the first conductive layer 63 and the insulating layer 5 are etched using the first resist R1 as a mask, so that the width of the upper surface 5A and the width of the first conductive layer 63 are substantially the same, and substantially the entire upper surface 5A is covered with the first conductive layer 63. The first conductive layer 63 is made of, for example, a titanium-based material. The second conductive layer 64 is made of, for example, an aluminum-based material.

[0101] The upper portion 62 has a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. The first conductive layer 63 and the upper portion 62 protrude from the side surface of the second conductive layer 64. The first thin film 65 is made of, for example, a titanium-based material. The second thin film 66 is made of, for example, an oxide conductive material.

[0102] The cap layer CP1 is disposed on the upper electrode UE1. The sealing layer SE1 covers the cap layer CP1 and the partition wall 6. The cap layer CP2 is disposed on the upper electrode UE2. The sealing layer SE2 covers the cap layer CP2 and the partition wall 6. The sealing layers SE1 and SE2 are formed of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0103] As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability and a manufacturing method thereof.

[0104] All display devices and manufacturing methods thereof that can be implemented by a person skilled in the art through appropriate design modifications based on the display device and manufacturing method thereof described above as embodiments of the present invention are within the scope of the present invention as long as they include the gist of the present invention.

[0105] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0106] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0107] DSP: Display device PNL: Display panel 10...Substrate 5...Insulating layer AP1, AP2, AP3...Openings 6...Bulkhead 61...Lower 62...Upper 63: First conductive layer 64: Second conductive layer 65: First thin film 66: Second thin film SP1, SP2, SP3...Subpixels DE1, DE2, DE3...Display element (organic EL element) LE1, LE2, LE3...lower electrode UE1, UE2, UE3...upper electrode OR1, OR2, OR3…Organic layer R1...First resist R2...Second resist R3...Third resist PR…Protective film

Claims

1. A lower electrode is formed on the substrate; forming an inorganic insulating layer covering the lower electrode; forming a lower layer and an upper layer in sequence on the inorganic insulating layer; forming a patterned first resist on the upper layer; performing etching using the first resist as a mask to sequentially remove the upper layer and the lower layer exposed from the first resist; After removing the first resist, a second resist is formed to cover the lower layer and the upper layer and to expose the inorganic insulating layer; performing etching using the second resist as a mask to form an opening in the inorganic insulating layer that overlaps the lower electrode; removing the second resist, and then etching the lower layer to form a partition wall having a lower portion located on the inorganic insulating layer and an upper portion located on the lower portion and protruding from a side surface of the lower portion; performing deposition using the partition as a mask to form a laminated film including an organic layer and an upper electrode on the lower electrode in the opening; A method for manufacturing a display device.

2. A lower electrode is formed on the substrate; forming an inorganic insulating layer covering the lower electrode; forming a lower layer and an upper layer in sequence on the inorganic insulating layer; forming a patterned first resist on the upper layer; performing etching using the first resist as a mask to sequentially remove the upper layer, the lower layer, and the inorganic insulating layer exposed from the first resist, and forming an opening in the inorganic insulating layer that overlaps the lower electrode; removing the first resist, and then etching the lower layer to form a partition wall having a lower portion located on the inorganic insulating layer and an upper portion located on the lower portion and protruding from a side surface of the lower portion; performing deposition using the partition as a mask to form a laminated film including an organic layer and an upper electrode on the lower electrode in the opening; A method for manufacturing a display device.

3. The step of forming the lower layer comprises: forming a first conductive layer on the inorganic insulating layer; forming a second conductive layer on the first conductive layer; The step of etching the lower layer comprises: recessing the second conductive layer from each end of the first conductive layer and the top layer. The method for manufacturing the display device according to claim 1 or 2.

4. The second conductive layer is formed of an aluminum-based material. The method for manufacturing the display device according to claim 3 .

5. The first conductive layer is formed of a titanium-based material. The method for manufacturing the display device according to claim 4 .

6. The step of forming the upper layer includes: forming a first thin film on the second conductive layer; forming a second thin film on the first thin film; The first thin film is formed of a titanium-based material. The method for manufacturing the display device according to claim 5 .

7. The etching of the lower layer is a wet etch. The method for manufacturing the display device according to claim 3 .

8. The step of forming the lower electrode includes: An adhesive layer is formed on the insulating layer; forming a reflective layer on the adhesive layer; forming a transparent layer on the reflective layer; The method for manufacturing the display device according to claim 1 or 2.

9. The reflective layer is formed of silver. The method for manufacturing a display device according to claim 8 .

10. Furthermore, after forming the opening, a protective film is formed to cover the opening; After etching the lower layer, the protective film is removed. The method for manufacturing a display device according to claim 8 .

11. Furthermore, after forming the laminated film, forming a sealing layer covering the laminated film and the partition wall using an inorganic insulating material; The method for manufacturing the display device according to claim 1 or 2.

12. Furthermore, after forming the sealing layer, forming a patterned third resist on the sealing layer; performing etching using the third resist as a mask, and sequentially removing the sealing layer and the laminated film exposed from the third resist; The method for manufacturing the display device according to claim 11 .

13. The inorganic insulating layer is formed of silicon oxide, silicon nitride, or silicon oxynitride. The method for manufacturing the display device according to claim 1 or 2.

14. A substrate; a lower electrode disposed above the substrate; an inorganic insulating layer covering a peripheral portion of the lower electrode; a partition wall having a lower portion disposed on the inorganic insulating layer and an upper portion disposed on the lower portion; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed over the organic layer and in contact with the lower portion; the lower portion has a first conductive layer covering an upper surface of the inorganic insulating layer and a second conductive layer disposed on the first conductive layer, The first conductive layer and the upper portion protrude from a side surface of the second conductive layer. Display device.

15. the organic layer includes a hole injection layer spaced from the first conductive layer; The display device according to claim 14.

16. moreover, a cap layer disposed on the upper electrode; a sealing layer formed of an inorganic insulating material and covering the cap layer and the partition wall; The display device according to claim 14.

17. the first conductive layer is formed of a titanium-based material; The second conductive layer is formed of an aluminum-based material. The display device according to claim 14.

18. The upper portion has a first thin film formed of a titanium-based material disposed on the second conductive layer, and a second thin film disposed on the first thin film. The display device according to claim 17.

19. The lower electrode is A reflective layer formed of silver; a transparent layer disposed on the reflective layer, The display device according to claim 14.

20. The inorganic insulating layer is formed of silicon oxide, silicon nitride, or silicon oxynitride. The display device according to claim 14.

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