Memory system

Abstract

To realize a memory system capable of reducing the size of a data buffer used when accessing a nonvolatile memory.SOLUTION: According to one embodiment, a memory system includes a nonvolatile memory chip, a write buffer, and a controller. The nonvolatile memory chip includes a memory cell array. The write buffer is capable of storing data received in accordance with receiving a write request from a host. The controller performs a data transfer operation of transferring a piece of data of a second size, which is smaller than a piece of data of a first size written in a single write operation to the nonvolatile memory chip, from the write buffer to the nonvolatile memory chip multiple times. The controller writes, into the memory cell array, pieces of data of the second size transferred to the nonvolatile memory chip through the data transfer operations multiple times, respectively.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The present invention relates to a technique for controlling a non-volatile memory. [Background technology]

[0002] In recent years, memory systems equipped with non-volatile memories have become widespread. One such memory system is a solid-state drive (SSD) equipped with a NAND flash memory. SSDs are used as the main storage of various computing devices.

[0003] When the nonvolatile memory is accessed from the host, the memory system generally includes a data buffer. Access from the host to the nonvolatile memory includes, for example, an operation of receiving data from the host and writing it to the nonvolatile memory, and an operation of reading data from the nonvolatile memory and transmitting it to the host. The data buffer includes, for example, a write buffer and a read buffer. The write buffer stores data to be written to the nonvolatile memory. The read buffer stores data read from the nonvolatile memory. By including a data buffer, the memory system can efficiently transmit and receive data to and from the host, and efficiently perform write and read operations on the nonvolatile memory. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2022 / 0342585 [Patent Document 2] US Patent Application Publication No. 2017 / 0269856 [Patent Document 3] US Patent Application Publication No. 2019 / 0163620 Summary of the Invention [Problem to be solved by the invention]

[0005] The size of the data buffer can be greatly affected by the write method and the write order for the non-volatile memory. For example, if the write method and the write order are optimized to reduce the size of the write buffer, the size of the read buffer may be large. On the other hand, if the write method and the write order are optimized to reduce the size of the read buffer, the size of the write buffer may be large.

[0006] One embodiment provides a memory system that can reduce the size of a data buffer used when accessing a non-volatile memory. [Means for solving the problem]

[0007] According to an embodiment, a memory system includes a non-volatile memory chip, a write buffer, and a controller. The non-volatile memory chip includes a memory cell array. The write buffer is capable of storing data received in response to receiving a write request from a host. The controller performs a data transfer operation multiple times to transfer data of a second size, which is smaller than data of a first size written in one write operation to the non-volatile memory chip, from the write buffer to the non-volatile memory chip. The controller writes the multiple pieces of data of the second size, which are respectively transferred to the non-volatile memory chip by the multiple data transfer operations, to the memory cell array. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to a first embodiment. [Diagram 2] 2 is a block diagram showing an example of the configuration of a nonvolatile memory chip included in the memory system of the first embodiment. [Diagram 3] 1 is a perspective view showing a configuration example of a block included in a memory system according to a first embodiment. [Figure 4] FIG. 2 is a diagram showing an example of a circuit configuration of a block included in the memory system of the first embodiment. [Diagram 5] 4 is a diagram showing an example of a write order in a nonvolatile memory chip included in the memory system of the first embodiment. [Figure 6] 11 is a diagram showing an example of a write order in a plurality of nonvolatile memory chips included in a memory system of a comparative example. [Figure 7] 11 is a diagram showing a write operation to a nonvolatile memory chip in a memory system of a comparative example. [Figure 8] 11 is a diagram showing a read operation from a nonvolatile memory chip in a memory system of a comparative example. [Figure 9] FIG. 13 is a diagram showing another example of a write order in a plurality of nonvolatile memory chips included in a memory system of the comparative example. [Figure 10] 4A and 4B are diagrams showing an example of a write operation to a nonvolatile memory chip included in the memory system of the first embodiment. [Figure 11] 4 is a diagram showing an example of a command sequence for a nonvolatile memory chip included in the memory system of the first embodiment. [Figure 12A] 10 is a flowchart showing an example of a procedure of a write control process executed in the memory system of the first embodiment. [Figure 12B] 12B is a flowchart showing an example of the procedure of the write control process subsequent to FIG. 12A. [Figure 13A] 10 is a flowchart showing an example of a procedure of a non-volatilization process executed in a memory system according to a second embodiment. [Figure 13B] 13B is a flowchart showing an example of the procedure of the non-volatilization process subsequent to FIG. 13A. [Figure 14] FIG. 11 is a diagram showing an example of a command sequence for a nonvolatile memory chip included in a memory system according to a third embodiment. [Figure 15] 13 is a flowchart showing an example of a procedure of a non-volatilization process executed in a memory system according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings.

[0010] (First embodiment) First, the configuration of an information processing system 1 including a memory system according to a first embodiment will be described with reference to Fig. 1. The information processing system 1 includes a host device 2 and a memory system 3.

[0011] The host device 2 may be a storage server that stores a large amount of diverse data in the memory system 3, or may be a personal computer. Hereinafter, the host device 2 will also be referred to as a host 2.

[0012] The memory system 3 is a storage device configured to write data to a nonvolatile memory and read data from the nonvolatile memory. The nonvolatile memory is, for example, a NAND flash memory. The memory system 3 is also called a storage device or a semiconductor storage device. The memory system 3 is realized, for example, as a solid-state drive (SSD) having a NAND flash memory or a Universal Flash Storage (UFS) device.

[0013] The memory system 3 can be used as storage for the host 2. The memory system 3 may be built into the host 2, or may be connected to the host 2 via a cable or a network.

[0014] The interface for connecting the host 2 and the memory system 3 is PCI Express. TM (PCIe TM ), Ethernet TM , Fiber channel, NVM Express TM (NVMe TM ), UFS, etc.

[0015] The memory system 3 includes, for example, a memory device 4 and a controller 6. The memory system 3 may further include a DRAM 5.

[0016] The memory device 4 includes one or more nonvolatile memory chips 41. The one or more nonvolatile memory chips 41 are, for example, nonvolatile memory chips 41-0, 41-1, 41-2, 41-3, . . . In the following, a case where the memory device 4 includes four nonvolatile memory chips 41-0, 41-1, 41-2, and 41-3 will be mainly illustrated. An unspecified one of the nonvolatile memory chips 41-0, 41-1, 41-2, 41-3, . . . is also referred to as the nonvolatile memory chip 41. In addition, the i-th nonvolatile memory chip of the nonvolatile memory chips 41-0, 41-1, 41-2, 41-3, . . . is referred to as the i-th nonvolatile memory chip 41. The nonvolatile memory chip 41 is, for example, a NAND type flash memory die.

[0017] The non-volatile memory chip 41 includes a plurality of blocks. One block functions as the smallest unit of a data erase operation. A block may also be referred to as an "erase block" or a "physical block." Each of the plurality of blocks includes a plurality of pages. Each of the plurality of pages includes a plurality of memory cells connected to a single word line. One page functions as a unit of a data write operation and a data read operation. Note that a word line may function as a unit of a data write operation and a data read operation.

[0018] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block, which is called the maximum P / E cycle number. One P / E cycle for a block includes a data erase operation for putting all memory cells in the block into an erased state, and a data program operation for writing data to each page of the block. Note that writing data to a block (more specifically, a memory cell) is synonymous with programming data to the block (memory cell).

[0019] The non-volatile memory chip 41 may be implemented as a flash memory configured to store multiple bits per memory cell.

[0020] Examples of flash memories configured to store multiple bits per memory cell include multi-level cell (MLC, or 4LC) flash memories, triple-level cell (TLC, or 8LC) flash memories, and quad-level cell (QLC, or 16LC) flash memories. MLC flash memories can store two bits of data per memory cell. TLC flash memories can store three bits of data per memory cell. QLC flash memories can store four bits of data per memory cell. Flash memories configured to store one bit per memory cell are also called single-level cell (SLC, or 2LC) flash memories.

[0021] When the non-volatile memory chip 41 is realized as an MLC flash memory, two pages of data are usually written to a plurality of memory cells connected to the same word line. The two pages of data are composed of Lower page data and Upper page data. This allows two bits to be written to each memory cell. Any area (for example, one or more arbitrary blocks) in the MLC flash memory can be used as an area (SLC area) in which only one bit can be stored per memory cell. In an operation of writing data to the SLC area, only one page of data (Lower page data) is written to a plurality of memory cells connected to the same word line. This allows only one bit to be written to each memory cell in each block used as an SLC area, similar to each block (SLC block) in the SLC flash memory. As a result, each block used as an SLC area functions as a pseudo SLC block.

[0022] When the non-volatile memory chip 41 is realized as a TLC flash memory, typically, three pages of data are written to a plurality of memory cells connected to the same word line. The three pages of data are composed of lower page data, middle page data, and upper page data. This allows three bits to be written to each memory cell. Any area (for example, one or more arbitrary blocks) in this TLC flash memory may be used as the above-mentioned SLC area, or may be used as an MLC area capable of storing two bits per memory cell. The SLC area and the MLC area may be set in units smaller than a block. In the MLC area, only two pages of data are written to a plurality of memory cells connected to the same word line. This allows only two bits to be written to each memory cell in the MLC area.

[0023] When the non-volatile memory chip 41 is realized as a QLC flash memory, typically, four pages of data are written to a plurality of memory cells connected to the same word line. This allows four bits to be written to each memory cell. Any area (for example, one or more arbitrary blocks) in this QLC flash memory may be used as an SLC area, an MLC area, or a TLC area capable of storing three bits per memory cell. The SLC area, the MLC area, and the TLC area may be set in units smaller than a block. In the TLC area, only three pages of data are written to a plurality of memory cells connected to the same word line. This allows three bits to be written to each memory cell in the TLC area.

[0024] The non-volatile memory chip 41 may be configured to store 5 or more bits per memory cell. Even in this case, any area of ​​the non-volatile memory chip 41 may be used as an area in which only 4 or less bits of data per memory cell are written.

[0025] The DRAM 5 is a volatile memory. For example, the DRAM 5 includes a storage area for firmware (FW) 51 and a storage area for a logical-physical address conversion table 52.

[0026] The FW 51 is a program for controlling the operation of the controller 6. The FW 51 is loaded from the memory device 4 to the DRAM 5, for example.

[0027] The controller 6 may be realized by a circuit such as a System-on-a-chip (SoC). The controller 6 is configured to control the memory device 4. The functions of each unit in the controller 6 may be realized by dedicated hardware in the controller 6, or may be realized by a processor that executes the FW.

[0028] The controller 6 may function as a flash translation layer (FTL) configured to perform data management and block management of the memory device 4. The data management performed by the FTL includes (1) management of mapping information indicating the correspondence between each logical address and each physical address of the memory device 4, and (2) processing for concealing the difference between page-based data read / write operations and block-based data erase operations. The block management includes bad block management, wear leveling, and garbage collection.

[0029] The logical address is used by the host 2 to address a storage area of ​​the memory system 3. The logical address is, for example, a logical block address (LBA).

[0030] The management of the mapping between each logical address and each physical address is performed, for example, by using a logical-physical address conversion table 52. The controller 6 uses the logical-physical address conversion table 52 to manage the mapping between each logical address and each physical address in a specific management size unit. A physical address corresponding to a certain logical address indicates a physical storage location in the memory device 4 to which data of this logical address is written. The controller 6 uses the logical-physical address conversion table 52 to manage a plurality of storage areas obtained by logically dividing the storage area of ​​the memory device 4. These multiple storage areas correspond to a plurality of logical addresses, respectively. That is, each of these multiple storage areas is specified by one logical address. The logical-physical address conversion table 52 may be loaded from the memory device 4 to the DRAM 5 when the memory system 3 is started up.

[0031] Data can be written to one page only once per P / E cycle. Therefore, the controller 6 writes updated data corresponding to a certain logical address to a different physical storage location, not to the physical storage location where the previous data corresponding to this logical address is stored. Then, the controller 6 invalidates the previous data by updating the logical-physical address conversion table 52 so as to associate this logical address with this different physical storage location. Data referenced by the logical-physical address conversion table 52 (i.e., data associated with a logical address) is called valid data. Data not associated with any logical address is called invalid data. Valid data is data that may be read by the host 2 later. Invalid data is data that may no longer be read by the host 2.

[0032] Also, the controller 6 can execute a write operation on the non-volatile memory chip 41 in, for example, any of the SLC method, the MLC method, the TLC method, and the QLC method. The SLC method is a method in which one bit is written per memory cell. The MLC method is a method in which two bits are written per memory cell. The TLC method is a method in which three bits are written per memory cell. The QLC method is a method in which four bits are written per memory cell.

[0033] The controller 6 may include, for example, a host interface circuit (host I / F) 11, a memory interface circuit (memory I / F) 12, a DRAM interface circuit (DRAM I / F) 13, a static random access memory (SRAM) 14, and a CPU 15. The host I / F 11, the memory I / F 12, the DRAM I / F 13, the SRAM 14, and the CPU 15 may be connected via a bus 10.

[0034] The host I / F 11 functions as a circuit that receives various commands, such as input / output (I / O) commands, various control commands, and data, from the host 2. The I / O commands include, for example, write commands and read commands. The control commands include, for example, a flush command. The host I / F 11 also functions as a circuit that transmits responses to commands and data to the host 2.

[0035] The memory I / F 12 electrically connects the controller 6 and the memory device 4. The memory I / F 12 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0036] The memory I / F 12 functions as a NAND control circuit configured to control the memory device 4. The memory I / F 12 may be connected to multiple nonvolatile memory chips 41 in the memory device 4 via multiple channels ch0, ch1, ch2, ch3, . . . Driving the multiple nonvolatile memory chips 41 in parallel can increase the bandwidth of access to the entire memory device 4.

[0037] The DRAM I / F 13 functions as a DRAM control circuit configured to control access to the DRAM 5 .

[0038] The SRAM 14 is a volatile memory. For example, a buffer area for temporarily storing data is provided in the SRAM 14. The buffer area includes, for example, a write buffer 141 and a read buffer 142. The write buffer 141 temporarily stores user data to be written to the nonvolatile memory chip 41. The read buffer 142 temporarily stores user data read from the nonvolatile memory chip 41. Note that the write buffer 141 and the read buffer 142 may be allocated to storage areas of the DRAM 5. Furthermore, the SRAM 14 may be allocated to storage areas of the FW 51 and the logical-physical address conversion table 52. When storage areas of the SRAM 14 are allocated to storage areas of the write buffer 141, the read buffer 142, the FW 51, and the logical-physical address conversion table 52, the memory system 3 may not include the DRAM 5.

[0039] The CPU 15 is a processor configured to control the host I / F 11, the memory I / F 12, the DRAM I / F 13, and the SRAM 14. The CPU 15 performs various processes by executing FW 51 loaded from the memory device 4 to the DRAM 5. The FW 51 is a control program including a group of instructions for causing the CPU 15 to perform various processes. The CPU 15 can execute command processes for processing various commands from the host 2, etc. The operation of the CPU 15 is controlled by the FW 51 executed by the CPU 15.

[0040] The functions of each unit in the controller 6 may be realized by dedicated hardware in the controller 6, or may be realized by the CPU 15 executing the FW 51.

[0041] The CPU 15 functions, for example, as a write control unit 151 and a read control unit 152. The CPU 15 functions as each of these units by executing the FW 51, for example.

[0042] In response to receiving a write request (e.g., a write command) from the host 2, the write control unit 151 receives user data from the host 2 and controls an operation for writing the user data to the nonvolatile memory chip 41. In response to receiving a read request (e.g., a read command) from the host 2, the read control unit 152 controls an operation for reading user data from the nonvolatile memory chip 41 and transmitting it to the host 2.

[0043] Here, a more specific description will be given of the configuration of the nonvolatile memory chip 41. FIG.

[0044] The non-volatile memory chip 41 includes, for example, T planes 45. T is an integer equal to or greater than 1. In FIG. 2, an example is shown in which the T planes 45 are four planes 45-0, 45-1, 45-2, and 45-3.

[0045] Each of the T planes 45 includes a peripheral circuit 31 , a latch 32 , and a memory cell array 33 .

[0046] The peripheral circuit 31 is a circuit that controls the memory cell array 33. The peripheral circuit 31 includes, for example, a row decoder, a column decoder, and a sense amplifier. The peripheral circuit 31 can execute a program operation (write operation), a sense operation (read operation), and an erase operation on the memory cell array 33.

[0047] The latch 32 is a circuit including a storage area for temporarily storing data transferred between the controller 6 and the non-volatile memory chip 41. The latch 32 is also called a register or a buffer. During a data write operation, data received from the controller 6 is temporarily stored in the latch 32 and then programmed in the memory cell array 33. Hereinafter, an operation of transferring (inputting) data received from the controller 6 and stored in the write buffer 141 to the latch 32 is referred to as a data-in operation. Also, an operation of programming the data stored in the latch 32 in the memory cell array 33 is referred to as a program operation. The latch 32 includes, for example, one data input latch (DL) 321 and M program latches (PL) 322. M is an integer equal to or greater than 1.

[0048] The data input latch 321 temporarily stores the data transferred from the write buffer 141 .

[0049] Each of the M program latches 322 temporarily stores data transferred from the data input latch 321. All of the data stored in the M program latches 322 is written to the memory cell array 33 in, for example, one program operation. Specifically, when data is written to the memory cell array 33 in the TLC method, for example, three pages of data stored in the three program latches 322 are written to the memory cell array 33 in one program operation. The three program latches 322 are also referred to as a 0th program latch (0th PL) 322-0, a first program latch (1st PL) 322-1, and a second program latch (2nd PL) 322-2.

[0050] The memory cell array 33 includes a plurality of blocks. Each of the plurality of blocks includes a plurality of non-volatile memory cell transistors arranged in a matrix. Hereinafter, the non-volatile memory cell transistors are simply referred to as memory cells. FIG. 2 shows an example in which the plurality of blocks are blocks B0, B1, B2, ...

[0051] Each of the multiple blocks includes multiple string units. In Fig. 2, an example is shown in which each block includes four string units SU0, SU1, SU2, and SU3.

[0052] Each of the multiple string units is a collection of memory cells. Each string unit includes, for example, multiple NAND strings NS. Each NAND string NS is a collection of memory cells connected in series.

[0053] 3 and 4, the configuration of the blocks included in the memory cell array 33 will be described in more detail. Although an example of the configuration of block B0 is shown in FIG. 3 and FIG. 4, the other blocks in the memory cell array 33 have the same configuration.

[0054] FIG. 3 is a perspective view showing an example of the configuration of the block B0.

[0055] The block B0 includes four string units SU0, SU1, SU2, and SU3.

[0056] The four string units SU0, SU1, SU2, and SU3 are arranged in a direction (horizontal direction in FIG. 3) perpendicular to the direction (vertical direction in FIG. 3) in which the word lines WL0, ..., WLx are stacked. Each of the four string units SU0, SU1, SU2, and SU3 includes a plurality of NAND strings NS.

[0057] One end of each NAND string NS is connected to a corresponding bit line among a plurality of bit lines BL0, ..., BLy. Each NAND string NS extends in the vertical direction. The control gates of the memory cells included in each NAND string NS are connected to a plurality of word lines WL0, ..., WLx, respectively.

[0058] FIG. 4 shows an example of the circuit configuration of block B0.

[0059] Each NAND string NS includes, for example, a number of memory cells MT0, ..., MTx and two select transistors ST1 and ST2. Each of the memory cells MT0, ..., MTx includes a control gate and a charge storage layer, and stores data in a non-volatile manner. The memory cells MT0, ..., MTx are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. The drain of the select transistor ST1 is connected to a corresponding bit line among the number of bit lines BL0, ..., BLy. The source of the select transistor ST2 is connected to a source line SL common to the number of string units SU0, SU1, SU2, and SU3.

[0060] The gate of the select transistor ST1 in the string unit SU0 is connected to the select gate line SGD0 corresponding to the string unit SU0. The gate of the select transistor ST1 in the string unit SU1 is connected to the select gate line SGD1 corresponding to the string unit SU1. The gate of the select transistor ST1 in the string unit SU2 is connected to the select gate line SGD2 corresponding to the string unit SU2. The gate of the select transistor ST1 in the string unit SU3 is connected to the select gate line SGD3 corresponding to the string unit SU3.

[0061] The gates of the select transistors ST2 in the string units SU0, SU1, SU2, and SU3 are commonly connected to a select gate line SGS. The gates of the select transistors ST2 in the string units SU0, SU1, SU2, and SU3 may be connected to different select gate lines for each string unit. The control gates of the memory cells MT0, ..., MTx included in the block B0 are commonly connected to the word lines WL0, ..., WLx, respectively.

[0062] Each of the program operation and the sense operation by the peripheral circuit 31 can be executed collectively on a plurality of memory cells connected to one word line in one string unit. In each of the program operation and the sense operation, a set of memory cells selected collectively is called a memory cell group.

[0063] When one memory cell is configured to store one bit of data, the size of data stored per memory cell group is called one page of data. For example, when one memory cell is configured to store three bits of data, the size of data stored per memory cell group is three pages of data.

[0064] The erase operation by the peripheral circuit 31 is executed, for example, in units of blocks. That is, data stored in all memory cells included in one block is erased at once.

[0065] Next, a description will be given of the relationship between the write method and write order for the nonvolatile memory chip 41 and the sizes (capacities) of the write buffer 141 and the read buffer 142. The write order indicates the order of addresses to which data is written in the nonvolatile memory chip 41. The write order is also called write addressing.

[0066] The sizes of the write buffer 141 and the read buffer 142 may depend on the write method and write order for the non-volatile memory chip 41. For example, if the write method and write order are optimized to reduce the size of the write buffer 141, the size of the read buffer 142 may become large. On the other hand, if the write method and write order are optimized to reduce the size of the read buffer 142, the size of the write buffer 141 may become large.

[0067] In the following, a case where a full sequence program (FSP) operation is used as a write method for the nonvolatile memory chip 41 will be exemplified. The FSP operation is an operation for programming multiple pages of data into one or more blocks in one program operation. For example, when data is programmed into a block in the nonvolatile memory chip 41 by the TLC method, in the FSP operation, three pages of data (Lower page data, Middle page data, and Upper page data) are transferred (input) to the nonvolatile memory chip 41, and the transferred three pages of data are programmed collectively into one block. Note that the following description is not limited to the case where the TLC method is used, but can be similarly applied to any case where a certain amount of data is programmed collectively into one or more blocks.

[0068] A single FSP operation may be performed on a single block, or on multiple blocks included in multiple planes 45 in one non-volatile memory chip 41. A block included in a plane 45 is also called a plane block (PB). Performing a single program operation on multiple plane blocks included in multiple planes 45 is also called a multi-plane program. When the non-volatile memory chip 41 includes multiple planes 45, multi-plane program is generally used with emphasis on program performance.

[0069] 5 shows an example of a write order in one nonvolatile memory chip 41. Here, it is assumed that an FSP operation using the TLC method and a multi-plane program is performed on a nonvolatile memory chip 41 including four planes 45. The four planes 45 are a 0th plane 45-0, a first plane 45-1, a second plane 45-2, and a third plane 45-3.

[0070] The four blocks to be written that are included in the four planes 45 are referred to as plane blocks PB0, PB1, PB2, and PB3. Specifically, plane block PB0 is a block included in the 0th plane 45-0 that is to be written to by the TLC method. Plane block PB1 is a block included in the first plane 45-1 that is to be written to by the TLC method. Plane block PB2 is a block included in the second plane 45-2 that is to be written to by the TLC method. Plane block PB3 is a block included in the third plane 45-3 that is to be written to by the TLC method. The position in each plane block to which data is written in one FSP operation is identified by, for example, a string number.

[0071] As shown in FIG. 5, in the FSP operation corresponding to string number “0”, page data is input (transferred) to the nonvolatile memory chip 41 in the following order (0) to (11). (0) Lower page data for plain block PB0 (1) Lower page data for plain block PB1 (2) Lower page data for plain block PB2 (3) Lower page data for plain block PB3 (4) Middle page data for plane block PB0 (5) Middle page data for plain block PB1 (6) Middle page data for plain block PB2 (7) Middle page data for plain block PB3 (8) Upper page data for plane block PB0 (9) Upper page data for plain block PB1 (10) Upper page data for plain block PB2 (11) Upper page data for plain block PB3 The number indicating the order corresponds to the numerical value within the box identified by one of the Lower page, Middle page, and Upper page, and one of the plain blocks PB0, PB1, PB2, and PB3 in the corresponding string number (here, string number "0") in Figure 5.

[0072] The 12 pages of data input in the order of (0) to (11) are written in one FSP operation. The 12 pages of data are programmed into plane blocks PB0, PB1, PB2, and PB3 in the input order.

[0073] Next, the data write sequence proceeds in the string direction. Specifically, the string number is incremented from 0 to 1. In the FSP operation corresponding to string number "1", 12 pages of data are input to the non-volatile memory chip 41 in the order of (12) to (23). The specific page data input in the order of (12) to (23) is the same as (0) to (11). The input 12 pages of data are programmed into the plane blocks PB0, PB1, PB2, and PB3 in the input order.

[0074] Thereafter, FSP operations corresponding to the incremented string numbers can be performed in the same manner.

[0075] In order to improve program performance, an interleaved write operation may be performed in the memory system 3. The interleaved write operation is a write operation that is executed in parallel on a plurality of nonvolatile memory chips 41.

[0076] Now, with reference to FIGS. 6 and 7, an interleaved write operation to a plurality of nonvolatile memory chips in a memory system according to a comparative example will be described.

[0077] FIG. 6 shows an example of a write order in a plurality of nonvolatile memory chips included in a memory system according to a comparative example. Here, it is assumed that the memory system according to the comparative example includes four nonvolatile memory chips, and FSP operations using the TLC method and the multi-plane program are performed on the four nonvolatile memory chips, each including four planes. The four nonvolatile memory chips are the 0th nonvolatile memory chip 41A-0, the first nonvolatile memory chip 41A-1, the second nonvolatile memory chip 41A-2, and the third nonvolatile memory chip 41A-3. In each of the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, the four blocks to be written, which are included in the four planes, are referred to as plane blocks PB0, PB1, PB2, and PB3.

[0078] As shown in Fig. 6, in the FSP operation corresponding to string number "0", first, page data is input to the 0th nonvolatile memory chip 41A-0 in the order of (0) to (11). This page data input in the order of (0) to (11) is the same as the page data input in the order of (0) to (11) described above with reference to Fig. 5. Note that the number indicating the order corresponds to the numerical value in the box specified by any one of the Lower page, Middle page, and Upper page, and any one of the plane blocks PB0, PB1, PB2, and PB3 in the combination of the corresponding string number and nonvolatile memory chip in Fig. 6 (here, the combination of string number "0" and the 0th nonvolatile memory chip 41A-0).

[0079] The 12 pages of data input in the order of (0) to (11) are written to the 0th nonvolatile memory chip 41A-0 in one FSP operation. The 12 pages of data are programmed into the plane blocks PB0, PB1, PB2, and PB3 of the 0th nonvolatile memory chip 41A-0 in the input order.

[0080] When interleaved write operations are performed on multiple nonvolatile memory chips, after data input in the order (0) to (11) for the 0th nonvolatile memory chip 41A-0, the write sequence proceeds in the chip direction rather than the string direction, from the 0th nonvolatile memory chip 41A-0 to the 1st nonvolatile memory chip 41A-1.

[0081] Therefore, next, page data is input to the first nonvolatile memory chip 41A-1 in the order of (12) to (23). The specific page data input in the order of (12) to (23) is similar to the page data input in the order of (0) to (11), and the target of the data-in operation is replaced from the 0th nonvolatile memory chip 41A-0 to the first nonvolatile memory chip 41A-1.

[0082] The 12 pages of data input in the order of (12) to (23) are written to the first nonvolatile memory chip 41A-1 in one FSP operation. The 12 pages of data are programmed into the plane blocks PB0, PB1, PB2, and PB3 of the first nonvolatile memory chip 41A-1 in the input order.

[0083] Next, page data is input to the second nonvolatile memory chip 41A-2 in the order of (24) to (35). The specific page data input in the order of (24) to (35) is similar to the page data input in the order of (0) to (11), and the target of the data-in operation is replaced from the 0th nonvolatile memory chip 41A-0 to the second nonvolatile memory chip 41A-2.

[0084] The 12 pages of data input in the order of (24) to (35) are written to the second nonvolatile memory chip 41A-2 in one FSP operation. The 12 pages of data are programmed into the plane blocks PB0, PB1, PB2, and PB3 of the second nonvolatile memory chip 41A-2 in the input order.

[0085] Then, page data is input to the third nonvolatile memory chip 41A-3 in the order of (36) to (47). The specific page data input in the order of (36) to (47) is similar to the page data input in the order of (0) to (11), and the target of the data-in operation is changed from the 0th nonvolatile memory chip 41A-0 to the third nonvolatile memory chip 41A-3.

[0086] The 12 pages of data input in the order of (36) to (47) are written to the third nonvolatile memory chip 41A-3 in one FSP operation. The 12 pages of data are programmed into the plane blocks PB0, PB1, PB2, and PB3 of the third nonvolatile memory chip 41A-3 in the input order.

[0087] After the data-in operations are performed on the four non-volatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 in the order of (0) to (47), the write order proceeds in the string direction (i.e., in the direction of increasing string numbers). Thereafter, in the same manner, FSP operations can be performed sequentially on the non-volatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 according to the incremented string numbers.

[0088] In a write process in response to a write request from the host, data received from the host is programmed in sequence into the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3. In order to execute the FSP operation for each of the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, it is necessary to input 12 pages of data (=3 pages×4 PB of data) into one nonvolatile memory chip. In other words, if 12 pages of data are not input, the FSP operation for one nonvolatile memory chip cannot be executed. Therefore, the controller of the memory system of the comparative example starts inputting (transferring) the accumulated 12 pages of data to the nonvolatile memory chip after, for example, 12 pages of data are accumulated in the write buffer.

[0089] Fig. 7 shows write operations to nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 in a memory system 3A of a comparative example in accordance with the write order shown in Fig. 6. The memory system 3A performs a write operation in response to a write request from the host 2A.

[0090] The memory system 3A includes a memory device 4A and a controller 6A. The memory device 4A includes nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3. Each of the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 includes four planes. In FIG. 7, in the 0th nonvolatile memory chip 41A-0, four plane blocks PB0, PB1, PB2, and PB3 included in each of the four planes are assigned as blocks to be written in the TLC method.

[0091] The controller 6A includes a write control unit 151A that controls the write operation, and a write buffer 141A. The write control unit 151A stores user data transferred from the host 2A in response to receiving a write request from the host 2 in the write buffer 141A ((1) in FIG. 7).

[0092] In response to the user data 61A required for one FSP operation on the four plane blocks PB0, PB1, PB2, and PB3 being stored in the write buffer 141A, the write control unit 151A performs a data-in operation to input the user data 61A from the write buffer 141A to the 0th nonvolatile memory chip 41A-0 ((2) in FIG. 7). The user data 61A required for one FSP operation on the four plane blocks PB0, PB1, PB2, and PB3 is 12 pages of user data.

[0093] Then, the write control unit 151A performs a program operation to program the user data 61A into the four plane blocks PB0, PB1, PB2, and PB3 ((3) in FIG. 7). This completes one FSP operation for the 0th nonvolatile memory chip 41A-0 (more specifically, the four plane blocks PB0, PB1, PB2, and PB3 in the 0th nonvolatile memory chip 41A-0).

[0094] When the data-in operation of inputting the user data 61A from the write buffer 141A to the 0th nonvolatile memory chip 41A-0 is completed, the storage area of ​​the write buffer 141A in which the user data 61A is stored is released. Then, for example, user data required for the next FSP operation on the first nonvolatile memory chip 41A-1 (i.e., another 12 pages of user data) is newly stored in the write buffer 141A. The write control unit 151A performs the data-in operation and program operation on the first nonvolatile memory chip 41A-1 in the same manner as in the case of the 0th nonvolatile memory chip 41A-0. Furthermore, the write control unit 151A performs the data-in operation and program operation on each of the second nonvolatile memory chip 41A-2 and the third nonvolatile memory chip 41A-3 in the same manner.

[0095] In this way, when the write order shown in Fig. 6 is followed, the size of the storage area allocated as the write buffer 141A is only the size of data required for one FSP operation on one non-volatile memory chip 41A (here, the size of 12 pages). In other words, the write order shown in Fig. 6 can be said to be optimized to reduce the size of the write buffer 141A.

[0096] On the other hand, when user data written in the write order shown in FIG. 6 is read from the non-volatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 and transmitted to the host 2A, the size of the read buffer in the controller 6A that temporarily stores the read user data tends to become large.

[0097] Fig. 8 shows a read operation from the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 of the data written in the write order shown in Fig. 6 in the memory system 3A of the comparative example. The memory system 3A performs a read operation in response to a read request from the host 2A.

[0098] The controller 6A and the four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 are connected by four-channel data buses ch0, ch1, ch2, and ch3, respectively. The four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 can transmit data in parallel to the controller 6A via the data buses ch0, ch1, ch2, and ch3 of the corresponding channels.

[0099] The controller 6A includes a read control unit 152A that controls the read operation, and four read buffers 142A. The four read buffers 142 are a 0th read buffer 142A-0, a first read buffer 142A-1, a second read buffer 142A-2, and a third read buffer 142A-3. The four read buffers 142A-0, 142A-1, 142A-2, and 142A-3 correspond to the four non-volatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, respectively.

[0100] In response to receiving a read request from the host 2A, the read control unit 152A reads user data in parallel from the four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, and stores the read user data in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 ((1) in FIG. 8). Specifically, the read control unit 152A stores the user data 62A-0 read from the 0th nonvolatile memory chip 41A-0 in the 0th read buffer 142A-0. The read control unit 152A stores the user data 62A-1 read from the first nonvolatile memory chip 41A-1 in the first read buffer 142A-1. The read control unit 152A stores the user data 62A-2 read from the second nonvolatile memory chip 41A-2 in the second read buffer 142A-2. The read control unit 152A stores the user data 62A-3 read from the third nonvolatile memory chip 41A-3 in the third read buffer 142A-3.

[0101] Then, the read control unit 152A transfers the user data 62A-0, 62A-1, 62A-2, and 62A-3 to the host 2A ((2) in FIG. 8) in accordance with the write order shown in FIG 6. In other words, the read control unit 152A controls the order in which the user data 62A-0, 62A-1, 62A-2, and 62A-3 stored in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 are transferred to the host 2A so as to follow the write order shown in FIG 6.

[0102] For example, let us look at the 0th nonvolatile memory chip 41A-0 in the write order shown in Fig. 6. In the 0th nonvolatile memory chip 41A-0, 12 pages of user data from (0) to (11) are input, and then 12 pages of user data from (48) to (59) are input.

[0103] Between the input of 12 pages of user data from (0) to (11) and the input of 12 pages of user data from (48) to (59), 36 pages of user data from (12) to (47) are input to the first nonvolatile memory chip 41A-1, the second nonvolatile memory chip 41A-2, and the third nonvolatile memory chip 41A-3.

[0104] Therefore, during a read operation, after 12 pages of user data from (0) to (11) have been transferred to the host 2A, the user data from (48) to (59) is not transferred to the host 2A until 36 pages of user data from (12) to (47) from the first nonvolatile memory chip 41A-1, the second nonvolatile memory chip 41A-2, and the third nonvolatile memory chip 41A-3 have been transferred to the host 2A.

[0105] In this way, when the user data written in the write order shown in FIG. 6 is read from the non-volatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 and transferred to the host 2A, the amount of user data waiting to be transferred in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 after being read increases in order to transfer the data to the host 2A according to the write order. Therefore, the size of the storage area allocated as the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 increases. Therefore, in the write order shown in FIG. 6, the size of the write buffer 141A can be reduced, but the size of the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 may increase.

[0106] In contrast, a write order for optimizing the sizes of the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 to be smaller will be described.

[0107] 9 shows another example of the write order in a plurality of nonvolatile memory chips included in a memory system according to a comparative example. Here, as in the example of the write order shown in FIG. 6, it is assumed that the memory system 3A of the comparative example includes four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, and that the FSP operation by the TLC method and the multi-plane program is performed on the four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 each including four planes. In each of the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, the four blocks to be written included in the four planes are referred to as plane blocks PB0, PB1, PB2, and PB3.

[0108] As shown in FIG. 9, in the FSP operation corresponding to the string number "0", first, page data is input to the 0th nonvolatile memory chip 41A-0 in the following order (0) to (3). (0) Lower page data for plain block PB0 (1) Lower page data for plain block PB1 (2) Lower page data for plain block PB2 (3) Lower page data for plain block PB3 The number indicating the order corresponds to the numerical value within the box identified by one of the Lower page, Middle page, and Upper page, and one of the plain blocks PB0, PB1, PB2, and PB3 in the combination of the corresponding string number and nonvolatile memory chip in Figure 9 (here, the combination of string number "0" and the 0th nonvolatile memory chip 41A-0).

[0109] After the lower page data is input to the 0th nonvolatile memory chip 41A-0 in the order of (0) to (3), the data write order proceeds in the chip direction, not in the page direction.

[0110] Therefore, next, the lower page data is input to the first nonvolatile memory chip 41A-1 in the order of (4) to (7). The specific page data input in the order of (4) to (7) is similar to the page data input in the order of (0) to (3), and the target of the data-in operation is replaced from the 0th nonvolatile memory chip 41A-0 to the first nonvolatile memory chip 41A-1.

[0111] Next, the lower page data is input to the second nonvolatile memory chip 41A-2 in the order of (8) to (11). The specific page data input in the order of (8) to (11) is similar to the page data input in the order of (0) to (3), and the target of the data-in operation is replaced from the 0th nonvolatile memory chip 41A-0 to the second nonvolatile memory chip 41A-2.

[0112] Then, the lower page data is input to the third nonvolatile memory chip 41A-3 in the order of (12) to (15). The specific page data input in the order of (12) to (15) is similar to the page data input in the order of (0) to (3), and the target of the data-in operation is changed from the 0th nonvolatile memory chip 41A-0 to the third nonvolatile memory chip 41A-3.

[0113] After the lower page data is input to the 0th nonvolatile memory chip 41A-0, the first nonvolatile memory chip 41A-1, the second nonvolatile memory chip 41A-2, and the third nonvolatile memory chip 41A-3 in the order of (0) to (15), the write order proceeds in the page direction.

[0114] Therefore, the Middle page data is input to the 0th nonvolatile memory chip 41A-0, the first nonvolatile memory chip 41A-1, the second nonvolatile memory chip 41A-2, and the third nonvolatile memory chip 41A-3 in the order of (16) to (31). Then, the Upper page data is input to the 0th nonvolatile memory chip 41A-0, the first nonvolatile memory chip 41A-1, the second nonvolatile memory chip 41A-2, and the third nonvolatile memory chip 41A-3 in the order of (32) to (47).

[0115] The 12 pages of data input in the order of (0) to (3), (16) to (19), and (32) to (35) are the data to be written to the 0th nonvolatile memory chip 41A-0 in one FSP operation. The 12 pages of data are programmed into the plane blocks PB0, PB1, PB2, and PB3 of the 0th nonvolatile memory chip 41A-0 in the input order.

[0116] Similarly, the 12 pages of data input in the order of (4) to (7), (20) to (23), and (36) to (39) are written to the first nonvolatile memory chip 41A-1 in one FSP operation. The 12 pages of data are programmed into the plane blocks PB0, PB1, PB2, and PB3 of the first nonvolatile memory chip 41A-1 in the input order.

[0117] Similarly, 12 pages of data are programmed into each of the second nonvolatile memory chip 41A-2 and the third nonvolatile memory chip 41A-3.

[0118] After data input to the four non-volatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 in the order of (0) to (47), the write sequence proceeds in the string direction. Thereafter, FSP operations corresponding to incremented string numbers can be performed in the same manner.

[0119] 8, when the controller 6A receives a read request from the host 2A, the controller 6A stores the user data 62A-0, 62A-1, 62A-2, and 62A-3 read from the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3. Then, the controller 6A controls the user data 62A-0, 62A-1, 62A-2, and 62A-3 stored in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 to be transferred to the host 2A in the order in which they were written.

[0120] 9, attention is focused on the 0th nonvolatile memory chip 41A-0. In the 0th nonvolatile memory chip 41A-0, four pages of user data are input in the order of (0) to (3), and then four pages of user data are input in the order of (16) to (19).

[0121] Between the input of four pages of user data (0) to (3) and the input of four pages of user data (16) to (19), twelve pages of user data (4) to (15) are input to the first nonvolatile memory chip 41A-1, the second nonvolatile memory chip 41A-2, and the third nonvolatile memory chip 41A-3.

[0122] Therefore, in a read operation, four pages of user data from (0) to (3) are transferred to the host 2A, and after 12 pages of user data from (4) to (15) are transferred from the first nonvolatile memory chip 41A-1, the second nonvolatile memory chip 41A-2, and the third nonvolatile memory chip 41A-3 to the host 2A, four pages of user data from (16) to (19) are transferred to the host 2A.

[0123] In contrast, in a read operation using the write order shown in FIG. 6, as described above, after the user data (0) to (11) are transferred to the host 2A, 12 pages of user data (48) to (59) are stored in the read buffer 142A-0 until 36 pages of user data (12) to (47) from the first nonvolatile memory chip 41A-1, the second nonvolatile memory chip 41A-2, and the third nonvolatile memory chip 41A-3 are transferred to the host 2A.

[0124] Therefore, when the user data written in the write order shown in Fig. 9 is read from the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 and transferred to the host 2A, the amount of user data waiting to be transferred in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 after being read is reduced compared to the case where the write order shown in Fig. 6 is used. Therefore, the size of the storage area allocated as the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 is reduced.

[0125] On the other hand, when the write order shown in FIG. 9 is used, in order to perform one FSP operation on the 0th nonvolatile memory chip 41A-0, for example, after 36 pages of data corresponding to (0) through (35) have been accumulated in the write buffer 141A, the controller 6A begins inputting the accumulated 36 pages of data to the nonvolatile memory chip 41A.

[0126] In contrast, when the write order shown in FIG. 6 is used, the size of the storage area allocated as the write buffer 141A need only be the size of data required for the FSP operation on one nonvolatile memory chip 41A (for example, 12 pages).

[0127] Therefore, when user data is written to non-volatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 in the write order shown in FIG. 9, the size of the memory area allocated as write buffer 141A is larger than when the write order shown in FIG. 6 is used.

[0128] Thus, in the memory system 3A of the comparative example, when the write order shown in Fig. 6 is used, the size of the write buffer 141A can be reduced, but the size of the read buffer 142A cannot be reduced. Also, in the memory system 3A of the comparative example, when the write order shown in Fig. 9 is used, the size of the read buffer 142A can be reduced, but the size of the write buffer 141A cannot be reduced. Therefore, in the memory system 3A of the comparative example, the sizes of both the write buffer 141A and the read buffer 142A cannot be reduced.

[0129] In contrast, in the memory system 3 of the first embodiment, a write operation is performed to reduce both the size of the write buffer 141 and the size of the read buffer 142. Specifically, the controller 6 performs a data-in operation multiple times to transfer user data of a second size, which is smaller than the user data of the first size written in one write operation to the nonvolatile memory chip 41, from the write buffer 141 to the nonvolatile memory chip 41 (more specifically, the latch 32). Then, the controller 6 writes the multiple pieces of user data of the second size, which have been transferred to the nonvolatile memory chip 41 by the multiple data-in operations, to the memory cell array 33. The total size of the multiple pieces of user data of the second size is, for example, equal to the first size.

[0130] In this way, in the memory system 3, a data transfer operation for transferring the user data of the second size from the write buffer 141 to the nonvolatile memory chip 41 is performed multiple times. As a result, in the memory system 3, not only the write buffer 141 but also the nonvolatile memory chip 41 (more specifically, the latch 32) is used as a storage area for buffering the user data of the second size. Therefore, in the memory system 3, the size of the write buffer 141 can be reduced compared to, for example, the memory system 3A of the comparative example in which the data-in operation to the nonvolatile memory chip 41A is started after the user data of the first size is accumulated in the write buffer 141A. Furthermore, in the memory system 3, the size of the read buffer 142 can also be reduced by using the write order shown in FIG. 9. Therefore, in the memory system 3, the size of the data buffer (for example, the write buffer 141 and the read buffer 142) used when the host 2 accesses the nonvolatile memory chip 41 can be reduced.

[0131] The write operation in the memory system 3 of the first embodiment will be specifically described.

[0132] FIG. 10 shows an example of a write operation to the non-volatile memory chip 41. Here, an interleaved write operation to the four non-volatile memory chips 41-0, 41-1, 41-2, and 41-3 in the case of following the write order shown in FIG. 9 is illustrated. That is, it is assumed that the FSP operation by the TLC method and the multi-plane program is performed on the four non-volatile memory chips 41-0, 41-1, 41-2, and 41-3 each including four planes 45. The memory system 3 performs a write operation in response to a write request from the host 2. The write operation is controlled by the CPU 15 functioning as the write control unit 151, for example.

[0133] 10, in the 0th nonvolatile memory chip 41A-0, four plane blocks PB0, PB1, PB2, and PB3 included in four planes 45-0, 45-1, 45-2, and 45-3, respectively, are assigned as blocks to be written to in the TLC method. An operation of writing user data to the four plane blocks PB0, PB1, PB2, and PB3 in the 0th nonvolatile memory chip 41A-0 will be described.

[0134] The write control unit 151 stores user data transferred from the host 2 in response to a write request received from the host 2 in the write buffer 141 ((1) in FIG. 10).

[0135] The write control unit 151 performs an operation (data-in operation) of transferring user data of a second size, which is smaller than the user data of the first size written in one FSP operation for the 0th nonvolatile memory chip 41-0, from the write buffer 141 to the data input latch (DL) 321 of the 0th nonvolatile memory chip 41-0 ((2) in FIG. 10). The user data of the first size is, for example, data for 12 pages. The user data of the second size is, for example, user data 61 for one page. In addition, the second size is, for example, smaller than the size of user data received from the host 2 in response to receiving a write request from the host 2. The write control unit 151 performs a data-in operation, for example, every time user data of the second size is accumulated in the write buffer 141. The user data stored in the write buffer 141 is data that has not yet been written to the nonvolatile memory chip 41 (more specifically, the memory cell array 33). The write control unit 151 releases the storage area in the write buffer 141 in which the user data of the second size was stored in response to the transfer of the user data of the second size to the data input latch 321. The released storage area becomes available for storing new user data.

[0136] When one page of user data 61 is stored in the data input latches 321 in all of the planes 45-0, 45-1, 45-2, and 45-3 by the data-in operation, the write control unit 151 performs an operation (data movement operation) of moving the user data 61 stored in the data input latches 321 to the 0th program latch (0th PL) 322-0 in each of the planes 45-0, 45-1, 45-2, and 45-3 ((3) in FIG. 10). The data stored in the 0th program latch 322-0 is, for example, data to be programmed as Lower page data in the plane blocks PB0, PB1, PB2, and PB3.

[0137] The operation for storing data to be programmed as Lower page data in the plane blocks PB0, PB1, PB2, and PB3 in the 0th program latches 322-0 of the planes 45-0, 45-1, 45-2, and 45-3 will be described in more detail.

[0138] First, for example, in response to one page of user data 61 being accumulated in the write buffer 141, the write control unit 151 transfers the one page of user data 61 from the write buffer 141 to the data input latch 321 of the 0th plane 45-0. The write control unit 151 releases the storage area in the write buffer 141 in which the transferred one page of user data 61 was stored. The released storage area becomes available for storing new user data.

[0139] Next, in response to one page of user data 61 being newly accumulated in the write buffer 141, the write control unit 151 transfers the one page of user data 61 from the write buffer 141 to the data input latch 321 of the first plane 45-1. The write control unit 151 releases the storage area in the write buffer 141 in which the transferred one page of user data 61 was stored.

[0140] In the same manner, the write control unit 151 transfers one page of user data 61 from the write buffer 141 to the data input latch 321 of the second plane 45-2. Then, the write control unit 151 transfers one page of user data 61 from the write buffer 141 to the data input latch 321 of the third plane 45-3.

[0141] In response to one page of user data 61 being stored in the data input latches 321 in all of the planes 45-0, 45-1, 45-2, and 45-3, the write control unit 151 moves the user data 61 stored in the data input latches 321 to the 0th program latch 322-0 in each of the planes 45-0, 45-1, 45-2, and 45-3. As a result, data to be programmed as Lower page data in each of the plane blocks PB0, PB1, PB2, and PB3 is stored in the 0th program latch 322-0 of each of the planes 45-0, 45-1, 45-2, and 45-3.

[0142] Next, the write control unit 151 performs an operation to store data to be programmed as Middle page data in the plane blocks PB0, PB1, PB2, and PB3 in the first program latches (first PL) 322-1 of the planes 45-0, 45-1, 45-2, and 45-3, respectively. A specific operation corresponds to an operation in which the 0th program latch 322-0 is replaced with the first program latch 322-1 in the data-in operation and data movement operation for storing the Lower page data in the 0th program latch 322-0 described above.

[0143] Then, the write control unit 151 performs an operation to store the data to be programmed as Upper page data in the plane blocks PB0, PB1, PB2, and PB3 in the second program latches (second PL) 322-2 of the planes 45-0, 45-1, 45-2, and 45-3, respectively. A specific operation corresponds to an operation in which the 0th program latch 322-0 is replaced with the second program latch 322-2 in the data-in operation and data movement operation for storing the Lower page data in the 0th program latch 322-0 described above.

[0144] As a result, in all of the planes 45-0, 45-1, 45-2, and 45-3, the lower page data is stored in the 0th program latch 322-0, the middle page data is stored in the 1st program latch 322-1, and the upper page data is stored in the 2nd program latch 322-2. That is, by performing a page-in operation of inputting one page of data (i.e., user data of the second size) to the 0th nonvolatile memory chip 41-0 12 times, the 12 pages of data (i.e., data of the first size) required for one FSP operation on the 0th nonvolatile memory chip 41-0 is input to the nonvolatile memory chip 41.

[0145] Then, the write control unit 151 programs the data stored in the program latches 322-0, 322-1, and 322-2 in the planes 45-0, 45-1, 45-2, and 45-3, respectively, into the corresponding plane block PB0, PB1, PB2, or PB3 ((4) in FIG. 10). That is, the write control unit 151 performs an FSP operation on the 0th nonvolatile memory chip 41A-0. Specifically, the write control unit 151 programs the Lower page data stored in the 0th program latch 322-0, the Middle page data stored in the first program latch 322-1, and the Upper page data stored in the second program latch 322-2 in the 0th plane 45-0, into the 0th plane block PB0. Similarly, the write control unit 151 programs the Lower page data, Middle page data, and Upper page data in the corresponding plane blocks PB1, PB2, and PB3 for each of the first plane 45-1, the second plane 45-2, and the third plane 45-3.

[0146] By the above-mentioned write operation, the write control unit 151 can perform FSP operation by the TLC method and the multi-plane program on the 0th nonvolatile memory chip 41-0. The write control unit 151 similarly performs FSP operation by the TLC method and the multi-plane program on the first nonvolatile memory chip 41-1, the second nonvolatile memory chip 41-2, and the third nonvolatile memory chip 41-3 according to the write order shown in Fig. 9, for example. This allows the write control unit 151 to perform interleaved write operation on the four nonvolatile memory chips 41-0, 41-1, 41-2, and 41-3.

[0147] In this write operation, the write control unit 151 transfers user data of a second size, which is smaller than the user data of the first size written in one FSP operation to the nonvolatile memory chip 41, from the write buffer 141 to the data input latch 321. For example, the write control unit 151 sequentially transfers the user data of the second size accumulated in the write buffer 141 to the data input latch 321. Then, the write control unit 151 releases the storage area in the write buffer 141 in which the user data of the second size transferred to the data input latch 321 was stored. The released storage area becomes available for storing new user data.

[0148] As a result, in the memory system 3 of the first embodiment, the size of the write buffer 141 can be reduced, compared to the memory system 3A of the comparative example in which data of a first size (e.g., 12 pages of data) to be programmed into the non-volatile memory chip 41A in one FSP operation is accumulated in the write buffer 141A and then the data is input into the non-volatile memory chip 41A.

[0149] The read operation in the memory system 3 is similar to the read operation in the memory system 3A of the comparative example shown in FIG. 8, except that the data read from the nonvolatile memory chip 41 in response to a read request from the host 2 and stored in the read buffer 142 is transferred to the host 2 according to the write order shown in FIG. 9, not the write order shown in FIG. 6. Specifically, in response to receiving a read request from the host 2, the read control unit 152 reads user data in parallel from, for example, the four nonvolatile memory chips 41-0, 41-1, 41-2, and 41-3, and stores the read user data in the read buffer 142. Then, the read control unit 152 transfers the user data stored in the read buffer 142 to the host 2 according to the write order shown in FIG. That is, the read control unit 152 controls the order in which the user data stored in the read buffer 142 is transferred to the host 2 to follow the write order shown in FIG. 9. This allows the size of the read buffer 142 to be reduced, as described above with reference to FIG. 9.

[0150] FIG. 11 shows an example of a command sequence for the nonvolatile memory chip 41. This command sequence corresponds to one FSP operation for one nonvolatile memory chip 41. Here, it is assumed that the FSP operation is performed for the nonvolatile memory chip 41 by the TLC method and the multi-plane program. This command sequence is sent to the nonvolatile memory chip 41 by the memory I / F 12 under the control of the write control unit 151, for example. The nonvolatile memory chip 41 includes T planes 45. T plane blocks PBx, ..., PBy included in each of the T planes 45 are assigned as blocks to be written in the TLC method. The plane 45 including the plane block PBx is referred to as a plane 45-x. The plane 45 including the plane block PBy is referred to as a plane 45-y.

[0151] The command sequence shown in FIG. 11 includes a sequence from the beginning to timing A, a sequence from timing A to timing B, and a sequence from timing B to the end. The sequence from the beginning to timing A is a sequence for inputting Lower page data. The sequence from timing A to timing B is a sequence for inputting Middle page data. The sequence from timing B to the end is a sequence for inputting Upper page data and programming the input Lower page data, Middle page data, and Upper page data in a plane block. An instruction to the non-volatile memory chip 41 is given in units of, for example, a set of a first command, an address, data, and a second command. Below, the sequence from the beginning to timing A, the sequence from timing A to timing B, and the sequence from timing B to the end will be described in order.

[0152] (Sequence from the beginning to timing A: Input of Lower page data) First, the memory I / F 12 sends a first command 701, an address 702, lower page data 703, and a second command 704 to the plane 45-x of the non-volatile memory chip 41. The first command 701 is a command "80h" or "85h". The commands "80h" and "85h" are commands to start data input. The address 702 specifies the plane block PBx to which the lower page data 703 is written. The lower page data 703 is user data for the lower page to be written to the plane block PBx. The second command 704 is a command "11h". The command "11h" is a command to leave the input data as it is in the latch 32 (here, the data input latch 321). Note that the values ​​defined as each command are merely examples, and values ​​defined by standards or specifications are used. In response to a first command 701, an address 702, lower page data 703, and a second command 704, the lower page data 703 transferred from the write buffer 141 is stored (input) in the data input latch 321 of the plane 45-x.

[0153] The memory I / F 12 similarly executes a sequence for storing the lower page data transferred from the write buffer 141 in the data input latch 321 in the corresponding plane 45 for each of the remaining planes 45, excluding plane 45-x and plane 45-y from the T planes 45.

[0154] Then, the memory I / F 12 sends a first command 705, an address 706, lower page data 707, and a second command 708 to the plane 45-y of the non-volatile memory chip 41. The first command 705 is a command "80h" or "85h". The address 706 specifies the plane block PBy to which the lower page data 707 is written. The lower page data 707 is user data for the lower page to be written to the plane block PBy. The second command 708 is a command "1Ah". The command "1Ah" is a command to move data input to the data input latches 321 of the T planes 45 to the program latches 322 to prepare for data input of the next page.

[0155] By the first command 705, the address 706, the lower page data 707, and the second command 708, the lower page data 707 transferred from the write buffer 141 is stored in the data input latch 321 of the plane 45-y, and further, in each of the T planes 45, the lower page data stored in the data input latch 321 is moved to the 0th program latch 322-0. Specifically, the lower page data 703 stored in the data input latch 321 of the plane 45-x is moved to the 0th program latch 322-0 of the plane 45-x. In addition, the lower page data 707 stored in the data input latch 321 of the plane 45-y is moved to the 0th program latch 322-0 of the plane 45-y. Therefore, by the sequence from the beginning to the timing A, the lower page data is stored in the 0th program latch 322-0 in all of the T planes 45.

[0156] (Sequence from timing A to timing B: Input of Middle page data) Next, the memory I / F 12 sends a first command 709, an address 710, Middle page data 711, and a second command 712 to the plane 45-x of the non-volatile memory chip 41. The first command 709 is a command "80h" or "85h". The address 710 specifies the plane block PBx to which the Middle page data 711 is written. The Middle page data 711 is user data for the Middle page to be written to the plane block PBx. The second command 712 is a command "11h". The first command 709, the address 710, the Middle page data 711, and the second command 712 cause the Middle page data 711 transferred from the write buffer 141 to be stored in the data input latch 321 of the plane 45-x.

[0157] The memory I / F 12 similarly executes a sequence for transferring Middle page data to the data input latch 321 in the corresponding plane 45 for each of the remaining plane blocks excluding plane 45-x and plane 45-y from the T planes 45.

[0158] Then, the memory I / F 12 sends a first command 713, an address 714, Middle page data 715, and a second command 716 to the plane 45-y of the non-volatile memory chip 41. The first command 713 is a command "80h" or "85h". The address 714 specifies the plane block PBy to which the Middle page data 715 is written. The Middle page data 715 is user data for the Middle page to be written to the plane block PBy. The second command 716 is a command "1Ah".

[0159] By the first command 713, the address 714, the Middle page data 715, and the second command 716, the Middle page data 715 transferred from the write buffer 141 is stored in the data input latch 321 of the plane 45-y, and further, in each of the T planes 45, the Middle page data stored in the data input latch 321 is moved to the first program latch 322-1. Specifically, the Middle page data 711 stored in the data input latch 321 of the plane 45-x is moved to the first program latch 322-1 of the plane 45-x. Also, the Middle page data 715 stored in the data input latch 321 of the plane 45-y is moved to the first program latch 322-1 of the plane 45-y. Therefore, by the sequence from timing A to timing B, the Middle page data is stored in the first program latch 322-1 in all of the T planes 45.

[0160] (Sequence from timing B to the end: Upper page data input and program) Next, the memory I / F 12 sends a first command 717, an address 718, Upper page data 719, and a second command 720 to the plane 45-x of the non-volatile memory chip 41. The first command 717 is a command "80h" or "85h". The address 718 specifies the plane block PBx to which the Upper page data 719 is written. The Upper page data 719 is user data for the Upper page to be written to the plane block PBx. The second command 720 is a command "11h". The Upper page data 719 transferred from the write buffer 141 is stored in the data input latch 321 of the plane 45-x by the first command 717, the address 718, the Upper page data 719, and the second command 720.

[0161] The memory I / F 12 similarly executes a sequence for transferring Upper page data to the data input latches 321 in the corresponding planes 45 for the remaining planes 45 excluding planes 45-x and planes 45-y from the T planes 45.

[0162] Then, the memory I / F 12 sends a first command 721, an address 722, Upper page data 723, and a second command 724 to the plane 45-y of the non-volatile memory chip 41. The first command 721 is a command "80h" or "85h". The address 722 specifies the plane block PBy to which the Upper page data 723 is written. The Upper page data 723 is user data for the Upper page to be written to the plane block PBy. The second command 724 is a command "10h" or "15h". The command "10h" or "15h" is a command to start a program based on the specified contents.

[0163] By the first command 721, address 722, upper page data 723, and second command 724, the upper page data 723 transferred from the write buffer 141 is stored in the data input latch 321 of plane 45-y, and in each of the T planes 45, the upper page data stored in the data input latch 321 is moved to the second program latch 322-2, and the lower page data, middle page data, and upper page data stored in the program latches 322-0, 322-1, and 322-3, respectively, are programmed into the plane block.

[0164] Specifically, the Upper page data 719 stored in the data input latch 321 of the plane 45-x is moved to the second program latch 322-2 of the plane 45-x. Then, in the plane 45-x, the Lower page data 703 stored in the 0th program latch 322-0, the Middle page data 711 stored in the first program latch 322-1, and the Upper page data 719 stored in the second program latch 322-2 are programmed into the plane block PBx.

[0165] Also, the Upper page data 723 stored in the data input latch 321 of the plane 45-y is moved to the second program latch 322-2 of the plane 45-y. Then, in the plane 45-y, the Lower page data 707 stored in the 0th program latch 322-0, the Middle page data 715 stored in the first program latch 322-1, and the Upper page data 723 stored in the second program latch 322-2 are programmed into the plane block PBy.

[0166] The above command sequence allows the memory I / F 12 to perform one FSP operation by the TLC method and the multi-plane program on the non-volatile memory chip 41 including the T planes 45. In this command sequence, for example, every time one page of user data is accumulated in the write buffer 141, the one page of user data is transferred from the write buffer 141 to the data input latch 321 of the non-volatile memory chip 41. In response to the transfer of the user data to the data input latch 321, the storage area in the write buffer 141 in which the user data was stored is released. In addition, the user data stored in the data input latch 321 is moved to the program latch 322. Therefore, in the memory system 3, not only the write buffer 141 but also the data input latch 321 and the program latch 322 are used as buffers for user data to be written to the non-volatile memory chip 41. Therefore, in the memory system 3, for example, the size of the write buffer 141 can be made smaller than that of the memory system 3A of the comparative example in which all pages of user data (here, T×3 pages of user data) programmed in a single FSP operation to the non-volatile memory chip 41A are accumulated in the write buffer 141A and then the user data is input to the non-volatile memory chip 41A.

[0167] When an interleaved write operation is performed on multiple nonvolatile memory chips 41, the memory I / F 12 performs, for example, the command sequence shown in Fig. 11 in parallel on each of the multiple nonvolatile memory chips 41. Also, the configurations of the command types, the number of latches 32, etc. described above are merely examples, and the write operation in the memory system 3 of the first embodiment can be applied to any configuration in which a certain amount of data is written collectively to one or more blocks.

[0168] 12A and 12B are flowcharts showing an example of the procedure of the write control process executed by the CPU 15. The write control process is a process for writing user data to the memory device 4. The CPU 15 executes the write control process in response to, for example, receiving a write command from the host 2. Here, a case where user data is written in parallel to S nonvolatile memory chips 41 is illustrated. Each of the S nonvolatile memory chips 41 includes T planes 45. S is an integer equal to or greater than 1. T is an integer equal to or greater than 1. In addition, in the write control process, data is written to a block (plane block) by a first method. The first method is a method in which M pages of data are written in one program operation (that is, M bits of data are written per memory cell). In the following, M is an integer equal to or greater than 2.

[0169] First, the CPU 15 sets each of variables i, j, and k to 0 (step S101). The variable i is used to identify one of the S nonvolatile memory chips 41. The variable j is used to identify one of the T planes 45. The variable k is used to identify one page of data among M pages of data written to one plane block in one program operation. For example, when three pages of data are written to one plane block in one program operation (i.e., when the first method is the TLC method), the variable k identifies any one of the Lower page, the Middle page, and the Upper page. Specifically, for example, the variable k that is 0 indicates the Lower page, the variable k that is 1 indicates the Middle page, and the variable k that is 2 indicates the Upper page.

[0170] Next, the CPU 15 determines whether one page of user data is stored in the write buffer 141 (step S102).

[0171] If one page of user data is not stored in the write buffer 141 (No in step S102), the process by the CPU 15 returns to step S102. That is, the CPU 15 waits until one page of user data is stored in the write buffer 141.

[0172] If one page of user data is stored in the write buffer 141 (Yes in step S102), the CPU 15 transfers the one page of user data from the write buffer 141 to the data input latch 321 of the j-th plane 45 in the i-th nonvolatile memory chip 41 (step S103). The CPU 15 releases the storage area in the write buffer 141 in which the transferred user data was stored (step S104). The CPU 15 updates the variable j by adding 1 to it (step S105). Then, the CPU 15 determines whether the updated variable j is equal to the number of planes T (step S106).

[0173] If the updated variable j is smaller than the number of planes T (No in step S106), the process by the CPU 15 returns to step S102. That is, the CPU 15 further performs a process for transferring one page of user data to the data input latches 321 of the j-th plane 45 in the i-th nonvolatile memory chip 41 based on the updated variable j. Therefore, the CPU 15 repeats the procedures from step S102 to step S106 until one page of user data is transferred to each of the data input latches 321 of the T planes 45 in the i-th nonvolatile memory chip 41.

[0174] If the updated variable j is equal to the number of planes T (Yes in step S106), the CPU 15 moves one page of user data from the data input latch 321 to the k-th program latch 322 in each of the T planes 45 in the i-th nonvolatile memory chip 41 (step S107), as shown in Fig. 12B. The CPU 15 sets the variable j to 0 (step S108). Then, the CPU 15 determines whether the variable k is equal to a value obtained by subtracting 1 from the number of pages M (step S109).

[0175] If the variable k is smaller than the number of pages M minus 1 (No in step S109), the CPU 15 updates the variable i by adding 1 to it (step S110). Then, the CPU 15 determines whether the updated variable i is equal to the number of nonvolatile memory chips S (step S111).

[0176] If the updated variable i is smaller than the number S of nonvolatile memory chips (No in step S111), the process by the CPU 15 returns to step S102 as shown in Fig. 12A. That is, the CPU 15 further performs a process for transferring one page of user data to the k-th program latch 322-k for each plane 45 for the i-th nonvolatile memory chip 41 based on the updated variable i.

[0177] If the updated variable i is equal to the number S of nonvolatile memory chips (Yes in step S111), the CPU 15 sets the variable i to 0 (step S112). Then, the CPU 15 updates the variable k by adding 1 to the variable k (step S113), and returns to step S102 as shown in Fig. 12A. That is, the CPU 15 further performs a process for transferring one page of user data to the k-th program latch 322-k for each plane 45 for each of the S nonvolatile memory chips 41 based on the updated variable k.

[0178] Also, when the variable k is equal to the number of pages M minus 1 (Yes in step S109), the CPU 15 performs the FSP operation on the i-th nonvolatile memory chip 41 (step S114). When the variable k is equal to the number of pages M minus 1, the M program latches 322 of the T planes 45 in the i-th nonvolatile memory chip 41 store user data to be written in one FSP operation on the i-th nonvolatile memory chip 41. In the FSP operation, the CPU 15 programs the stored user data into the T plane blocks included in the T planes 45, respectively. That is, in each of the T planes 45, the user data of M pages stored in the M program latches 322 are written to the plane block in the corresponding plane 45.

[0179] Next, the CPU 15 updates the variable i by adding 1 to the variable i (step S115). The CPU 15 determines whether the updated variable i is equal to the number S of nonvolatile memory chips (step S116).

[0180] If the updated variable i is smaller than the number S of nonvolatile memory chips (No in step S116), the process by the CPU 15 returns to step S102 as shown in Fig. 12A. That is, the CPU 15 further performs a process for transferring one page of user data to the k-th program latch 322-k for each plane 45 for the i-th nonvolatile memory chip 41 based on the updated variable i.

[0181] If the updated variable i is equal to the number S of nonvolatile memory chips (Yes in step S116), the CPU 15 determines whether there is data to be written to the subsequent string (step S117). For example, the CPU 15 determines whether there is a need to write data to the subsequent string in response to a write request from the host 2.

[0182] If there is data to be written to the subsequent string (Yes in step S117), the process by the CPU 15 returns to step S101 as shown in FIG. 12A, and a process for writing data to the subsequent string is performed.

[0183] If there is no data to be written to the subsequent string (No in step S117), the CPU 15 ends the write control process.

[0184] By the above-described write control process, when the CPU 15 performs FSP operations for each of the S nonvolatile memory chips 41 in parallel, the size of the write buffer 141 provided in the memory system 3 can be reduced. Specifically, the CPU 15 transfers one page of user data stored in the write buffer 141 to the data input latch 321 without waiting for all user data written in one FSP operation to be accumulated in the write buffer 141. The CPU 15 further transfers one page of user data stored in the data input latch 321 to the program latch 322. As a result, the user data written in one FSP operation is held in the latch 32 and the time spent in the write buffer 141 is shortened, so that the size of the write buffer 141 provided in the memory system 3 can be reduced.

[0185] Furthermore, by using the write order shown in FIG. 9 as the write order for the S nonvolatile memory chips 41, the size of the read buffer 142 can also be reduced.

[0186] Therefore, in the memory system 3, the size of the data buffer used when the host 2 accesses the nonvolatile memory chip 41 can be reduced.

[0187] Second embodiment In the memory system 3 of the first embodiment, the controller 6 performs a data transfer operation multiple times to transfer user data of a second size, which is smaller than user data of a first size written in one write operation (e.g., one FSP operation) to the nonvolatile memory chip 41, from the write buffer 141 to the latch 32. Then, the controller 6 writes the multiple pieces of user data of the second size, which have been transferred to the latch 32 in the multiple data transfer operations, to the memory cell array 33.

[0188] In contrast, the memory system 3 of the second embodiment further includes a configuration for making the user data non-volatile when a request to make the user data non-volatile is received from the host 2 while the size (third size) of the user data that has not yet been written to the memory cell array 33 of the non-volatile memory chip 41 after being received from the host 2 is less than the first size.

[0189] The configuration of the memory system 3 according to the second embodiment is similar to that of the memory system 3 according to the first embodiment. The memory system 3 according to the second embodiment is different from the memory system 3 according to the first embodiment in that the memory system 3 according to the second embodiment has a configuration for making user data non-volatile. The following mainly describes the differences from the first embodiment.

[0190] In response to the user data of the second size being accumulated in the write buffer 141, the write control unit 151 of the controller 6 transfers the user data of the second size to the data input latch 321 of the nonvolatile memory chip 41. That is, the write control unit 151 starts inputting data to the nonvolatile memory chip 41 before receiving, from the host 2, user data of the first size to be written in one FSP operation to the nonvolatile memory chip 41. In this case, it is not necessarily possible to receive user data necessary for one FSP operation from the host 2 after starting data input to the nonvolatile memory chip 41.

[0191] When the write control unit 151 receives a request to make the user data nonvolatile (e.g., a flash command) from the host 2 while the third size of the user data that has not yet been written to the memory cell array 33 of the nonvolatile memory chip 41 after being received from the host 2 is less than the first size, the write control unit 151 transfers dummy data of a fourth size, which is the first size minus the third size, to the latch 32 of the nonvolatile memory chip 41. Then, the write control unit 151 writes the user data of the third size and the dummy data of the fourth size to the memory cell array 33.

[0192] This allows the user data received from the host 2 to be made non-volatile even if a non-volatile request is received from the host 2 after data input to the non-volatile memory chip 41 has started and before the user data required for one FSP operation has been received from the host 2.

[0193] Therefore, in the memory system 3 of the second embodiment, the sizes of the write buffer 141 and the read buffer 142 can be reduced, and processing in response to a non-volatilization request from the host 2 can also be executed.

[0194] 13A and 13B are flowcharts showing an example of the procedure of the non-volatile process executed by the CPU 15 (more specifically, the write control unit 151). The non-volatile process is a process for non-volatileizing (i.e., writing to the non-volatile memory chip 41) user data that has been received from the host 2 and has not yet been written to the non-volatile memory chip 41. The CPU 15 executes the non-volatile process in response to receiving a non-volatile request from the host 2 while executing the write control process described above with reference to FIG. 12A and FIG. 12B. The values ​​of the variables i, j, and k used in the non-volatile process are assumed to be the values ​​of the variables i, j, and k in the write control process being executed, respectively. In addition, the number S of non-volatile memory chips, the number T of planes, and the number M of pages are common to the write control process.

[0195] First, the CPU 15 determines whether or not user data is stored in the write buffer 141 (step S201).

[0196] If user data is stored in the write buffer 141 (Yes in step S201), the CPU 15 determines whether the user data stored in the write buffer 141 is user data of one page or more (step S202).

[0197] If the user data stored in the write buffer 141 is one page or more of user data (Yes in step S202), the CPU 15 transfers one page of user data from the write buffer 141 to the data input latch 321 of the jth plane 45 in the ith non-volatile memory chip 41 (step S203), and proceeds to step S205.

[0198] If the user data stored in the write buffer 141 is less than one page of user data (No in step S202), the CPU 15 transfers one page of data consisting of the user data and dummy data to the data input latch 321 of the jth plane 45 in the ith nonvolatile memory chip 41 (step S204), and proceeds to step S205.

[0199] Then, the CPU 15 releases the storage area in the write buffer 141 in which the transferred user data has been stored (step S205), and proceeds to step S207.

[0200] Also, if no user data is stored in the write buffer 141 (No in step S201), the CPU 15 transfers one page of dummy data to the data input latch 321 of the jth plane 45 in the ith non-volatile memory chip 41 (step S206), and proceeds to step S207.

[0201] Next, the CPU 15 updates the variable j by adding 1 to the variable j (step S207). Then, the CPU 15 determines whether the updated variable j is equal to the number of planes T (step S208).

[0202] If the updated variable j is smaller than the number of planes T (No in step S208), the process by CPU 15 returns to step S201. That is, CPU 15 further performs a process for transferring one page of data to the data input latches 321 of the j-th plane 45 in the i-th nonvolatile memory chip 41 based on the updated variable j. Therefore, CPU 15 repeats the procedure from step S201 to step S208 until one page of data is transferred to each of the data input latches 321 of the T planes 45 in the i-th nonvolatile memory chip 41. The transferred one page of data is composed of at least one of user data and dummy data.

[0203] If the updated variable j is equal to the number of planes T (Yes in step S208), as shown in FIG. 13B, the CPU 15 moves one page of data from the data input latch 321 to the kth program latch 322 in each of the T planes 45 in the i-th non-volatile memory chip 41 (step S107).

[0204] The subsequent steps from step S210 to step S218 are the same as the steps from step S108 to step S116 of the write control process described above with reference to FIG. 12A and FIG. 12B. In step S107 of the write control process shown in FIG. 12B, one page of user data is transferred from the data input latch 321 to the k-th program latch 322-k. In contrast, in step S209 of the non-volatilization process shown in FIG. 13B, one page of user data transferred to the data input latch 321 in step S203, one page of data consisting of user data and dummy data transferred to the data input latch 321 in step S204, or one page of dummy data transferred in step S206 is transferred to the k-th program latch 322-k. The transferred data is written to the plane block by the FSP operation in each non-volatile memory chip 41.

[0205] By the above non-volatilization process, even if the amount of user data received from the host 2 is less than the amount of data required for the FSP operation, the CPU 15 can non-volatilize the user data received from the host 2 in response to a non-volatilization request. The CPU 15 can input data required for the FSP operation to the non-volatile memory chip 41 by transferring dummy data to the data input latch 321 and the program latch 322.

[0206] Third embodiment In the memory system 3 of the first embodiment, the controller 6 performs a data transfer operation multiple times to transfer user data of a second size, which is smaller than the user data of the first size written in one write operation to the nonvolatile memory chip 41, from the write buffer 141 to the latch 32. Then, the controller 6 writes the multiple pieces of user data of the second size, which have been transferred to the latch 32 in the multiple data transfer operations, to the memory cell array 33 in the first method.

[0207] In addition, the memory system 3 of the second embodiment has a configuration for making non-volatile data, which is the user data plus dummy data, using the first method when a request to make data non-volatile is received from the host 2 while the third size of the user data that has not yet been written to the memory cell array 33 of the non-volatile memory chip 41 after being received from the host 2 is less than the first size.

[0208] In contrast, the memory system 3 of the third embodiment has a configuration for making the user data input into the latch 32 non-volatile using a second method different from the first method when a request to make data non-volatile is received from the host 2 while the user data already input into the latch 32 is less than a first size.

[0209] The configuration of the memory system 3 according to the third embodiment is similar to that of the memory system 3 according to the first and second embodiments. The memory system 3 according to the third embodiment is different from the memory systems 3 according to the first and second embodiments in that the memory system 3 according to the third embodiment includes a configuration for making user data non-volatile by a second method. The following mainly describes the differences from the first and second embodiments.

[0210] The write control unit 151 of the controller 6 performs a data transfer operation multiple times to transfer user data of a second size, which is smaller than the user data of the first size written in one write operation to the nonvolatile memory chip 41, from the write buffer 141 to the latch 32 of the nonvolatile memory chip 41. Then, the write control unit 151 writes the multiple pieces of user data of the second size to the memory cell array 33 by the first method.

[0211] When the write control unit 151 receives a request to make the user data nonvolatile from the host 2 while the total size of one or more pieces of user data of the second size that have been transferred to the latch 32 of the nonvolatile memory chip 41 and have not yet been written to the memory cell array 33 is less than the first size, the write control unit 151 makes at least a part of the user data that has been input to the latch 32 nonvolatile by a second method different from the first method. The user data that has been input to the latch 32 is, for example, user data stored in at least one of the data input latch 321, the 0th program latch 322-0, the first program latch 322-1, and the second program latch 322-2. Specifically, the write control unit 151 writes at least a part of the user data that has been input to the latch 32 to another block in the plane 45 that includes a block (for example, plane block PB0, PB1, PB2, or PB3) that is the target of writing by the first method by the second method.

[0212] The first method is a method in which M bits of data are written per memory cell. The second method is a method in which N bits of data are written per memory cell. M is an integer equal to or greater than 2. N is a number smaller than M. For example, when the TLC method is used as the first method, the SLC method is used as the second method. Therefore, the size of data required for one program operation in the second method is smaller than the size of data required for one program operation in the first method.

[0213] 14 shows an example of a command sequence for the nonvolatile memory chip 41. This command sequence corresponds to one nonvolatile operation for one nonvolatile memory chip 41. Here, it is assumed that the nonvolatile operation is performed for the nonvolatile memory chip 41 including a plurality of planes 45. This command sequence is sent to the nonvolatile memory chip 41 by the memory I / F 12 under the control of, for example, the write control unit 151. An instruction to the nonvolatile memory chip 41 is given in units of a set of, for example, a first prefix command, a second prefix command, a first command, an address, and a second command.

[0214] First, the memory I / F 12 sends a first prefix command 801, a second prefix command 802, a first command 803, an address 804, and a second command 805 to the non-volatile memory chip 41. The first prefix command 801 is, for example, one of the commands “01h”, “02h”, and “03h”. The commands “01h”, “02h”, and “03h” are commands that specify the latch 32 in which the data to be programmed is stored among the data input latch 321 and the program latches 322-0, 322-1, and 322-2. The latch 32 specified by the first prefix command 801 is referred to as the first target latch 32. The data stored in the first target latch 32 is referred to as the first data. The second prefix command 802 is, for example, the command “A2h”. The command “A2h” is a command that specifies a second method for programming data. The first command 803 is a command “80h” or “85h”. The commands “80h” and “85h” are commands to start inputting data. The address 804 specifies a block (hereinafter referred to as a first block) to which the first data is to be programmed by the second method. The first block is another block in the plane 45 including the block in which the first data was to be programmed by the first method. The address 804 may further specify a string in the first block to which the first data is to be programmed by the second method. The second command 805 is, for example, a command “11h”. The command “11h” is a command to leave the input data as it is in the latch 32. When the memory I / F 12 performs non-volatilization operations on other planes 45 included in the non-volatile memory chip 41 in parallel, the memory I / F 12 sends the command “11h” as the second command 805.

[0215] A first prefix command 801, a second prefix command 802, a first command 803, an address 804, and a second command 805 specify that the first data stored in the first target latch 32 is to be programmed into a first block (more specifically, a string within the first block) in a second manner.

[0216] Similarly, for another plane 45, the memory I / F 12 executes a sequence to specify that data already input to one of the latches 32 is to be programmed in the second method in a block other than the block that was to be programmed in the first method.

[0217] Then, the memory I / F 12 sends the first prefix command 806, the second prefix command 807, the first command 808, the address 809, and the second command 810 to the non-volatile memory chip 41. The first prefix command 806 is, for example, one of the commands “01h”, “02h”, and “03h”. The latch 32 designated by the first prefix command 806 is referred to as the second target latch 32. The data stored in the second target latch 32 is referred to as the second data. The second prefix command 807 is, for example, the command “A2h”. The first command 808 is the command “80h” or “85h”. The address 809 designates a block (hereinafter referred to as the second block) in which the second data is to be programmed by the second method. The second block is another block in the plane 45 including the block in which the second data was to be programmed by the first method. The address 809 may further specify a string in a second block to program second data in a second manner. The second command 810 is, for example, the command "10h". The command "10h" is a command to start programming based on the specified content.

[0218] The first prefix command 806, the second prefix command 807, the first command 808, the address 809, and the second command 810 cause the data stored in the designated latch 32 to be programmed in the designated block (more specifically, the designated string in the designated block) in the designated manner. Specifically, the first data stored in the first target latch 32 is programmed in the first block in the second manner. Also, the second data stored in the second target latch 32 is programmed in the second block in the second manner. Note that when the designated latch 32 is the data input latch 321, the data stored in the data input latch 321 may be moved to the program latch 322 and then programmed in the designated block.

[0219] When data exceeding the size programmed in one program operation of the second method is stored in the data input latches 321 and program latches 322 of each plane 45, the memory I / F 12 repeatedly executes the command sequence shown in Fig. 14 while changing the latches 32 specified by the first prefix commands 801 and 806. The size of data written in one write operation of the second method is, for example, one page of data in one write operation of the SLC method.

[0220] By the above command sequence, the memory I / F 12 can perform a non-volatile operation on the non-volatile memory chip 41 including a plurality of planes 45. In this command sequence, the memory I / F 12 writes the data already input to the latch 32 to a block by the second method (for example, the SLC method). That is, the memory I / F 12 can write, for example, one page of data to a block by the SLC method without the constraints imposed when programming data by the FSP operation. Also, there is no need to input dummy data to the non-volatile memory chip 41 in order to write the data already input to the latch 32 by the first method (for example, the TLC method). Therefore, in the memory system 3, the data already input to the latch 32 can be non-volatile at high speed. Therefore, the memory system 3 can respond to a non-volatile request from the host 2 with low latency.

[0221] FIG. 15 is a flowchart showing an example of the procedure of the non-volatile process executed by the CPU 15. The non-volatile process is a process for non-volatileizing user data that has not yet been written to the non-volatile memory chip 41 after being received from the host 2. The CPU 15 executes the non-volatile process in response to receiving a non-volatile request from the host 2 while executing the write control process described above with reference to FIG. 12, for example. The CPU 15 executes this non-volatile process for, for example, each of the S non-volatile memory chips 41. The number S of non-volatile memory chips and the number T of planes are the same as those in the write control process. In addition, in this non-volatile process, data is programmed into blocks by the second method. The second method is a method in which N pages of data are programmed in one program operation (that is, N bits of data are programmed per memory cell).

[0222] First, the CPU 15 determines whether or not user data is stored in the P program latches 322 of each plane 45 in the nonvolatile memory chip 41 (step S301), where P is an integer equal to or greater than 1 and equal to or less than the number of pages M.

[0223] If no user data is stored in any of the program latches 322 of the planes 45 (No in step S301), the process by the CPU 15 proceeds to step S306.

[0224] When user data is stored in the P program latches 322 of each plane 45 (Yes in step S301), the CPU 15 sets 0 to a variable k (step S302). The variable k is used to identify one of the P program latches 322 in which user data is stored. The CPU 15 programs the user data stored in the k-th program latch 322-k in each of the T planes 45 in the second method to a block of the corresponding plane 45 (step S303). The block in which data is programmed in the second method is a block different from the block in which data is programmed in the first method (e.g., a block targeted for the FSP operation in the write control process). The CPU 15 may program the user data in the second method in parallel in the T planes 45. Next, the CPU 15 updates the variable k by adding 1 to the variable k (step S304). The CPU 15 determines whether the updated variable k is less than the number P of the program latches 322 in which user data is stored (step S305).

[0225] If the updated variable k is less than P (Yes in step S305), the process by the CPU 15 returns to step S303. That is, the CPU 15 further performs a process for writing the user data stored in the k-th program latch 322 in the second mode based on the updated variable k.

[0226] If the updated variable k is equal to P (No in step S305), the process by the CPU 15 proceeds to step S306.

[0227] Next, the CPU 15 determines whether or not user data is stored in the data input latches 321 in the Q planes 45 in the nonvolatile memory chip 41 (step S306). Q is an integer equal to or greater than 1 and equal to or less than the number of planes T.

[0228] When user data is stored in the data input latches 321 in the Q planes 45 (Yes in step S306), the CPU 15 programs the user data stored in the data input latches 321 in each of the Q planes 45 in the block in the corresponding plane 45 by the second method (step S307), and ends the non-volatilization process. When Q is 2 or more, the CPU 15 may write the user data in the second method in parallel in the Q planes 45. The CPU 15 may also write the user data stored in the data input latches 321 in the second method after transferring it to the program latches 322.

[0229] If no user data is stored in the data input latches 321 of any of the planes 45 (No in step S306), the CPU 15 ends the non-volatilization process.

[0230] By the above non-volatilization process, the CPU 15 can non-volatilize the user data stored in the data input latch 321 and the user data stored in the program latch 322 in accordance with a non-volatilization request from the host 2 using the second method. By non-volatilizing the user data using the second method in which N-bit data is written per memory cell, the CPU 15 can respond to the non-volatilization request with lower latency than when non-volatilizing the user data and the dummy data using the first method in which M-bit data is written per memory cell. In addition, since data is programmed in small data units (e.g., 4KB units) corresponding to the second method, for example, dummy data does not need to be input to the non-volatile memory chip 41 as data required for performing the FSP operation. In addition, the CPU 15 can write the user data stored in the write buffer 141 to a block in accordance with the second method in accordance with a non-volatilization request from the host 2.

[0231] As described above, according to the first to third embodiments, the size of the data buffer used when accessing the nonvolatile memory can be reduced. The write control unit 151 performs a data transfer operation multiple times to transfer data of a second size, which is smaller than data of a first size written in one write operation to the nonvolatile memory chip 41, from the write buffer 141 to the nonvolatile memory chip 41 (more specifically, the latch 32). The write control unit 151 writes the multiple pieces of data of the second size, which have been transferred to the nonvolatile memory chip 41 by the multiple data transfer operations, to the memory cell array 33 of the nonvolatile memory chip 41.

[0232] As a result, in the memory system 3, the size of the write buffer 141 can be reduced compared to the memory system 3A of the comparative example in which data transfer to the nonvolatile memory chip 41A starts after data of the first size is accumulated in the write buffer 141A. Furthermore, in the memory system 3, the size of the read buffer 142 can also be reduced by using the write order shown in Fig. 9. Therefore, in the memory system 3, the sizes of the write buffer 141 and the read buffer 142 used when the host 2 accesses the nonvolatile memory chip 41 can be reduced.

[0233] Each of the various functions described in the first to third embodiments may be realized by a circuit (processing circuit). An example of a processing circuit includes a programmed processor, such as a central processing unit (CPU). The processor executes each of the described functions by executing a computer program (a set of instructions) stored in a memory. The processor may be a microprocessor including an electric circuit. Examples of the processing circuit include a digital signal processor (DSP), an application specific integrated circuit (ASIC), a microcontroller, a controller, and other electric circuit components. Each of the components other than the CPU described in these embodiments may also be realized by a processing circuit.

[0234] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0235] 1...information processing system, 2...host, 3...memory system, 4...memory device, 5...DRAM, 6...controller, 11...host I / F, 12...memory I / F, 13...DRAM I / F, 14...SRAM, 15...CPU, 141...write buffer, 142...read buffer, 151...write control unit, 152...read control unit, 31...peripheral circuit, 32...latch, 321...data input latch, 322...program latch, 322-0...0th program latch, 322-1...1st program latch, 322-2...2nd program latch, 33...memory cell array, 41...non-volatile memory chip, 41-0...0th non-volatile memory chip, 41-1...1st non-volatile memory chip, 41-2...2nd non-volatile memory chip, 41-3...3rd non-volatile memory chip, 45...plane, 45-0...0th plane, 45-1...1st plane, 45-2...2nd plane, 45-3...3rd plane, 51...FW, 52...logical-physical address conversion table, 61...user data.

Claims

1. a non-volatile memory chip including a memory cell array; a write buffer capable of storing data received in response to a write request from a host; performing a data transfer operation a plurality of times to transfer data of a second size, the second size being smaller than data of a first size written in one write operation to the nonvolatile memory chip, from the write buffer to the nonvolatile memory chip; and a controller configured to write the plurality of data of the second size transferred to the non-volatile memory chip by the plurality of data transfer operations to the memory cell array. Memory system.

2. The controller: when a request to make the data nonvolatile is received from the host while a third size of the data that has been received from the host and has not yet been written to the memory cell array is less than the first size, dummy data having a fourth size obtained by subtracting the third size from the first size is transferred to the nonvolatile memory chip; configured to write the data of the third size and the dummy data of the fourth size to the memory cell array; 2. The memory system of claim 1.

3. the memory cell array includes a first block into which data is written by a first method, and a second block into which data is written by a second method different from the first method; The controller: writing the plurality of data of the second size to the first block in the first method; when a request for non-volatilization of data is received from the host while a total size of one or more pieces of data of the second size that have been transferred to the non-volatile memory chip and have not yet been written to the memory cell array is less than the first size, writing at least a part of the one or more pieces of data of the second size to the second block in the second method; 2. The memory system of claim 1.

4. The first method is a method in which M bits of data are written to each memory cell, The second method is a method in which N bits of data are written to each memory cell, The M is an integer of 2 or more, The N is a number smaller than the M.

4. The memory system of claim 3.

5. the controller is further configured to release a storage area in the write buffer in which the data of the second size is stored after performing the data transfer operation of transferring the data of the second size to the non-volatile memory chip.

2. The memory system of claim 1.

6. a total size of the plurality of data of the second size is equal to the first size; 2. The memory system of claim 1.

7. the non-volatile memory chip includes a plurality of latch circuits; the plurality of second size data are stored in the plurality of latch circuits, respectively; the controller is configured to write the plurality of second size data respectively stored in the plurality of latch circuits to the memory cell array; 2. The memory system of claim 1.

8. the non-volatile memory chip includes a first latch circuit and a second latch circuit; The controller: Transferring the first data of the second size stored in the write buffer to the first latch circuit; moving the first data stored in the first latch circuit to the second latch circuit; configured to write the first data stored in the second latch circuit to the memory cell array; 2. The memory system of claim 1.

9. the non-volatile memory chip includes a first plane and a second plane; The controller: performing a data transfer operation to transfer first data of the second size from the write buffer to the first plane; performing a data transfer operation to transfer second data of the second size from the write buffer to the second plane; configured to perform an operation of writing the first data to a block in the first plane and an operation of writing the second data to a block in the second plane in parallel; 2. The memory system of claim 1.

10. The non-volatile memory chip includes a block, The controller: performing a data transfer operation to transfer the first data of the second size from the write buffer to the non-volatile memory chip; performing a data transfer operation to transfer second data of the second size from the write buffer to the non-volatile memory chip; The first data and the second data are configured to be written to the block in a manner in which M bits of data are written per memory cell; The M is an integer of 2 or more.

2. The memory system of claim 1.

11. The write buffer is provided in the controller.

2. The memory system of claim 1.

12. a read buffer capable of storing data read from the non-volatile memory chip in response to a read request from the host; A memory system according to any preceding claim.

13. a non-volatile memory chip having a first plane including a first memory cell array, a first latch circuit, and a second latch circuit, and a second plane including a second memory cell array, a third latch circuit, and a fourth latch circuit; a write buffer capable of storing data received in response to a write request from a host; a first command set including a first command for instructing a start of data input, a first address for indicating a first block in the first memory cell array, first data to be written to the first block, and a second command for causing the first latch circuit to hold the first data; a second command set including a third command instructing a data input start, a second address indicating a second block in the second memory cell array, second data to be written to the second block, and a fourth command for moving the first data held in the first latch circuit to the second latch circuit and for moving the second data input to the third latch circuit to the fourth latch circuit; a third command set including a fifth command instructing to start data input, a third address indicating the first block, third data to be written to the first block, and a sixth command for causing the first latch circuit to hold the third data; a controller configured to transmit to the non-volatile memory chip a fourth command set including a seventh command instructing to start inputting data, a fourth address indicating the second block, fourth data to be written to the second block, and an eighth command instructing to program the first data, the second data, the third data, and the fourth data into the first memory cell array and the second memory cell array. Memory system.

14. the received data is data of a first size; the first data is data of a second size smaller than the first size; 14. The memory system of claim 13.

15. each of the first data, the second data, the third data, and the fourth data is data of a second size smaller than data of a third size written in one write operation to the non-volatile memory chip; The controller: when a request to make data nonvolatile is received from the host while a fourth size of data that has not yet been written to a memory cell array in the nonvolatile memory chip including the first memory cell array and the second memory cell array is less than the third size, dummy data of a fifth size obtained by subtracting the fourth size from the third size is transferred to the nonvolatile memory chip; configured to write the data of the fourth size and the dummy data of the fifth size to the memory cell array; 14. The memory system of claim 13.

16. each of the first data, the second data, the third data, and the fourth data is data of a second size smaller than data of a third size written in one write operation to the non-volatile memory chip; the first memory cell array includes a first block into which data is written using a first method, and a third block into which data is written using a second method different from the first method; The controller: writing the first data and the third data to the first block in the first manner; is configured to write at least a part of the one or more pieces of data of the second size to the third block in the second method when a request for non-volatilization of data is received from the host while a total size of the one or more pieces of data of the second size that have been transferred to the non-volatile memory chip and have not yet been written to memory cell arrays in the non-volatile memory chip including the first memory cell array and the second memory cell array is less than the third size.

14. The memory system of claim 13.

17. the controller is configured to transmit to the non-volatile memory chip a command set including a ninth command indicating a fifth latch circuit in the first plane in which a fifth data of the one or more second size data is stored, a tenth command specifying the second method, an eleventh command instructing a data input start, a fifth address specifying the third block, and a twelfth command instructing the fifth data to be held in the fifth latch circuit or to program the fifth data into the first memory cell array; 17. The memory system of claim 16.

18. The first method is a method in which M bits of data are written to each memory cell, The second method is a method in which N bits of data are written to each memory cell, The M is an integer of 2 or more, The N is a number smaller than the M.

17. The memory system of claim 16.

19. the controller is further configured to release a storage area in the write buffer in which the data of the second size is stored after performing a data transfer operation of transferring the data of the second size from the write buffer to the non-volatile memory chip.

19. A memory system according to any one of claims 14 to 18.

20. The write buffer is provided in the controller.

14. The memory system of claim 13.

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