Liquid crystal display device

Abstract

To suppress variation in electric characteristic and improve reliability in a transistor including an oxide semiconductor.SOLUTION: A semiconductor device includes a transistor. The transistor includes a first conductive film functioning as a first gate electrode, a first gate insulating film, a first oxide semiconductor film including a channel region, a second gate insulating film, and a second oxide semiconductor film and a second conductive film functioning as a second gate electrode. The second oxide semiconductor film includes a region with higher carrier density than the first oxide semiconductor film. The second conductive film has a region in contact with the first conductive film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. This relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. More specifically, the present invention relates to a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, The present invention relates to a device, a storage device, an imaging device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that configures thin-film transistors (FETs or TFTs) is attracting attention. The transistor is used in electronic devices such as integrated circuits (ICs) and image display devices. Silicon is widely used in semiconductor thin films that can be used in transistors. Semiconductor materials such as , are widely known, but oxide semiconductors are also attracting attention. It has been done.

[0005] For example, a transistor is fabricated using an In-Ga-Zn oxide as an oxide semiconductor. A technology for achieving this has been disclosed (see Patent Document 1). A technique for fabricating a transistor using an oxide thin film has been disclosed (see Patent Document 2).

[0006] In addition, a base insulating layer of the oxide semiconductor layer in which a channel is formed is heated to release oxygen. A semiconductor device is disclosed in which an insulating layer is used to reduce oxygen vacancies in the oxide semiconductor layer. (See Patent Document 3). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-96055 A [Patent Document 2] JP 2009-278115 A [Patent Document 3] JP 2012-009836 A Summary of the Invention [Problem to be solved by the invention]

[0008] As a transistor having an oxide semiconductor film, for example, an inverted staggered type (bottom gate structure) The oxide semiconductor When a transistor having a thin film is applied to a display device, it is preferable to use an inverted type transistor rather than a staggered type transistor. The manufacturing process of staggered transistors is relatively simple and the manufacturing costs are reduced. However, as the screen size of display devices increases, As image quality becomes increasingly finer, the gate electrode and source electrode of the inverted staggered transistor and Parasitic capacitance between the drain electrode and the signal delay increases, degrading the image quality of the display device. Therefore, in a staggered transistor including an oxide semiconductor film, Therefore, there is a need to develop a structure that has stable electrical characteristics and high reliability.

[0009] In addition, when a transistor is manufactured by using an oxide semiconductor film for a channel region, Oxygen vacancies formed in the channel region of the conductive film affect transistor characteristics. For example, when oxygen vacancies are formed in the channel region of the oxide semiconductor film, the oxygen Carriers are generated due to electron vacancies. Carriers are generated in the channel region of the oxide semiconductor film. When the oxide semiconductor film is generated, the electrical characteristics of a transistor having a channel region including the oxide semiconductor film change. For example, a shift in threshold voltage occurs. Also, the electrical characteristics of each transistor vary. Therefore, in the channel region of the oxide semiconductor film, oxygen vacancies occur. On the other hand, in a transistor using an oxide semiconductor film for a channel region, The oxide semiconductor film in contact with the source electrode and the drain electrode is In order to reduce the contact resistance with the rain electrode, it is preferable that the electrode has many oxygen vacancies and low resistance.

[0010] In view of the above problems, in one embodiment of the present invention, a transistor including an oxide semiconductor is Another object of the present invention is to suppress the change in electrical characteristics. An object of the present invention is to improve the reliability of a transistor including a semiconductor material. Another embodiment of the present invention provides a transistor which includes an oxide semiconductor and has high on-state current. Another object of one embodiment of the present invention is to provide an oxide semiconductor It is an object of the present invention to provide a transistor having a small off-state current. In the present invention, one object is to provide a semiconductor device with reduced power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device. An object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0011] Note that the above description of the object does not preclude the existence of other objects. It is not necessary to solve all of these problems. Problems other than those mentioned above can be solved by the description of the specification, etc. It is obvious from the description of the specification, etc. that other problems can be extracted. do. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a transistor, the transistor comprising: a first insulating film on the first conductive film, and a first conductive film with the first insulating film sandwiched therebetween. a first oxide semiconductor film having an overlapping region with a second insulating film on the first oxide semiconductor film; a second oxide semiconductor film having a region overlapping with the first oxide semiconductor film with a second insulating film interposed therebetween; a second conductive film on the first oxide semiconductor film; a third insulating film over the second oxide semiconductor film and the second conductive film; The semiconductor film has a channel region in contact with the second insulating film and a source region in contact with the third insulating film. The second oxide semiconductor film has a channel region and a drain region in contact with the third insulating film. The second conductive film has a region having a higher carrier density than the first conductive film, and the second conductive film has a region in contact with the first conductive film. It is a semiconductor device.

[0013] Another embodiment of the present invention is a semiconductor device including a transistor. The capacitor includes a first conductive film, a first insulating film on the first conductive film, and a second insulating film sandwiched between the first insulating film and the first insulating film. a first oxide semiconductor film having a region overlapping with the first conductive film; a second insulating film and a region overlapping with the first oxide semiconductor film with the second insulating film therebetween; a second oxide semiconductor film, a second conductive film over the second oxide semiconductor film, and a first oxide semiconductor film. a third insulating film over the conductive film, the second oxide semiconductor film, and the second conductive film; The first oxide semiconductor film has a channel region in contact with the second insulating film and a semiconductor region in contact with the third insulating film. a source region and a drain region in contact with the third insulating film, a first insulating film, a second insulating film, and a second insulating film; The second oxide semiconductor film has a first opening, and the second conductive film has a first opening. The semiconductor device has a region in contact with a first conductive film.

[0014] In each of the above structures, the second conductive film preferably has a light-shielding property. The sheet resistance of the film is preferably 10 Ω / square (Ω / sq.) or less.

[0015] In each of the above structures, the transistor further includes a third conductive film and a fourth conductive film. and the third conductive film is connected to the source through a second opening provided in the third insulating film. the fourth conductive film has a region electrically connected to the first oxide semiconductor film, The first oxide semiconductor is exposed in the drain region through a third opening provided in the insulating film of the third insulating film. It is preferred that the device has a region for electrical connection to the body membrane.

[0016] In each of the above structures, the first oxide semiconductor film and the second oxide semiconductor film At least one of the electrodes has In, Zn, and M (wherein M is Al, Ga, Y, or Sn). This is preferable.

[0017] In each of the above structures, when the second oxide semiconductor film contains In, Zn, and M, In this case, it is preferable that the first oxide has a region in which the content of In is equal to or greater than the content of M. When the semiconductor film contains In, Zn, and M, the content of In is equal to or greater than the content of M. It is preferable that the region has a

[0018] In each of the above structures, the third insulating film contains at least one of nitrogen and hydrogen. It is preferable to do so.

[0019] In each of the above structures, the first oxide semiconductor film has a crystal part, and the crystal part has a c-axis It is preferable that the film has an orientation.

[0020] Another embodiment of the present invention is a display device including the semiconductor device of any of the above embodiments and a display element. Another embodiment of the present invention is an electronic device including the semiconductor device of the above embodiment and a sensor. In this specification, the display device refers to an image display device. Connectors, such as FPC (Flexible Printed Circuit), Module with TCP (Tape Carrier Package) attached, T A module with a printed wiring board at the end of the CP, or a display device with a COG (Chip On Gauge) All modules with ICs directly mounted on glass are also available. This is included in one aspect of the invention. Effect of the Invention

[0021] According to one embodiment of the present invention, a transistor including an oxide semiconductor can be prevented from fluctuating in electrical characteristics. According to one embodiment of the present invention, a transistor including an oxide semiconductor can be formed. In addition, the reliability of the oxide semiconductor device can be improved. It is possible to provide a transistor having a large on-state current and including a nitride semiconductor. According to one embodiment of the present invention, a transistor including an oxide semiconductor and having low off-state current is provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided. Cut.

[0022] Note that the description of these effects does not preclude the existence of other effects. It is not necessary to have all of these effects. Effects other than these are described in the specification. The disclosure of the specification, drawings, claims, etc. is self-evident, and the disclosure of the specification, drawings, claims, etc. is self-evident. From this, it is possible to extract other effects. [Brief description of the drawings]

[0023] [Figure 1] 1A and 1B are diagrams illustrating a top view and a cross section of a semiconductor device. [Diagram 2] 1A and 1B are diagrams illustrating a top view and a cross section of a semiconductor device. [Diagram 3] 1A and 1B are cross-sectional views of a semiconductor device. [Figure 4] 1A and 1B are cross-sectional views of a semiconductor device. [Diagram 5]1A and 1B are cross-sectional views of a semiconductor device. [Figure 6] 1A and 1B are cross-sectional views of a semiconductor device. [Figure 7] 1A and 1B are cross-sectional views of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 14] FIG. 1 illustrates a range of atomic ratios of an oxide semiconductor according to one embodiment of the present invention. [Figure 15] A diagram explaining the InMZnO4 crystal. [Figure 16] FIG. 1 is a band diagram of a stacked structure of oxide semiconductors. [Figure 17] 1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Figure 18] Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Figure 19] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 20] Cross-sectional TEM image of a-like OS. [Figure 21] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 22] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 23] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 24] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 25] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 26] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 27] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 28] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 29] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 30] 1A and 1B are graphs and circuit diagrams illustrating one embodiment of the present invention. [Diagram 31] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 32] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 33] 1A to 1C are a block diagram, a circuit diagram, and waveform diagrams illustrating one embodiment of the present invention. [Diagram 34] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 35] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Diagram 36] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 37] FIG. 2 is a diagram illustrating a display module. [Figure 38] 1A to 1C are diagrams illustrating electronic devices. [Figure 39] 1A to 1C are diagrams illustrating electronic devices. [Diagram 40] FIG. 1 is a perspective view illustrating a display device. [Diagram 41] FIG. 11 is a diagram illustrating the measurement results of sheet resistance in the example. [Diagram 42] FIG. 11 is a diagram illustrating the measurement results of contact chain resistance in the example. [Diagram 43] 1A and 1B are cross-sectional views of a transistor according to an embodiment. [Diagram 44] FIG. 13 is a graph showing Id-Vg characteristics of a transistor in the embodiment. [Diagram 45] FIG. 13 is a graph showing Id-Vg characteristics of a transistor in the embodiment. [Diagram 46]13A to 13C are diagrams illustrating reliability test results of transistors in the examples. [Figure 47] FIG. 13 is a graph showing the Id-Vg characteristics of a transistor when irradiated with light in the embodiment. [Figure 48] FIG. 13 is a graph showing the Id-Vg characteristics of a transistor when irradiated with light in the embodiment. [Figure 49] 1A to 1C are TEM images of a transistor in accordance with an embodiment. [Figure 50] FIG. 13 is a diagram illustrating the results of a TDS analysis according to an embodiment. [Figure 51] FIG. 13 is a diagram illustrating the results of a TDS analysis according to an embodiment. [Figure 52] FIG. 13 is a diagram illustrating the results of a TDS analysis according to an embodiment. [Figure 53] FIG. 13 is a diagram illustrating the ESR measurement results according to the embodiment. [Figure 54] FIG. 1 is a diagram illustrating the measurement results of three signal spin densities according to an embodiment. [Figure 55] FIG. 13 is a diagram illustrating the results of a TDS analysis according to an embodiment. [Figure 56] FIG. 13 is a diagram illustrating the results of a TDS analysis according to an embodiment. [Figure 57] FIG. 13 is a diagram illustrating the results of a TDS analysis according to an embodiment. [Figure 58] 1A and 1B are cross-sectional views of a transistor according to an embodiment. [Figure 59] FIG. 13 is a graph showing Id-Vg characteristics of a transistor in the embodiment. [Figure 60] FIG. 13 is a graph showing Id-Vg characteristics of a transistor in the embodiment. [Figure 61] FIG. 13 is a graph showing Id-Vg characteristics of a transistor in the embodiment. [Figure 62] FIG. 13 is a graph showing Id-Vg characteristics of a transistor in the embodiment. [Figure 63] FIG. 13 is a graph showing Id-Vg characteristics of a transistor in the embodiment. [Figure 64] 13A to 13C are diagrams illustrating reliability test results of transistors in the examples. [Figure 65]FIG. 13 is a graph showing the Id-Vg characteristics of a transistor when irradiated with light in the embodiment. [Figure 66] FIG. 13 is a graph showing the Id-Vg characteristics of a transistor when irradiated with light in the embodiment. [Figure 67] FIG. 13 is a graph showing the Id-Vg characteristics of a transistor when irradiated with light in the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above description, and the embodiments and details thereof are not limited to those described above without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the embodiments described below. The terms of the present disclosure are not to be construed as being limited to the content.

[0025] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily shown in order to facilitate understanding. The actual position, size, range, etc. may not be shown. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc.

[0026] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. In some cases, the order of steps or layers may not be indicated. For example, "first" may be replaced with "second" or " " can be appropriately replaced with "the third" etc. The ordinal numbers used to identify an aspect of the present invention may not match those used in the present invention. be.

[0027] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used. The relationship is used for convenience in describing the drawings. The terms change depending on the direction in which each component is depicted. It can be rephrased appropriately depending on the situation.

[0028] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, The reference numerals are used commonly among different drawings.

[0029] In addition, even when the term "semiconductor" is used in this specification, for example, If the electrical conductivity is low enough, the material may have the properties of an insulator. The boundary between "insulators" and "insulators" is unclear, and it may not be possible to strictly distinguish them. In some cases, the term "semiconductor" in the above can be replaced with "insulator." In some cases, the term "insulator" in the specification can be replaced with "semiconductor." In some cases, the term "insulator" in this specification can be rephrased as "semi-insulator." .

[0030] In addition, even when the term "semiconductor" is used in this specification, for example, If the electrical conductivity is high enough, it may have the properties of a "conductor". The boundary between the term "conductor" and the term "electrical conductor" is unclear, and it may not be possible to strictly distinguish between them. In some cases, the term "semiconductor" in the above can be replaced with "conductor." The term "conductor" in the specification etc. may be replaced with "semiconductor" in some cases.

[0031] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A current flows through the drain, the channel region, and the source. In this specification and the like, the channel region is a region through which a current mainly flows. This refers to.

[0032] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably.

[0033] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). The source region or the channel region This refers to the distance between the drain (drain region or drain electrode) and the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one of the values, maximum The value may be the minimum or average value.

[0034] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the electrode (the area where the current flows) forms a channel. This refers to the length of the part of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. That is, The channel width of a transistor may not be determined to a single value. In the fine print, the channel width is any one of the values ​​in the region where the channel is formed, the maximum The value may be the minimum or average value.

[0035] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." The term "connection" is not particularly limited as long as it is possible to transmit and receive electrical signals between the connection objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. switching elements, resistor elements, inductors, capacitors, and other elements with various functions This includes children, etc.

[0036] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, voltage can be replaced with electric potential. be.

[0037] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to:

[0038] In this specification and the like, unless otherwise specified, the off-state current refers to the current that occurs when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise specified, for n-channel transistors, V is the voltage between the gate and source When gs is lower than the threshold voltage Vth, the gate and This refers to a state in which the voltage Vgs between the n-channel transistors is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage between the gate and source, Vgs, that is, the threshold voltage, Vt This may refer to the drain current when it is lower than h.

[0039] The off-state current of a transistor may depend on Vgs. The off-state current is I or less if there exists a Vgs value at which the off-state current of the transistor is I or less. The off-state current of a transistor is the current that flows through it in the off-state at a given Vgs. , an off-state at Vgs within a given range or a sufficiently reduced off-current is obtained. In some cases, it may refer to the off-state current at Vgs.

[0040] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -1 3 A, and the drain current at Vgs -0.5 V is 1×10 -19 A and Vg The drain current at s = -0.8 V is 1 × 10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: , or 1×10 when Vgs is in the range of -0.5V to -0.8V -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 There are cases where it is said to be A or lower. The drain current of the transistor is 1×10 -22 A or less Vgs exists. Therefore, the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0041] In this specification, the off-state current of a transistor having a channel width W is expressed as It is sometimes expressed as the current value that flows per watt. Also, for a given channel width (for example, 1 μm), In the latter case, the unit of the off-state current is current / length. It may be expressed in units with an element (e.g., A / μm).

[0042] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the operating temperature is room temperature, 60°C, 85°C, 95°C, or 125°C. Or, the reliability of a semiconductor device including the transistor may be guaranteed. The temperature at which the transistor is certified, or the temperature at which a semiconductor device or the like that contains the transistor is used (e.g. For example, it may represent the off-state current at a temperature equal to or higher than 5° C. and equal to or lower than 35° C. The off-state current of a transistor is I or less at room temperature, 60°C, 85°C, 95°C, and 125°C. ° C., the temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or The temperature at which the semiconductor device containing the transistor is used (for example, 5°C to 35°C) There exists a value of Vgs at which the off-state current of the transistor at any one of the temperatures is I or less. This may refer to the fact that...

[0043] The off-state current of a transistor may depend on the voltage Vds between the drain and source In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or In some cases, it indicates the off-state current at 20 V. In other cases, it indicates the off-state current at 20 V. Vds that guarantees the reliability of semiconductor devices, or semiconductor devices including the transistor The term may refer to the off-state current at Vds used in the transistor off-state. The current is equal to or less than I when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device in which the transistor is used, or Vds used in semiconductor devices, etc., where the off-state current of the transistor is I or less This may refer to the existence of a gs value.

[0044] In the above description of the off-state current, the drain may be read as the source. The current may also refer to the current through the source when the transistor is in the off state.

[0045] In this specification and the like, the term "leak current" may be used to mean the same thing as the "off current." In this specification, the off-state current refers to, for example, the current flowing when a transistor is in an off state. , may refer to the current flowing between the source and drain.

[0046] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it includes the case where the angle is between 85° and 95°. refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0047] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0048] (Embodiment 1) In this embodiment, a semiconductor device and a manufacturing method of the semiconductor device according to one embodiment of the present invention will be described. An example will be described below with reference to FIGS.

[0049] <Configuration Example 1 of Semiconductor Device> FIG. 1A is a top view of a transistor 100 included in a semiconductor device of one embodiment of the present invention. FIG. 1B is a cross-sectional view taken along the dashed line X1-X2 in FIG. FIG. 1(C) is a cross-section taken along dashed line Y1-Y2 shown in FIG. 1(A). In FIG. 1A, for clarity, components of a transistor 100 are shown. Some parts (such as the substrate 102 and the insulating film) are omitted in the figure.

[0050] The direction of the dashed line X1-X2 in FIG. 1A corresponds to the channel length of the transistor 100. The (L) direction and the dashed line Y1-Y2 direction are called the channel width (W) direction of the transistor 100. It may be referred to as.

[0051] The transistor 100 includes a first gate electrode (also called a bottom gate electrode) on a substrate 102. a conductive film 106 which functions as an insulating film; an insulating film 104 on the substrate 102 and the conductive film 106; An oxide semiconductor film 108 on the insulating film 104, an insulating film 110 on the oxide semiconductor film 108, A second gate electrode (also called a top gate electrode) is formed on the insulating film 110. The conductive film 112, the conductive film 114, the insulating film 104, the oxide semiconductor film 108, and the oxide semiconductor The oxide semiconductor film 10 includes an insulating film 112 and an insulating film 116 over the conductive film 114. A channel 8 overlaps with the oxide semiconductor film 112 and the conductive film 114 and is in contact with the insulating film 110. A channel region 108i contacting the insulating film 116, a source region 108s contacting the insulating film 116, and a and a drain region 108d.

[0052] The transistor 100 also includes an insulating film 118 on the insulating film 116, an insulating film 116 and an insulating Through an opening 141s provided in the film 118, an oxide semiconductor A conductive film 120s electrically connected to the conductive film 108, and an insulating film 116 and an insulating film 118 The oxide semiconductor film 1 is exposed to the drain region 108d through an opening 141d provided in the drain region 108d. 08. The semiconductor device further includes a conductive film 120d electrically connected to the semiconductor device 120.

[0053] In this specification and the like, the insulating film 104 is referred to as a first insulating film, and the insulating film 110 is referred to as a second insulating film. The insulating film 116 is referred to as a third insulating film, and the insulating film 118 is referred to as a fourth insulating film. In the transistor 100, the insulating film 104 may be a first gate insulating film. The insulating film 110 functions as a second gate insulating film. Therefore, in this specification and the like, the insulating film 104 is referred to as a first gate insulating film, and the insulating film 110 is referred to as a second gate insulating film. The conductive film 120s may be referred to as a second gate insulating film. The conductive film 120d functions as a drain electrode. In the detailed description, the conductive film 120s is referred to as a source electrode and the conductive film 120d is referred to as a drain electrode. This may be the case.

[0054] The oxide semiconductor film 112 has a function of supplying oxygen to the insulating film 110. The film 112 has a function of supplying oxygen to the insulating film 110, and thus the insulating film 110 does not contain excess oxygen. By having the insulating film 110 have an excess oxygen region, the oxide Providing the excess oxygen in the semiconductor film 108, more specifically in the channel region 108i Therefore, a highly reliable semiconductor device can be provided.

[0055] In order to supply excess oxygen to the oxide semiconductor film 108, Excess oxygen may be supplied to the insulating film 104 formed below the insulating film 8. The oxygen contained in the insulating film 104 is used to form a source region 108s of the oxide semiconductor film 108 and The source region 108s and the drain region 108d may also be supplied with a current. When excess oxygen is supplied to the source region 108s and the drain region 108d, the resistance of the source region 108s and the drain region 108d increases. The resistance may be high.

[0056] On the other hand, in the structure in which the insulating film 110 formed above the oxide semiconductor film 108 contains excess oxygen, By forming the semiconductor layer 108 in this manner, it is possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, the channel region 108i, the source region 108s, and the drain region 108 After supplying excess oxygen to the source region 108s and the drain region 108d, All you have to do is selectively increase the rear density.

[0057] The insulating film 116 contains at least one of nitrogen and hydrogen. By using a structure containing at least one of the oxide semiconductor film 108 and the oxide At least one of nitrogen and hydrogen can be supplied to the semiconductor film 112. As a result, A source region 108s and a drain region 108d are formed in the oxide semiconductor film 108. can.

[0058] In addition, the oxide semiconductor film 112 is formed by supplying oxygen to the insulating film 110 and then Alternatively, at least one of nitrogen and hydrogen is supplied from the conductive film 114, so that the In other words, a donor level is formed in the oxide semiconductor film 112, and the carrier density is increased. It also functions as an oxide conductor (OC). Therefore, the oxide semiconductor film 112 is formed by arranging at least the channel region 112 of the oxide semiconductor film 108. The carrier density is higher than that of the 08i.

[0059] In general, oxide semiconductors have a large energy gap and are therefore transparent to visible light. On the other hand, an oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. Therefore, the effect of absorption due to donor levels is small in oxide conductors, and they are oxidative to visible light. Therefore, light does not enter the oxide semiconductor film 112. For this purpose, the conductive film 114 is preferably provided over the oxide semiconductor film 112.

[0060] The conductive film 114 is preferably made of a material having a light-shielding property. In addition, a material having a high conductivity is preferable. In other words, it is preferable that the sheet resistance is low. Specifically, the sheet resistance of the conductive film 114 is , preferably 100 Ω / sq. or less, and more preferably 10 Ω / sq. or less. Therefore, the conductive film 114 preferably contains a metal.

[0061] In addition, the conductive film 114 has a function of supplying at least one of nitrogen and hydrogen in excess. As a result, at least one of nitrogen and hydrogen is introduced into the channel region 108i of the oxide semiconductor film 108. Therefore, the conductive film 114 is preferably made of at least nitrogen and hydrogen. In addition, the conductive film 114 has a low function of supplying either nitrogen or hydrogen. At least one of them preferably has a low ability to transmit light.

[0062] In addition, the source region 108s and the drain region 108d of the oxide semiconductor film 108 and the oxide semiconductor film 112 may each contain an element that forms oxygen vacancies. Representative elements that form the oxygen vacancies include hydrogen, boron, carbon, nitrogen, and fluorine. , phosphorus, sulfur, chlorine, and rare gases. Representative examples of rare gas elements include helium, Examples of fluorine include fluorine, neon, argon, krypton, and xenon.

[0063] When an impurity element is added to an oxide semiconductor film, a bond between a metal element and oxygen in the oxide semiconductor film is formed. The bond is broken, and oxygen vacancies are formed. Alternatively, an impurity element is added to the oxide semiconductor film. Then, oxygen that has been bonded to a metal element in the oxide semiconductor film is bonded to an impurity element, and the metal element As a result, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The carrier density increases and the conductivity becomes higher.

[0064] In the transistor 100, the side edge of the insulating film 110 and the oxide semiconductor film 112 It is preferable that the side edge of the conductive film 114 is aligned with the side edge of the conductive film 114. In the transistor 100, the upper end of the insulating film 110 and the upper end of the oxide semiconductor film 112 are The upper end of the oxide semiconductor film 112 and the lower end of the conductive film 114 are approximately aligned. For example, the insulating film 110 is processed using the conductive film 114 as a mask. The structure can be as follows.

[0065] The transistor 100 includes an insulating film 104, an insulating film 110, and an oxide semiconductor film 11. 2, an area where the conductive film 106 and the conductive film 114 are in contact with each other is provided through an opening 143. Therefore, the conductive film 106 and the conductive film 114 have the same potential. is given.

[0066] In order to reduce the power consumption of the transistor 100 or to improve the electrical characteristics of the transistor 100 In order to stabilize the contact resistance between the conductive film 106 and the conductive film 114, Alternatively, it is preferable that the contact chain resistance is low.

[0067] In this manner, the transistor 100 has a gate electrode above and below the oxide semiconductor film 108. It has a functioning conductive film.

[0068] ≪S-channel structure≫ As shown in FIG. 1C, the oxide semiconductor film 108 is formed by forming a first gate insulating film and a second gate insulating film. A conductive film 106 functioning as a first gate electrode and a second gate insulating film are sandwiched between the conductive film 106 and the second gate electrode. The conductive film 114 is sandwiched between the oxide semiconductor film 112 which functions as a gate electrode. The length of the oxide semiconductor film 106 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction. The length of the oxide semiconductor film 112 in the channel width direction is longer than that of the oxide semiconductor film 108. The length of the conductive film 114 in the channel width direction is longer than the length of the conductive film 114 in the channel width direction. The length of the conductive film 106 and the conductive film 11 is longer than the length of the conductive film 108 in the channel width direction. The opening 14 is provided in the insulating film 104, the insulating film 110, and the oxide semiconductor film 112. Since the oxide semiconductor film 1 has a contact region at 43 and the two are electrically connected to each other, At least one of the side surfaces of the channel width direction of the gate electrode 08 is connected to the conductive film 114 via the insulating film 110. That is, the entire channel width direction of the oxide semiconductor film 108 faces the first gate The insulating film and the second gate insulating film are disposed between the conductive film 106 and the conductive film 114 .

[0069] In other words, in the channel width direction of the transistor 100, the conductive film 106 and the conductive The film 114 is connected to the oxide semiconductor film 108 via the first gate insulating film and the second gate insulating film. The structure surrounds the above.

[0070] With such a structure, the oxide semiconductor film 108 included in the transistor 100 can be A conductive film 106 functioning as a first gate electrode and a conductive film 107 functioning as a second gate electrode. The transistor 100 can be electrically surrounded by the electric field of the conductive film 114. An oxide film in which a channel region is formed by the electric field of the first gate electrode and the second gate electrode. The device structure of a transistor that electrically surrounds a semiconductor film is called the Surrounded channel. This can be called a nel (abbreviation: S-channel) structure.

[0071] Since the transistor 100 has an S-channel structure, the conductive film 106 and the conductive The film 114 effectively applies an electric field to the oxide semiconductor film 108 to induce a channel. Therefore, the current driving capability of the transistor 100 is improved, and a high on-state current can be obtained. It is also possible to increase the on-current, It is possible to miniaturize the transistor 100. In addition, the transistor 100 has a conductive Since the transistor 100 has a structure surrounded by the film 106 and the conductive film 114, The mechanical strength can be increased.

[0072] In addition, with the above structure, carriers can flow in the oxide semiconductor film 108. The region is a region between the insulating film 104 side of the oxide semiconductor film 108 and the insulating film 11 side of the oxide semiconductor film 108. 0 side and further into the oxide semiconductor film 108. 0 increases the amount of carrier movement. As a result, the on-current of the transistor 100 increases. At the same time, the field effect mobility increases, specifically, when the field effect mobility is 10 cm 2 / V· Note that the field effect mobility here is the mobility as a physical property value of the oxide semiconductor film. It is not an approximation of the current driving force in the saturation region of a transistor, but an index of the current driving force in the saturation region. is the field effect mobility.

[0073] An opening 143 is formed in the channel width direction of the transistor 100. An opening different from the opening 143 is formed on the opposite side of the oxide semiconductor film 108 from the opening 143. Good too.

[0074] <Components of Semiconductor Device> The components included in the semiconductor device of this embodiment will be described in detail below.

[0075] <Oxide semiconductor film> The oxide semiconductor film 108 in the transistor 100 according to one embodiment of the present invention includes an oxide An oxide semiconductor can be used.

[0076] The oxide semiconductor preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. One or more of these may be included.

[0077] Here, a case will be considered in which the oxide semiconductor contains indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Applicable elements for element M include boron, silicon, titanium, iron, nickel, and germanium. Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Tantalum However, the element M may be a combination of multiple of the above elements. It's okay to combine them.

[0078] First, referring to FIG. 14(A), FIG. 14(B), and FIG. 14(C), a semiconductor device according to one embodiment of the present invention will be described. Regarding the preferable range of the atomic ratio of indium, the element M, and zinc contained in the oxide semiconductor, The atomic ratio of oxygen is not shown in FIG. The atomic ratios of indium, element M, and zinc in the body are [In] and [M], respectively. , and [Zn].

[0079] In FIG. 14(A), FIG. 14(B), and FIG. 14(C), the dashed lines indicate [In]:[M] :[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1, α is -1 or more and 1 or less) (below), the number of atoms is [In]:[M]:[Zn]=(1+α):(1-α):2 The ratio line, [In]:[M]:[Zn]=(1+α):(1-α):3 atomic ratio The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):4 The line and the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5 This represents the line where

[0080] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0, The line where the data is 0 or more) and the atomic ratio of [In]:[M]:[Zn]=1:2:β The line where the atomic ratio of [In]:[M]:[Zn]=1:3:β is :[M]:[Zn]=1:4:β atomic ratio line, [In]:[M]:[Zn] The line with the atomic ratio of [In]:[M]:[Zn]=5:1:β This represents the line that represents the atomic ratio.

[0081] In addition, the atomic ratio of [In]:[M]:[Zn]=0:2:1 shown in FIG. 14 or Oxide semiconductors with values ​​close to this range tend to have a spinel type crystal structure.

[0082] 14A and 14B show a structure in which an oxide semiconductor according to one embodiment of the present invention has An example of a preferred range of the atomic ratio of indium, element M, and zinc is shown.

[0083] As an example, FIG. 15 shows InMZn where [In]:[M]:[Zn]=1:1:1. Figure 15 shows the crystal structure of InMZ when observed from a direction parallel to the b-axis. The crystal structure of nO4 is shown in FIG. 15. The metal element in the (M,Zn) layer below represents element M or zinc. In this case, The ratio of element M to zinc is equal. Element M and zinc can be substituted, and the arrangement is irregular. This is the rule.

[0084] InMZnO4 has a layered crystal structure (also called a layered structure), as shown in Figure 15. The layer containing indium, indium, and oxygen (hereinafter referred to as the In layer) is 1, while the (M,Zn) layer is 2. It becomes.

[0085] Indium and element M can be substituted for each other. Therefore, the elements of the (M, Zn) layer The element M can be replaced with indium and expressed as an (In,M,Zn) layer. In that case, In It has a layered structure with one layer and two (In,M,Zn) layers.

[0086] In addition, an oxide semiconductor with an atomic ratio of [In]:[M]:[Zn]=1:1:2 is I It has a layered structure with one n layer and three (M,Zn) layers. That is, [In] and [M When the oxide semiconductor crystallizes, the (M ,Zn) layer ratio increases.

[0087] However, in the oxide semiconductor, the number of In layers is 1 and the number of (M, Zn) layers is a non-integer. In this case, there may be multiple types of layered structures in which the number of In layers is 1 and the number of (M, Zn) layers is an integer. For example, when [In]:[M]:[Zn]=1:1:1.5, the In layer is 1: The layered structure with two (M, Zn) layers and the layered structure with three (M, Zn) layers are mixed. In some cases, a layered structure may result.

[0088] For example, when an oxide semiconductor is formed by a sputtering device, the atomic ratio of the target In particular, depending on the substrate temperature during film formation, the target In some cases, the [Zn] of the film may be smaller than the [Zn] of the substrate.

[0089] In addition, a plurality of phases may coexist in an oxide semiconductor (eg, two-phase coexistence, three-phase coexistence, etc.). For example, in the atomic ratio [In]:[M]:[Zn]=0:2:1, which is close to the atomic ratio In [In], two phases, a spinel type crystal structure and a layered crystal structure, tend to coexist. At the atomic ratio near the atomic ratio of [M]:[Zn]=1:0:0, Two phases, a crystalline structure with a silicide layer and a layered crystalline structure, tend to coexist. When these coexist, grain boundaries form between different crystal structures. may be formed.

[0090] In addition, by increasing the indium content, the carrier mobility (electron transfer) of the oxide semiconductor is improved. This is because the oxide semiconductor having indium, element M and zinc can be In conductors, the s-orbitals of heavy metals mainly contribute to carrier conduction, and the indium content By increasing the indium content, the area where the s orbitals overlap becomes larger. Oxide semiconductors with a high indium content have a higher carrier mobility than oxide semiconductors with a low indium content. This is because

[0091] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0 and its In the atomic ratios near the values ​​(eg, region C shown in FIG. 14C), the insulating properties are high.

[0092] Therefore, the oxide semiconductor according to one embodiment of the present invention has high carrier mobility and a grain boundary. The atomic ratio shown in region A in FIG. 14(A) is favorable for forming a layered structure with few atoms. preferable.

[0093] In addition, in the region B shown in FIG. 14B, [In]:[M]:[Zn]=4:2:3 to 4 .1 and its neighboring values. For example, the atomic ratio [In]:[M] The oxide semiconductor having the atomic ratio shown in region B is In particular, it is an excellent oxide semiconductor having high crystallinity and high carrier mobility.

[0094] The condition for an oxide semiconductor to form a layered structure is not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. However, depending on the formation conditions, a layered structure may or may not be formed. The illustrated region is a region showing the atomic ratio in which the oxide semiconductor has a layered structure. The boundaries between areas A and C are not strict.

[0095] Next, a structure in which an oxide semiconductor is used for a transistor will be described.

[0096] By using an oxide semiconductor for a transistor, carrier scattering at grain boundaries can be reduced. This allows the realization of a transistor with high field effect mobility. Moreover, a highly reliable transistor can be realized.

[0097] In addition, an oxide semiconductor with low carrier density is used for a channel region of a transistor. For example, the oxide semiconductor has a carrier density of 8×10 11 / cm 3 Less than, good Preferably 1×10 11 / cm 3 less than 1×10 10 / cm 3 Less than , 1×10 -9 / cm 3 That should be enough.

[0098] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a carrier generation source. Since the carrier density is low, the carrier density can be reduced. Intrinsic oxide semiconductors have a low density of defect states and therefore a low density of trap states. There are cases.

[0099] In addition, the time required for the charge trapped in the trap level of the oxide semiconductor to disappear is Therefore, the trap level density is high. In a transistor in which a channel region is formed in a thin oxide semiconductor, the electrical characteristics may become unstable. There is a match.

[0100] Therefore, in order to stabilize the electrical characteristics of a transistor, the oxide semiconductor in the channel region It is effective to reduce the impurity concentration in the oxide semiconductor. In order to achieve this, it is preferable to also reduce the impurity concentration in the adjacent films. Examples include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0101] Here, the influence of each impurity in an oxide semiconductor will be described.

[0102] When oxide semiconductors contain silicon or carbon, which is one of the group 14 elements, they become oxidized. Defect levels are formed in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (secondary ion mass spectrometry) (SIMS: Secondary Ion Mass Spectrometry) The concentration that can be obtained is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 a toms / cm 3 The following applies.

[0103] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, the defect level is reduced. Therefore, alkali metals or alkaline earth metals A transistor that uses an oxide semiconductor containing Therefore, the alkali metal or alkali metal in the oxide semiconductor in the channel region is easily It is preferable to reduce the concentration of alkaline earth metals. The concentration of alkali metal or alkaline earth metal in the oxide semiconductor is set to 1×10 18 atom s / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0104] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and As a result, the oxide semiconductor containing nitrogen is channeled. The transistor in the channel region tends to be normally on. In the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible. For example, The nitrogen concentration in the semiconductor was 5×10 19 atoms / cm 3 Less than, good Preferably 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0105] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the carrier, In some cases, hydrogen atoms are formed by bonding with oxygen atoms that bond with metal atoms. Therefore, the oxide semiconductor containing hydrogen can generate electrons that are carriers. A transistor having an oxide in the channel region tends to have a normally-on characteristic. It is preferable that the amount of hydrogen in the semiconductor is reduced as much as possible. The hydrogen concentration measured by SIMS in the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than 5×1 0 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than Let us assume that.

[0106] By using an oxide semiconductor with sufficiently reduced impurities for the channel region of a transistor, , and stable electrical characteristics can be imparted.

[0107] In addition, the oxide semiconductor film has an energy gap of 2 eV or more, or 2.5 eV or more. Alternatively, it is preferably 3 eV or more.

[0108] The thickness of the oxide semiconductor film is 3 nm to 200 nm, preferably 3 nm to 100 nm. 00 nm or less, and more preferably 3 nm or more and 60 nm or less.

[0109] In addition, when the oxide semiconductor film is an In-M-Zn oxide film, the In-M-Zn oxide film is formed. The atomic ratio of the metal elements in the sputtering target used for the sputtering was In:M:Zn. =1:1:0.5, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, I n:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2 :1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M: Zn=5:1:7, etc. is preferred.

[0110] The atomic ratio of metal elements in the oxide semiconductor film to be formed is set to the above-mentioned sputtering ratio. The atomic ratio of metal elements contained in the target varies by about ±40%. For example, a sputtering target with an atomic ratio of In:Ga:Zn=4: When 2:4.1 is used, the atomic ratio of the oxide semiconductor film to be formed is In:Ga:Zn= In some cases, the atomic ratio is around 4:2:3. In the case where In:Ga:Zn=5:1:7 is used, the atomic ratio of the oxide semiconductor film to be formed is In some cases, the ratio is approximately In:Ga:Zn=5:1:6.

[0111] On the other hand, the source region 108s and the drain region 108d are in contact with the insulating film 116. The source region 108s and the drain region 108d are in contact with the insulating film 116. 116 to the source region 108s and the drain region 108d, Since one of them is added, the carrier density becomes high.

[0112] Note that the oxide semiconductor film 108 is not limited to the above structure and may be any structure as required for a transistor. The appropriate composition is selected according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the capacitor. In order to obtain the required semiconductor characteristics of the transistor, an oxide Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance of semiconductor film It is preferable to appropriately adjust the spacing, density, etc.

[0113] The oxide semiconductor film 108 may have a non-single crystal structure. CAAC-OS (C Axis Aligned Crystalline Ox ide Semiconductor), polycrystalline structure, microcrystalline structure (described later), or amorphous structure Among non-single crystal structures, the amorphous structure has the highest defect level density and CAAC -OS has the lowest defect state density.

[0114] Note that the oxide semiconductor film 108 may have an amorphous structure, a microcrystalline structure, or a polycrystalline structure. a monolayer film having two or more of a CAAC-OS region, a CAAC-OS region, and a single crystal structure region, or The film may have a laminated structure.

[0115] In the oxide semiconductor film 108, the channel region 108i and the source region 108s The crystallinity of the oxide semiconductor film 108c may be different from that of the drain region 108d. In the case of 108, the source region 108s and the drain region 108 are closer to each other than the channel region 108i. The source region 108s and the drain region 108d may have a lower crystallinity. When an impurity element is added to the source region 108s and the drain region 108d, This is because damage occurs and the crystallinity decreases.

[0116] The oxide semiconductor film 112 can be formed using a material similar to that of the oxide semiconductor film 108 described above. For example, the oxide semiconductor film 112 can be formed using the following method. In oxide, In-Sn oxide, In-Zn oxide, In-Ga oxide, Zn oxide, A In-Zn oxide, In-Ga-Zn oxide, etc. can be used. It is preferable to use an oxide semiconductor such as In--Sn oxide or In--Ga--Zn oxide. The film 112 may be made of indium tin oxide (ITO), indium tin oxide containing silicon, or the like. A material such as an oxide (abbreviation: ITSO) can be used. and the oxide semiconductor film 108 contain the same metal element, It is possible to suppress the above.

[0117] For example, when an In-M-Zn oxide is used as the oxide semiconductor film 112, The atomic ratio of the metal elements in the sputtering target used to form the -Zn oxide film is It is preferable that the sputtering target has a region in which In is equal to or larger than M. The atomic ratio of the metal elements in the alloy is In:M:Zn=2:1:3, In:M:Zn=3:1 :2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:7, etc. Note that the oxide semiconductor film 112 can be formed by using the above sputtering target. The composition of the oxide semiconductor film 112 is not limited to the above. It may have a laminated structure of more than one layer.

[0118] The oxide semiconductor film 112 is formed of an oxide semiconductor such as In-Ga-Zn oxide. The oxide semiconductor can be formed by absorbing at least nitrogen and hydrogen from the insulating film 116. When either one of them is supplied, the carrier density increases. The oxide semiconductor of 12 is an oxide conductor (OC). Therefore, the oxide semiconductor can be used as a gate electrode. .

[0119] For example, the second gate electrode may have a structure including an oxide semiconductor film 112 and a conductive film 114. In this case, the oxide semiconductor film 112 is made of the above-mentioned oxide conductor (OC), and the conductive film 114 is made of gold. A laminate structure using a metal film is preferred.

[0120] The second gate electrode has a laminated structure of an oxide semiconductor and a metal film having a light-shielding property. In this case, the channel region 108i formed below the oxide semiconductor film 112 can be shielded from light. In addition, the oxide semiconductor film 112 is preferably made of an oxide semiconductor or When a laminated structure of an oxide semiconductor (OC) and a metal film with light-shielding properties is used, A metal film (e.g., titanium film, tungsten film, etc.) is formed on an oxide conductor (OC). By forming a metal film, the constituent elements in the metal film diffuse into the oxide semiconductor or oxide conductor (OC) side. The resistance of the metal film is reduced by the damage caused during deposition (e.g., sputtering damage, etc.). The resistance becomes lower, or the oxide semiconductor or oxide conductor (OC) in the metal film is The diffusion of elements causes oxygen vacancies, resulting in low resistance.

[0121] <Insulating film that functions as the first gate insulating film> The insulating film 104 is formed by a method such as sputtering, CVD, vapor deposition, or pulsed laser deposition (PLD). The insulating film 104 can be formed by appropriately using a deposition method, a printing method, a coating method, or the like. For example, a single layer or a stack of an oxide insulating film and a nitride insulating film can be formed. In order to improve the interface characteristics with the oxide semiconductor film 108, at least In either case, a region in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. In the case where an oxide insulating film which releases oxygen by heating is used as the insulating film 104, As a result, oxygen contained in the insulating film 104 can be moved to the oxide semiconductor film 108. be.

[0122] The thickness of the insulating film 104 is 50 nm or more, or 100 nm or more and 3000 nm or less, or The thickness of the insulating film 104 can be set to 200 nm or more and 1000 nm or less. This can increase the amount of oxygen released from the insulating film 104 and also can prevent the insulating film 104 and the oxide semiconductor from The interface state at the interface with the conductive film 108 and the channel region 1 of the oxide semiconductor film 108 It is possible to reduce the oxygen vacancies contained in 08i.

[0123] The insulating film 104 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitrogen. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The insulating film may be a single layer or a stacked layer. The layer structure of the silicon nitride film and the silicon oxynitride film is used as the layer 104. The insulating film 104 has a laminated structure, with a silicon nitride film on the lower layer and an oxynitride film on the upper layer. By using a silicon film, oxygen can be efficiently introduced into the oxide semiconductor film 108. Cut.

[0124] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. The oxygen content is preferably 55 atomic % or more and 65 atomic % or less, and the nitrogen content is preferably 1 % to 20 atomic %, silicon is 25 atomic % to 35 atomic %, hydrogen is 0.1 atomic % Silicon oxide nitride refers to silicon that is contained in the range of 10 atomic % or more. The nitrogen content is preferably 55 atomic % or more and more preferably 65 atomic % or more. 5 atomic % or less, oxygen is 1 atomic % to 20 atomic % or less, silicon is 25 atomic % to 35 atomic % %, and hydrogen at a concentration in the range of 0.1 atomic % to 10 atomic %.

[0125] Note that at least a region of the insulating film 104 that is in contact with the oxide semiconductor film 108 is made of an oxide It is preferable that the insulating film is an insulating film, and the region containing oxygen in excess of the stoichiometric composition (oxygen excess) In other words, the insulating film 104 has a function of releasing oxygen. In order to provide an oxygen excess region in the insulating film 104, for example, The insulating film 104 may be formed in a nitrogen atmosphere. A method for adding oxygen to the insulating film 104 after deposition will be described later.

[0126] The insulating film 104 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide The material containing hafnium or yttrium can be preferably used. The dielectric constant of the insulating film 104 is higher than that of silicon or silicon oxynitride. By using gh-k materials, the film thickness can be made larger than when using silicon oxide films. Therefore, the leakage current due to the tunnel current can be reduced. It is possible to realize small transistors. Furthermore, hafnium oxide has a crystalline structure. has a higher dielectric constant than hafnium oxide having an amorphous structure. To make a transistor with a small current, hafnium oxide with a crystalline structure is used. Examples of the crystal structure include a monoclinic system and a cubic system. However, one aspect of the present invention is not limited to these.

[0127] In this embodiment, a silicon nitride film is formed on the conductive film 106 side as the insulating film 104, and an oxide film is formed on the conductive film 106 side. A silicon oxide film is formed on the side of the nitride semiconductor film 108 by lamination. It has a higher dielectric constant than silicon film, which is necessary to obtain the same capacitance as silicon oxide film. Therefore, the first gate insulating film of the transistor 100 is made of silicon nitride. By including the contact film, the first gate insulating film can be physically thickened. The decrease in the dielectric strength of the transistor 100 is suppressed, and the dielectric strength is improved. Therefore, electrostatic damage to the sensor 100 can be suppressed.

[0128] <An insulating film that functions as a second gate insulating film> The insulating film 110 functions as a gate insulating film of the transistor 100. The oxide semiconductor film 100 has a function of supplying oxygen to the oxide semiconductor film 108, particularly to the channel region 108i. For example, the insulating film 110 may be a single layer or a stack of an oxide insulating film or a nitride insulating film. In order to improve interface characteristics with the oxide semiconductor film 108, In the insulating film 110, at least a region in contact with the oxide semiconductor film 108 is made of an oxide insulating material. The insulating film 110 is preferably formed using a film such as silicon oxide or oxynitride. Silicon oxide, silicon nitride, silicon oxide, silicon nitride, or the like may be used.

[0129] The thickness of the insulating film 110 is 5 nm or more and 400 nm or less, or 5 nm or more and 300 nm or less. m or less, or from 10 nm to 250 nm.

[0130] In addition, it is preferable that the insulating film 110 has few defects. (ESR: Electron Spin Resonance) observed signal For example, the above signal is observed at a g value of 2.001. The E' center is a dangling bond of silicon. The insulating film 110 has a spin density due to the E' center of 3×10 17 spi ns / cm 3 Less than or equal to 5×10 16 spins / cm 3Silicon oxide is less than A silicon oxynitride film or a silicon oxide nitride film may be used.

[0131] In addition to the above-mentioned signals, the insulating film 110 also contains signals due to nitrogen dioxide (NO2). A null may be observed. The signal is divided into three signals due to the nuclear spin of N. The g value of each is between 2.037 and 2.039 (this is the first signal). , g value is 2.001 to 2.003 (second signal), and g value is 1.96 It is observed between 4 and 1.966 (referred to as the third signal).

[0132] For example, the insulating film 110 may have a spin density of 1×10 1 7 spins / cm 3 More than 1×10 18 spins / cm 3 When an insulating film having a thickness of less than This is preferable.

[0133] In addition, nitrogen oxides (NO x ) creates a level in the insulating film 110 The level is located within the energy gap of the oxide semiconductor film 108. Therefore, nitrogen oxides (NOx) diffuse to the interface between the insulating film 110 and the oxide semiconductor film 108. When this level occurs, the level may trap electrons on the insulating film 110 side. The trapped electrons remain near the interface between the insulating film 110 and the oxide semiconductor film 108. This causes the threshold voltage of the transistor to shift in the positive direction. 0, if a film with a low content of nitrogen oxide is used, the threshold voltage of the transistor The shift can be reduced.

[0134] Nitrogen oxides (NO x An example of an insulating film with a low emission amount of ) is a silicon oxynitride film. The silicon oxynitride film can be analyzed by thermal desorption spectroscopy (TDS). Nitrogen oxides were detected by thermal desorption spectroscopy. (NO x ) is a membrane that releases more ammonia than water. Output is 1×10 18 cm -3 5×10 or more 19 cm -3 The above is the ammo. The amount of Ni released was 50°C or more and 650°C or less for the TDS heat treatment. This is the total amount in the range of ℃ to 550℃.

[0135] Nitrogen oxides (NO x ) reacts with ammonia and oxygen during heat treatment, By using an insulating film that releases a large amount of monia, nitrogen oxides (NO x ) is reduced.

[0136] When the insulating film 110 was analyzed by SIMS, the nitrogen concentration in the film was 6×10 20 ato ms / cm 3 It is preferable that the following is true:

[0137] The insulating film 110 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ) and high-k materials such as hafnium oxide may also be used. The use of this high-k material can reduce gate leakage of transistors.

[0138] The insulating film 110 may be formed by a CVD method using an organic silane gas. The silane gas used is ethyl silicate (TEOS: chemical formula Si(OC2H5)4), tetrahydrofuran (TEOS: chemical formula Si(OC2H5)4), etc. Methylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyl Disilazane (HMDS), triethoxysilane (SiH(OC2H5)3), tris(dimethylamino) Silicon-containing compounds such as ethylaminosilane (SiH(N(CH3)2)3) can be used. By using the CVD method using organic silane gas, it is possible to form an insulating film 11 having high coverage. 0 can be formed.

[0139] <Third insulating film> The insulating film 116 contains at least one of nitrogen and hydrogen. For example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, It can be formed using silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. The hydrogen concentration in the insulating film 116 is 1×10 22 atoms / cm 3 That's all. The insulating film 116 is preferably formed on the source region 108s of the oxide semiconductor film 108 and The insulating film 116 is in contact with the oxide semiconductor film 112 and the drain region 108d. Therefore, the source region 108s and the drain region 108s are in contact with the insulating film 116. The hydrogen concentration in the source region 108s, the drain region 108c, and the oxide semiconductor film 112 becomes high. The carrier density in the drain region 108d and the oxide semiconductor film 112 can be increased. Note that the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are , and the insulating film 116 are in contact with each other, so that there may be regions in which the hydrogen concentrations in the films are the same. .

[0140] <Fourth insulating film> The insulating film 118 is formed as a single layer or a stack of an oxide insulating film or a nitride insulating film. The insulating film 118 can be made of, for example, silicon oxide, silicon oxynitride, or silicon nitride. Silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or G It is sufficient to use a-Zn oxide or the like, and the film can be provided as a single layer or a multilayer.

[0141] The insulating film 118 functions as a barrier film against hydrogen, water, and the like from the outside. It is preferable that

[0142] The thickness of the insulating film 118 is 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less. m or less.

[0143] <Conductive film functioning as first gate electrode and a pair of electrodes> The conductive film 106 and the conductive films 120s and 120d can be formed by sputtering or vacuum deposition. The film can be formed by a method such as a photolithography method, a pulsed laser deposition (PLD) method, or a thermal CVD method. The conductive film 106 and the conductive films 120s and 120d may be made of, for example, aluminum, quartz, or the like. From chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten The selected metal element or the alloy containing the above-mentioned metal elements or the combination of the above-mentioned metal elements In addition, it can be formed by using an alloy of manganese and zirconium. Alternatively, one or more metal elements may be used. The conductive films 120s and 120d may have a single-layer structure or a laminated structure of two or more layers. For example, A single layer structure of aluminum film containing silicon, a single layer structure of copper film containing manganese, A two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, A two-layer structure in which a tungsten film is laminated on a titanium nitride film, a tantalum nitride film or a tungsten nitride film Two-layer structure with tungsten film laminated on stainless film, copper film laminated on copper film containing manganese A two-layer structure with a copper film on a titanium film; a two-layer structure with a titanium film and an aluminum film on the titanium film; A three-layer structure in which a titanium film is laminated on top of the aluminum film, and a copper film containing manganese is formed on top of that. There is also a three-layer structure in which a copper film is laminated on top and a manganese-containing copper film is formed on top of that. In addition, aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium , scandium or a combination of two or more selected from the group consisting of an alloy film and a nitride film. This is also fine.

[0144] In particular, the conductive film 106 and the conductive films 120s and 120d are made of a material containing copper. When a material containing copper is used for the conductive films 106, 120s, and 120d, the resistance can be reduced. For example, even when a large-area substrate is used as the substrate 102, the signal This can reduce signal delays, etc.

[0145] The conductive film 106 and the conductive films 120s and 120d are formed of an oxide containing indium and tin. (abbreviation: ITO), oxide containing tungsten and indium, oxides containing titanium and zinc, oxides containing titanium and indium, oxides containing titanium, indium and tin oxides containing indium and zinc; oxides containing indium, gallium and zinc and oxide containing silicon, indium and tin (abbreviation: ITSO). In addition, the conductive material having the light-transmitting property and the conductive material having the light-transmitting property may be used. A laminated structure of metal elements may also be used.

[0146] The thickness of the conductive film 106 and the conductive films 120s and 120d is 30 nm or more and 500 nm or less. m or less, or from 100 nm to 400 nm.

[0147] <Conductive film 114 functioning as second gate electrode> The conductive film 114 functioning as the second gate electrode is the same as the first gate electrode described above. The conductive film 106 functions as a pair of electrodes, and the conductive films 120s and 120d function as a pair of electrodes. The material and manufacturing method can be used to form the semiconductor device. good.

[0148] In addition, the conductive film 114 has a low function of supplying at least one of nitrogen and hydrogen. In addition, the conductive film 114 has a low permeability to at least one of nitrogen and hydrogen. Specifically, for example, copper, molybdenum, tungsten, titanium, and titanium Molybdenum nitride, tantalum nitride and titanium nitride are preferred. Nitrides having nitrogen and metals such as lanthanides have high electrical conductivity and high barrier properties against copper or hydrogen. It is preferred because it has an acidic property and is stable.

[0149] <Substrate> The substrate 102 can be made of various substrates and is not particularly limited. Examples of the substrate include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, Glass substrate, quartz substrate, ceramic substrate, sapphire substrate, plastic substrate, metal substrate , stainless steel substrate, substrate with stainless steel foil, tungsten substrate Plates, tungsten foil substrates, flexible substrates, laminated films, fibrous materials Examples of glass substrates include barium borate-containing paper and base film. Examples include silicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of the functional substrate, laminate film, base film, etc. are as follows. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), There are plastics such as polyethersulfone (PES). Examples of the material include synthetic resins such as acrylic. ester, polyvinyl fluoride, polyvinyl chloride, etc. Or, as an example, poly Examples of the material include amide, polyimide, aramid, epoxy, inorganic vapor deposition film, and paper. In particular, a transistor is manufactured using a semiconductor substrate, a single crystal substrate, or an SOI substrate. This results in less variation in characteristics, size, or shape, higher current capability, and It is possible to manufacture transistors with low circuit noise. By configuring a circuit, it is possible to reduce the power consumption of the circuit or to increase the integration density of the circuit.

[0150] When a glass substrate is used as the substrate 102, the sixth generation (1500 mm×185 0mm), 7th generation (1870mm x 2200mm), 8th generation (2200mm x 240 0mm), 9th generation (2400mm x 2800mm), 10th generation (2950mm x 34 By using a large area substrate such as a 300 mm substrate, a large display device can be manufactured.

[0151] In addition, a flexible substrate is used as the substrate 102, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor. After a semiconductor device is partially or entirely completed on the substrate, the semiconductor device is separated from the substrate 102 and another In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The transfer can also be performed on a flexible substrate. The above-mentioned release layer may be, for example, a tungsten film and a silicon oxide film. A laminated structure of inorganic film with silicon film, or a resin film such as polyimide is formed on the substrate. The above configuration can be used.

[0152] An example of a substrate on which a transistor is transferred is a substrate on which the above-mentioned transistor is formed. In addition to the substrates that can be used, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, Rubber substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, hemp), synthetic fibers (nylon) , polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, These substrates include recycled polyester, leather substrates, and rubber substrates. By using this, it is possible to form transistors with good characteristics and low power consumption. It is possible to form, manufacture devices that are less likely to break, are heat resistant, or are lighter or thinner. .

[0153] <Configuration Examples 2 to 6 of Semiconductor Device> Next, regarding the semiconductor device having a different structure from that shown in FIGS. 1(A), 1(B), and 1(C), the following will be described with reference to FIGS. This will be explained using:

[0154] <Configuration Example 2 of Semiconductor Device> FIG. 2A is a top view of a transistor 100A, and FIG. 2B is a cross-sectional view of a portion of FIG. 2A. 2(C) is a cross-sectional view taken along dashed line X1-X2, and FIG. 2(C) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 2(A). FIG.

[0155] The transistor 100A shown in FIGS. 2A, 2B, and 2C is the same as the transistor 100 shown above. The shapes of the oxide semiconductor film 112 and the conductive film 114 are different from those of the transistor 1. The lower end of the oxide semiconductor film 112 in the first embodiment is located inside the upper end of the insulating film 110. In other words, the side edge of the insulating film 110 is closer to the side edge of the oxide semiconductor film 112 than the side edge of the oxide semiconductor film 112. Located on the outside.

[0156] For example, the oxide semiconductor film 112, the conductive film 114, and the insulating film 110 are formed using the same mask. The oxide semiconductor film 112 and the conductive film 114 are then processed by a wet etching method to remove the insulating film 11 The above structure can be obtained by processing each of the layers 10 and 11 by dry etching.

[0157] In addition, when the oxide semiconductor film 112 and the conductive film 114 have the above structures, In some cases, a region 108f may be formed in the body membrane 108. The region 108f is a channel region. 108i and the source region 108s, and between the channel region 108i and the drain region 108 It is formed between d.

[0158] The region 108f functions as either a high resistance region or a low resistance region. The resistance region is an oxide film that has a resistance equivalent to that of the channel region 108i and functions as a gate electrode. The region 108f is a region where the semiconductor film 112 and the conductive film 114 do not overlap. In this case, the region 108f functions as a so-called offset region. When the second region functions as a gate region, a decrease in the on-state current of the transistor 100A is suppressed. To achieve this, the region 108f may be set to 1 μm or less in the channel length (L) direction.

[0159] The low resistance region is a region having a lower resistance than the channel region 108i and a The region 108f is a low resistance region. In this case, the region 108f is a so-called LDD (Lightly Doped Drain) region. When the region 108f functions as an LDD region, the drain This allows the electric field in the drain region to be relaxed, which reduces the threshold voltage of the transistor caused by the electric field in the drain region. This can reduce fluctuations in the value voltage.

[0160] In addition, when the region 108f is to be a low resistance region, for example, At least one of hydrogen and nitrogen is supplied to 8f, or the insulating film 110, the oxide semiconductor An impurity element is injected from above the conductive film 114 using the conductive film 112 and the conductive film 114 as a mask. By the addition, the impurity is added to the oxide semiconductor film 108 through the insulating film 110. This is what is formed.

[0161] <Configuration example 3 of semiconductor device> Next, regarding the modified example of the semiconductor device shown in FIG. 2(A), (B), and (C), This will be explained using:

[0162] 3A and 3B are cross-sectional views of the transistor 100B. The top view is the same as that of the transistor 100A shown in FIG. FIG. 3(A) is a cross-sectional view taken along dashed line X1-X2 in FIG. 2(A). FIG. 3B is a cross-sectional view taken along dashed line Y1-Y2 in FIG.

[0163] The transistor 100B has a function as a planarizing insulating film for the transistor 100A shown above. The difference is that an insulating film 122 is provided. It has the same configuration as the transistor 100A and provides the same effects.

[0164] The insulating film 122 has a function of planarizing unevenness due to transistors and the like. The film 122 may be made of any insulating material, and may be made of an inorganic or organic material. The inorganic material may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, etc. Examples of the organic material include aluminum oxide, aluminum nitride, etc. Examples of the material include photosensitive resin materials such as acrylic resin and polyimide resin.

[0165] In addition, in FIG. 3(A) and (B), the shape of the opening in the insulating film 122 is opening 1. 41s, 141d, but is not limited thereto. For example, the opening 141 The openings 141s and 141d may have the same shape as the openings 141s and 141d, or may be larger than the openings 141s and 141d. stomach.

[0166] In addition, in FIG. 3(A) and (B), conductive films 120s and 120d are provided on the insulating film 122. However, the present invention is not limited to this. For example, a conductive film 120 on an insulating film 118 Alternatively, the insulating film 122 may be provided on the conductive films 120s and 120d. good.

[0167] <Configuration Example 4 of Semiconductor Device> Next, regarding the modified example of the semiconductor device shown in FIG. 1(A), (B), and (C), FIG. 4 and FIG. 5 are used. I will explain this in more detail.

[0168] 4A and 4B are cross-sectional views of the transistor 100C. The top view is the same as that of the transistor 100 shown in FIG. FIG. 4(A) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 4(B) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 1(A).

[0169] The transistor 100C is different from the transistor 100 shown above in that the shape of the insulating film 110 is different. The rest of the configuration is the same as that of the transistor 100 shown above. It has an effect.

[0170] The insulating film 110 of the transistor 100C is located inside the oxide semiconductor film 112. In other words, the side surface of the insulating film 110 is located on the inner side than the bottom end of the oxide semiconductor film 112. For example, after the oxide semiconductor film 112 and the conductive film 114 are processed, The insulating film 110 is side-etched by wet etching using a fluorine compound or the like. The insulating film 110 may have the structure shown in FIG. As a result, a hollow region 147 is formed under the oxide semiconductor film 112 .

[0171] The hollow region 147 contains air and functions as a part of the gate insulating film. The dielectric constant of 147 is approximately 1, the same as that of air. Therefore, the transistor 100C By using this structure, a voltage is applied to the oxide semiconductor film 112 which functions as a gate electrode. In this case, the voltage applied to the channel region 108i below the hollow region 147 is The voltage applied to the hollow region 108i is lower than the voltage applied to the channel region 108i below the hollow region 108i. The channel region 108i below 47 is effectively an overlap region (also called the Lov region). The Lov region is a region of the oxide semiconductor film that functions as a gate electrode. 112 and has a lower resistance than the channel region 108i.

[0172] 5A and 5B are cross-sectional views of the transistor 100D. The top view is the same as that of the transistor 100 shown in FIG. FIG. 5(A) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 5(B) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 1(A).

[0173] The transistor 100D is a transistor including the transistor 100 and the insulating film 110 and the insulating film 11. The shape of the transistor 6 is different. Other than that, the structure is the same as that of the transistor 100 shown above. It is composed of the same components and has the same effect.

[0174] The insulating film 110 in the transistor 100D includes an oxide semiconductor film 112 and a conductive film 11 In other words, the side surface of the insulating film 110 is located inside the oxide semiconductor film 112. For example, the oxide semiconductor film 112 and the conductive film 114 are processed. After that, the insulating film 110 is side-etched by wet etching using an etchant. By performing the above-mentioned process, the insulating film 11 can be formed as shown in FIG. 5(A)(B). After forming the above structure, the insulating film 116 is formed. The insulating film 116 is an oxide semiconductor. The insulating film 116 is located below the oxide semiconductor film 112. The oxide semiconductor film 108 is in contact with the insulating film 106 .

[0175] With the above-mentioned configuration, the source region 108s and the drain region 108d are made of oxide semiconductor. The transistor 100D is located inside the lower end of the conductive film 112. Has an area.

[0176] A structure having a Lov region such as transistor 100C and transistor 100D. By this, the channel region 108i, the source region 108s, and the drain region 108d are Since no high resistance region is formed between the do.

[0177] <Configuration Example 5 of Semiconductor Device> Next, regarding the modified example of the semiconductor device shown in FIG. 1(A), (B), and (C), FIG. 6 and FIG. 7 are used. I will explain this in more detail.

[0178] 6A and 6B are cross-sectional views of the transistor 100E. The top view is the same as that of the transistor 100 shown in FIG. FIG. 6A is a cross-sectional view taken along the dashed line X1-X2 in FIG. 6(B) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 1(A).

[0179] The transistor 100E has the same structure as the transistor 100 and the oxide semiconductor film 108. The other configuration is the same as that of the transistor 100 shown above. , has a similar effect.

[0180] The oxide semiconductor film 108 included in the transistor 100E is an oxide semiconductor film over the insulating film 116. an oxide semiconductor film 108_1, an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1, and an oxide and an oxide semiconductor film 108_3 over the semiconductor film 108_2.

[0181] The channel region 108i, the source region 108s, and the drain region 108d are The oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 1 It has a three-layer laminated structure of 08_3.

[0182] 7A and 7B are cross-sectional views of the transistor 100F. The top view is the same as that of the transistor 100 shown in FIG. FIG. 7A is a cross-sectional view taken along the dashed line X1-X2 in FIG. 7(B) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 1(A).

[0183] The transistor 100F has the same structure as the transistor 100 described above and the oxide semiconductor film 108. The other configuration is the same as that of the transistor 100 shown above. , has a similar effect.

[0184] The oxide semiconductor film 108 included in the transistor 100F is an oxide semiconductor film over the insulating film 116. and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. do.

[0185] The channel region 108i, the source region 108s, and the drain region 108d are Each of the oxide semiconductor films 108_1 and 108_2 has a stacked structure of two layers, an oxide semiconductor film 108_3, be.

[0186] In the transistor 100F, the oxide semiconductor film 1 108_2, and an oxide semiconductor film 108_3.

[0187] <Band structure> Here, the case where the oxide semiconductor has a two-layer structure or a three-layer structure will be described. A barrier layer made of an insulator is in contact with the stacked structure of the semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S3. The band diagram of the insulator in contact with the stacked structure of the oxide semiconductor S2 and the oxide semiconductor S3. The above and the above will be described with reference to FIG. 16. Note that in FIG. 16, the oxide semiconductor film 1 The oxide semiconductors in the oxide semiconductor layers 08_1, 108_2, and 108_3 are oxide semiconductors S1 and S2. , and S3, and the insulators of the insulating films 104 and 110 are represented as insulators I1 and I2. .

[0188] FIG. 16A shows an insulator I1, an oxide semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S FIG. 16 is an example of a band diagram in the thickness direction of a laminated structure having an insulator I2 and an insulator I3. (B) has an insulator I1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. 1 is an example of a band diagram in the film thickness direction of a laminated structure. Note that the band diagram is shown in FIG. Insulator I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S3, and insulator I2 The energy level (Ec) at the bottom of the conduction band of

[0189] The oxide semiconductors S1 and S3 have a lower energy at the conduction band edge than the oxide semiconductor S2. The energy level is close to the vacuum level, typically the energy level at the bottom of the conduction band of the oxide semiconductor S2. The difference between the energy level of the oxide semiconductor S1 and the energy level of the oxide semiconductor S3 at the bottom of the conduction band is 0 .15eV or more, or 0.5eV or more and 2eV or less, or 1eV or less In other words, the electron affinity of the oxide semiconductor S1 and the oxide semiconductor S3 and the The difference between the electron affinity of the conductor S2 is 0.15 eV or more, or 0.5 eV or more and 2 eV It is preferably 1 eV or less, or 1 eV or less.

[0190] As shown in FIG. 16(A) and FIG. 16(B), an oxide semiconductor S1, an oxide semiconductor S 2. In the oxide semiconductor S3, the energy level at the bottom of the conduction band changes gradually. In other words, it can be said that the band changes continuously or that the junction is continuous. In order to have the above, the interface between the oxide semiconductor S1 and the oxide semiconductor S2 or the oxide semiconductor When the defect level density of the mixed layer formed at the interface between S2 and the oxide semiconductor S3 is reduced, good.

[0191] Specifically, the oxide semiconductor S1 and the oxide semiconductor S2, the oxide semiconductor S2 and the oxide semiconductor S3 S3 has a common element other than oxygen (as the main component), so that the defect level density is low. For example, when the oxide semiconductor S2 is an In-Ga-Zn oxide semiconductor, In the case of the body, the oxide semiconductor S1 and the oxide semiconductor S3 are In-Ga-Zn oxide semiconductors. , Ga-Zn oxide semiconductor, gallium oxide, or the like may be used.

[0192] At this time, the main carrier path is the oxide semiconductor S2. Defects at the interface with the oxide semiconductor S2 and the interface between the oxide semiconductor S2 and the oxide semiconductor S3 Since the density of recessed levels can be reduced, the effect of interface scattering on carrier conduction is small. , a high on-current can be obtained.

[0193] When an electron is captured in a trap level, the captured electron behaves like a fixed charge. Therefore, the threshold voltage of the transistor is shifted in the positive direction. By providing the oxide semiconductor S3, the trap level is moved away from the oxide semiconductor S2. By adopting this configuration, the threshold voltage of the transistor can be shifted in the positive direction. This can prevent the device from being damaged.

[0194] The oxide semiconductors S1 and S3 have sufficient electrical conductivity compared to the oxide semiconductor S2. In this case, the oxide semiconductor S2 and the oxide semiconductor S The interface between the oxide semiconductor S1 and the oxide semiconductor S2 and the oxide semiconductor S3 are mainly the channel region. For example, the oxide semiconductor S1 and the oxide semiconductor S3 have the following functions: In this case, an oxide semiconductor having an atomic ratio shown in region C where the insulating property is high may be used. Region C shown in FIG. 14(C) is [In]:[M]:[Zn]=0:1:0 or its vicinity. The atomic ratios shown are the atomic ratios.

[0195] In particular, when an oxide semiconductor having an atomic ratio shown in region A is used for the oxide semiconductor S2, In the compound semiconductor S1 and the oxide semiconductor S3, [M] / [In] is 1 or more, preferably 2 It is preferable to use an oxide semiconductor having a conductivity of at least 100 nm. Oxides with [M] / ([Zn]+[In]) of 1 or more that can provide high insulating properties It is preferable to use a semiconductor.

[0196] <Method 1 for manufacturing semiconductor device> Next, an example of a method for manufacturing the transistor 100 shown in FIG. 1 will be described with reference to FIGS. 8 to 11 are diagrams illustrating a method for manufacturing the transistor 100. 1 is a cross-sectional view in the channel length (L) direction and the channel width (W) direction.

[0197] First, a conductive film that will become the conductive film 106 is formed on the substrate 102, and then the conductive film is The conductive film 106 is formed by processing the conductive film 106 into a conductive film (see FIG. 8A).

[0198] The conductive film 106 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The film can be formed by appropriately using a PLD method, a printing method, a coating method, or the like. As the conductive film 106, a tungsten film having a thickness of 100 nm is formed by sputtering. Alternatively, a tantalum nitride film with a thickness of 10 nm and a copper film with a thickness of 100 nm are formed by sputtering. The film is formed by a coating method. Next, the insulating film 104 is formed on the substrate 102 and the conductive film 106. An oxide semiconductor film is formed. Then, the oxide semiconductor film is processed into an island shape. Then, a compound semiconductor film 107 is formed (see FIG. 8(B)).

[0199] The insulating film 104 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The film can be formed by appropriately using a PLD method, a printing method, a coating method, or the like. In this case, a silicon nitride film having a thickness of 400 nm was deposited as the insulating film 104 using a PECVD apparatus. Then, a silicon oxynitride film having a thickness of 50 nm is formed.

[0200] After the insulating film 104 is formed, oxygen may be added to the insulating film 104. The oxygen added to 4 can be oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions. In addition, oxygen can be added by ion doping, ion implantation, plasma In addition, a film that suppresses oxygen desorption is formed on the insulating film, and then the insulating film is exposed to the atmosphere through the film. Oxygen may be added to the insulating film 104.

[0201] The above-mentioned oxygen desorption-suppressing film may be made of indium, zinc, gallium, tin, aluminum, or the like. Aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, tungsten A metal element selected from the above, an alloy containing the above metal element, or a combination of the above metal elements. an alloy having the above-mentioned metal element, a metal nitride having the above-mentioned metal element, a metal oxide having the above-mentioned metal element, The insulating layer 11 is formed by using a conductive material such as a metal nitride oxide having the above-mentioned metal element. This can be done.

[0202] In addition, when oxygen is added in plasma treatment, the oxygen is excited by microwaves to produce high-density oxygen. By generating atomic plasma, the amount of oxygen added to the insulating film 104 can be increased. .

[0203] The oxide semiconductor film 107 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, or a method using a deposition method such as a deposition method. It can be formed by a laser ablation method, a thermal CVD method, etc. To process the conductive film 107, a mask is formed on the oxide semiconductor film by a lithography process. Then, part of the oxide semiconductor film is etched using the mask. Alternatively, the oxide semiconductor film 107 may be directly formed by using a printing method. .

[0204] When an oxide semiconductor film is formed by a sputtering method, a power source for generating plasma The device may be an RF power supply device, an AC power supply device, a DC power supply device, or the like. In the case of forming an oxide semiconductor film, a sputtering gas is a rare gas (typically, argon). ), oxygen, rare gas, and mixed gas of oxygen are used as appropriate. Note that the mixed gas of rare gas and oxygen In this case, it is preferable to increase the gas ratio of oxygen to the rare gas.

[0205] Note that when the oxide semiconductor film is formed by, for example, a sputtering method, Temperature: 150℃ to 750℃, 150℃ to 450℃, or 200℃ By forming the oxide semiconductor film at a temperature of 350° C. or less, the crystallinity can be improved. .

[0206] Note that in this embodiment, the oxide semiconductor film 107 is formed by a sputtering apparatus. The sputtering target was In-Ga-Zn metal oxide (In:Ga:Zn = 4:2:4.1 [atomic ratio]) to form a 40-nm-thick oxide semiconductor film.

[0207] After the oxide semiconductor film 107 is formed, heat treatment is performed. The temperature of the heat treatment is typically 150° C. or higher. Less than the strain point, or 250°C to 450°C, or 300°C to 450°C .

[0208] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or It can be carried out in an inert gas atmosphere containing nitrogen. Alternatively, it can be heated in an inert gas atmosphere. After that, heating may be performed in an oxygen atmosphere. Note that hydrogen, water, etc. may be added to the inert atmosphere and oxygen atmosphere. It is preferable that the treatment time does not include the above-mentioned. The treatment time may be from 3 minutes to 24 hours.

[0209] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. The processing time can be reduced.

[0210] The oxide semiconductor film is formed while being heated, or the oxide semiconductor film is formed and then subjected to heat treatment. By performing the process, the hydrogen concentration in the oxide semiconductor film obtained by secondary ion mass spectrometry can be 5×10 19 atoms / cm 3 or less, or 1×10 19 atoms / cm 3 Below, 5 ×10 18 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 The following also is 5 x 10 17 atoms / cm 3 or less, or 1×10 16 atoms / cm 3 Below and It is possible.

[0211] Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107 (FIG. 8 (See (C)).

[0212] The insulating film 110_0 is a silicon oxide film or a silicon oxynitride film formed by PECVD. In this case, the source gas is a deposition gas containing silicon. It is preferable to use a gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include Examples of oxidizing gases include silane, disilane, trisilane, and fluorinated silane. Examples of oxidizing gases include oxygen. , ozone, nitrous oxide, nitrogen dioxide, etc.

[0213] In addition, for the insulating film 110_0, the flow rate of the oxidizing gas is set to 20 times the flow rate of the deposition gas. The pressure in the treatment chamber should be 100P or more but less than 100 times, or 40 times or more but less than 80 times. By using the PECVD method with a pressure of less than a or 50 Pa or less, the amount of defects is reduced. A silicon hydride film can be formed.

[0214] In addition, the insulating film 110_0 is placed in a vacuum-evacuated processing chamber of a PECVD apparatus. The substrate is maintained at a temperature of 280° C. or higher and 400° C. or lower, and a source gas is introduced into the processing chamber. The pressure in the chamber is set to 20 Pa or more and 250 Pa or less, and more preferably 100 Pa or more and 250 Pa or less. Under the conditions of supplying high frequency power to an electrode provided in the processing chamber, the insulating film 110 is 0, a dense silicon oxide film or silicon oxynitride film can be formed. .

[0215] In addition, the insulating film 110_0 may be formed by using a plasma CVD method using microwaves. Microwaves refer to the frequency range from 300MHz to 300GHz. In this case, the electron temperature is low and the electron energy is small. The proportion of the electrons used to accelerate the molecules is small, and the electrons can be used to dissociate and ionize more molecules. This allows for the excitation of high density plasma. The plasma damage to the deposition surface and the deposit is minimal, and an insulating film 110_0 with few defects is formed. It can be achieved.

[0216] In addition, the insulating film 110_0 can be formed by a CVD method using an organic silane gas. As an organic silane gas, ethyl silicate (TEOS: chemical formula Si(OC2H5)4 ), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetramethylsilane (TMS: chemical formula Si(CH3)4), Lasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), Silicon-containing compounds such as trisdimethylaminosilane (SiH(N(CH3)2)3) By using the CVD method using organic silane gas, it is possible to obtain a high coating property. An insulating film 110_0 can be formed.

[0217] In this embodiment, a PECVD apparatus is used to deposit a 150 nm thick insulating film 110_0. A silicon oxynitride film is formed.

[0218] Next, an oxide semiconductor film 112_0 is formed over the insulating film 110_0. During the formation of the oxide semiconductor film 112_0, Oxygen is added (see FIG. 8(D)).

[0219] The oxide semiconductor film 112_0 is formed by a sputtering method. It is preferable to form the oxide semiconductor in an atmosphere containing oxygen gas during the formation. By forming the insulating film 112_0, oxygen can be suitably added to the insulating film 110_0. Cut.

[0220] In FIG. 8D, oxygen added to the insulating film 110_0 is represented by arrows. Note that the oxide semiconductor film 112_0 is the same as the oxide semiconductor film 107 described above. The same materials as those mentioned above can be used.

[0221] In this embodiment, the oxide semiconductor film 112_0 is formed by a sputtering apparatus. As a sputtering target, In-Ga-Zn metal oxide (In:Ga:Zn = A 20-nm-thick oxide semiconductor film is formed using a SiO2 / SiO2 (atomic ratio: 5:1:7).

[0222] Next, a mask is formed at a desired position on the oxide semiconductor film 112_0 by lithography. After that, the oxide semiconductor film 112_0, the insulating film 110_0, and the insulating film 104 are partly etched. By this etching, an opening 143 reaching the conductive film 106 is formed (see FIG. 9A).

[0223] The opening 143 can be formed by wet etching and / or dry etching. In this embodiment, a dry etching method is used. An opening 143 is formed.

[0224] Next, a conductive film 114_0 is formed over the oxide semiconductor film 112_0 so as to cover the opening 143. The conductive film 114_0 is formed so as to cover the opening 143. 6 and the conductive film 114_0 are electrically connected (see FIG. 9B).

[0225] Next, a mask 140 is formed at a desired position on the conductive film 114_0 by a lithography process. (See FIG. 9(C)).

[0226] Next, etching is performed from above the mask 140 to remove the conductive film 114_0 and the oxide semiconductor After processing the conductor film 112_0 and the insulating film 110_0, the mask 140 is removed. Thus, the island-shaped conductive film 114, the island-shaped oxide semiconductor film 112, and the island-shaped insulating film 110 are formed. (See FIG. 9(D)).

[0227] In this embodiment, the conductive film 114_0, the oxide semiconductor film 112_0, and the insulating film The processing of 110_0 is carried out by using a dry etching method.

[0228] Note that when the conductive film 114, the oxide semiconductor film 112, and the insulating film 110 are processed, The thickness of the oxide semiconductor film 107 in a region where the film 114 does not overlap with the oxide semiconductor film 107 might be thin. In processing the conductive film 114, the oxide semiconductor film 112, and the insulating film 110, In some cases, the thickness of the insulating film 104 in the region where the solid film 107 does not overlap may become thin.

[0229] Next, the insulating film 104, the oxide semiconductor film 107, the oxide semiconductor film 112, and the conductive film 11 An impurity element 145 is added from above (see FIG. 10(A)).

[0230] The impurity element 145 can be added by ion doping, ion implantation, plasma In the case of plasma treatment, the plasma is heated in a gas atmosphere containing the impurity element to be added. Impurity elements can be added by generating a plasma and performing a plasma treatment. The plasma generating device may be a dry etching device, an ashing device, A plasma CVD apparatus, a high density plasma CVD apparatus, or the like can be used.

[0231] The source gas for the impurity element 145 is B2H6, PH3, CH4, N2, NH3 , AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2 and one or more of the rare gases Alternatively, B2H6, PH3, N2, NH3, diluted with rare gases, One or more of AlH3, AlCl3, F2, HF, and H2 can be used. Diluted B2H6, PH3, N2, NH3, AlH3, AlCl3, F2, HF, and The impurity element 145 is added to the oxide semiconductor film 107 and the oxide semiconductor film 11 using one or more of H2 and H2. Addition of 2 to rare gases, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, and salts One or more elements can be added to the oxide semiconductor films 107 and 112.

[0232] Or after adding rare gases, B2H6, PH3, CH4, N2, NH3, AlH3, At least one of AlCl3, SiH4, Si2H6, F2, HF, and H2 is added to the oxide semiconductor film 1 The oxide semiconductor film 112 may be doped with fluorine.

[0233] Or B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4 After adding one or more of Si2H6, F2, HF, and H2, a rare gas is added to the oxide semiconductor film 1. The oxide semiconductor film 112 may be doped with fluorine.

[0234] The addition of the impurity element 145 is controlled by appropriately setting implantation conditions such as acceleration voltage and dose amount. For example, when argon is added by ion implantation, the acceleration voltage is set to 10 kV or more. 00kV or less, dose amount is 1×10 13 ions / cm 2 More than 1×10 16 ions / c m 2 For example, 1×10 14 ions / cm 2 Also, When phosphorus ions are added by the on-implantation method, the acceleration voltage is 30 kV and the dose is 1×10 13 ions / cm 2 5×10 or more 16 ions / cm 2 For example, 1×1 0 15 ions / cm 2 This can be done as follows.

[0235] In this embodiment, the mask 140 is removed, and then the impurity element 145 is added. However, the present invention is not limited to this. For example, the mask 140 may be left in place. The impurity element 145 may be added in this state.

[0236] In this embodiment, the impurity element 145 is doped using a doping device. Argon is added to the oxide semiconductor film 107 and the oxide semiconductor film 112. In the embodiment, a configuration in which argon is added as the impurity element 145 is illustrated. However, the present invention is not limited to this, and may be configured to add, for example, nitrogen. The step of adding element 145 may not be performed.

[0237] Next, the insulating film 104, the oxide semiconductor film 107, the oxide semiconductor film 112, and the conductive film 11 An insulating film 116 is formed on the insulating film 116. The oxide semiconductor film 107 in contact with the source region 108s and the drain region 108d. In addition, the oxide semiconductor film 107 that is not in contact with the insulating film 116, in other words, the oxide semiconductor film 107 that is in contact with the insulating film 110 The oxide semiconductor film 107 becomes a channel region 108i. i, a source region 108s, and a drain region 108d are formed in the oxide semiconductor film 108. (See FIG. 10(B)).

[0238] The insulating film 116 is formed by selecting a material that can be used for the insulating film 116. In this embodiment, the insulating film 116 is formed by a PECVD apparatus. A 00 nm thick silicon nitride film is formed.

[0239] By using a silicon nitride film as the insulating film 116, the oxide semiconductor layer in contact with the insulating film 116 The conductive film 112, the source region 108s, and the drain region 108d are provided with water in the silicon nitride film. The oxide semiconductor film 112, the source region 108s, and the drain region 108d The carrier density can be increased.

[0240] Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 10C).

[0241] The insulating film 118 is formed by selecting a material that can be used for the insulating film 118. In this embodiment, the insulating film 118 is formed by a PECVD apparatus. A 00 nm thick silicon oxynitride film is formed.

[0242] Next, a mask is formed by lithography at a desired position on the insulating film 118, and then the insulating film By etching a part of the insulating film 118 and the insulating film 116, an opening reaching the source region 108s is formed. An opening 141s and an opening 141d reaching the drain region 108d are formed (FIG. 11 (See (A)).

[0243] The method for etching the insulating film 118 and the insulating film 116 is a wet etching method. and / or dry etching can be appropriately used. The insulating film 118 and the insulating film 116 are processed by dry etching.

[0244] Next, a conductive film 120 is formed on the insulating film 118 so as to cover the openings 141s and 141d. (See FIG. 11(B)).

[0245] For the conductive film 120, a material that can be used for the conductive films 120s and 120d is selected. In this embodiment, the conductive film 120 is formed by a sputtering device. The titanium film with a thickness of 50 nm, the aluminum film with a thickness of 400 nm, and the aluminum film with a thickness of 100 A titanium film having a thickness of nm is formed.

[0246] Next, a mask is formed at a desired position on the conductive film 120 by a lithography process, and then, By etching a part of the conductive film 120, conductive films 120s and 120d are formed (FIG. 11(C)).

[0247] The conductive film 120 can be processed by wet etching and / or dry etching. In this embodiment, a dry etching method is used to remove the conductive film. The substrate 120 is processed to form conductive films 120s and 120d.

[0248] Through the above steps, the transistor 100 illustrated in FIG. 1 can be manufactured.

[0249] Note that the films constituting the transistor 100 (the insulating film, the oxide semiconductor film, the conductive film, and the like) are Sputtering, Chemical Vapor Deposition (CVD), Vacuum Evaporation, Pulsed Laser Deposition (PLD) ) method or atomic layer deposition (ALD) method. Alternatively, coating method or printing method The film can be formed by a sputtering method, a plasma chemical vapor deposition method, etc. The most typical method is the plasma-epiplasmic chemical vapor deposition (PECVD) method, but the thermal CVD method may also be used. Examples of the method include metal organic chemical vapor deposition (MOCVD).

[0250] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0251] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The film is formed by repeatedly introducing the gas into the chamber and reacting it. A reactive gas (such as argon or nitrogen) may be introduced as a carrier gas. For example, two types of At least one type of source gas may be supplied to the chamber in sequence. In order to avoid this, after the reaction of the first raw material gas, an inert gas is introduced, and then the second raw material gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is discharged by evacuation. After that, the second source gas may be introduced. The first source gas is adsorbed and reacted with the surface of the substrate. The first layer is formed, and the second source gas introduced later is adsorbed and reacted with the first layer. The order of gas introduction is controlled to obtain a thin film of the desired thickness. By repeating the process several times up to 1000 nm, a thin film with excellent step coverage can be formed. The thickness can be adjusted by repeating the gas introduction, allowing precise adjustment of the film thickness. This makes it suitable for fabricating miniaturized FETs.

[0252] Thermal CVD methods such as MOCVD can be used to form the above-mentioned conductive films, insulating films, oxide semiconductor films, and metal It is possible to form films such as oxide films. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3 )3) and dimethylzinc (Zn(CH3)2). Instead of trimethylgallium, triethylgallium (Ga(C2H5)3) is used. Alternatively, diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc. can.

[0253] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide Hafnium (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamine) C) Hafnium amide (e.g. hafnium) is vaporized as a raw material gas, and ozone is used as an oxidizer. Two types of gases are used:

[0254] For example, when forming an aluminum oxide film using an ALD deposition system, A liquid containing a catalyst and an aluminum precursor (trimethylaluminum (TMA, Al(CH3) 3) and other) are used as the raw material gas and as the oxidizing agent, H2O. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate) There are some.

[0255] For example, when forming a silicon oxide film using a deposition system that uses ALD, Chlorodisilane is adsorbed on the surface to be coated, and the radicals of oxidizing gases (O2, nitrous oxide) are The adsorbate is reacted with the adsorbate.

[0256] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film is formed by sequentially introducing B2H6 gas and WF6 gas. The tungsten film is formed using H2 gas. Note that SiH4 gas is used instead of B2H6 gas. A suction cup may also be used.

[0257] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, an In-O layer is formed using In(CH3)3 gas and O3 gas. Then, a GaO layer is formed using Ga(CH3)3 gas and O3 gas, and then Z The ZnO layer is formed using n(CH3)2 gas and O3 gas. The order of these layers is The present invention is not limited to this example. In addition, In-Ga-O layers and In-Zn-O layers can be formed by using these gases. Alternatively, a mixed compound layer such as a Ga-Zn-O layer may be formed. H2O gas obtained by bubbling water with an inert gas such as HO may be used, but it is not recommended to use gas that does not contain H. It is preferable to use O3 gas, which is less oxidative.

[0258] <Method 2 for manufacturing semiconductor device> Next, an example of a method for manufacturing the transistor 100B shown in FIG. 3 will be described with reference to FIGS. 12 and 13 are used to explain a method for manufacturing the transistor 100B. 1 is a cross-sectional view in the channel length (L) direction and the channel width (W) direction.

[0259] First, in the same manner as in the manufacturing method of the transistor 100 described above, a conductive film 1 is formed on a substrate 102. 06, the insulating film 104, the oxide semiconductor film 107, the oxide semiconductor film 112_0, and the conductive film 1 14_0 (see FIG. 8 and FIG. 9(A)(B)).

[0260] Next, a mask 140 is formed at a desired position on the conductive film 114_0 by a lithography process. (See FIG. 9(C)).

[0261] Next, etching is performed from above the mask 140 to remove the conductive film 114_0 and the oxide semiconductor The conductive film 112_0 is processed to form an island-shaped conductive film 114 and an island-shaped oxide semiconductor film 112. (See FIG. 12(A)).

[0262] In this embodiment, the conductive film 114_0 and the oxide film 114_1 are etched by wet etching. The semiconductor film 112_0 is processed.

[0263] Subsequently, the insulating film 110_0 is processed by etching from above the mask 140, and the island Then, a tubular insulating film 110 is formed (see FIG. 12(B)).

[0264] In this embodiment, the insulating film 110_0 is processed by using a dry etching method.

[0265] Next, after removing the mask 140, the insulating film 104, the oxide semiconductor film 107, and the oxide semiconductor An impurity element 145 is added from above the conductive film 112 and the conductive film 114 (see FIG. 12(C)). see).

[0266] Note that when the impurity element 145 is added, the oxide semiconductor film 107 is doped with the impurity element 145 in a region where the surface of the oxide semiconductor film 107 is exposed. There are many impurities in the regions (which will later become the source region 108s and the drain region 108d). On the other hand, the oxide semiconductor film 107 does not overlap with the oxide semiconductor film 112, In addition, the insulating film 110 is not applied to the region overlapping the insulating film 110 (the region that will become the region 108f later). Since the impurity element 145 is added through the source region 108s and the drain region 10 The amount of the impurity element 145 added is smaller than that of 8d.

[0267] In this embodiment, the impurity element 145 is doped using a doping device. Argon is added to the oxide semiconductor film 107 and the oxide semiconductor film 112.

[0268] In this embodiment, argon is added as the impurity element 145. However, the present invention is not limited to this, and for example, nitrogen may be added. For example, the step of adding the impurity element 145 may be omitted. If the step of adding the impurity is not performed, the region 108f will have the same impurity concentration as the channel region 108i. It becomes.

[0269] Next, the insulating film 104, the oxide semiconductor film 107, the insulating film 110, the oxide semiconductor film 112, An insulating film 116 is formed over the conductive film 114. Note that by forming the insulating film 116, The oxide semiconductor film 107 in contact with the insulating film 116 is a source region 108s and a drain region 108c. In addition, the oxide semiconductor film 107 that is not in contact with the insulating film 116, in other words, the insulating film The oxide semiconductor film 107 in contact with the oxide semiconductor film 110 becomes a channel region 108i. The semiconductor substrate has an oxide semiconductor layer having a channel region 108i, a source region 108s, and a drain region 108d. A membrane 108 is formed (see FIG. 12(D)).

[0270] In addition, between the channel region 108i and the source region 108s, and between the channel region 108 A region 108f is formed between the drain region 108d and the drain region 108i.

[0271] Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 13A).

[0272] Next, a mask is formed by lithography at a desired position on the insulating film 118, and then the insulating film By etching a part of the insulating film 118 and the insulating film 116, an opening reaching the source region 108s is formed. An opening 141s and an opening 141d reaching the drain region 108d are formed (FIG. 13). (See (B)).

[0273] Next, the insulating film 122 is formed over the insulating film 118 (see FIG. 13C).

[0274] Note that the insulating film 122 functions as a planarization insulating film. It has openings at positions overlapping with opening 141s and opening 141d.

[0275] In this embodiment, the insulating film 122 is formed by coating a photosensitive adhesive using a spin coater. An opening is formed by applying an acrylic resin and then exposing the desired area of ​​the acrylic resin to light. An insulating film 122 having a portion is formed.

[0276] Next, the conductive film 120 is formed on the insulating film 122 so as to cover the openings 141s and 141d. (See FIG. 13(D)).

[0277] Next, a mask is formed at a desired position on the conductive film 120 by a lithography process, and then, By etching a part of the conductive film 120, conductive films 120s and 120d are formed.

[0278] In this embodiment, the conductive film 120 is processed by dry etching. When the conductive film 120 is processed, a part of the upper portion of the insulating film 122 may be removed.

[0279] Through the above steps, the transistor 100B shown in FIG. 3 can be manufactured.

[0280] Note that in the manufacturing process of the transistor 100B, the insulating film 104, the oxide semiconductor film 107, insulating film 110_0, oxide semiconductor film 112_0, conductive film 114, impurity element 14 5, the insulating film 116, the insulating film 118, the openings 141s and 141d, and the conductive film 120 can be formed by invoking the contents described in <1-4. Manufacturing method 1 of semiconductor device>. can.

[0281] In this embodiment, an example in which a transistor includes an oxide semiconductor film is shown. However, one embodiment of the present invention is not limited thereto. As an example, the channel region of a transistor may not have a nitride semiconductor film. In the vicinity of the gate region, the source region, or the drain region, rumanium), SiGe (silicon germanium), GaAs (gallium arsenide), etc. The insulating layer 10 may be formed of a material having such a structure.

[0282] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0283] (Embodiment 2) In this embodiment, a structure of an oxide semiconductor will be described with reference to FIGS. He explains.

[0284] <Structure of oxide semiconductor> Oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Nanocrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconducting ductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- like oxide semiconductor) and amorphous oxide semiconductor. be.

[0285] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductors, and nc-OS.

[0286] Amorphous structures are generally isotropic and have no inhomogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The positions are not fixed, the bond angles are flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0287] That is, a stable oxide semiconductor is transformed into a completely amorphous s) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example, it has a periodic structure in a small area). An oxide semiconductor having an Al structure cannot be called a completely amorphous oxide semiconductor. ike OS is not isotropic, but has an unstable structure with voids. In terms of instability, the a-like OS is physically similar to an amorphous oxide semiconductor. stomach.

[0288] <caac-os> First, let me explain about CAAC-OS.

[0289] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0290] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals was analyzed by the out-of-plane method. As shown in FIG. 17(A), a peak appears at a diffraction angle (2θ) of about 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so In this case, the crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be confirmed that the direction is perpendicular to the surface of the crystal, or perpendicular to the surface of the crystal. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The nearby peak is due to a crystal structure classified into the space group Fd-3m. It is preferred that the C-OS does not exhibit such a peak.

[0291] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS in a direction parallel to the surface on which the X-ray is to be formed. When structural analysis was performed using the ane method, a peak appeared at 2θ of approximately 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. And, 2θ is fixed at around 56°. Then, the sample is rotated around the normal vector of the sample surface as an axis (φ axis) while analyzing (φ scan). Even if this is done, no clear peak appears, as shown in FIG. When 2θ is fixed at around 56° and φ is scanned for ZnO4, the results shown in Figure 17(C) As shown in the figure, six peaks attributable to crystal planes equivalent to the (110) plane are observed. XRD structural analysis revealed that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0292] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the process was parallel to the CAAC-OS surface. When an electron beam with a probe diameter of 300 nm is incident, a diffraction pattern ( This is also called a selected area electron diffraction pattern.) may appear. This diffraction pattern includes I The spots are due to the (009) plane of the nGaZnO4 crystal. Diffraction also confirmed that the pellets contained in the CAAC-OS have a c-axis orientation and that the c-axis is the unformed On the other hand, for the same sample, the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm was incident perpendicularly to the ) is shown. From FIG. 17(E), a ring-shaped diffraction pattern is confirmed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed that the PEG-1000 nanometers in the CAAC-OS It can be seen that the a-axis and b-axis of the slits have no orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. The second ring in Fig. 17(E) is thought to be due to the (110) plane. It is thought that.

[0293] In addition, a transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using a microscope. When observing the image (also called a high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain boundaries), are not clearly visible. (also called underly.) may not be clearly identified. It can be said that C-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0294] Figure 18(A) shows a high-resolution cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image is shown. A spherical aberration correction (SCA) was used for high-resolution TEM imaging. The spherical aberration corrector function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. Therefore, it can be observed.

[0295] From FIG. 18(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. The size of each pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used as a C-Axis Aligned Navigator (CANC). The pellets can also be called oxide semiconductors with no crystals. It reflects the unevenness of the surface on which the C-OS is formed or the top surface, and the unevenness of the surface on which the CAAC-OS is formed or It is parallel to the top surface.

[0296] FIG. 18(B) and FIG. 18(C) show CAA images observed from a direction approximately perpendicular to the sample surface. Cs-corrected high-resolution TEM images of the C-OS surface. 18(B) and 18(C), respectively. First, the method of processing is explained. Then, the FFT image is obtained by Fourier Transform (FFT) processing. In the acquired FFT image, the origin is used as the reference point, and the -1 From 5.0 nm -1 The range between The remaining FFT image is then masked. Next, the masked FFT image is transformed by inverse fast Fourier transform (IFFT : Inverse Fast Fourier Transform) processing is used to The image obtained in this way is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. This indicates a child array.

[0297] In FIG. 18(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area indicated by the dashed line is the connection between the pellets. The broken line shows the hexagonal shape, so we can see that the pellet is hexagonal. The shape of the let is not limited to a regular hexagon, and is often a non-regular hexagon.

[0298] In FIG. 18(E), a dot is drawn between an area with a uniform lattice arrangement and an area with a different uniform lattice arrangement. The grain boundaries are shown by dotted lines. Even in the vicinity of the dotted lines, no clear crystal grain boundaries can be confirmed. When connecting the surrounding lattice points with a nearby lattice point at the center, a distorted hexagon, pentagon, or / and heptagon is formed. In other words, the formation of grain boundaries can be suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is dense in the ab-plane direction. The substitution of metal elements changes the bond distance between atoms. , it is believed that this is because distortion can be tolerated.

[0299] As described above, the CAAC-OS has a c-axis orientation and is Multiple pellets (nanocrystals) are connected to form a distorted crystal structure. AAC-OS, CAA crystal(c-axis-aligned abp It can also be called an oxide semiconductor having lane-anchored crystals. Cut.

[0300] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is determined by the presence of impurities. CAAC-OS is designed to prevent impurities and defects from causing degradation. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0301] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0302] <nc-os> Next, we will explain nc-OS.

[0303] The following describes the case where nc-OS is analyzed by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0304] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region of m, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in Figure 9(A) was observed. In addition, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample ( The nanobeam electron diffraction pattern is shown in Figure 19(B). Therefore, the nc-OS has a probe diameter of 50 nm. No order was observed when an electron beam with a probe diameter of 1 nm was incident. When light is incident on it, order is confirmed.

[0305] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 19(C), an electron diffraction pattern was observed in which the spots were arranged in a substantially regular hexagonal shape. Therefore, it is considered that the nc-OS is ordered in the range of thickness less than 10 nm. It can be seen that the crystals are highly ordered. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0306] FIG. 19(D) shows the Cs-corrected height of the cross section of the nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image as the area indicated by the auxiliary lines. How to identify the crystals and the areas where no clear crystals can be identified The crystal parts in the nc-OS have a size of 1 nm to 10 nm. In particular, the size of the crystals is often between 1 nm and 3 nm. An oxide semiconductor having a size of 10 nm or more and 100 nm or less is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). o crystalline oxide semiconductor) For example, in the case of nc-OS, the grain boundaries are often not clearly visible in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, below, the crystalline part of the nc-OS may be referred to as a pellet.

[0307] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, particularly The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the Cr-Al-Al-Fe-Al-Fe-O-Pb-Al-Zn ... Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0308] In addition, since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is , oxidation with RANC (Random Aligned nanocrystals) Semiconductors or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor has a conductivity of 1000.

[0309] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0310] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0311] FIG. 20 shows a high-resolution cross-sectional TEM image of the a-like OS. is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. B) is 4.3 x 10 8 e - / nm 2 Electrons (e - ) A-like OS after irradiation High-resolution cross-sectional TEM images. Figures 20(A) and 20(B) show that a-like O It can be seen that striped bright regions extending in the vertical direction are observed in S from the start of electron irradiation. It can also be seen that the shape of the bright regions changes after electron irradiation. It is suspected to be a density region.

[0312] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0313] As samples, a-like OS, nc-OS and CAAC-OS are prepared. Both samples are In-Ga-Zn oxides.

[0314] First, high-resolution cross-sectional TEM images of each sample are obtained. Each of the above has a crystalline portion.

[0315] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers in the c-axis direction. The distance between these adjacent layers is the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is called InGaZ. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0316] Figure 21 shows the average size of the crystals (22 to 30 points) of each sample. This is an example of investigating the crystal size. As shown in Figure 21, the a-like OS has a large number of functions related to the acquisition of TEM images. The crystals change according to the cumulative electron dose. As can be seen from Figure 21, in the early stages of TEM observation, the area is 1. The crystal part (also called the initial nucleus), which was about 2 nm in size, - ) cumulative exposure 4.2×10 8 e - / nm 2 In the present study, it was found that the size of the nanoparticles had grown to approximately 1.9 nm. On the other hand, the nc-OS and CAAC-OS show a large increase in the cumulative electron irradiation from the start of electron irradiation. The amount is 4.2 x 10 8 e - / nm 2 No change in the size of the crystals is observed within the range As can be seen from Fig. 21, the nc-OS and CAAC-OS showed no significant difference regardless of the cumulative dose of electron irradiation. The sizes of the crystal parts are found to be approximately 1.3 nm and 1.8 nm, respectively. The electron beam irradiation and TEM observations were performed using a Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were an acceleration voltage of 300 kV and a current density of 6.7 × 10 5 e - / (nm 2 ·s), and the diameter of the irradiated area was 230 nm.

[0317] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. That is, a-like OS is not seen in comparison with nc-OS and CAAC-OS. , it is clear that this is an unstable structure.

[0318] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0319] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 Less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0320] If single crystals of the same composition are not available, single crystals of different compositions may be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions. However, the density can be estimated by using as few types of single crystals as possible. A combined estimate is preferred.

[0321] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0322] <Carrier density in oxide semiconductors> Next, the carrier density of an oxide semiconductor will be described below.

[0323] Factors that affect the carrier density of oxide semiconductors include oxygen vacancies in the oxide semiconductor. (Vo), or impurities in the oxide semiconductor.

[0324] When the number of oxygen vacancies in an oxide semiconductor increases, hydrogen bonds to the oxygen vacancies (this state is called VoH When the oxide semiconductor is filled with impurities, the density of defect states increases. In this case, the density of defect states due to the impurities increases. By controlling the density of states, the carrier density of the oxide semiconductor can be controlled.

[0325] Here, a transistor in which an oxide semiconductor is used for a channel region will be considered.

[0326] Suppression of negative shift of the threshold voltage of a transistor or suppression of off-current of a transistor In order to reduce the carrier density of the oxide semiconductor, it is preferable to reduce the carrier density of the oxide semiconductor. In order to reduce the carrier density of an oxide semiconductor, the impurity concentration in the oxide semiconductor must be increased. In the present specification and the like, the impurity concentration is low, and the defect level density is low. A low density of defect states is called high purity intrinsic or substantially high purity intrinsic. The carrier density of a quartz semiconductor is 8×10 15 cm -3 Less than 1 x 10 1 1 cm -3 less than 1×10 10 cm -3 Less than 1 x 10 -9 cm -3 That should be enough.

[0327] On the other hand, the improvement of the on-state current of a transistor or the field effect mobility of a transistor In that case, it is preferable to increase the carrier density of the oxide semiconductor. In order to increase the carrier density of a nitride semiconductor, the impurity concentration of the oxide semiconductor must be increased slightly. Alternatively, the density of defect states in the oxide semiconductor may be increased slightly. It is advantageous to make the band gap of the compound semiconductor smaller. For example, the Id-V In the range where the on / off ratio of the g characteristic can be obtained, the impurity concentration is slightly high or the defect level is low. Oxide semiconductors with slightly higher potential density can be considered essentially intrinsic. As a result, the band gap becomes smaller, and the number of thermally excited electrons ( An oxide semiconductor with an increased density of carriers can be considered to be essentially intrinsic. When an oxide semiconductor having a large charge is used, the threshold voltage of a transistor is lowered. do.

[0328] The oxide semiconductor with the increased carrier density is slightly n-type. Therefore, oxide semiconductors with increased carrier density can be called "slightly-n". good.

[0329] The carrier density of a substantially intrinsic oxide semiconductor is 1×10 5 cm -3 More than 1×10 18 cm -3 Less than 1×10 is preferable. 7 cm -3 More than 1×10 17 cm -3 The following is preferred: 1×10 9 cm -3 5×10 or more 16 cm -3 More preferably, 1×10 1 0 cm -3 More than 1×10 16 cm -3 More preferably, 1×10 11 cm -3 End 1×10 15 cm -3 The following is even more preferred:

[0330] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0331] (Embodiment 3) In this embodiment, a display device including the transistor described in the above embodiment will be An example will be described below with reference to FIGS.

[0332] 22 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 is provided on the first substrate 701, and a source driver is provided on the first substrate 701. A pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, A sealant 712 is disposed so as to surround the path portion 704 and the gate driver circuit portion 706. and a second substrate 705 disposed so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 22, a display element is provided between the first substrate 701 and the second substrate 705. can be done.

[0333] The display device 700 is surrounded by a sealant 712 on the first substrate 701. In a region different from the region, a pixel section 702, a source driver circuit section 704, a gate driver circuit section FPC terminals electrically connected to the path portion 706 and the gate driver circuit portion 706, A sub-unit 708 (FPC: Flexible printed circuit) is provided. In addition, an FPC 716 is connected to the FPC terminal portion 708. Various signals are supplied to the element section 702, the source driver circuit section 704, and the gate driver circuit section 706. In addition, a pixel section 702, a source driver circuit section 704, a gate driver circuit section A signal line 710 is connected to the path portion 706 and the FPC terminal portion 708. Various signals supplied from 716 are transmitted through signal lines 710 to the pixel section 702, the source driver 716, and the like. 704, a gate driver circuit section 706, and an FPC terminal section 708. do.

[0334] The display device 700 may include a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is formed on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited, and may be Use COG (Chip On Glass) method, wire bonding method, etc. can be done.

[0335] The display device 700 also includes a pixel portion 702, a source driver circuit portion 704, and a gate The driver circuit portion 706 includes a plurality of transistors. A transistor having a specific position can be applied.

[0336] The display device 700 can also include various elements, such as: For example, electroluminescence (EL) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (light-emitting elements that emit light according to electric current) transistors, electron emission elements, liquid crystal elements, electronic ink elements, electrophoretic elements, Rowetting element, plasma display panel (PDP), MEMS (microelectromechanical systems) Electro-mechanical systems) displays (e.g., grating light bars) GLV, Digital Micromirror Device (DMD), Digital Microsha Dispersive Modulation (DMS) element, Interferometric Modulation (IMOD) element ), piezoelectric ceramic displays, etc.

[0337] An example of a display device using an EL element is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat panel display (SED: Surface-conductio n Electron-emitter Display) and others. An example of such a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). Display, reflective LCD display, direct-view LCD display, projection LCD display Examples of display devices using electronic ink elements or electrophoretic elements include: Electronic paper. Semi-transmissive LCDs and reflective LCDs are also used. In this case, a part or the whole of the pixel electrode should function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This can further reduce power consumption.

[0338] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying in color are R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a pixel, and a pixel of white (W). As in the column, two colors of RGB compose one color element, and two different colors are created by the color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. may be selected for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, and may be used in monochrome display devices. can also be applied to.

[0339] Also, white light is emitted from the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) In order to display full color using (W), a colored layer (also called a color filter) is The colored layer may be, for example, red (R), green (G), blue (B), or red (C). ), yellow (Y), etc. can be used in appropriate combination. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a color layer and a region not having a color layer, The white light in the region may be directly used for display. By placing the colored layer over the entire display, the decrease in brightness caused by the colored layer can be reduced during bright display, and power consumption can be reduced by 2. However, in some cases, the emission of light from organic EL elements and inorganic EL elements can be reduced by about 10 to 30%. When using optical elements to display full color, R, G, B, Y, and W are each emitted in different colors. By using a self-luminous element, it is possible to obtain a light emission from a colored layer. In some cases, power consumption can be reduced even further.

[0340] In addition, as a colorization method, a part of the light emitted from the above-mentioned white light is passed through a color filter. In addition to the color filter method, which converts the light into red, green, and blue by filtering the light, A method that uses two colors of light (three-color method), or a method that uses part of the light emitted from the blue light to emit red or A method for converting to green (color conversion method, quantum dot method) may be applied.

[0341] In this embodiment, a liquid crystal element and an EL element are used as display elements. 23 and 24. Note that FIG. 23 shows the state of the circuit shown in FIG. 22. FIG. 24 is a cross-sectional view of the liquid crystal display device, which uses a liquid crystal element as a display element. 22, which is a cross-sectional view taken along the dashed line QR, and shows a configuration in which an EL element is used as a display element. It is.

[0342] First, the common parts shown in FIG. 23 and FIG. 24 will be explained, and then the different parts will be explained. This will be explained below.

[0343] <Explanation of common parts of display device> The display device 700 shown in FIG. 23 and FIG. 24 includes a wiring portion 711 and a pixel portion 702. The display panel 700 includes a source driver circuit section 704 and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Yes.

[0344] Transistor 750 and transistor 752 are similar to transistor 100 shown above. The structures of the transistors 750 and 752 are the same as those described above. Any other transistors than those shown in the embodiment modes may be used.

[0345] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. It is possible to extend the retention time of electrical signals such as signals, and the write interval can be extended when the power is on. This allows the frequency of refresh operations to be reduced, resulting in reduced power consumption. It has the effect of suppressing power.

[0346] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section In other words, the driver transistor can be formed on the same substrate as the driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, a high quality image can be provided.

[0347] The capacitor 790 is formed using the same oxide semiconductor film as that of the transistor 750. The lower electrode formed through a process of processing the semiconductor film and the source electrode of the transistor 750 The conductive film that functions as the electrode and drain electrode is formed through a process of processing the same conductive film. A transistor 750 is disposed between the lower electrode and the upper electrode. The third insulating film and the fourth insulating film are formed through a process of forming the same insulating film. That is, the capacitor 790 functions as a dielectric between the pair of electrodes. It has a laminated structure in which an insulating film is sandwiched between the insulating film.

[0348] 23 and 24, a transistor 750, a transistor 752, and a capacitor A planarization insulating film 770 is provided on the capacitor 790 .

[0349] The planarization insulating film 770 may be made of a polyimide resin, an acrylic resin, or a polyimide amide resin. Heat-resistant organic materials such as benzocyclobutene resin, polyamide resin, and epoxy resin In addition, by stacking multiple insulating films made of these materials, A planarization insulating film 770 may be formed. Alternatively, the planarization insulating film 770 may not be provided. This is also fine.

[0350] 23 and 24, the transistor 750 and the A transistor having the same structure as the transistor 752 included in the source driver circuit portion 704 is used. The configuration used is illustrated above, but is not limited to this. For example, A transistor different from that in the driver circuit section 704 may be used.

[0351] Note that different transistors are used for the pixel portion 702 and the source driver circuit portion 704. In this case, the staggered transistor and the inverted staggered transistor shown in Embodiment 1 may be used. Specifically, a staggered transistor may be used in the pixel portion 702. 703 is configured to use an inverted staggered transistor in the source driver circuit section 704, Alternatively, an inverted staggered transistor is used in the pixel portion 702, and a source driver circuit portion 704 is used. A configuration using staggered transistors is also possible. The path section 704 may be read as a gate driver circuit section. The sintered body may have a channel-etched structure or a channel-protected structure. In addition, the inverted Starbuck transistor also has the S-channel structure described above. In addition, these transistor structures can be freely combined. Good too.

[0352] Signal line 710 functions as the source and drain electrodes of transistors 750 and 752. The signal line 710 is formed through the same process as the conductive film that functions as the transistor 750. , 752 source electrode and drain electrode, a conductive film formed through a process different from that, for example, The oxide semiconductor film formed through the same process as the oxide semiconductor film functioning as the gate electrode is For example, when a material containing copper is used for the signal line 710, the wiring resistance This reduces signal delays and enables large-screen display.

[0353] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed through the same process as the conductive film that functions as the drain electrode. , and is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780 .

[0354] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0355] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. A device for controlling the distance (cell gap) between the first substrate 701 and the second substrate 705 is provided. In addition, a spherical spacer may be used as the structure 778.

[0356] In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and A colored film 736 that functions as a color filter, a light-shielding film 738 that is in contact with the colored film 736, and An insulating film 734 is provided.

[0357] <Example of the configuration of a display device using a liquid crystal element> The display device 700 shown in FIG. 23 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film The conductive film 774 is a second substrate 705. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. By controlling the light transmission or non-transmission, an image can be displayed.

[0358] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is connected to a conductive film that functions as a pixel electrode. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display device 700 shown in FIG. The liquid crystal display device 730 is a so-called reflective color liquid crystal display device, which reflects the light and displays it through the colored film 736.

[0359] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a reflectivity can be used. For example, a material containing one of the elements indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed of A conductive film that is reflective in visible light is used.

[0360] In the display device 700 shown in FIG. 23, the planarization insulating film 770 of the pixel section 702 The unevenness is provided in a part. For example, the flattening insulating film 770 is made of a resin film. The surface of the resin film may be provided with irregularities to form the reflecting electrode. The conductive film 772 is formed along the above-mentioned unevenness. When the light is incident on the conductive film 772, the light can be diffusely reflected on the surface of the conductive film 772. It is possible to improve the performance.

[0361] The display device 700 shown in FIG. 23 is a reflective color liquid crystal display device. However, the present invention is not limited to this. For example, the conductive film 772 may be a conductive film that transmits visible light. A transmissive color liquid crystal display device may be formed by using the above-mentioned. In this case, the unevenness provided in the planarization insulating film 770 does not necessarily have to be provided.

[0362] An example of a transmissive color liquid crystal display device is shown in FIG. 25. FIG. 25 shows the same as that shown in FIG. This is a cross-sectional view taken along the dashed line QR, and shows a configuration in which liquid crystal elements are used as display elements. In addition, the display device 700 shown in FIG. 25 uses a horizontal electric field method (for example, F In the configuration shown in FIG. 25, the pixel electrode functions as An insulating film 773 is provided over a conductive film 772, and a conductive film 774 is provided over the insulating film 773. In this case, the conductive film 774 functions as a common electrode. An electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773 causes the liquid The orientation of the crystal layer 776 can be controlled.

[0363] Although not shown in FIGS. 23 and 25, the conductive film 772 or the conductive film 774 An alignment film is provided on either one or both of the surfaces of the liquid crystal layer 776. 23 and 25, a polarizing member, a phase difference member, a reflecting member, etc. Optical members (optical substrates) such as a polarizing substrate and a positioning member may be provided as appropriate. Circularly polarized light produced by a retardation substrate may be used. Either may be used.

[0364] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0365] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. Since the liquid crystal display has a short rotational angle and is optically isotropic, no alignment treatment is required. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is prevented. This can prevent the occurrence of defects or damage to the liquid crystal display device during the manufacturing process. Furthermore, liquid crystal materials exhibiting a blue phase have little viewing angle dependency.

[0366] In addition, when liquid crystal elements are used as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero lectric Liquid Crystal) mode, AFLC (AntiFerr Electrochemical Liquid Crystal (ECC) mode can be used. .

[0367] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode mode, ASV mode, etc. can be used.

[0368] <Display device using light-emitting elements> The display device 700 shown in FIG. 24 includes a light-emitting element 782. The light-emitting element 782 is a conductive film The display device 700 shown in FIG. The EL layer 786 of the light element 782 emits light, thereby displaying an image. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0369] Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy type quantum dot materials, core-shell type quantum dot materials, core type quantum dot materials, In addition, the elements of the 12th and 16th families, the 13th and 15th families, or the 14th and 16th families Materials containing the element group may also be used. Cadmium (Cd), selenium (Se), Zinc (Zn), Sulfur (S), Phosphorus (P), Indium (In), Tellurium (Te), Lead (P b) Quantum with elements such as gallium (Ga), arsenic (As), aluminum (Al), etc. Dot material may also be used.

[0370] The conductive film 784 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is connected to a conductive film that functions as a pixel electrode. The conductive film 784 functions as an electrode, that is, one of the electrodes of the display element. In the above, a conductive film that transmits light or a conductive film that reflects visible light can be used. Examples of conductive films that are transparent to visible light include indium (In), zinc (Zn), and ZnO. It is recommended to use a material containing one of the following elements: Zn (Zn) or tin (Sn). The reflective conductive film may be made of a material containing aluminum or silver. stomach.

[0371] In addition, in the display device 700 shown in FIG. An insulating film 730 is provided. The insulating film 730 covers a part of the conductive film 784. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits the light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to this. For example, a bottom emission structure in which light is emitted to both the conductive film 784 and the conductive film 788; It can also be applied to al-emission structures.

[0372] A colored film 736 is provided at a position overlapping the light emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided at the position where the light-shielding film 738 is to be formed, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is illustrated. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0373] <Example of configuration in which an input / output device is provided in a display device> Also, an input / output device may be provided in the display device 700 shown in FIG. An example of the force device is a touch panel.

[0374] 26 and 27, a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. 24 and FIG. 25 is shown. This is shown in Figure 27.

[0375] FIG. 26 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. FIG. 27 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. be.

[0376] First, the touch panel 791 shown in FIG. 26 and FIG. 27 will be described below.

[0377] The touch panel 791 shown in FIG. 26 and FIG. 27 is provided between a substrate 705 and a colored film 736. The touch panel 791 is a so-called in-cell type touch panel. 736 may be formed on the substrate 705 side before the colored film 736 is formed.

[0378] The touch panel 791 includes a light-shielding film 738, an insulating film 792, an electrode 793, and an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. When a detection object such as a stylus approaches, the mutual capacitance between electrode 793 and electrode 794 changes. It is possible to detect the change.

[0379] 26 and 27, an electrode 793 and The electrode 796 is formed by passing through an opening in the insulating film 795. The electrode 794 is electrically connected to the two electrodes 793 that sandwich the electrode 794 via the electrodes 793. 27, a configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702 is illustrated. However, the present invention is not limited to this. For example, the light emitting diode 704 may be formed in the source driver circuit section 704.

[0380] The electrodes 793 and 794 are provided in a region overlapping with the light-shielding film 738. As shown in FIG. 1, the electrode 793 is preferably provided so as not to overlap with the light-emitting element 782. As shown in FIG. 27, the electrode 793 is provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 overlaps with the light-emitting element 782 and the liquid crystal element 775. In other words, the electrode 793 has a mesh shape. By this configuration, the electrode 793 does not block the light emitted by the light emitting element 782. Alternatively, the electrode 793 may be configured so as not to block light passing through the liquid crystal element 775. Therefore, the reduction in brightness due to the placement of the touch panel 791 is extremely small. Since the number of pixels is small, a display device with high visibility and reduced power consumption can be realized. The pole 794 may be of a similar configuration.

[0381] In addition, since the electrodes 793 and 794 do not overlap with the light-emitting element 782, The electrode 794 may be made of a metal material having a low transmittance of visible light. Since the electrodes 793 and 794 do not overlap with the liquid crystal element 775, In addition, a metal material having a low transmittance of visible light can be used.

[0382] Therefore, compared with electrodes using oxide materials with high visible light transmittance, the electrodes 793 and The resistance of the electrode 794 can be reduced, improving the sensor sensitivity of the touch panel. It is possible.

[0383] For example, the electrodes 793, 794, and 796 may be made of conductive nanowires. The nanowires have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm. The size of the nanoparticles may be 5 nm or less, and more preferably 5 nm or more and 25 nm or less. The wires are metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires. For example, electrodes 664, 665, 6666, etc. may be used. When Ag nanowires are used for either 65 or 667, or for all of them, the The light transmittance is 89% or more, and the sheet resistance is 40Ω / sq. to 100Ω / sq. It is possible.

[0384] 26 and 27 show examples of the configuration of an in-cell type touch panel. However, the present invention is not limited to this. For example, a so-called on-cell type transistor formed on the display device 700 may be used. A so-called out-cell type touch panel that is attached to the display device 700. It is also possible to use the following.

[0385] In this manner, the display device according to one embodiment of the present invention can be used in combination with various types of touch panels. It can be used.

[0386] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0387] (Embodiment 4) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0388] <Circuit configuration of display device> The display device shown in FIG. 28A has a region having pixels of a display element (hereinafter, referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504) and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. This is also fine.

[0389] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or the whole of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Band). It can be implemented by using the onding.

[0390] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter, referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter, a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a) to provide a signal (data signal) for driving the display element of the pixel. The pixel circuit 504 includes a driver circuit such as a circuit (hereinafter, referred to as a source driver 504b).

[0391] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via a terminal unit 507, and a signal is output. For example, a start pulse signal, a clock signal, etc. are input to the gate driver 504a. The gate driver 504a outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it. However, the gate driver 50 has a function of supplying 4a may also provide another signal.

[0392] The source driver 504b includes a shift register and the like. Through the terminal section 507, a signal for driving the shift register as well as a source of a data signal are input. The source driver 504b outputs a pixel circuit based on the image signal. The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data line 101 through the data line 102. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may supply other signals. It is possible.

[0393] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a number of analog switches, The image signal can be time-division-multiplexed and output as a data signal. Also, a shift register, etc. This may be used to configure the source driver 504b.

[0394] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is inputted through the data line DL, and a data signal is given through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. For example, The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or smaller than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via a source driver 504c (n is a natural number equal to or smaller than Y).

[0395] The protection circuit 506 shown in FIG. 28(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal unit 507. Alternatively, the protection circuit 506 may be a wiring between the source driver 504b and the terminal unit 507. The terminal unit 507 can be connected to a power supply and a power supply line from an external circuit to the display device. This refers to the part provided with terminals for inputting control signals and image signals.

[0396] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit This is a circuit that brings one wire into electrical continuity with another wire.

[0397] As shown in FIG. 28A, a protection circuit 50 is provided in each of a pixel section 502 and a driver circuit section 504. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrent caused by electrostatic discharge (ESD) and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal portion 507. It can also be written as:

[0398] In FIG. 28A, the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit is formed separately. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is It may also be configured to be equipped with

[0399] In addition, the pixel circuits 501 shown in FIG. 28(A) may be, for example, a configuration shown in FIG. 28(B). It can be said that:

[0400] The pixel circuit 501 shown in FIG. 28B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiment. can be applied.

[0401] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0402] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned M icro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of different types of sensors can be used.

[0403] In the pixel circuit 501 in the mth row and the nth column, One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the scan lines G The transistor 550 is electrically connected to the data signal writing terminal L_m. It has the function of controlling.

[0404] One of a pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0405] For example, in a display device having the pixel circuit 501 shown in FIG. The pixel circuits 501 in each row are sequentially selected by a gate driver 504a shown in FIG. 550 is turned on to write data of the data signal.

[0406] In the pixel circuit 501 in which data has been written, the transistor 550 is turned off. By repeating this process row by row, an image can be displayed.

[0407] In addition, the pixel circuits 501 shown in FIG. 28(A) may have a configuration shown in FIG. 28(C), for example. It can be said that:

[0408] The pixel circuit 501 shown in FIG. 28C includes transistors 552 and 554 and a capacitance element. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either or both of the above. .

[0409] A data signal is applied to one of the source and drain electrodes of the transistor 552. The transistor 55 is electrically connected to a wiring (hereinafter, referred to as a signal line DL_n). The gate electrode of 2 is electrically connected to the wiring (hereinafter referred to as the scanning line GL_m) to which the gate signal is applied. are connected to the network.

[0410] The transistor 552 has a function of controlling writing of data signals.

[0411] One of a pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0412] The capacitor 562 functions as a storage capacitor for storing written data.

[0413] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. In addition, the gate electrode of the transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0414] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b. The other one is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0415] The light-emitting element 572 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0416] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0417] In a display device having the pixel circuit 501 shown in FIG. 28C, for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0418] In the pixel circuit 501 to which the data has been written, the transistor 552 is turned off. Furthermore, the transistor 554 is in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted with a brightness that corresponds to the flow rate. By performing this process row by row, an image can be displayed.

[0419] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0420] (Embodiment 5) In this embodiment, the circuit configuration to which the transistors described in the above embodiment can be applied is An example will be described with reference to FIGS.

[0421] Note that in this embodiment, the transistor having the oxide semiconductor described in the above embodiment In the following description, the above-mentioned transistor will be referred to as an OS transistor.

[0422] <Example of inverter circuit configuration> FIG. 29(A) shows a circuit that can be applied to a shift register, a buffer, etc. in a driver circuit. 8 shows a circuit diagram of an inverter 800 that can convert the logic of a signal provided to an input terminal IN into a The inverter 800 outputs an inverted signal of the OS transistors to the output terminal OUT. Signal S BG is a signal that can switch the electrical properties of an OS transistor. The number is.

[0423] FIG. 29B is an example of an inverter 800. The inverter 800 is an OS transistor. The inverter 800 includes an n-channel Since it can be fabricated using only complementary metal-oxide semiconductor (CMOS) transistors, Y Metal Oxide Semiconductor inverter (CMOS inverter) It is possible to manufacture the device at a lower cost than manufacturing a conventional inverter.

[0424] The inverter 800 having OS transistors is made of Si transistors. The inverter 800 can be placed on the CMOS circuit. Therefore, an increase in the circuit area due to the addition of the inverter 800 can be suppressed.

[0425] The OS transistors 810 and 820 each have a first gate functioning as a front gate and a back gate. The second gate acts as a gate electrode and the first gate acts as either a source or a drain. It has one terminal and a second terminal that functions as the other of the source or drain.

[0426] The first gate of the OS transistor 810 is connected to the second terminal. The second gate of 10 is the signal S BG The OS transistor 810 is connected to a wiring that supplies The first terminal of the OS transistor 810 is connected to a wiring that supplies a voltage VDD. The input terminal is connected to the output terminal OUT.

[0427] A first gate of the OS transistor 820 is connected to the input terminal IN. A second gate of the OS transistor 820 is connected to the input terminal IN. The second terminal of the OS transistor 820 is connected to the output terminal OUT. The GND is connected to a wire that supplies

[0428] FIG. 29C is a timing chart for explaining the operation of the inverter 800. In the timing chart of FIG. 29(C), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are Signal waveform, signal S BG 8 and the change in the threshold voltage of the OS transistor 810. This shows the following:

[0429] signal S BG to the second gate of the OS transistor 810. The threshold voltage of 810 can be controlled.

[0430] signal S BG is the voltage V for shifting the threshold voltage negatively. BG_A ,threshold Voltage V for positively shifting the voltage BG_B The second gate has a voltage V BG_A By providing TH_A negative shift to Also, the second gate can be connected to the voltage V BG_B By providing The threshold voltage V TH_B can be shifted positively to

[0431] To visualize the above explanation, Figure 30(A) shows one of the electrical characteristics of a transistor. 1 shows an Id-Vg curve.

[0432] The electrical characteristics of the OS transistor 810 described above are as follows: BG_A of By increasing the value so as to shift the curve to the dashed line 840 in FIG. The electrical characteristics of the OS transistor 810 can be expressed as follows: Voltage V BG_B By making it smaller, the curve represented by the solid line 841 in FIG. As shown in FIG. 30A, the OS transistor 810 can be signal S BG to the voltage V BG_A Or voltage V BG_B By switching like this, The threshold voltage can be shifted positively or negatively.

[0433] Threshold voltage V TH_B By shifting the OS transistor The capacitor 810 can be made to have a state in which it is difficult for a current to flow. Visualize and show.

[0434] As shown in FIG. 30B, a current I B Extremely small Therefore, when the signal applied to the input terminal IN is high level, the OS trans When the resistor 820 is in the ON state, it causes the voltage at the output terminal OUT to drop sharply. can be done.

[0435] As shown in FIG. 30B, a current is unlikely to flow through the OS transistor 810. Therefore, the output terminal in the timing chart shown in FIG. The signal waveform 831 can be changed sharply. Since the through current flowing between the wiring that supplies S can be reduced, it is possible to achieve low power consumption. The action can be performed.

[0436] Also, the threshold voltage is V TH_A By shifting it negatively, the OS The transistor 810 can be made to be in a state in which a current can easily flow. The state is visualized. As shown in FIG. 30(C), the current I A Less At least current I B Therefore, the signal applied to the input terminal IN can be When the OS transistor 820 is in an off state (OFF) at a low level, the voltage of the output terminal OUT As shown in FIG. 30(C), the OS transistor Since the current flowing through 810 can be made to flow easily, the type shown in FIG. This allows the signal waveform 832 at the output terminal in the timing chart to be changed sharply.

[0437] In addition, signal S BG The control of the threshold voltage of the OS transistor 810 by It is preferable to perform this before the state of register 820 changes, i.e., before time T1 or T2. For example, as shown in FIG. 29(C), when the signal applied to the input terminal IN is high level, Before the time T1 when the transistor switches to the TH_A From the threshold voltage V TH _B It is preferable to change the threshold voltage of the OS transistor 810 in FIG. As shown in FIG. 9(C), the signal applied to the input terminal IN is switched to a low level at time T Before 2, the threshold voltage V TH_B to threshold voltage V TH_A OS transistor It is preferable to switch the threshold voltage of 810.

[0438] In the timing chart of FIG. 29(C), the signal changes according to the signal applied to the input terminal IN. No. S BG However, other configurations may be used. For example, the threshold voltage is The control voltage is applied to the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. As shown in (A).

[0439] In FIG. 31A, in addition to the circuit configuration shown in FIG. 29B, an OS transistor 850 The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to a voltage V BG_B (Or electricity Pressure V BG_A The first gate of the OS transistor 850 is connected to a wiring that provides a signal No. S F The second gate of the OS transistor 850 is connected to a wiring that supplies a voltage V BG _B (or voltage V BG_A ) is connected to the wire that provides the

[0440] The operation of FIG. 31(A) will be described with reference to the timing chart of FIG. 31(B).

[0441] A voltage for controlling the threshold voltage of the OS transistor 810 is applied to the input terminal IN. The second gate of OS transistor 810 is turned on before time T3 when the signal The signal S F is set to a high level to turn on the OS transistor 850. In this state, node N BG Voltage V for controlling the threshold voltage BG_B Gives.

[0442] Node N BG is the voltage V BG_B After this, the OS transistor 850 is turned off. The OS transistor 850 has an extremely small off-state current and can be kept in an off state. So, once node N BG The threshold voltage V BG_B It is possible to hold Therefore, the second gate of the OS transistor 850 is supplied with a voltage V BG_B The number of actions to give is reduced. Therefore, the voltage V BG_B Therefore, the power consumption required for rewriting the data can be reduced.

[0443] In the circuit configurations in FIGS. 29B and 31A, the second We have shown a configuration in which the voltage applied to the gate is controlled from outside, but we will also consider other configurations. For example, a signal for controlling the threshold voltage may be applied to the input terminal IN. and provided to the second gate of the OS transistor 810. FIG. 32A shows an example of a circuit configuration that can realize the above configuration.

[0444] In FIG. 32(A), the input terminal IN and the OS transistor are connected in the circuit configuration shown in FIG. 29(B). A CMOS inverter 860 is provided between the second gate of the transistor 810 and the CMOS inverter 860. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal is connected to the second gate of OS transistor 810.

[0445] The operation of FIG. 32(A) will be described with reference to the timing chart of FIG. 32(B). In the timing chart of FIG. 32(B), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are 8, the output waveform IN_B of the CMOS inverter 860, and the output waveform IN_C of the OS transistor 810. The change in threshold voltage is shown.

[0446] The output waveform IN_B, which is the inverted signal of the signal applied to the input terminal IN, is The threshold voltage of the transistor 810 can be controlled by the signal shown in FIG. As described with reference to FIGS. 30A to 30C, the threshold voltage of the OS transistor 810 is controlled. For example, at time T4 in FIG. 32(B), the signal applied to the input terminal IN is When the signal is at a high level, the OS transistor 820 is turned on. B is at a low level. Therefore, the OS transistor 810 is in a state where it is difficult for a current to flow. Therefore, the rising voltage of the output terminal OUT can be made to drop sharply.

[0447] At time T5 in FIG. 32(B), the signal applied to the input terminal IN becomes low. At this time, the OS transistor 820 is turned off. Therefore, the OS transistor 810 can be in a state where a current easily flows. This allows the voltage at the output terminal OUT to rise sharply.

[0448] As described above, in the configuration of this embodiment, the inverter having the OS transistor The back gate voltage is switched according to the logic of the signal at the input terminal IN. By using this configuration, the threshold voltage of the OS transistor can be controlled. The threshold voltage of the OS transistor is controlled by the signal applied to IN. The OUT voltage can be changed sharply. This allows the current to be reduced, thereby enabling low power consumption.

[0449] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0450] (Embodiment 6) In this embodiment, the transistor including the oxide semiconductor described in the above embodiment ( FIG. 33 and FIG. 34 show an example of a semiconductor device using an OS transistor in a plurality of circuits. This will be explained using 6.

[0451] <Example of circuit configuration of semiconductor device> FIG. 33A is a block diagram of a semiconductor device 900. The semiconductor device 900 is A circuit 901, a circuit 902, a voltage generating circuit 903, a circuit 904, a voltage generating circuit 905, and a circuit It has a path 906.

[0452] The power supply circuit 901 supplies a reference voltage V ORG This is a circuit that generates a voltage V ORG teeth, It is acceptable to use multiple voltages instead of a single voltage. Voltage V ORG From the outside of the semiconductor device 900 The semiconductor device 900 can generate the voltage V1 based on the voltage V2 given from the outside. Based on a single power supply voltage, the voltage V ORG Therefore, the semiconductor device 900 can generate It can operate without applying multiple power supply voltages from the outside.

[0453] Circuits 902, 904, and 906 are circuits that operate on different power supply voltages. The power supply voltage of the circuit 902 is the voltage V ORG and voltage V SS (V ORG >V SS ) and applied by The power supply voltage for the circuit 904 is the voltage V POG and voltage V SS ( V POG >V ORG ) is a voltage applied by the power supply of the circuit 906. Voltage is voltage V ORG and voltage V NEG (V ORG >V SS >V NEG ) and applied by The voltage V SS If the potential is the same as the ground (GND), the power supply circuit The number of types of voltages generated by 901 can be reduced.

[0454] The voltage generating circuit 903 generates a voltage V POG The voltage generating circuit 903 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V POG Therefore, The semiconductor device 900 having the circuit 904 operates based on a single power supply voltage provided from the outside. It can be made.

[0455] The voltage generating circuit 905 generates a voltage V NEG The voltage generating circuit 905 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V NEG Therefore, The semiconductor device 900 having the circuit 906 operates based on a single power supply voltage provided from the outside. It can be made.

[0456] Figure 33(B) shows the voltage V POG FIG. 33C shows an example of a circuit 904 that operates in accordance with the 4 is an example of a waveform of a signal for operating the

[0457] FIG. 33B shows a transistor 911. The applied signal is, for example, a voltage V POG and voltage V SS The signal is generated based on the When the transistor 911 is in the conductive state, the voltage V POG , the voltage when in non-conducting state V SS Let the voltage V POG As shown in FIG. 33(C), the voltage V ORG Bigger Therefore, the transistor 911 is in a conductive state between the source (S) and the drain (D). As a result, the circuit 904 is less likely to malfunction. The circuit can be constructed as follows.

[0458] Figure 33(D) shows the voltage V NEG FIG. 33(E) shows an example of a circuit 906 that operates in accordance with the 4 is an example of a waveform of a signal for operating the

[0459] FIG. 33D shows a transistor 912 having a back gate. The signal applied to the gate of the transistor 912 is, for example, a voltage V ORG and voltage V SS Generated based on The signal is a voltage V ORG , Non-guided When the voltage V SS In addition, the back gate of the transistor 912 is The voltage that can be applied is V NEG It is generated based on the voltage V NEG is illustrated in FIG. So, the voltage V SS (GND). Therefore, the threshold voltage of transistor 912 The voltage can be controlled to be positively shifted. This makes it possible to more reliably put the device into a non-conductive state, and current flowing between the source (S) and the drain (D) is As a result, the circuit 906 can reduce malfunctions and consume less power. The circuit shown in FIG.

[0460] In addition, the voltage V NEG can also be applied directly to the back gate of the transistor 912. Alternatively, the voltage V ORG and voltage V NEG Based on this, a voltage is applied to the gate of the transistor 912. Alternatively, a signal that corresponds to the back gate of the transistor 912 may be generated and provided to the back gate of the transistor 912. good.

[0461] Also, Figures 34(A) and (B) show modifications of Figures 33(D) and (E).

[0462] In the circuit diagram shown in FIG. 34(A), a control circuit is provided between a voltage generating circuit 905 and a circuit 906. A transistor 922 whose conduction state can be controlled by a path 921 is shown. The control signal S output from the control circuit 921 is an n-channel OS transistor. BG is a signal for controlling the conduction state of the transistor 922. Transistors 912A and 912B are OS transistors similar to transistor 922.

[0463] In the timing chart of FIG. 34(B), the control signal S BG and transistor 912A, The state of the potential of the back gate of 912B is BG The control signal S B G When the voltage at the node N BG is the voltage V N EG Then, the control signal S BG When is low, node N BG Electrically flow Since the transistor 922 is an OS transistor, its off-state current is small. Therefore, node N BG Even if the voltage V is electrically floating, NEG can be held.

[0464] FIG. 35A shows an example of a circuit configuration that can be applied to the voltage generating circuit 903 described above. The voltage generating circuit 903 shown in FIG. The charge pump has five stages including C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 through C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS and is applied by If the voltage V ORG is boosted to a positive voltage five times higher than the Voltage V POG The forward voltage of the diodes D1 to D5 is 0V. In addition, by changing the number of charge pump stages, the desired voltage V POG Get It is possible.

[0465] FIG. 35B shows an example of a circuit configuration that can be applied to the voltage generating circuit 905 described above. The voltage generating circuit 905 shown in FIG. The charge pump has four stages including C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 through C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS and is applied by If the voltage at the clock signal CLK is SS From Pressure V ORG The voltage V is stepped down to a negative voltage four times higher than the NEG It is possible to obtain the above. The forward voltage of the nodes D1 to D5 is set to 0 V. In addition, the number of stages of the charge pump is changed. This allows the desired voltage V NEG can be obtained.

[0466] The circuit configuration of the voltage generating circuit 903 described above corresponds to the circuit configuration shown in FIG. For example, modified examples of the voltage generating circuit 903 are shown in FIGS. In addition, the modified example of the voltage generating circuit 903 is the voltage generating circuit shown in FIG. In the circuits 903A to 903C, the voltage applied to each wiring may be changed, or the elements This can be achieved by changing the arrangement of the

[0467] The voltage generating circuit 903A shown in FIG. The clock signal CLK is supplied to the transistors C11 to C14 and the inverter INV1. The gates of the transistors M1 to M10 are supplied directly or through an inverter INV1. The clock signal CLK drives the voltage V ORG The voltage V is boosted to four times the positive voltage PO G By changing the number of stages, the desired voltage V POG to get The voltage generating circuit 903A shown in FIG. By using S transistors, the off-state current can be reduced, and the capacitors C11 to C14 are This effectively suppresses the leakage of the charge. ORG to voltage V POG Ascension to It is possible to measure pressure.

[0468] The voltage generating circuit 903B shown in FIG. The clock signal CLK is , directly to the gates of transistors M11 to M14 or via inverter INV2 The clock signal CLK generates a voltage V ORG The voltage boosted to twice the positive voltage Pressure V POG The voltage generating circuit 903B shown in FIG. By using OS transistors as the transistors M11 to M14, the off-state current can be reduced. This can suppress leakage of the charge stored in the capacitors C15 and C16. Therefore, the voltage V ORG to voltage V POG It is possible to boost the voltage to

[0469] The voltage generating circuit 903C shown in FIG. The transistor M15 has a diode D6 and a capacitor C17. The conduction state is controlled by the control signal EN. The control signal EN controls the voltage V ORG but The boosted voltage V POG The voltage generating circuit 903C shown in FIG. Since the inductor Ind1 is used to boost the voltage, the voltage is boosted with high conversion efficiency. It is possible to do so.

[0470] As described above, in the configuration of this embodiment, the voltage required for the circuit of the semiconductor device is This allows the semiconductor device to reduce the number of power supply voltages that are applied from the outside. It can be reduced.

[0471] The configurations described in this embodiment mode may be used in appropriate combination with configurations described in other embodiment modes. There can be.

[0472] (Embodiment 7) In this embodiment, a display module and an electronic device each including a semiconductor device according to one embodiment of the present invention will be described. This will be described with reference to FIGS.

[0473] <Display module> The display module 7000 shown in FIG. 37 includes an upper cover 7001 and a lower cover 7002. Between them, touch panel 7004 connected to FPC 7003 and A display panel 7006, a backlight 7007, a frame 7009, and a printed circuit board 701 0, has battery 7011.

[0474] The semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.

[0475] The upper cover 7001 and the lower cover 7002 are connected to the touch panel 7004 and the display panel The shape and dimensions can be changed as appropriate to match the size of 7006.

[0476] The touch panel 7004 is a resistive or capacitive touch panel. The display panel 7006 may be overlapped with the opposing substrate (sealing substrate). It is also possible to provide the display panel 7 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 006 to make it into an optical touch panel.

[0477] The backlight 7007 has a light source 7008. In the above embodiment, the light source 7008 is disposed on the light source 7007. However, the present invention is not limited to this. For example, a light source 7008 is arranged at the end of a backlight 7007, and a light diffusion plate is further used. In addition, when a self-luminous light-emitting element such as an organic EL element is used, or when a reflective In the case of a liquid crystal panel, the backlight 7007 may not be provided.

[0478] The frame 7009 protects the display panel 7006 and also supports the movement of the printed circuit board 7010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the frame. The frame 7009 may also function as a heat sink.

[0479] The printed circuit board 7010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 7011 provided separately. , this can be omitted when using a commercial power source.

[0480] In addition, the display module 7000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0481] <Electronic equipment 1> Next, examples of electronic devices are shown in FIGS.

[0482] FIG. 38(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0483] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0484] In this example, a camera 8000 is used, and a lens 8006 is detached from a housing 8001 and replaced. However, the lens 8006 and the housing may be integrated together.

[0485] The camera 8000 can capture an image by pressing the shutter button 8004. The display unit 8002 also functions as a touch panel. It is also possible to capture an image by doing so.

[0486] The housing 8001 of the camera 8000 has a mount having electrodes, and a finder 810 In addition to 0, strobe devices etc. can also be connected.

[0487] The finder 8100 includes a housing 8101, a display unit 8102, a button 8103, and the like. .

[0488] The housing 8101 has a mount that engages with the mount of the camera 8000, The mount can be attached to the camera 8000. The mount also includes an electrode The image received from the camera 8000 through the electrode is displayed on the display unit 8102. It is possible to do so.

[0489] The button 8103 functions as a power button. The 8102 display can be switched on and off.

[0490] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied.

[0491] In FIG. 38(A), the camera 8000 and the finder 8100 are treated as separate electronic devices. These are configured to be removable, but the camera 8000 has a housing 8001 equipped with a display device. The camera may have a built-in viewfinder that can be used to capture images.

[0492] FIG. 38B is a diagram showing the external appearance of the head mounted display 8200.

[0493] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0494] A cable 8205 supplies power from a battery 8206 to the main body 8203. 03 is equipped with a wireless receiver and the like, and image information such as image data received is displayed on a display unit 8204. In addition, the camera installed in the main body 8203 can record the movement of the user's eyeballs and eyelids. The system captures the user's gaze and calculates the coordinates of the user's gaze based on that information. It can be used as an input means.

[0495] Furthermore, the mounting unit 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 detects the current flowing through the electrodes in response to the movement of the user's eyeball, The device may have a function of recognizing the user's viewpoint. Also, the device may have a function of detecting the current flowing through the electrode. By doing so, the mounting unit 820 may have a function of monitoring the pulse of the user. The sensor 1 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The device may have a function of displaying the user's biological information on the display unit 8204. The image displayed on the display unit 8204 is changed according to the movement of the part. Good too.

[0496] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0497] 38(C), (D), and (E) are diagrams showing the appearance of the head mounted display 8300. be.

[0498] The head mounted display 8300 includes a housing 8301, a display unit 8302, and a band-shaped It has a fixture 8304 and a pair of lenses 8305 .

[0499] A user can view the display on the display unit 8302 through the lens 8305 . It is preferable to arrange the display portion 8302 in a curved manner. By placing the device in this way, users can experience a high level of realism.

[0500] The display device of one embodiment of the present invention can be applied to the display portion 8302. A display device having such a semiconductor device can have extremely high definition. Even if the image is enlarged using a lens 8305 as in (E), the pixels are still visible to the user. This makes it possible to display more realistic images without requiring special equipment.

[0501] <Electronic equipment 2> Next, an example of an electronic device different from the electronic devices shown in FIG. 38(A) to FIG. 38(E) will be described with reference to FIG. 9(A) to 39(G).

[0502] The electronic device shown in FIG. 39A to FIG. 39G includes a housing 9000, a display portion 9001, a switch A speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared rays), 9008, etc.

[0503] The electronic devices shown in FIGS. 39A to 39G have various functions. Function to display various information (still images, videos, text images, etc.) on the display unit, touch panel function , calendar, date or time display functions, various software (programs) A function for controlling processing by wireless communication, a function for controlling various computers by using wireless communication, Functions for connecting to a network and transmitting or receiving various data using wireless communication functions A function to read out a program or data recorded on a recording medium and display it on the display unit. The electronic devices shown in FIGS. The functions that can be possessed by the can be not limited to these, and can have various functions. Although not shown in FIG. 39(A) to FIG. 39(G), the electronic device may have a plurality of display units. The electronic device may be provided with a camera or the like to capture still images. , the function to shoot videos, and save the captured images to a recording medium (external or built-in to the camera) The camera may have a function of capturing an image on a display unit, a function of displaying a captured image on a display unit, etc.

[0504] The electronic devices shown in FIGS. 39A to 39G will be described in detail below.

[0505] FIG. 39(A) is a perspective view showing a television device 9100. 100 is a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more It is possible to incorporate a display unit 9001 such as the above.

[0506] FIG. 39B is a perspective view showing a portable information terminal 9101. For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. Specifically, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The information terminal 9101 can display text and image information on multiple sides. The four operation buttons 9050 (also called operation icons or simply icons) are provided on the display unit 9001. In addition, information 9051 indicated by a dashed rectangle can be displayed on one surface of the display unit 900. 1. An example of the information 9051 is an e-mail or Displays to notify you of incoming calls and SNS (social networking services), Subject of email or SNS, sender name of email or SNS, date and time, time, The remaining battery level, antenna reception strength, etc. Or, the information 9051 is displayed. In place of the information 9051, operation buttons 9050 or the like may be displayed.

[0507] FIG. 39C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different sides. The user of the portable information terminal 9102 holds the portable information terminal 9102 in the breast pocket of the clothes. In this state, the display (information 9053 in this case) can be confirmed. The telephone number or name of the caller is displayed on the mobile information terminal 9102 so that it can be observed from above. The user can read the display without taking the mobile information terminal 9102 out of his pocket. You can check the number and decide whether to answer the call or not.

[0508] 39(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The 9200 is used for mobile phone calls, e-mail, document browsing and writing, music playback, and Internet communications. It is possible to execute various applications such as computer games. The display unit 9001 has a curved display surface, and displays information along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, The mobile information terminal 9200 also has a connection terminal 9006. It has a connector and can directly exchange data with other information terminals. Charging can also be performed via the connection terminal 9006. Power may also be supplied wirelessly without going through 6.

[0509] 39(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 39(E) is a perspective view of the portable information terminal 9201 in an unfolded state. (F) shows the mobile information terminal 9201 being changed from one of the unfolded and folded states to the other. FIG. 39(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded and is unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 9001 is made up of three housings 9000 connected by hinges 9055. The two housings 9000 are supported by the hinge 9055. The portable information terminal 9201 can be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0510] 40(A) and (B) are perspective views of a display device having a plurality of display panels. FIG. 40(A) is a perspective view of a state in which a plurality of display panels are rolled up, and FIG. ) is a perspective view of a state in which a plurality of display panels are unfolded.

[0511] The display device 9500 shown in FIG. 40(A) and (B) includes a plurality of display panels 9501 and a shaft portion 9 511 and a bearing portion 9512. The display panels 9501 have a display area 9502 and a light-transmitting region 9503.

[0512] In addition, the display panels 9501 are flexible. The filters 9501 are arranged so that they partially overlap each other. For example, A light-transmitting region 9503 of the display panel 9501 can be overlapped. By using the display panel 9501, a large-screen display device can be provided. The display panel 9501 can be rolled up depending on the situation, making it a versatile display. The display device may be a display device.

[0513] In addition, in FIG. 40(A) and (B), the display area 9502 is adjacent to the display panel 950 1 shows a state in which the display panels are spaced apart from each other, but this is not limited thereto. For example, the display panels 9 By overlapping the display areas 9502 of 501 without any gaps, a continuous display area 9502 is created. You may do so.

[0514] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is an electronic device that does not have a display portion. This can also be applied to vessels.

[0515] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done. EXAMPLES

[0516] In this embodiment, a gate electrode of a transistor according to one embodiment of the present invention can be used. The results of measuring the sheet resistance and contact resistance of the materials are shown below.

[0517] The preparation method of the samples used in this example will be described below. Samples A1 and A2 Then, a thin film is formed from a material that can be used as the second gate electrode, and the sheet resistance of the film is As samples A3 to A5, the first gate electrode (bottom gate electrode) was The material that can be used as the second gate electrode (top gate, also called BGE) is A laminated film is formed using a material that can be used as a thermal conduction electrode (TGE), and the laminate The contact chain resistance of the film was measured. A resistor is a contact structure (contact holes) between conductive films arranged in a chain of 100 pieces. The resistance of the elements (contact chain) connected in a row is also shown. The structure is shown below.

[0518] [Table 1]

[0519] [Table 2]

[0520] <Preparation of Samples A1 to A5> As the sample A1, an oxide semiconductor film corresponding to the oxide semiconductor film 112 was formed on a glass substrate. The oxide semiconductor film was formed to a thickness of 10 nm. Note that the oxide semiconductor film was formed by a sputtering apparatus using a A metal oxide having an atomic ratio of 2:4.1 was used as a sputtering target. The power source applied to the target was an AC power source. A conductive film corresponding to the conductive film 114 was formed over the semiconductor film. A 50 nm thick tungsten film and a 100 nm thick titanium film were deposited using a sputtering device. The layers were then formed in sequence.

[0521] As the sample A2, an oxide semiconductor film corresponding to the oxide semiconductor film 112 was formed on a glass substrate. The oxide semiconductor film was formed to a thickness of 100 nm. Note that the oxide semiconductor film was formed by a sputtering apparatus using a deposition method ... A metal oxide with an atomic ratio of 4:2:4.1 was used as a sputtering target. The power applied to the ring target was formed using an AC power source.

[0522] For the sample A3, a conductive film equivalent to the conductive film 106 was formed on a glass substrate. The conductive film is a 10 nm thick titanium film and a 200 nm thick copper film, which are sputtered. Then, an insulating film was formed on the conductive film, and an oxide film was formed on the insulating film. An oxide semiconductor film corresponding to the semiconductor film 112 was formed. An oxide semiconductor film having a thickness of 10 nm was formed. Using a stacking device, metal oxide with an atomic ratio of In:Ga:Zn=4:2:4.1 was stacked. The sputtering target is a power source that is AC Then, a hole corresponding to the opening 143 was formed in the insulating film and the oxide semiconductor film. An opening (contact hole) was formed. The number of holes was 100, each with a diameter of 2.5 μm. A conductive film corresponding to the conductive film 114 was formed on the semiconductor film. A tungsten film with a thickness of 50 nm and a titanium film with a thickness of 100 nm were deposited using a sputtering device. In the sample A3, a conductive film corresponding to the conductive film 106 and a conductive film 11 were formed in this order. 4, 100 of which are connected in series through the opening (contact hole). It is a structure having a region.

[0523] For the sample A4, a conductive film equivalent to the conductive film 106 was formed on a glass substrate. The conductive film is a 10 nm thick titanium film and a 200 nm thick copper film, which are sputtered. Then, an insulating film was formed on the conductive film, and an opening 1 was formed in the insulating film. An opening (contact hole) corresponding to 43 was formed. The hole diameter was 2.5 μm, and 100 holes were used as the hole. An oxide semiconductor film corresponding to the oxide semiconductor film 112 was formed on the insulating film. As the film, an oxide semiconductor film with a thickness of 10 nm was formed. A sputtering device was used to deposit In:Ga:Zn=4:2:4.1 [atomic ratio]. A metal oxide is used as a sputtering target, and a voltage is applied to the sputtering target. The conductive film 114 was then formed on the oxide semiconductor film. The conductive film was a tungsten film having a thickness of 15 nm. A titanium film with a thickness of 100 nm was then formed on the sample A4 using a sputtering device. In the example, a conductive film corresponding to the conductive film 106 and an oxide semiconductor film corresponding to the oxide semiconductor film 112 are The conductor film has an area where 100 pieces are connected in series at the opening (contact hole). This is the structure.

[0524] For sample A5, a conductive film equivalent to the conductive film 106 was formed on a glass substrate. The conductive film is a 10 nm thick titanium film and a 200 nm thick copper film, which are sputtered. Then, an insulating film was formed on the conductive film, and an opening 1 was formed in the insulating film. An opening (contact hole) corresponding to 43 was formed. The hole diameter was 2.5 μm, and 100 holes were used as the hole. An oxide semiconductor film corresponding to the oxide semiconductor film 112 was formed on the insulating film. As the film, an oxide semiconductor film with a thickness of 100 nm was formed. A sputtering device was used, and the atomic ratio of In:Ga:Zn was 4:2:4.1. The metal oxide is used as a sputtering target, and a voltage is applied to the sputtering target. The power source was an AC power source. The conductive film and the conductive film corresponding to the oxide semiconductor film 112 are formed in an opening (contact hole). The structure has an area in which 100 are connected in series.

[0525] <Measurement of sheet resistance and contact chain resistance> The sheet resistance of the above-prepared samples A1 and A2 was measured. The measurement results are shown in FIG. The sheet resistances of samples A1 and A2 were 2.41 Ω / sq. and 508 Ω / sq., respectively. It was sq.

[0526] That is, sample A1 has a lower sheet resistance than sample A2. An oxide semiconductor film corresponding to the conductive film 112 and a conductive film corresponding to the conductive film 114 are stacked. By using the structure for the second gate electrode, the sheet resistance of the second gate electrode can be reduced. It was shown that:

[0527] In addition, the contact chain resistance of the samples A3 to A5 prepared above was measured. The measurement results are shown in Figure 42. The contact chain resistance of samples A3, A4, and A5 The resistance was 3.0 × 10 2 Ω, 5.6×10 7 Ω, and 1.9×10 8 It was Omega.

[0528] That is, sample A3 has a lower contact chain resistance than samples A4 and A5. In this manner, a conductive film corresponding to the conductive film 106 and a conductive film corresponding to the conductive film 114 are formed. The first gate electrode and the second gate electrode have a structure having a contact region. This makes it possible to reduce the contact chain resistance between the first gate electrode and the second gate electrode. It was shown that.

[0529] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. EXAMPLES

[0530] In this example, a sample corresponding to a transistor according to one embodiment of the present invention was fabricated. The electrical characteristics of the transistor were measured, and the cross-sectional shape was observed.

[0531] The method for preparing the samples used in this example will be described below. A sample B1 corresponding to the transistor 100B shown in FIGS. In the following description, the structure of the transistor 100B shown in FIGS. Components having similar functions will be described using similar reference numerals.

[0532] For comparison, as shown in FIGS. 43(A) and 43(B), the second gate electrode is a conductive film 11 A sample B2 corresponding to the transistor 100G having a configuration without 4 was also fabricated. In (A) and (B), the transistor 100B shown in FIG. Components having similar functions will be described using similar reference numerals.

[0533] <How to fabricate a transistor> <Preparation of Sample B1> A glass substrate was used as the substrate 102 for fabricating the sample B1. The conductive film 106 was formed by a tantalum nitride film having a thickness of 10 nm and a tantalum nitride film having a thickness of 1 A 00 nm thick copper film was then formed in this order using a sputtering apparatus.

[0534] Next, an insulating film 104 was formed on the substrate 102 and the conductive film 106. In the insulating film 104, the insulating film 104_1, the insulating film 104_2, and the insulating film 104 The insulating film 104_3 and the insulating film 104_4 are successively formed in vacuum in this order using a PECVD apparatus. The insulating film 104_1 was a silicon nitride film having a thickness of 50 nm. The insulating film 104_2 was a silicon nitride film having a thickness of 300 nm. The insulating film 104_3 is a silicon nitride film having a thickness of 50 nm. The film used was a silicon oxynitride film having a thickness of 50 nm.

[0535] Next, an oxide semiconductor film is formed over the insulating film 104 and processed into an island shape. The oxide semiconductor film 108 was formed by depositing a 4000g SiO 2 thin film of 4000g of SiO 2 on the oxide semiconductor film 108. The oxide semiconductor film 108 was formed using a sputtering method. Using a sputtering device, metal oxide with an atomic ratio of In:Ga:Zn=4:2:4.1 was sputtered. The sputtering target is an AC power source. The oxide semiconductor film 108 was formed by a wet etching method. there was.

[0536] Next, an insulating film that will become the insulating film 110 later is formed over the insulating film 104 and the oxide semiconductor film 108. The insulating film was formed by using a silicon oxynitride film having a thickness of 30 nm and a silicon oxide film having a thickness of 100 nm. A silicon oxynitride film having a thickness of 20 nm and a silicon oxynitride film having a thickness of 20 nm were deposited on the substrate using a PECVD apparatus. The layers were successively formed in a vacuum using a vacuum chamber.

[0537] Next, a heat treatment was performed. The heat treatment was performed in a mixed gas atmosphere of nitrogen and oxygen for 3 h. The heat treatment was carried out at 50°C for 1 hour.

[0538] Next, an oxide semiconductor film which is to become the oxide semiconductor film 112 later was formed over the insulating film. The oxide semiconductor film was formed to a thickness of 20 nm. The compound semiconductor film was prepared by sputtering with In:Ga:Zn=5:1:7 [source material]. A metal oxide having a molecular weight ratio of 1:1 is used as a sputtering target. The applied power was formed using an AC power source.

[0539] Then, a mask is formed over the oxide semiconductor film, and the oxide semiconductor film is An opening 143 is formed in the insulating film 104, the insulating film in contact with the lower side of the oxide semiconductor film, and the insulating film 104. The opening 143 was processed using a dry etching device.

[0540] Next, a conductive film 114 is formed on the oxide semiconductor film 112. A conductive film was formed. The conductive film consisted of a tungsten film having a thickness of 15 nm and a tungsten film having a thickness of 10 A 100 nm thick titanium film was then formed on the SiO 2 film using a sputtering apparatus.

[0541] Next, the conductive film and the oxide semiconductor film formed in the above manner are processed into an island shape to form the conductive film 114. The conductive film 114 and the oxide semiconductor film 112 were formed. After the formation, the insulating film in contact with the lower side of the oxide semiconductor film 112 is processed to form an insulating film. 110 was formed.

[0542] Note that the conductive film 114 and the oxide semiconductor film 112 are processed by a wet etching method. The insulating film 110 was processed by dry etching.

[0543] Next, the insulating film 104, the oxide semiconductor film 108, the insulating film 110, the oxide semiconductor film 112, The impurity element was added from above the conductive film 114. A doping device was used, and argon was used as the impurity element.

[0544] Next, the insulating film 104, the oxide semiconductor film 108, the insulating film 110, the oxide semiconductor film 112, An insulating film 116 was formed on the conductive film 114. The insulating film 116 was a 100 nm thick film. The silicon nitride film was formed using a PECVD apparatus.

[0545] Next, an insulating film 118 was formed on the insulating film 116. The insulating film 118 had a thickness of 30 A 0 nm silicon oxynitride film was formed using a PECVD apparatus.

[0546] Next, a mask is formed on the insulating film 118, and the insulating films 116 and 118 are The openings 141a and 141b were formed in the substrate 141. A light etching apparatus was used.

[0547] Next, an insulating film 122 was formed on the insulating film 118. The insulating film 122 had a thickness of 1.5 The insulating film 122 was formed by using an acrylic photosensitive resin having a thickness of 1 μm. , an opening is provided in the area overlapping with 141b.

[0548] Next, a conductive film is formed on the insulating film 122 so as to fill the openings 141a and 141b. The conductive film was processed into islands to form conductive films 120s and 120d.

[0549] The conductive films 120s and 120d are a copper film containing manganese having a thickness of 50 nm and a copper film containing manganese having a thickness of A 100 nm copper film was then formed in succession in a vacuum using a sputtering device.

[0550] Through the above steps, a sample B1 corresponding to the transistor 100B shown in FIGS. was prepared.

[0551] In this embodiment, a sample B1 corresponding to the transistor 100B is a channel The width W of the hole was set to 50 μm, and the channel width L was set to 2.0 μm, 3.0 μm, and 6.0 μm. In addition, 20 transistors of each channel width L were formed on the substrate.

[0552] <Preparation of sample B2> As for the sample B2, similarly to the sample B1, a conductive film 106, an insulating film 104, and a An oxide semiconductor film 108 was formed.

[0553] Next, an insulating film that will become the insulating film 110 later is formed over the insulating film 104 and the oxide semiconductor film 108. The insulating film was formed by using a silicon oxynitride film having a thickness of 30 nm and a silicon oxide film having a thickness of 100 nm. A silicon oxynitride film having a thickness of 20 nm and a silicon oxynitride film having a thickness of 20 nm were deposited on the substrate using a PECVD apparatus. The layers were successively formed in a vacuum using a vacuum chamber.

[0554] Next, a heat treatment was performed. The heat treatment was performed in a mixed gas atmosphere of nitrogen and oxygen for 3 h. The heat treatment was carried out at 50°C for 1 hour.

[0555] Next, a mask is formed on the insulating film, and the insulating film and insulating film 1 are removed using the mask. An opening 143 was formed in the substrate 14. The opening 143 was processed using a dry etching device. Used.

[0556] Next, an oxide semiconductor film which is to become the oxide semiconductor film 112 later was formed over the insulating film. As the oxide semiconductor film, an oxide semiconductor film with a thickness of 100 nm was formed. The compound semiconductor film was prepared by sputtering with In:Ga:Zn=5:1:7 [source material]. A metal oxide having a molecular weight ratio of 1:1 is used as a sputtering target. The applied power was formed using an AC power source.

[0557] Next, the oxide semiconductor film formed as described above is processed into an island shape to form the oxide semiconductor film 112. After the oxide semiconductor film 112 was formed, the lower side of the oxide semiconductor film 112 was The insulating film in contact with the insulating film 110 was formed by processing the insulating film.

[0558] Note that the oxide semiconductor film 112 is processed by a wet etching method. The dry etching method was used for processing.

[0559] Next, the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the oxide semiconductor film 11 The impurity element was added from the top of the substrate. The impurity element used was argon.

[0560] Next, the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the oxide semiconductor film 11 An insulating film 116 was formed on the substrate 2. The insulating film 116 was a silicon nitride film having a thickness of 100 nm. The silicon film was formed using a PECVD apparatus.

[0561] Next, an insulating film 118 was formed on the insulating film 116. The insulating film 118 had a thickness of 30 A 0 nm silicon oxynitride film was formed using a PECVD apparatus.

[0562] Next, a mask is formed on the insulating film 118, and the insulating films 116 and 118 are The openings 141a and 141b were formed in the substrate 141. A light etching apparatus was used.

[0563] Next, an insulating film 122 was formed on the insulating film 118. The insulating film 122 had a thickness of 1.5 The insulating film 122 was formed by using an acrylic photosensitive resin having a thickness of 1 μm. , an opening is provided in the area overlapping with 141b.

[0564] Next, a conductive film is formed on the insulating film 122 so as to fill the openings 141a and 141b. The conductive film was processed into islands to form conductive films 120s and 120d.

[0565] The conductive films 120s and 120d are a copper film containing manganese having a thickness of 50 nm and a copper film containing manganese having a thickness of A 100 nm copper film was then formed in succession in a vacuum using a sputtering device.

[0566] Through the above steps, sample B corresponding to transistor 100G shown in FIGS. 2 was produced.

[0567] In this embodiment, a sample B2 corresponding to the transistor 100G is The width W of the hole was set to 50 μm, and the channel width L was set to 2.0 μm, 3.0 μm, and 6.0 μm. In addition, 20 transistors of each channel width L were formed on the substrate.

[0568] <Evaluation of the electrical characteristics of transistors> 44 and 45 show the drain current vs. gate voltage curves for samples B1 and B2 fabricated in this example. The Id-Vg characteristics of the sample B1 are shown in FIG. 44. 5 shows the measurement results for sample B2.

[0569] 44(A) and 45(A) show the channel width of 50 μm and the channel length of 2.0 μm. The characteristics of the 50 μm channel size are shown in Fig. 44(B) and Fig. 45(B). The characteristics are for a channel length of 3.0 μm, and Fig. 44(C) and Fig. 45(C) are for a channel width of 5 The characteristics are shown in Figs. 44 and 45. The first vertical axis is Id (A), and the second vertical axis is field effect mobility (μFE(cm 2 / Vs) The horizontal axis represents Vg (V).

[0570] The Id-Vg characteristics of the transistor were measured under the following conditions: A voltage (hereinafter also referred to as a gate voltage (Vg)) is applied to the conductive film 106 which functions as a gate electrode. ), and a voltage applied to the oxide semiconductor film 112 and the conductive film 114 which function as a second gate electrode. The supply voltage (also called Vbg) ranges from -15V to +20V in 0.25V steps. The voltage applied to the conductive film 120s functioning as the source electrode (hereinafter, The source voltage (Vs) is set to 0V (comm), and the conductor that functions as the drain electrode The voltage applied to the conductive film 120d (hereinafter also referred to as drain voltage (Vd)) is set to 1 V or It was set to 0V.

[0571] As shown in FIG. 44 and FIG. 45, the samples B1 and B2 prepared in this example were It was shown that the electrical properties were good regardless of the length of the cable (L).

[0572] <Reliability evaluation in gate BT testing> Next, the sample B1 and sample B2 with a channel width of 50 μm and a channel length of 6.0 μm were prepared as described above. The reliability of sample B1 and sample B2 was evaluated by applying a stress voltage to the gate electrode. The gate BT (Bias Temperature) test was conducted. The T-test consisted of the following four test methods.

[0573] ≪PBTS:Positive Bias Temperature Stress≫ The gate voltage (Vg) is set to +30V, and the drain voltage (Vd) and source voltage (Vs) are set to 0 V(COMMON), stress temperature is 60°C, and stress application time is 1 hour. The measurement was performed in a dark environment. The gate electrode is applied with a different potential from the source and drain electrodes for a certain period of time. The potential applied to the gate electrode was higher than the potentials of the source electrode and the drain electrode. (applied to the positive side).

[0574] ≪NBTS:Negative Bias Temperature Stress≫ The gate voltage (Vg) is set to -30V, and the drain voltage (Vd) and source voltage (Vs) are set to 0 V(COMMON), stress temperature is 60°C, and stress application time is 1 hour. The measurement was performed in a dark environment. The gate electrode is applied with a different potential from the source and drain electrodes for a certain period of time. The potential applied to the gate electrode was lower than the potentials of the source electrode and the drain electrode. (applied to the negative side).

[0575] ≪PBITS:Positive Bias Illumination Temper ature Stress≫ The gate voltage (Vg) is set to +30V, and the drain voltage (Vd) and source voltage (Vs) are set to 0 V(COMMON), stress temperature is 60°C, and stress application time is 1 hour. The measurement was performed in a photo environment (approximately 10,000 Lx with white LED). The source and drain electrodes of the transistor are set to the same potential, and the gate electrode is connected to the source and drain electrodes. A potential different from that applied to the source electrode was applied for a certain period of time. The potential is higher than that of the source electrode and drain electrode (applied to the positive side).

[0576] ≪NBITS:Negative Bias Illumination Temper ature Stress≫ The gate voltage (Vg) is set to -30V, and the drain voltage (Vd) and source voltage (Vs) are set to 0 V(COMMON), stress temperature is 60°C, and stress application time is 1 hour. The measurement was performed in a photo environment (white LED, approximately 10,000 Lx). The source and drain electrodes of the transistor are set to the same potential, and the gate electrode is connected to the source and drain electrodes. A potential different from that applied to the source electrode was applied for a certain period of time. The potential is lower than that of the source electrode and drain electrode (applied to the negative side).

[0577] The gate BT test is a type of accelerated test that detects transistor defects that occur during long-term use. The change in characteristics of the gate BT test can be evaluated in a short time. The change in threshold voltage of a transistor (ΔVth) is an important index for examining reliability. The smaller the change in threshold voltage (ΔVth) before and after the gate BT test, High reliability.

[0578] ΔVth indicates the change in threshold voltage (Vth) after stress. This is the difference between Vth before stress and Vth before stress.

[0579] The gate BT test results of the samples B1 and B2 are shown in FIG.

[0580] From the results in Figure 46, it can be seen that the variation in the NBITS test for sample B1 is smaller than that for sample B2. This is because the sample B1 includes the conductive film 114, which reduces the channel width of the oxide semiconductor film 108. This is because the second gate electrode and the gate electrode region are prevented from being irradiated with light. In particular, a structure including the conductive film 114 is preferable.

[0581] <Evaluation of the electrical characteristics of transistors under light irradiation> Next, the sample B1 and sample B2 with a channel length of 6 μm and a channel width of 50 μm were The electrical characteristics of the transistors in sample B2 were measured when exposed to light. The electrical characteristics were measured as drain current (Id)-gate voltage (Vg) characteristics. The measurement environment was a stress temperature of 60°C and light irradiation of about 1000 hours with a white LED. I went there at 0Lx.

[0582] The electrical characteristics of the transistors of Sample B1 and Sample B2 are shown in FIGS. In FIG. 48, the source electrode (Vs) is set to 0V (comm), and the drain voltage (Vd) is set to 1V and 10V, and the gate voltage (Vg and Vbg) is changed from -15V to +15V. The results are shown for voltages applied at 25V intervals. In Figs. 47 and 48, the vertical axis indicates the drain voltage. The horizontal axis represents the in-current (Id) and the horizontal axis represents the gate voltage (Vg). FIG. 47(A) shows the measurement results of sample B1, and FIG. 48 shows the measurement results of sample B2. FIG. 47(B) and FIG. 48(B) show the electrical characteristics of the transistor when irradiated with light. ) and when not irradiated with light.

[0583] From the electrical characteristics results shown in Figures 47 and 48, the transistor of sample B2 under light irradiation The electrical characteristics of the capacitor are such that the threshold voltage is negative (also called normally-on characteristics). On the other hand, in sample B1, the transistor The electrical characteristics are such that the threshold voltage is positive (also called normally-off characteristics). That is, the structure having the conductive film 114 as the second gate electrode is preferable. I wish.

[0584] As described above, the electrical characteristics of the transistor of one embodiment of the present invention do not change even when exposed to light. Therefore, it can be said that this is a transistor with low power consumption.

[0585] <Cross-section observation of transistor> Next, the transistor with a channel width of 50 μm and a channel length of 2.0 μm was fabricated. The cross-sectional observation of the transistor was performed. The results of the cross-sectional observation are shown in Figure 49(A) and (B). For cross-sectional observation, a transmission electron microscope (TEM) was used. A lectron microscope was used.

[0586] FIG. 49(A) is a cross-section of sample B1, and FIG. 49(B) is a cross-section of sample B2. Each corresponds to a cross section taken along the dashed line X1-X2 in FIG. Alternatively, elements corresponding to those in FIG. 43(A) are denoted by the same reference numerals.

[0587] As shown in FIGS. 49(A) and (B), the samples B1 and B2 prepared in this example were excellent. The cross-sectional shape was as shown in FIG. 1. The width of the second gate electrode (TGE width) of sample B1 was 1.70 μm. The second gate electrode width (TGE width) of sample B2 was 1.75 μm.

[0588] As described above, the configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. This can be done. EXAMPLES

[0589] In this embodiment, the use of the conductive film for the second gate electrode of the transistor according to one aspect of the present invention shows the results of evaluating the amounts of hydrogen and oxygen released from the conductive film that can be used.

[0590] A method for evaluating the amounts of hydrogen and oxygen released from the conductive film that can be used for the second gate electrode used temperature-programmed desorption gas analysis (TDS). In the TDS analysis of the conductive film, the amounts of hydrogen molecules released from the conductive film and oxygen molecules released from the insulating film under the conductive film were measured and evaluated.

[0591] First, in order to evaluate the amount of hydrogen released from the conductive film, the following samples C1 to C4 were prepared. .

[0592] <Preparation of Samples C1 to C4> As sample C1, a 30-nm-thick tantalum film was formed on a glass substrate using a sputtering apparatus.

[0593] As sample C2, a 30-nm-thick titanium film was formed on a glass substrate using a sputtering apparatus.

[0594] As sample C3, a 30-nm-thick tantalum nitride film was formed on a glass substrate using a sputtering apparatus.

[0595] As sample C4, a 30-nm-thick titanium nitride film was formed on a glass substrate using a sputtering apparatus.

[0596] <Evaluation of Hydrogen Release Amount by TDS Analysis 1> To evaluate the amounts of hydrogen molecules released from the prepared samples C1 to C4, TDS analysis was performed. The TDS analysis results are shown in FIGS. 50(A) to (D).

[0597] ​From the results of the TDS analysis shown in Figures 50(A) to (D), hydrogen molecules released from various conductive films The amount of can be evaluated.

[0598] As shown in FIGS. 50(A), (C) and (D), a tungsten film, a tantalum nitride film, and Almost no hydrogen was released from the titanium nitride film. As shown in the figure, many hydrogen molecules were released from the titanium film. Therefore, the conductive film 114 and the oxide semiconductor film in the channel region may become n-type. The materials used as the electrode are preferably tungsten, tantalum nitride, and titanium nitride. do.

[0599] Next, in order to evaluate the amount of hydrogen permeating the conductive film, the following samples C5 to C9 were prepared. did.

[0600] <Preparation of Samples C5 to C9> Sample C5 was a 100 nm thick nitride silicon film formed on a glass substrate using a PECVD apparatus. A recombinant membrane was formed.

[0601] Sample C6 was prepared by depositing a 100 nm thick nitride silicon film on a glass substrate using a PECVD apparatus. A silicon nitride film was then formed on the silicon nitride film. A 30 nm tungsten film was formed.

[0602] Sample C7 was a 100 nm thick nitride silicon film formed on a glass substrate using a PECVD apparatus. A silicon nitride film was then formed on the silicon nitride film. A 30 nm titanium film was formed.

[0603] Sample C8 was a 100 nm thick nitride silicon film formed on a glass substrate using a PECVD apparatus. A silicon nitride film was formed. Subsequently, a tantalum nitride film with a thickness of of 30 nm was formed on the silicon nitride film using a sputtering apparatus.

[0604] As Sample C9, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD apparatus. Subsequently, a titanium nitride film with a thickness of of 30 nm was formed on the silicon nitride film using a sputtering apparatus.

[0605] <Evaluation of Hydrogen Release Amount by TDS Analysis 2> To evaluate the hydrogen molecule release amounts of the above-prepared Samples C5 to C9, TDS analysis was performed. The TDS analysis results are shown in FIGS. 51(A) to (D).

[0606] From the results of the TDS analysis shown in FIG. 51, the amount of hydrogen molecules released from the silicon nitride film under various conductive films can be evaluated. That is, when the amount of hydrogen molecules released from the silicon nitride film is small, it can be seen that the conductive film can block the hydrogen. As shown in FIGS. 51(A) to (D), from Sample C5 (silicon nitride film), hydrogen molecule release was confirmed at 350° C. or higher. On the other hand, as shown in FIG. 51(A), from Sample C6 (tungsten film on silicon nitride film), hydrogen molecule release was not confirmed at 350° C. or higher and 480° C. or lower. That is, it was shown that by forming a tungsten film on the silicon nitride film, the hydrogen molecules released by the silicon nitride can be blocked. Also, as shown in FIGS. 51(C) and (D), from Sample C8 (tantalum nitride film on silicon nitride film) and Sample C9 (titanium nitride film on silicon nitride film), it was confirmed that there was little hydrogen molecule release even at 350° C. or higher. That is, a tantalum nitride film or a titanium nitride film on the silicon nitride film

[0607] As shown in FIGS. 51(A) to (D), from Sample C5 (silicon nitride film), hydrogen molecule release was confirmed at 350° C. or higher. On the other hand, as shown in FIG. 51(A), from Sample C6 (tungsten film on silicon nitride film), hydrogen molecule release was not confirmed at 350° C. or higher and 480° C. or lower. That is, it was shown that by forming a tungsten film on the silicon nitride film, the hydrogen molecules released by the silicon nitride can be blocked. Also, as shown in FIGS. 51(C) and (D), from Sample C8 (tantalum nitride film on silicon nitride film) and Sample C9 (titanium nitride film on silicon nitride film), it was confirmed that there was little hydrogen molecule release even at 350° C. or higher. That is, a tantalum nitride film or a titanium nitride film on the silicon nitride film As shown in FIGS. 51(A) to (D), from Sample C5 (silicon nitride film), hydrogen molecule release was confirmed at 350° C. or higher. On the other hand, as shown in FIG. 51(A), from Sample C6 (tungsten film on silicon nitride film), hydrogen molecule release was not confirmed at 350° C. or higher and 480° C. or lower. That is, it was shown that by forming a tungsten film on the silicon nitride film, the hydrogen molecules released by the silicon nitride can be blocked. Also, as shown in FIGS. 51(C) and (D), from Sample C8 (tantalum nitride film on silicon nitride film) and Sample C9 (titanium nitride film on silicon nitride film), it was confirmed that there was little hydrogen molecule release even at 350° C. or higher. That is, a tantalum nitride film or a titanium nitride film on the silicon nitride film As shown in FIGS. 51(C) and (D), from Sample C8 (tantalum nitride film on silicon nitride film) and Sample C9 (titanium nitride film on silicon nitride film), it was confirmed that there was little hydrogen molecule release even at 350° C. or higher. That is, a tantalum nitride film or a titanium nitride film on the silicon nitride film As shown in FIGS. 51(C) and (D), from Sample C8 (tantalum nitride film on silicon nitride film) and Sample C9 (titanium nitride film on silicon nitride film), it was confirmed that there was little hydrogen molecule release even at 350° C. or higher. That is, a tantalum nitride film or a titanium nitride film on the silicon nitride film By forming a film, it is possible to block hydrogen molecules released by silicon nitride. However, as shown in FIG. 51(B), sample C7 (on a silicon nitride film) In addition to hydrogen release from the titanium film, many hydrogen molecules were released from the titanium film at temperatures above 250°C. In other words, a tungsten film, a tantalum nitride film, or a tantalum nitride film was formed on a silicon nitride film. By forming a titanium nitride film, the hydrogen molecules released by silicon nitride can be blocked. Therefore, the material used for the conductive film 114 is tongue. Stainless steel, tantalum nitride, and titanium nitride are preferred.

[0608] Next, in order to evaluate the amount of oxygen absorbed by the conductive film, the following samples C10 and C11-1 Sample C14-2 was prepared.

[0609] <Preparation of Samples C10, and C11-1 to C14-2> Sample C10 was prepared by depositing a 100 nm thick nitride film on a glass substrate using a PECVD apparatus. A silicon oxide film was formed.

[0610] Sample C11-1 was prepared by depositing a 100 nm thick film on a glass substrate using a PECVD device. A silicon oxynitride film was formed. Then, a sputtering device was placed on the silicon oxynitride film. A tungsten film was formed using a vacuum chamber. Then, a heat treatment was performed at 250°C for 1 hour. The tungsten film is removed by wet etching to expose the silicon oxynitride film. Ta.

[0611] For sample C11-2, a 100 nm thick film was deposited on a glass substrate using a PECVD device. A silicon oxynitride film was formed. Then, a sputtering device was placed on the silicon oxynitride film. An oxide semiconductor film having a thickness of 10 nm was formed using a SiO2 laser. Sputtering target is a metal oxide with an atomic ratio of n:Ga:Zn=4:2:4.1 The power applied to the sputtering target was an AC power source. Then, a tungsten film was formed over the oxide semiconductor film using a sputtering apparatus. Then, after heat treatment at 250°C for 1 hour, the oxide was removed using a wet etching method. The semiconductor film and the tungsten film were removed to expose the silicon nitride oxide film.

[0612] For sample C12-1, a 100 nm thick film was deposited on a glass substrate using a PECVD device. A silicon oxynitride film was formed. Then, a sputtering device was placed on the silicon oxynitride film. A titanium film was formed using a vacuum oven. Then, a heat treatment was performed at 250°C for 1 hour. The titanium film was removed by a thermal etching method to expose the silicon nitride oxide film.

[0613] For sample C12-2, a 100 nm thick film was deposited on a glass substrate using a PECVD device. A silicon oxynitride film was formed. Then, a sputtering device was placed on the silicon oxynitride film. An oxide semiconductor film having a thickness of 10 nm was formed using a SiO2 laser. Sputtering target is a metal oxide with an atomic ratio of n:Ga:Zn=4:2:4.1 The power applied to the sputtering target was an AC power source. Then, a titanium film was formed over the oxide semiconductor film using a sputtering apparatus. After heat treatment at 250°C for 1 hour, the oxide semiconductor was removed by wet etching. The film and the titanium film were removed to expose the silicon oxynitride film.

[0614] Sample C13-1 was prepared by depositing a 100 nm thick film on a glass substrate using a PECVD device. A silicon oxynitride film was formed. Then, a sputtering device was placed on the silicon oxynitride film. A tantalum nitride film was formed using a vacuum chamber. Then, a heat treatment was performed at 250°C for 1 hour. The tantalum nitride film is removed by wet etching to expose the silicon nitride oxide film. Ta.

[0615] For sample C13-2, a 100 nm thick film was deposited on a glass substrate using a PECVD device. A silicon oxynitride film was formed. Then, a sputtering device was placed on the silicon oxynitride film. An oxide semiconductor film having a thickness of 10 nm was formed using a SiO2 laser. Sputtering target is a metal oxide with an atomic ratio of n:Ga:Zn=4:2:4.1 The power applied to the sputtering target was an AC power source. Then, a tantalum nitride film was formed on the oxide semiconductor film by using a sputtering apparatus. Then, after heat treatment at 250°C for 1 hour, the oxide was removed using a wet etching method. The semiconductor film and the tantalum nitride film were removed to expose the silicon nitride oxide film.

[0616] Sample C14-1 was prepared by depositing a 100 nm thick film on a glass substrate using a PECVD device. A silicon oxynitride film was formed. Then, a sputtering device was placed on the silicon oxynitride film. A titanium nitride film was formed using a vacuum oven. Then, a heat treatment was performed at 250°C for 1 hour. The titanium nitride film was removed by wet etching to expose the silicon nitride oxide film.

[0617] For sample C14-2, a 100 nm thick film was deposited on a glass substrate using a PECVD device. A silicon oxynitride film was formed. Subsequently, an oxide semiconductor film with a thickness of 10 nm was formed on the silicon oxynitride film using a sputtering apparatus. As the oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as a sputtering target, and an AC power supply was used as the power supply applied to the sputtering target for formation. Subsequently, a titanium nitride film was formed on the oxide semiconductor film using a sputtering apparatus. Subsequently, after performing heat treatment at 250 °C for 1 hour, the oxide semiconductor film and the titanium nitride film were removed using a wet etching method to expose the silicon oxynitride film. Subsequently, after heat treatment at 250 °C for 1 hour, the oxide semiconductor film and the titanium nitride film were removed using a wet etching method to expose the silicon oxynitride film. Subsequently, after heat treatment at 250 °C for 1 hour, the oxide semiconductor film and the titanium nitride film were removed using a wet etching method to expose the silicon oxynitride film.

[0618] <Evaluation of the amount of oxygen released by TDS analysis> To evaluate the amount of oxygen molecules released from the prepared sample C10 and samples C11-1 to C14-2, TDS analysis was performed. The TDS analysis results are shown in FIGS. 52(A) to (E). From the results of the TDS analysis shown in FIG. 52, the amount of oxygen molecules released by the silicon oxynitride film can be evaluated. That is, when the amount of oxygen molecules released by the silicon oxynitride film is small, it can be seen that the oxygen possessed by the silicon oxynitride film is absorbed by the conductive film.

[0619] From the results of the TDS analysis shown in FIG. 52, the amount of oxygen molecules released by the silicon oxynitride film can be evaluated. That is, when the amount of oxygen molecules released by the silicon oxynitride film is small, it can be seen that the oxygen possessed by the silicon oxynitride film is absorbed by the conductive film. From the results of the TDS analysis shown in FIG. 52, the amount of oxygen molecules released by the silicon oxynitride film can be evaluated. That is, when the amount of oxygen molecules released by the silicon oxynitride film is small, it can be seen that the oxygen possessed by the silicon oxynitride film is absorbed by the conductive film. From the results of the TDS analysis shown in FIG. 52, the amount of oxygen molecules released by the silicon oxynitride film can be evaluated. That is, when the amount of oxygen molecules released by the silicon oxynitride film is small, it can be seen that the oxygen possessed by the silicon oxynitride film is absorbed by the conductive film.

[0620] As shown in FIG. 52(A), the release of oxygen molecules was confirmed from sample C10 (silicon oxynitride film). Also, as shown in FIGS. 52(B) to (E), from samples C11-2, C12-2, C13-2, and C14-2 in which various conductive films were formed after forming an oxide semiconductor film on the silicon oxynitride film, the release of oxygen molecules from the silicon oxynitride film was also confirmed in the same manner as sample C10. On the other hand, various conductive films were directly formed on the silicon oxynitride film. As shown in FIG. 52(A), the release of oxygen molecules was confirmed from sample C10 (silicon oxynitride film). Also, as shown in FIGS. 52(B) to (E), from samples C11-2, C12-2, C13-2, and C14-2 in which various conductive films were formed after forming an oxide semiconductor film on the silicon oxynitride film, the release of oxygen molecules from the silicon oxynitride film was also confirmed in the same manner as sample C10. On the other hand, various conductive films were directly formed on the silicon oxynitride film. As shown in FIG. 52(A), the release of oxygen molecules was confirmed from sample C10 (silicon oxynitride film). Also, as shown in FIGS. 52(B) to (E), from samples C11-2, C12-2, C13-2, and C14-2 in which various conductive films were formed after forming an oxide semiconductor film on the silicon oxynitride film, the release of oxygen molecules from the silicon oxynitride film was also confirmed in the same manner as sample C10. On the other hand, various conductive films were directly formed on the silicon oxynitride film. As shown in FIG. 52(A), the release of oxygen molecules was confirmed from sample C10 (silicon oxynitride film). Also, as shown in FIGS. 52(B) to (E), from samples C11-2, C12-2, C13-2, and C14-2 in which various conductive films were formed after forming an oxide semiconductor film on the silicon oxynitride film, the release of oxygen molecules from the silicon oxynitride film was also confirmed in the same manner as sample C10. On the other hand, various conductive films were directly formed on the silicon oxynitride film. As shown in FIG. 52(A), the release of oxygen molecules was confirmed from sample C10 (silicon oxynitride film). Also, as shown in FIGS. 52(B) to (E), from samples C11-2, C12-2, C13-2, and C14-2 in which various conductive films were formed after forming an oxide semiconductor film on the silicon oxynitride film, the release of oxygen molecules from the silicon oxynitride film was also confirmed in the same manner as sample C10. On the other hand, various conductive films were directly formed on the silicon oxynitride film. Samples C11-1, C12-1, C13-1, and C14-1 were found to be nitridic acid. Almost no oxygen molecules were observed in the silicon oxide film.

[0621] That is, an oxide semiconductor film is formed on a silicon nitride oxide film, and a conductive layer is formed on the oxide semiconductor film. When a conductive film is formed, the conductive film absorbs oxygen contained in the silicon nitride oxide. It has been shown that it is possible to suppress

[0622] When the insulating film 110 contains a sufficient amount of oxygen, oxygen is supplied to the oxide semiconductor film in the channel region. This allows the supply of oxygen to the channel region, thereby reducing oxygen vacancies in the channel region. It is preferable that the insulating film used for the film 110 has a high oxygen release rate.

[0623] Therefore, the second gate electrode formed on the insulating film 110 is made of an oxide semiconductor film. A configuration having a conductive film is preferable.

[0624] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. EXAMPLES

[0625] In this embodiment, the second gate electrode of the transistor of one embodiment of the present invention is An evaluation was conducted to determine the damage to the insulating film that occurs during the deposition of the conductive film.

[0626] The damage caused by the formation of the insulating film during the formation of the conductive film can be evaluated by using electron spin resonance (ESR). The electron spin resonance (ESR) measurements were performed.

[0627] The preparation method of the samples used in this example will be described below. The structure of sample D6-2 is shown below.

[0628] [Table 3]

[0629] <Preparation of Samples D1-1 to D6-2> As the samples D1-1 and D1-2, a semiconductor layer equivalent to the oxide semiconductor film 108 was formed on a quartz substrate. The oxide semiconductor film was formed using an oxide semiconductor layer having a thickness of 40 nm. A conductive film was formed using a sputtering apparatus. Sputtering target is a metal oxide with an atomic ratio of n:Ga:Zn=4:2:4.1 The power applied to the sputtering target was an AC power source. Next, an insulating film corresponding to the insulating film 110 was formed over the oxide semiconductor film. A silicon oxynitride film having a thickness of 100 nm was formed as the film. An oxide semiconductor film corresponding to the oxide semiconductor film 112 was formed on the oxide semiconductor film 111. As the oxide semiconductor film, a 10 nm-thick oxide semiconductor film was formed. The metals were deposited in a sputtering apparatus with an atomic ratio of In:Ga:Zn=4:2:4.1. The oxide is used as a sputtering target, and a power source is applied to the sputtering target. The AC power supply was used for the formation. Sample D1-2 was fabricated by the above process. As the oxide semiconductor film 1-1, a wet oxide semiconductor film corresponding to the oxide semiconductor film 112 formed as above was used. The thin film was removed by a thermal etching method.

[0630] The samples D2-1 and D2-2 are formed by depositing a conductive film 11 on the samples D1-1 and D1-2. It was fabricated by forming a conductive film corresponding to 4. As the conductive film, a tungsten film was formed using a sputtering apparatus.

[0631] As Samples D3-1 and D3-2, they were fabricated by forming a conductive film corresponding to 14 on Samples D1-1 and D1-2. As the conductive film, a titanium film was formed using a sputtering apparatus.

[0632] As Samples D4-1 and D4-2, they were fabricated by forming a conductive film corresponding to 14 on Samples D1-1 and D1-2. As the conductive film, a tantalum nitride film was formed using a sputtering apparatus.

[0633] As Samples D5-1 and D5-2, they were fabricated by forming a conductive film corresponding to 14 on Samples D1-1 and D1-2. As the conductive film, a titanium nitride film was formed using a sputtering apparatus.

[0634] As Samples D6-1 and D6-2, they were fabricated by forming a conductive film corresponding to 14 on Samples D1-1 and D1-2. As the conductive film, a copper film was formed using a sputtering apparatus.

[0635] <ESR Measurement> ESR measurement was performed on the fabricated Samples D1-1 to D6-2. For the ESR measurement, the measurement temperature was set to 85 K, the high-frequency power (microwave power) at 8.92 GHz was set to 10 mW, and the direction of the magnetic field was made parallel to the film surface of the fabricated samples. Note that the detection limit of the spin density of the signal due to NO is 1.0×10 x spins / cm 16 3 The number of spins was small. It can be said that the smaller the thickness, the fewer defects there are in the insulating film.

[0636] The measured ESR signal is shown in Figure 53. Note that the insulating film is a nitride oxide (NO x ) If yes, NO x In some cases, a signal with three characteristic lines originating from These three signals are the first signal with a g value between 2.037 and 2.039, the second signal with a g value between 2.037 and 2.039, A second signal between .001 and 2.003 and a g value between 1.964 and 1.966 These three signals are observed as NO x Due to N It is understood that the signal has a hyperfine structure due to the nuclear spin of NO. x Due to The signal is an asymmetric waveform due to the anisotropy of the spin species.

[0637] In samples D1-1 to D6-2, NO x The spin density of the three signals due to The measurement results are shown in Figure 54. Note that the measured spin numbers are converted into unit volume here. The calculated spin densities are shown.

[0638] The conductive film does not include an oxide corresponding to the oxide semiconductor film 112 and is formed of tantalum nitride or Samples D4-1 and D5-1, which have titanium oxide, have large spin densities of three signals. This is because the insulating film is conductive and has a large number of defects. When forming the film, NO x On the other hand, the oxide semiconductor film 11 Samples D1-2, D2-2, D3-2, D4-2, and D5 having oxide semiconductors corresponding to 2 -2 and D6-2 are NO x The spin density of the signal caused by is small and below the measurement limit. It was.

[0639] From this, the oxide semiconductor film 112 is formed on the insulating film 110. By forming a compound semiconductor film, damage to the insulating film that occurs when forming a conductive film is suppressed. It has been shown that it can be controlled.

[0640] Therefore, the second gate electrode includes the oxide semiconductor film 112 and the conductive film 114. It can be said that such a configuration is preferable.

[0641] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. EXAMPLES

[0642] In this embodiment, the second gate electrode of the transistor of one embodiment of the present invention is The results of evaluating the amounts of hydrogen and oxygen released from the conductive film that can achieve this are shown below.

[0643] Method for evaluating hydrogen and oxygen release amount of conductive film usable for second gate electrode Thermal desorption spectrometry (TDS) was used for the analysis. The amount of hydrogen molecules released by the film and the amount of oxygen molecules released by the insulating film under the conductive film were measured and evaluated. The evaluation was carried out.

[0644] First, in order to evaluate the amount of hydrogen released from the conductive film, a sample E1 was prepared.

[0645] <Preparation of Sample E1> As the sample E1, a copper film with a thickness of 50 nm was deposited on a glass substrate using a sputtering device. was formed.

[0646] <Evaluation of Hydrogen Release Amount by TDS Analysis 3> To evaluate the hydrogen molecule release amount of the prepared sample E1, TDS analysis was performed. TD The TDS analysis results are shown in Fig. 55.

[0647] From the TDS analysis results shown in Fig. 55, almost no hydrogen release was observed from the copper film. Excessive hydrogen release may n-type the oxide semiconductor film in the channel region. Therefore, it can be said that copper is preferable as the material used for the conductive film 114.

[0648] Next, in order to evaluate the amount of hydrogen permeating through the conductive film, the following samples E2 to E6 were prepared. The following were prepared.

[0649] <Preparation of Samples E2 to E6> As sample E2, a 100-nm-thick silicon nitride film was formed on a glass substrate using a PECVD apparatus. The following were prepared.

[0650] As sample E3, a 100-nm-thick silicon nitride film was formed on a glass substrate using a PECVD apparatus. Subsequently, a 100-nm-thick copper film was formed on the silicon nitride film using a sputtering apparatus. The following were prepared.

[0651] As sample E4, a 100-nm-thick silicon nitride film was formed on a glass substrate using a PECVD apparatus. Subsequently, a 100-nm-thick copper film was formed on the silicon nitride film using a sputtering apparatus. Subsequently, a 50-nm-thick titanium film was formed on the copper film using a sputtering apparatus. The following were prepared.

[0652] As sample E5, a 100-nm-thick silicon nitride film was formed on a glass substrate using a PECVD apparatus. A silicon nitride film was formed. Subsequently, a copper film with a thickness of of 100 nm was formed on the silicon nitride film using a sputtering apparatus. Subsequently, a tungsten film with a thickness of of 50 nm was formed on the copper film using a sputtering apparatus.

[0653] As Sample E6, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD apparatus. Subsequently, a copper film with a thickness of of 100 nm was formed on the silicon nitride film using a sputtering apparatus. Subsequently, a titanium nitride film with a thickness of of 50 nm was formed on the copper film using a sputtering apparatus.

[0654] <Evaluation of hydrogen release amount by TDS analysis 4> In order to evaluate the hydrogen molecule release amounts of the above-prepared Samples E2 to E6, TDS analysis was performed. The TDS analysis results are shown in FIGS. 56 and 57.

[0655] From the TDS analysis results shown in FIGS. 56 and 57, the amount of hydrogen molecules released by the silicon nitride film under various conductive films can be evaluated. That is, it can be seen that when the amount of hydrogen molecules released by the silicon nitride film is small, the conductive film can block the hydrogen. As shown in FIG. 56, from Sample E2 (silicon nitride film), the release of hydrogen molecules was confirmed at 250 °C or higher. On the other hand, from Sample E3 (copper film on the silicon nitride film), the release of hydrogen molecules was not confirmed up to about 350 °C. That is, it was shown that by forming a copper film on the silicon nitride film, the hydrogen molecules released by the silicon nitride can be blocked.

[0656] As shown in FIG. 56, from Sample E2 (silicon nitride film), the release of hydrogen molecules was confirmed at 250 °C or higher. On the other hand, from Sample E3 (copper film on the silicon nitride film), the release of hydrogen molecules was not confirmed up to about 350 °C. That is, it was shown that by forming a copper film on the silicon nitride film, the hydrogen molecules released by the silicon nitride can be blocked.

[0657] Also, as shown in FIGS. 57(B)(C), from Sample E5 (copper film and tantalum on the silicon nitride film) ​​​​Sample E1 (copper film and titanium nitride film on silicon nitride film) and sample E2 (copper film and titanium nitride film on silicon nitride film) showed 350 It was confirmed that hydrogen molecules were released little up to about 1000°C. A silicon nitride film is formed by forming a tungsten film or a titanium nitride film on the copper film. It has been shown that the hydrogen molecules released by the ion exchange reaction can be blocked. As shown in 57(A), the copper and titanium films on the silicon nitride film of sample E4 were In addition to hydrogen release from the titanium film, the release of many hydrogen molecules was confirmed at temperatures above 250°C. That is, by forming a copper film, a tungsten film, and a titanium nitride film on a silicon nitride film, It has been shown that silicon nitride can block hydrogen molecules from escaping. The material used for the conductive film 114 is preferably copper, tungsten, or titanium nitride. It can be said that.

[0658] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. EXAMPLES

[0659] In this example, a sample corresponding to a transistor according to one embodiment of the present invention was fabricated. The electrical characteristics of the transistor were measured, and the cross-sectional shape was observed.

[0660] The method for preparing the samples used in this ...

Claims

1. a semiconductor film having a channel formation region of a transistor; a first insulating film located below the semiconductor film; a first conductive film overlapping the channel formation region with the first insulating film interposed therebetween; a second insulating film having a region in contact with an upper surface of the semiconductor film; a second conductive film having a region located on the second insulating film and having a region overlapping the channel formation region with the second insulating film interposed therebetween; a third insulating film having a region in contact with an upper surface of the second conductive film, a region in contact with a side surface of the second conductive film, and a region in contact with an upper surface of the second insulating film, the third insulating film including silicon nitride; a fourth insulating film having a region in contact with an upper surface of the third insulating film and including silicon oxide; a fifth insulating film having an area in contact with an upper surface of the fourth insulating film and including an organic material; a third conductive film having a region located over the fifth insulating film and functioning as one of a source electrode and a drain electrode of the transistor; a sixth insulating film having a region in contact with an upper surface of the third conductive film and a region in contact with an upper surface of the fifth insulating film, the sixth insulating film including an organic material; a liquid crystal element located on the sixth insulating film; the third insulating film has a first opening; the fourth insulating film has a second opening overlapping the first opening; the fifth insulating film has a third opening overlapping the first opening and the second opening; In a cross-sectional view, an upper end of the second opening does not coincide with a lower end of the third opening, In a cross-sectional view, a diameter of the third opening at a lower end of the third opening is larger than a diameter of the second opening at an upper end of the second opening, the third conductive film has a region in contact with an upper surface of the fifth insulating film and a region in contact with an upper surface of the semiconductor film in regions overlapping with the first opening to the third opening, the channel formation region comprises silicon; the sixth insulating film overlaps with the channel formation region in a region in contact with an upper surface of the fifth insulating film; the first conductive film includes a metal material having a light-shielding property; the second conductive film has the same material as the first conductive film; the first conductive film does not overlap with the first opening.

2. a semiconductor film having a channel formation region of a transistor; a first insulating film located below the semiconductor film; a first conductive film overlapping the channel formation region with the first insulating film interposed therebetween; a second insulating film having a region in contact with an upper surface of the semiconductor film; a second conductive film having a region located on the second insulating film and having a region overlapping the channel formation region with the second insulating film interposed therebetween; a third insulating film having a region in contact with an upper surface of the second conductive film, a region in contact with a side surface of the second conductive film, and a region in contact with an upper surface of the second insulating film, the third insulating film including silicon nitride; a fourth insulating film having a region in contact with an upper surface of the third insulating film and including silicon oxide; a fifth insulating film having an area in contact with an upper surface of the fourth insulating film and including an organic material; a third conductive film having a region located over the fifth insulating film and functioning as one of a source electrode and a drain electrode of the transistor; a sixth insulating film having a region in contact with an upper surface of the third conductive film and a region in contact with an upper surface of the fifth insulating film, the sixth insulating film including an organic material; a liquid crystal element located on the sixth insulating film; the third insulating film has a first opening; the fourth insulating film has a second opening overlapping the first opening; the fifth insulating film has a third opening overlapping the first opening and the second opening; In a cross-sectional view, an upper end of the second opening does not coincide with a lower end of the third opening, In a cross-sectional view, a diameter of the third opening at a lower end of the third opening is larger than a diameter of the second opening at an upper end of the second opening, In a cross-sectional view, a diameter of the second opening at an upper end of the second opening is larger than a diameter of the second opening at a lower end of the second opening, the third conductive film has a region in contact with an upper surface of the fifth insulating film and a region in contact with an upper surface of the semiconductor film in regions overlapping with the first opening to the third opening, the channel formation region comprises silicon; the sixth insulating film overlaps with the channel formation region in a region in contact with an upper surface of the fifth insulating film; the first conductive film includes a metal material having a light-shielding property; the second conductive film has the same material as the first conductive film; the first conductive film does not overlap with the first opening.

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