Information processor

Abstract

To effectively perform software update.SOLUTION: The information processor having a communication interface stores a compressed file containing firmware for updating a communication interface and performs signature verification and decompression of at least a portion of the compressed data in the compressed file in parallel.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an information processing device. [Background technology]

[0002] Data storage is a basic function of a computer system. In many computer systems, when large amounts of data are handled, they are stored in a storage system. The storage system stores data in storage media (storage drives) such as HDDs (Hard Disk Drives) and SSDs (Solid State Drives), and writes and reads data in response to external commands.

[0003] Background art of the present disclosure includes International Publication No. 2020 / 122024. International Publication No. 2020 / 122024 discloses the following: "The impact on system availability caused by rewriting circuit information of a network interface card (NIC) equipped with a programmable logic circuit is reduced. The NIC includes a programmable logic circuit that processes input packets according to recorded circuit information, a pair of switches that are arranged at the input end and output end of the programmable logic circuit, respectively, and are capable of switching between a first mode in which a packet is sent to the programmable logic circuit and a second mode in which the packet is bypassed without passing through the programmable logic circuit, a computer-side interface that transmits the packet to a computer equipped with a processor that can execute an application program that can execute packet processing instead of the programmable logic circuit, and a switch control circuit that switches the pair of switches to the second mode when the circuit information of the programmable logic circuit is rewritten." This technology requires a switch and a control circuit for program rewriting during service. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2020 / 122024 Summary of the Invention [Problem to be solved by the invention]

[0005] For example, as the interface devices (also called network devices) of storage systems become more sophisticated, the size of the software executed by the interface devices also increases. For example, a smart NIC equipped with a processor capable of executing high-load processing may execute software for ASICs in addition to executing the OS and applications that run on the OS.

[0006] As described above, the software size of the interface device is large, and therefore a large number of resources may be required to update the software. In addition, in a storage system that is required to operate continuously, it is required to update the software of the interface device without stopping IO, so it is difficult to allocate a large memory area to the interface device. Therefore, it is required to appropriately update the software of the interface device within the capacity limit. [Means for solving the problem]

[0007] An information processing device having a communications interface according to one aspect of the present invention stores a compressed file including firmware for updating the communications interface, and executes, in parallel, a signature verification process and a decompression process for at least a portion of compressed data in the compressed file.

[0008] In one aspect of the present invention, a method for updating firmware for a communication interface in an information processing device includes the information processing device executing, in parallel, a signature verification process and a decompression process for compressed data including at least a portion of update firmware for the communication interface. Effect of the Invention

[0009] According to one aspect of the present disclosure, software updates can be performed efficiently. [Brief description of the drawings]

[0010] [Figure 1] 1 illustrates an example configuration of a storage controller and a smart NIC according to an embodiment of the present specification. [Diagram 2] FIG. 1 is a conceptual operational diagram illustrating firmware update of a smart NIC according to an embodiment of the present specification. [Diagram 3] An example of data contained in smart NIC firmware is shown below. [Figure 4] 1 illustrates a flowchart of an overall process for updating firmware in a smart NIC, according to an embodiment of the present specification. [Diagram 5] 13 shows an example of the configuration of a CHB FW update status management table held by the storage controller. [Figure 6] 13 shows an example of the configuration of a CHB management table held by a storage controller. [Figure 7] Indicates the timing for updating the CHB firmware. [Figure 8] The criteria for updating CHB firmware are shown below. [Figure 9] 13 shows an example of the configuration of a CHB FW update status management table. [Figure 10] 13 shows an example of the configuration of a FW version management table. [Figure 11] FIG. 2 illustrates a sequence diagram of the overall process of firmware update for a smart NIC according to an embodiment of the present specification. [Figure 12] FIG. 13 is a conceptual diagram for explaining firmware update processing by a smart NIC. [Figure 13] 13 is a conceptual diagram for explaining firmware update processing of a smart NIC in a configuration including multiple CHBs. [Figure 14] This shows a sequence diagram of the initial part of a smart NIC firmware update. [Figure 15] A sequence diagram of processing for one block of an OS image in a firmware update of a smart NIC is shown. [Figure 16] This is a sequence diagram of the firmware termination processing and surface switching processing of a smart NIC. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components are generally designated by the same reference numerals, and repeated explanations will be omitted. Note that the embodiment described below is merely an example for realizing the present invention, and does not limit the technical scope of the present invention.

[0012] FIG. 1 shows an example of the configuration of a storage controller 10 and a smart NIC (Network Interface Card) 20 according to an embodiment of this specification. These are implemented in a storage system, which is an example of an information processing device. The smart NIC 20 is an example of an interface device or a network device, and is included in a channel board (CHB). In the example described below, the smart NIC 20 is an interface for communication between a host and the storage controller 10. The smart NIC of this embodiment can also be used as an interface device between storage devices or between storage controllers.

[0013] The storage controller 10 includes a solid state drive (SSD) 101, which is a non-volatile memory, a controller 102, and a DRAM 104, which is a volatile memory. The controller 102 includes multiple processor cores 103. The processor core 103 is a processor, and multiple CPUs, each including one or more processor cores, may be implemented.

[0014] The DRAM 104 stores programs executed by the controller 102 and information referenced by the controller 102. Specifically, a NIC FW update status management table 105 and a CHB management table 106 are stored. FW stands for firmware. In addition, an IO processing program 107 and a maintenance processing program 108 are stored. Data stored in the DRAM 104 is loaded from the SSD 101, for example. The controller 102 operates according to the programs to operate as a predetermined functional unit.

[0015] The IO processing program 107 performs processing according to an IO request received from a host device. The maintenance processing program 108 transmits maintenance commands (commands that a user can operate via a GUI) to the smart NIC 20, and performs network settings for communicating with the host device, FW firmware updates, etc. Firmware updates include replacing part or all of the existing firmware.

[0016] Smart NIC 20 includes a NIC ASIC 201, a controller 202, a DRAM 204, a flash memory 210, and an embedded memory 215 which is a non-volatile memory card. Controller 202 includes multiple processor cores 203. Processor core 203 is a processor, and may be implemented with multiple CPUs, each of which includes one or more processor cores.

[0017] The DRAM 204 stores programs executed by and information referenced by the controller 202. Specifically, it stores a smart NIC FW update status management table 205, a FW version management table 206, an IO processing program 207, a maintenance processing program 208, and a network protocol processing program 209. The DRAM 204 also stores an OS (not shown).

[0018] The network protocol processing program 209 converts between the communication protocol with the host device and the communication protocol within the storage system. The IO processing program 207 generates commands for communicating with the storage controller 10 in response to requests received from the host device, and performs data transfer processing to the host device / storage controller 10.

[0019] The maintenance processing program 208 reflects the setting values ​​in the smart NIC 20 based on the maintenance command information passed from the storage controller 10, and also executes firmware update.

[0020] Flash memory 210 stores firmware (NIC FW) 211 for NIC ASIC 201. Embedded memory 215 stores OS image 216, Bootloader 217, and configuration information / version information 218. Embedded memory 215 also temporarily stores temporary information 219 during firmware update of the smart NIC. Although not shown in Fig. 1, embedded memory 215 also stores a controller that stores temporary information 219. The operation of the controller will be described in detail later.

[0021] The OS image 216 includes the OS and programs 207 to 209 executed by the controller 202. The bootloader 217 is a boot program for the OS. The setting information / version information 218 includes the tables 205, 206 stored in the DRAM 204 and other management information.

[0022] 2 is a conceptual operation diagram showing a firmware update of the smart NIC 20 according to an embodiment of this specification. In the following, an example in which the entire old firmware is replaced with new firmware is described. The firmware update of the smart NIC 20 described in this specification can be applied to an information processing device other than a storage system, for example, a smart NIC 20 implemented in a server. It can also be applied to an interface device or communication processing device other than the smart NIC.

[0023] The management server 30 creates a smart NIC FW from a new OS image 216 and a NIC FW 211, and generates compressed data 301 (also called a compressed file). A signature is added to the compressed data 301. Here, the OS image 216 is assumed to also include a boot program Bootloader 217. The storage controller 10 receives the compressed data 301 of the smart NIC FW and its header information from the management server 30 via a management network (not shown), and stores it in the SSD 101. By compressing the data, it is possible to reduce the storage area required by the storage controller 10.

[0024] 3 shows an example of data included in smart NIC FW 300. Smart NIC FW includes SNIC FW header information 305 and SNIC FW data 307. SNIC FW header information 305 includes information about SNIC FW data 307, such as version information of SNIC FW data 307, date and time information when the data was generated, data size of compressed SNIC FW data 307, signature method, signatures of OS image 216 and NIC FW 211, etc.

[0025] The SNIC FW data 307 includes the NIC FW 211 and the OS image 216. As described above, the OS image 216 here also includes the Bootloader 217. The compressed data 301 written from the management server 30 to the SSD 101 of the storage controller 10 includes compressed SNIC FW data 307 and uncompressed SNIC FW header information 305.

[0026] Returning to FIG. 2, the front-end module 130 of the storage controller 10 includes an IO processing program 107 and a maintenance processing program 108. The front-end module 130 stores compressed data 301 of the smart NIC FW in the SSD 101. The front-end module 130 divides the compressed data into a plurality of blocks, and transfers the divided blocks to the smart NIC 20 via the DRAM 104 in the order of arrangement of the blocks from the first block. By transferring the blocks of compressed data, the number of transfers can be reduced. The DRAM 104 does not store all the blocks at the same time, but temporarily stores only one or a portion of the blocks. For example, each block is read from the SSD to the DRAM 104, and transferred without storing multiple blocks at the same time. The compressed data may be divided in the DRAM 104.

[0027] The front-end module 230 of the smart NIC 20 includes an IO processing program 207 and a maintenance processing program 208. The controller 202 executes the front-end module 230 to perform a signature verification process for each divided and transferred block, and a decompression process and a write process to the embedded memory 215 in parallel. As shown in FIG. 1, the controller 202 includes multiple cores 203. Different cores execute the signature verification process and the decompression and write processes of the blocks in parallel. This can increase the processing speed. For example, when a write request to the embedded memory 215 of one block is completed, the next block is stored in the DRAM 204. The operation of the front-end module 230 of the smart NIC 20 described below is also executed by the controller 202.

[0028] Before starting to transfer divided blocks of compressed data, the front-end module 130 of the storage controller 10 passes information on the total size of the compressed data to the smart NIC 20. It also notifies each block of which part of the entire compressed data the block being transferred is, and what the size of the block to be transferred is.

[0029] The front-end module 230 of the smart NIC 20 executes a part of the signature verification process that can be executed for each block, and also executes the process of decompressing the block and writing it to the embedded memory 215. When the signature verification of the last block is completed, the signature verification of the entire compressed data can be completed from the signature verification results of each block. In addition, the decompressed blocks are integrated into the OS image or NIC firmware by the association between the addresses.

[0030] As described above, by dividing the compressed data 301, it is possible to reduce the DRAM area of ​​the storage controller 10 and the smart NIC 20 required for firmware update. This makes it possible to suppress a reduction in the cache area of ​​the host data of the storage controller 10 or the buffer area of ​​the host data of the CHB. Note that the signature verification process and the decompression and writing process may be performed on the compressed data 301 collectively without dividing it. Also, the signature verification and decompression of the divided blocks can be performed using known techniques.

[0031] The signature verification process for the entire compressed data 301 is made up of partial processes for the blocks. The controller 202 can complete the signature verification process for the entire compressed data 301 by performing the signature verification process for all the blocks in the arrangement order starting from the first block.

[0032] Controller 202 writes the decompressed blocks to a storage area of ​​embedded memory 215 via DRAM 204. NIC FW 211 is stored in a temporary storage area of ​​embedded memory 215 and then stored in flash memory 210. Portions of decompressed OS image 216 are sequentially stored from DRAM 204 to a storage area of ​​embedded memory 215.

[0033] The flash memory 210 includes two logical partitions (storage areas), a front side and a back side. The new NIC FW 211 is stored in the back side of the flash memory 210. The old NIC FW 211 before the update is stored in the front side of the flash memory 210. The storage area of ​​the built-in memory 215 includes two logical partitions, a front side and a back side. The new OS image 216 is stored in the back side of the built-in memory 215.

[0034] The old OS image 216 before the update is stored in the front side of the flash memory 210. As described below, after the new firmware is normally stored in the secondary side, switching between the front side and the secondary side is executed. With the switching, the source from which the firmware is used is read changes from the front side before the switch to the secondary side before the switch. When the firmware is loaded again, it can be started in the front side after the switch. Since no writing is done to the currently active side and it is stored in the secondary side, services to the host (access from the host) can be continued.

[0035] 4 shows a flowchart of the overall process of firmware update of the smart NIC 20 according to one embodiment of the present specification. First, the management server 30 integrates the OS image and the NIC FW to generate smart NIC FW data 307 (S11). The management server 30 further compresses the smart NIC FW data 307 to generate compressed data 301 including smart NIC FW header information 305 (S12). A signature is added to the compressed data 301. This improves safety and reliability.

[0036] The controller 102 of the storage controller 10 receives the compressed data 301 from the management server 30 and stores it in the SSD 101. The controller 102 divides the compressed data 301 and sequentially transfers the divided data to the smart NIC 20 via the DRAM 104 (S13).

[0037] The front-end module 230 (controller 202) of the smart NIC 20 performs signature verification, decompression, writing to the storage area of ​​the embedded memory 215, and writing the NIC FW to the flash memory 210 (NIC FW update) for each transfer unit (divided block unit) (S14).

[0038] Next, the front-end module 230 reintegrates the multiple decompressed blocks (portions) of the new OS image 216 stored in the memory area of ​​the embedded memory 215 with the multiple decompressed blocks (portions) of the new NIC FW 211 stored in the flash memory 210 by associating addresses with each other (S15).

[0039] Next, the front-end module 230 switches the boot surface from the front surface to the secondary surface in each of the storage area of ​​the embedded memory 215 and the flash memory 210 (S16). Furthermore, the front-end module 230 executes a reboot of the smart NIC 20 (S17). This causes the new firmware stored in the new front surface to be executed. If the reboot is not executed normally (S18: NO), the smart NIC 20 is blocked (S19). If the reboot is executed normally (S18: YES), the smart NIC 20 resumes processing with the new firmware.

[0040] The information held by the storage controller 10 and the smart NIC 20 will be described. Fig. 5 shows an example of the configuration of a CHB FW update status management table 105 held by the storage controller 10. The CHB FW update status management table 105 manages the status of firmware update processing of the CHB. Note that here, the number of smart NICs implemented in each CHB is 1, and information about firmware update processing of the CHB means information about the update processing of the smart NIC.

[0041] The CHB FW update status management table 105 includes a CHB ID column 151, a firmware update reception status column 152, a firmware update in progress column 153, and a surface switching status column 154. The storage controller 10 updates the CHB FW update status management table 105 in response to a response from the smart NIC 20 as necessary.

[0042] The CHB ID field 151 indicates the identifier (ID) of the CHB, which can be considered the ID of the smart NIC. The firmware update accepting status field 152 indicates whether the CHB can accept a firmware update process. The firmware updating in progress field 153 indicates whether the CHB is in the process of updating firmware. The surface switching status field 154 indicates whether the CHB can perform a surface switching process.

[0043] 6 shows an example of the configuration of the CHB management table 106 held by the storage controller 10. The CHB management table 106 includes the firmware version and other attribute information of the CHB.

[0044] 6, the CHB management table 106 includes a CHB ID column 161, an operating status column 162, a firmware version column 163, and a network information column 164. The storage controller 10 manages and updates the CHB management table 106.

[0045] The operation status column 162 indicates whether the CHB is currently operating normally. The operation status column 162 is updated as needed in response to a response from the smart NIC 20. The firmware version column 163 indicates the version of the firmware of the CHB held by the storage controller. The network information column 164 indicates communication information of the CHB, such as an IP address and a packet size for data transfer.

[0046] 7 and 8 are diagrams for explaining other information held in advance by the storage controller 10. Fig. 7 shows a trigger for updating firmware of the CHB. In response to the trigger shown in Fig. 7, the storage controller 10 starts the sequence shown in Fig. 11 and executes the necessary firmware update of the CHB.

[0047] Fig. 8 shows the criteria for determining whether to update the firmware of the CHB. The presence or absence of a firmware update is determined based on the update firmware held by the storage controller 10, the current firmware version of the CHB, and the setting of the forced execution mode. Note that the determination may be based on only one of these, for example, only the relationship between the firmware versions, or other conditions may be used.

[0048] In the example shown in Fig. 8, when the version of the firmware for the update is the same as the version of the current CHB firmware, the firmware update is not performed regardless of whether the forced execution mode is on. When the version of the firmware for the update is smaller than the version of the current CHB firmware (when it is an older version), if the forced execution mode is ON, the firmware update is performed, and if it is OFF, it is not performed. When the version of the firmware for the update is larger than the version of the current CHB firmware (when it is a newer version), the firmware update is performed regardless of whether the forced execution mode is on.

[0049] 9 and 10 show examples of management information held by the smart NIC 20. Fig. 9 shows an example of the configuration of a CHB FW update status management table 205. The CHB FW update status management table 205 manages the status of the CHB in the firmware update process. The CHB FW update status management table 205 is updated by the controller 202 as needed.

[0050] In the example shown in FIG. 9, the CHB FW update status management table 205 includes a CHB ID column 251, a firmware update acceptance status column 252, a firmware transfer status column 253, a plane switching acceptance possible status column 254, a plane switching in progress column 255, and a reset waiting column 256.

[0051] The firmware update acceptance status field 252 indicates whether the smart NIC 20 is able to accept a firmware update. The firmware transfer status field 253 indicates the current status of the firmware update process. In the example shown in FIG. 9, the signature verification execution status field indicates the block currently executing signature verification. The decompression and writing status field indicates the block currently executing the decompression and writing process. The NIC FW decompression status field indicates whether decompression of the NIC FW has been completed.

[0052] The plane switching acceptance status field 254 indicates whether the smart NIC 20 can accept a plane switching. A plane switching is a switching between the front and secondary planes of the embedded memory 215 and the flash memory 210. The plane switching in progress field 255 indicates the execution status of the plane switching, indicating whether the plane switching has been performed or is in progress. The reset waiting field 256 indicates whether the smart NIC 20 can execute a reset process.

[0053] Fig. 10 shows an example of the configuration of the FW version management table 206. The FW version management table 206 manages the current version of the firmware of the smart NIC 20. In the example shown in Fig. 10, the FW version management table 206 includes a CHB ID column 261, a firmware version column 262, and an update time column 263. The firmware version column 262 indicates the current firmware version of the smart NIC 20, and the update time column 263 indicates the time of the update (including the date).

[0054] 11 shows a sequence diagram of the overall process of firmware update of the smart NIC 20 according to one embodiment of this specification. The storage controller 10 requests the current smart NIC firmware version from the smart NIC 20 (S31). The storage controller 10 can start firmware update processing at the opportunity described with reference to FIG. 7. The storage controller 10 can also refer to the CHB FW update status management table 105 to determine whether or not to start firmware update.

[0055] The controller 202 of the smart NIC 20 returns the firmware version information to the storage controller 10 (S32). The firmware version information is stored in the FW version management table 206. The storage controller 10 compares the received current firmware version of the smart NIC 20 with the firmware version indicated in the CHB management table 106 to determine whether or not the firmware of the smart NIC 20 needs to be updated. The determination of whether or not it needs to be updated can be based on the information described with reference to FIG. 8.

[0056] If a firmware update is required, the storage controller 10 and the smart NIC 20 execute steps S33 to S36 for each divided block of compressed data.

[0057] The storage controller 10 stages the compressed block of update firmware data from the SSD 106 to the DRAM 104 (S33) and sends a FW update request to the smart NIC 20 (S34). The smart NIC 20 receives the block by DMA (S35) and performs signature verification and decompression and writing in parallel as described with reference to Figure 2. The NIC firmware is temporarily stored in the embedded memory 215 and then written to the flash memory 210 (S36). The controller 202 of the smart NIC 20 returns a response to the storage controller 10 when processing of the block is complete.

[0058] When the above process is completed for all blocks, the storage controller 10 sends a plane switching request to the smart NIC 20 (S37). Whether or not the request is accepted may be based on the CHB FW update status management table 105. The controller 202 of the smart NIC 20 receives the request, executes plane switching (S38), and returns a response to the storage controller 10.

[0059] The following is a more detailed description of the flow of firmware update processing by the smart NIC 20. FIG.

[0060] Divided blocks of compressed data including NIC firmware 211 and OS image 216 are transferred sequentially from DRAM 104 of the storage controller to DRAM 204 of the smart NIC 20 by DMA. The smart NIC 20 performs signature verification, decompression, and writing for each compressed data block. Signature verification, decompression, and writing are performed in parallel by different cores 203. For example, after one block is written, the next block is transferred.

[0061] The smart NIC 20 judges the success / failure of the process when all blocks are available. It is successful only if both signature verification and decompression (and writing) are completed successfully. Processing of the compressed data as a whole cannot be completed unless all blocks are available, but by performing possible processing for each block, the required memory area can be reduced.

[0062] 13 is a conceptual diagram for explaining the firmware update process of the smart NIC 20 in a configuration including multiple CHBs. The storage controller 10 transfers the common block in parallel to all CHBs that perform firmware updates under its control. This allows for efficient firmware updates. Each CHB operates as described with reference to FIG.

[0063] The flow of firmware update processing of the smart NIC 20 will be described below with reference to multiple sequence diagrams. Fig. 14 shows a sequence diagram of the initial part of firmware update of the smart NIC 20. In the part shown in Fig. 14, the transmission of the updated firmware from the management server 30 to the storage controller 10, and the signature verification and decompression of the NIC firmware 211 part are performed.

[0064] First, the management server 30 creates compressed data of the firmware of the smart NIC 20 (S101) and stores it in the SSD 11 of the storage controller 10 (S102). The front-end module 130 of the storage controller 10 stages a block that is a part of the compressed data in the SSD 101 to the DRAM 104 (S103). Here, it is assumed that all of the compressed data of the NIC firmware 211 is stored in one block. The front-end module 130 requests the smart NIC 20 to transfer the block stored in the DRAM 104 (S104).

[0065] The front-end module 230 (controller 202) of the smart NIC 20 uses DMA transfer to store the blocks stored in the DRAM 104 of the storage controller 10 in its DRAM 204 (S105, S106).

[0066] The front-end module 230 reads the block from the DRAM 204 (S107), and executes the signature verification (S108) and the decompression / writing (S109) of the block in parallel. The front-end module 230 requests the controller 501 of the embedded memory 215 to stage the decompressed NIC firmware 211 (block) (S110). The controller 501 temporarily stores the decompressed NIC firmware 211 in the storage area 502 of the embedded memory 215 (S111).

[0067] Thereafter, the front-end module 230 writes the NIC firmware 211 in the storage area 502 to the secondary side of the flash memory 210 (S112). Furthermore, the front-end module 230 responds to the storage controller 10 with the success / failure of the processing of the NIC firmware 211 (S113).

[0068] 15 shows a sequence diagram of processing for one block of the OS image 216 in firmware update of the smart NIC 20. The sequence shown in FIG.

[0069] First, the front-end module 130 of the storage controller 10 stages a block of the SSD 101 in the DRAM 104 (S151). The front-end module 130 requests the smart NIC 20 to transfer the block stored in the DRAM 104 (S152).

[0070] The front-end module 230 of the smart NIC 20 uses DMA transfer to store the blocks stored in the DRAM 104 of the storage controller 10 in its DRAM 204 (S153, S154).

[0071] The front-end module 230 reads the block from the DRAM 204 (S155), and performs signature verification (S156) and decompression / writing (S157) of the block in parallel. The front-end module 230 requests the embedded memory controller 501 to write the block of the decompressed OS image (S158).

[0072] The controller 501 stores the decompressed block in the secondary side of the OS image in the memory area 502 of the embedded memory (S159). After writing the data, the controller 501 returns a response to the front-end module 230 (S160). The front-end module 230 responds to the storage controller 10 with the success / failure of processing the block (S161).

[0073] Next, the firmware termination process and the surface switching process will be described. Fig. 16 is a sequence diagram of the firmware termination process and the surface switching process of the smart NIC 20. The front-end module 130 of the storage controller 10 stages the termination block of the SSD 101 to the DRAM 104 (S181).

[0074] The front-end module 130 requests the smart NIC 20 to transfer the block stored in the DRAM 104 (S182). Thereafter, the signature verification and decompression / write processing are executed as described with reference to FIG.

[0075] Next, the front-end module 230 of the smart NIC 20 executes a flush process on the data stored in the embedded memory 215 (S183) to ensure that the data is written to the embedded memory 215. Next, the front-end module 230 refers to the results of the signature verification of all blocks and confirms that the signature verification of the entire compressed data is complete (S184).

[0076] If the signature verification is complete, it means that the smart NIC 20 can be started by the firmware stored in the secondary side of the embedded memory 215. Therefore, the front-end module 230 updates the Bootloader 217 (boot program) stored in the embedded memory 215 (S185). Finally, the front-end module 230 updates the CHB FW update status management table 205, and sets the smart NIC 20 to a state in which it can accept side switching.

[0077] The storage controller 10 receives a response indicating the success / failure of the firmware update from the smart NIC 20 (S187). If the update is successful, the storage controller 10 requests the smart NIC 20 to switch the surface (S188).

[0078] The front-end module 230 of the smart NIC 20 executes the plane switching in the built-in memory 215 and the flash memory 210 (S189), and updates the FW version management table 206 (S190). The front-end module 230 returns a response of the success / failure of the plane switching to the storage controller 10 (S191).

[0079] The present invention is not limited to the above-mentioned embodiment, and various modifications are included. For example, the above-mentioned embodiment has been described in detail to clearly explain the present invention, and is not necessarily limited to those having all of the configurations described. In addition, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration.

[0080] In addition, the above-mentioned configurations, functions, processing units, etc. may be realized in part or in whole by hardware, for example, by designing them as integrated circuits. In addition, the above-mentioned configurations, functions, etc. may be realized in software by a processor interpreting and executing a program that realizes each function. Information such as the program, table, file, etc. that realizes each function can be stored in a memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC card or SD card.

[0081] In addition, the control lines and information lines shown are those that are considered necessary for the explanation, and not all control lines and information lines in the product are necessarily shown. In reality, it can be considered that almost all components are connected to each other.

[0082] Several aspects of the disclosure are described below. (1) An information processing device, A controller; an interface device, The controller: storing a compressed file including firmware update for the interface device; Transmitting at least a portion of compressed data of the compressed file to the interface device; The interface device is an information processing device that executes a signature verification process and a decompression process of the received compressed data in parallel. (2) The information processing device according to (1), The controller sequentially transmits the divided blocks from the compressed file to the interface device; The interface device is an information processing device that executes a signature verification process and a decompression process for each block in parallel. (3) The information processing device according to (1), the interface device includes a non-volatile memory; the non-volatile memory includes a first area for storing currently executed firmware and a second area different from the first area; The interface device comprises: writing data obtained by decompressing the compressed data into the second area; the information processing device switches a read source of the firmware to be used from the first area to the second area after writing of the update firmware to all of the second areas is completed. (4) The information processing device according to (2), The interface device comprises: The memory includes a non-volatile memory and a volatile memory, storing the blocks received from the controller in the volatile memory; an information processing device that executes, in parallel, the signature verification process and the decompression process for a block stored in the volatile memory, and stores the decompressed block in the non-volatile memory. (5) The information processing device according to (1), The controller determines whether or not the firmware of the interface device needs to be updated based on a relationship between a current firmware version of the interface device and a version of the update firmware and a setting of a forced update execution mode. (6) The information processing device according to (2), A plurality of interface devices; The controller transmits a common block in parallel to the plurality of interface devices. (7) A network device, A processor; A first memory; a second memory; The processor, receiving compressed data including at least a portion of the firmware update for the network device from another device and storing the compressed data in the first memory; The network device executes a signature verification process and a decompression process of the compressed data in parallel, and stores the decompressed data of the compressed data in the second memory. (8) A network device according to (7), The processor sequentially receives divided blocks of the compressed file of the update firmware, and executes a signature verification process and a decompression process for each divided block in parallel. (9) A method for updating firmware of a network device, comprising: The network device receives compressed data including at least a part of the firmware update from another device and stores the compressed data in a first memory; The method further comprises the network device executing a signature verification process and a decompression process of the compressed data in parallel, and storing the decompressed data in a second memory. (10) The method according to (9), The method, wherein the network device sequentially receives divided blocks of the compressed file of the update firmware, and executes a signature verification process and a decompression process for each divided block in parallel. [Explanation of symbols]

[0083] 10 Storage Controller 20. Smart NIC 101 SSD 102 Controller 103 processor cores 104 DRAM 107 IO Processing Program 108 Maintenance Processing Program 130 Front-end module 201 NIC ASIC 202 Controller 203 processor cores 204 DRAM 207 IO Processing Program 208 Maintenance Processing Program 209 Network Protocol Processing Program 210 Flash Memory 211 NIC Firmware 215 Embedded Memory 216 OS Image 230 Front-end module 301 Compressed Data

Claims

1. An information processing device having a communication interface, storing a compressed file including firmware for updating the communication interface; An information processing device that executes, in parallel, a signature verification process and a decompression process of at least a portion of the compressed data of the compressed file.

2. 2. The information processing device according to claim 1, An information processing device that performs a signature verification process and a decompression process in parallel for each block divided from the compressed file.

3. 2. The information processing device according to claim 1, Contains non-volatile memory, the non-volatile memory includes a first area for storing currently executed firmware and a second area different from the first area; writing data obtained by decompressing the compressed data into the second area; the information processing device switches a read source of the firmware to be used from the first area to the second area after writing of the update firmware to all of the second areas is completed.

4. 3. The information processing device according to claim 2, The memory includes a non-volatile memory and a volatile memory, storing the blocks divided from the compressed file in the volatile memory; an information processing device that executes the signature verification process and the decompression process for a block stored in the volatile memory, and stores the decompressed block in the non-volatile memory.

5. 2. The information processing device according to claim 1, The information processing device determines whether or not the firmware of the communication interface needs to be updated based on a relationship between a current firmware version of the communication interface and a version of the update firmware, and on a setting of a forced update execution mode.

6. 3. The information processing device according to claim 2, the communication interface is a plurality of interface devices; An information processing apparatus, wherein decompressed data of blocks divided from the compressed file is stored for each of the plurality of interface devices.

7. A method for updating firmware of a communication interface in an information processing device, comprising: The method, wherein the information processing device executes, in parallel, a signature verification process and a decompression process for compressed data including at least a part of update firmware for the communication interface.

8. 8. The method of claim 7, The information processing device divides a compressed file including update firmware for the communication interface into blocks; The method, wherein the information processing device executes a signature verification process and a decompression process for each block in parallel.

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