Semiconductor integrated circuit

Abstract

To provide a semiconductor integrated circuit capable of effectively utilizing an extra area of an OTP memory.SOLUTION: An OTP memory 130 includes a first area 132 in which initial data D0 is written during first programming, and a second area 134 that is unused during the first programming. An OTP controller 140 loads the initial data D0 from the OTP memory 130 to a first memory 120. The OTP controller 140 can write a set of a first address value A1 indicating a position on the first memory 120 and first data D1 to the second area 134 of the OTP memory 130. The OTP controller 140 can read the first address value A1 and the first data D1 from the second area 134 of the OTP memory 130. The first data D1 can be written to a position adr on the first memory 120 indicated by the first address value A1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to semiconductor integrated circuits. [Background technology]

[0002] In semiconductor integrated circuits, PROMs (Programmable Read Only Memory), which can store data after manufacturing, are used to store various settings and programs. Among PROMs, OTP (One Time Programmable) memory, which can be written only once, is widely used because of its low cost. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 005956

[0004] [overview] The present disclosure has been made in light of the above-mentioned circumstances, and one of its exemplary purposes is to provide a semiconductor integrated circuit capable of effectively utilizing a surplus area of ​​an OTP memory.

[0005] A semiconductor integrated circuit according to an embodiment of the present disclosure includes a main circuit, a first volatile memory capable of storing data to be referenced by the main circuit, an OTP (One Time Programmable) memory including a first area to which initial data is written at the time of initial programming and a second area unused at the time of initial programming, and an OTP controller that loads the initial data from the OTP memory to the first volatile memory. The OTP controller is capable of writing a set of a first address value indicating a location on the first volatile memory and first data to the second area of ​​the OTP memory, is capable of reading the first address value and the first data from the second area of ​​the OTP memory, and is capable of writing the first data to a location on the first volatile memory indicated by the first address value.

[0006] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc., are also effective as aspects of the present invention. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of a semiconductor integrated circuit according to the first embodiment. [Diagram 2] FIG. 2 is a diagram for explaining the first loading of a program and initial data into the semiconductor integrated circuit of FIG. [Diagram 3] FIG. 3 is a diagram for explaining a second program and changes to initial data in the semiconductor integrated circuit of FIG. [Figure 4] FIG. 4 is a diagram for explaining a second program and modification of initial data in a semiconductor integrated circuit according to a modified example. [Diagram 5] FIG. 5 is a block diagram of a semiconductor integrated circuit according to the second embodiment. [Figure 6] FIG. 6 is a block diagram of a semiconductor integrated circuit according to the third embodiment. [Figure 7] FIG. 7 is a diagram for explaining the second program of the semiconductor integrated circuit of FIG. 6 and the transfer to the second memory.

[0008] [Detailed Description] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0009] A semiconductor integrated circuit according to one embodiment includes a main circuit, a first volatile memory capable of storing data to be referenced by the main circuit, an OTP (One Time Programmable) memory including a first area to which initial data is written at the time of initial programming and a second area unused at the time of initial programming, and an OTP controller that loads the initial data from the OTP memory to the first volatile memory. The OTP controller is capable of writing a set of a first address value indicating a location on the first volatile memory and first data to the second area of ​​the OTP memory, is capable of reading the first address value and the first data from the second area of ​​the OTP memory, and is capable of writing the first data to a location on the first volatile memory indicated by the first address value.

[0010] According to this configuration, after the initial program is completed, additional writing can be performed in the second area, thereby making it possible to rewrite information at any desired location in the first volatile memory with pinpoint accuracy.

[0011] In one embodiment, the semiconductor integrated circuit may further include an error correction code circuit. When loading initial data from the OTP memory to the first volatile memory, if a correction is made by the error correction code circuit to the initial data to be written to a certain position in the first volatile memory, the OTP controller may write a set of an address value indicating a position where the correction has occurred and a value of correct data after the correction to the second area as a set of a first address value and a first data.

[0012] If a correction occurs, it is highly likely that part of the initial data stored in the OTP memory is corrupted. In this case, reliability can be improved by saving the correct value of the initial data in the second area as the first data, and writing the first data read from the second area to the first volatile memory.

[0013] In one embodiment, the OTP controller may load initial data from the OTP memory to the first volatile memory when the semiconductor integrated circuit is powered up, and then, if the second area has been written, read from the second area and write to the first volatile memory.

[0014] In one embodiment, the second area of ​​the OTP memory may include a first portion having a capacity equal to that of the first area and capable of storing a first address value, and a second portion having a capacity equal to that of the first area and capable of storing first data.

[0015] In one embodiment, the first volatile memory may be a register.

[0016] In one embodiment, the semiconductor integrated circuit may further include a second volatile memory separate from the first volatile memory. The OTP controller may be capable of writing a set of a second address value indicating a location on the second volatile memory and second data to a second area of ​​the OTP memory, and may be capable of writing the second data to the location on the second volatile memory indicated by the second address value.

[0017] According to this configuration, it is possible to pinpoint and write information to any position in the second memory, which is not the load destination of the initial data stored in the first area.

[0018] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are illustrative and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0019] In this specification, "a state in which component A is connected to component B" includes a case in which component A and component B are directly physically connected to each other, and a case in which component A and component B are indirectly connected to each other via another component that does not affect the electrical connection state or impair the function.

[0020] Similarly, "a state in which component C is provided between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not affect the electrical connection state or impair the function.

[0021] (Embodiment 1) 1 is a block diagram of a semiconductor integrated circuit 100 according to embodiment 1. The semiconductor integrated circuit 100 includes a bus 102, a main circuit 110, a first volatile memory (hereinafter simply referred to as the first memory) 120, an OTP memory 130, and an OTP controller 140. The main circuit 110, the first memory 120, and the OTP controller 140 are connected to the bus 102.

[0022] The main circuit 110 has a configuration and functions according to the type and application of the semiconductor integrated circuit 100. The first memory 120 is, for example, a register, and is provided to store data to be referenced by the main circuit 110, that is, information necessary for the operation of the main circuit 110.

[0023] The OTP memory 130 includes a first area 132 and a second area 134. Initial data D0 is written to the first area 132 during the first programming. This initial data D0 is an initial value of the data stored in the first memory 120.

[0024] The OTP controller 140 loads the initial data D0 from the first area 132 of the OTP memory 130 into the first memory 120.

[0025] The semiconductor integrated circuit 100 is capable of modifying and changing the value of the initial data D0 to be loaded into the first memory 120. The second area 134 is used for this modification. The second area 134 is unused during the first programming. The second area 134 is used for the second and subsequent programming. The first area 132 is also called a base area, and the second area 134 is also called a spare area.

[0026] During the second or subsequent programming, the OTP controller 140 can write a set of a first address value A1 indicating a location on the first memory 120 and first data D1 to the second area 134 of the OTP memory 130.

[0027] Furthermore, the OTP controller 140 can read the first address value A1 and the first data D1 from the second area 134 of the OTP memory 130. Then, the OTP controller 140 can write the first data D1 to the position adr on the first memory 120 indicated by the first address value A1.

[0028] The above is the configuration of the semiconductor integrated circuit 100. Next, the operation of the semiconductor integrated circuit 100 will be described.

[0029] Fig. 2 is a diagram for explaining the first programming and loading of initial data D0 of the semiconductor integrated circuit 100 of Fig. 1. Fig. 2 shows the OTP memory 130 and the first memory 120. At the time of the first programming, the initial data D0 is written to the first area 132 of the OTP memory 130. The initial programming is usually performed by the manufacturer of the semiconductor integrated circuit 100 before shipment, but may also be performed by the user of the semiconductor integrated circuit 100 after shipment of the semiconductor integrated circuit 100.

[0030] When the semiconductor integrated circuit 100 is in operation, typically when the semiconductor integrated circuit 100 is started up, the OTP controller 140 reads the initial data D0 written in the first area 132, and loads it into a predetermined address range adr1-adr2 of the first memory 120. The address range adr1-adr2 may be a part of the first memory 120, or may be the entirety of the first memory 120.

[0031] FIG. 3 is a diagram for explaining a second program and changes to the initial data D0 of the semiconductor integrated circuit 100 of FIG.

[0032] In the second program, one or more sets S of a first address value A1 and first data D1 are written to the second area 134 of the OTP memory 130. In this example, two sets Sx and Sy are written. The set Sx includes a first address value A1x and a first data D1x, and the set Sy includes a first address value A1y and a first data D1y. The first address value A1x indicates a position adrx on the first memory 120, and the first data D1x indicates a value to be written to the position adrx on the first memory 120.

[0033] In this example, the second area 134 includes a first portion 134a and a second portion 134b. The first portion 134a and the second portion 134b may each have the same capacity as the first area 132. The OTP controller 140 writes the first address value A1 from the beginning of the first portion 134a, and writes the first data D1 from the beginning of the second portion 134b.

[0034] When the semiconductor integrated circuit 100 is started up, the OTP controller 140 loads the initial data D0 in the first area 132 into the address range adr1 to adr2 of the first memory 120.

[0035] If the second region 134 has been programmed, the OTP controller 140 reads the sets Sx and Sy from the second region 134. The OTP controller 140 writes the first data D1x to a location adrx in the first memory 120 indicated by the first address value A1x for the set Sx. Similarly, the OTP controller 140 writes the first data D1y to a location adry in the first memory 120 indicated by the first address value A1y for the set Sy.

[0036] The above is the operation of the semiconductor integrated circuit 100. According to this semiconductor integrated circuit 100, by performing additional writing to the second area 134 after the initial program is completed, it becomes possible to rewrite information at any position on the first memory 120 with pinpoint accuracy.

[0037] 3, the case where the initial data D0 of the first memory 120 is overwritten has been described, but the present disclosure is not limited thereto. For example, the position indicated by the first address value A1 of the set Sz to be programmed in the OTP memory 130 may be outside the range adr1-adr2 into which the initial data D0 is loaded.

[0038] Next, modified examples will be described.

[0039] Fig. 4 is a diagram for explaining a second program and a change in initial data D0 of the semiconductor integrated circuit 100 according to a modified example. In this modified example, the method of writing sets Sx and Sy in the second program differs from that in Fig. 3. Specifically, the pair of first address value A1x and first data D1x are written adjacent to each other, and the pair of first address value A1y and first data D1y are written adjacent to each other.

[0040] (Embodiment 2) 5 is a block diagram of a semiconductor integrated circuit 100A according to a second embodiment. The semiconductor integrated circuit 100A includes an error correction code (ECC) circuit 150 in addition to the semiconductor integrated circuit 100 of FIG. 1. The initial data D0 stored in the OTP memory 130 includes an additional bit (error correction code) for error correction for each word. The type of error correction code is not particularly limited, and examples include a Hamming code, a parity code, a Reed-Solomon code, and a BCH code.

[0041] In the second embodiment, an additional program is automatically performed on the OTP memory 130 during operation of the semiconductor integrated circuit 100A. Specifically, when the initial data D0 is loaded from the OTP memory 130 to the first memory 120, the ECC circuit 150 performs error detection and error correction for each word. When a correction is made by the error correction code circuit for the initial data D0 to be written to a certain position adrz of the first memory 120, the OTP controller 140A writes a set of an address value A1z indicating the position adrz where the correction has occurred and the value of the correct data after the correction to the second area 134 as a set of a first address value and first data D1.

[0042] If a correction occurs, there is a high possibility that a portion of the initial data D0 stored in the OTP memory 130 is corrupted. In this case, the reliability can be improved by saving the correct value of the initial data D0 as the first data D1 in the second area 134 of the OTP memory 130 and writing the first data D1 read from the second area to the first memory 120.

[0043] (Embodiment 3) Fig. 6 is a block diagram of a semiconductor integrated circuit 100B according to embodiment 3. The semiconductor integrated circuit 100B includes a second volatile memory (hereinafter simply referred to as the second memory) 160 in addition to the semiconductor integrated circuit 100 in Fig. 1. The second memory 160 is a memory independent of the OTP memory 130, and is connected to the bus 102.

[0044] The OTP controller 140B can write a set of a second address value A2 indicating a location on the second memory 160 and second data D2 to the second area 134 of the OTP memory 130. The OTP controller 140B can write the second data D2 to the location on the second memory 160 indicated by the second address value A2.

[0045] FIG. 7 is a diagram for explaining the second program of the semiconductor integrated circuit 100B of FIG.

[0046] In the second and subsequent programming, one or more sets of a first address A1 and first data D1 are written to the second area 134 of the OTP memory 130. In this example, one set Sx is written. The set Sx includes a first address value A1x and first data D1x. The first address value A1x indicates a location adrx on the first memory 120, and the first data D1x indicates a value to be written to the location adrx on the first memory 120.

[0047] Furthermore, in the second and subsequent programs, one or more sets of the second address value A2 and the second data D2 are written to the second area 134 of the OTP memory 130. In this example, one set Sz is written. The set Sz includes the second address value A2z and the second data D1z. The second address value A2z indicates the location adrz on the second memory 160, and the second data D2z indicates the value to be written to the location adrz on the second memory 160.

[0048] When the semiconductor integrated circuit 100 is started up, the initial data D0 in the first area 132 is loaded into the address range adr1 to adr2 of the first memory 120 by the OTP controller 140B.

[0049] If the second region 134 has been programmed, the OTP controller 140B reads the sets Sx and Sz from the second region 134. The OTP controller 140B writes the first data D1x to the location adrx in the first memory 120 indicated by the first address value A1x for the set Sx. Similarly, the OTP controller 140B writes the second data D2z to the location adrz in the second memory 160 indicated by the second address value A2z for the set Sz.

[0050] The above is the operation of the semiconductor integrated circuit 100 B. According to this semiconductor integrated circuit 100 B, after the initial program is completed, additional writing to the second area 134 makes it possible to rewrite information at any position on the second memory 160 with pinpoint accuracy.

[0051] 4 may be adopted in the second and third embodiments. Also, the second and third embodiments may be combined, and the semiconductor integrated circuit 100 may include both the second memory 160 and the ECC circuit 150.

[0052] The embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments without departing from the spirit of the present invention defined in the claims.

[0053] (Additional Note) In one aspect, the technology disclosed in this specification can be understood by the following items.

[0054] (Item 1) A main circuit; a first volatile memory capable of storing data to be referenced by the main circuit; An OTP (One Time Programmable) memory including a first area to which initial data is written at the time of a first program and a second area that is unused at the time of the first program; an OTP controller for loading the initial data from the OTP memory to the first volatile memory; Equipped with The OTP controller A set of a first address value indicating a location in the first volatile memory and a first data can be written to the second area of ​​the OTP memory; The first address value and the first data can be read from the second area of ​​the OTP memory; a semiconductor integrated circuit capable of writing the first data to a location on the first volatile memory indicated by the first address value;

[0055] (Item 2) An error correction code circuit is further provided, 2. The semiconductor integrated circuit of claim 1, wherein when loading the initial data from the OTP memory to the first volatile memory, if a correction is made by an error correcting code circuit to the initial data to be written to a certain location in the first volatile memory, the OTP controller writes a set of an address value indicating the location where the correction occurred and a value of the corrected data to the second area as a set of the first address value and the first data.

[0056] (Item 3) The OTP controller loading the initial data from the OTP memory to the first volatile memory when the semiconductor integrated circuit is started; 3. The semiconductor integrated circuit according to claim 1, further comprising: if data has been written to the second area, a read from the second area and a write to the first volatile memory are subsequently performed.

[0057] (Item 4) The second area of ​​the OTP memory includes: a first portion having a capacity equal to that of the first area and capable of storing the first address value; a second portion having a capacity equal to that of the first area and capable of storing the first data; 4. The semiconductor integrated circuit according to any one of items 1 to 3, comprising:

[0058] (Item 5) 5. The semiconductor integrated circuit according to any one of items 1 to 4, wherein the first volatile memory is a register.

[0059] (Item 6) Further comprising a second volatile memory separate from the first volatile memory; The OTP controller A set of a second address value indicating a location in the second volatile memory and a second data can be written to the second area of ​​the OTP memory; 6. The semiconductor integrated circuit according to any one of items 1 to 5, wherein the second data is writable to a location on the second volatile memory indicated by the second address value. [Explanation of symbols]

[0060] 100 Semiconductor integrated circuit 102 Bus 110 Main circuit 120 First Memory 130 OTP memory 132 First area 134 Second area 134a Part 1 134b Part 2 140 OTP Controller 150 ECC circuit 160 Second Memory D0 Initial data D1 First data A1 First address value D2 Second Data A2 Second address value

Claims

1. A main circuit; a first volatile memory capable of storing data to be referenced by the main circuit; An OTP (One Time Programmable) memory including a first area to which initial data is written at the time of initial programming, and a second area which is unused at the time of the initial programming; an OTP controller for loading the initial data from the OTP memory to the first volatile memory; Equipped with The OTP controller includes: A set of a first address value indicating a location on the first volatile memory and first data can be written to the second area of ​​the OTP memory; The first address value and the first data can be read from the second area of ​​the OTP memory; a semiconductor integrated circuit capable of writing the first data to a location on the first volatile memory indicated by the first address value;

2. An error correction code circuit is further provided, 2. The semiconductor integrated circuit of claim 1, wherein when loading the initial data from the OTP memory to the first volatile memory, if a correction occurs by an error correcting code circuit for the initial data to be written to a certain location in the first volatile memory, the OTP controller writes a set of an address value indicating the location where the correction occurred and a value of the corrected data to the second area as a set of the first address value and the first data.

3. The OTP controller includes: loading the initial data from the OTP memory to the first volatile memory when the semiconductor integrated circuit is started; 3 . The semiconductor integrated circuit according to claim 1 , further comprising: a read operation for reading data from said second area and a write operation for writing data to said first volatile memory when said second area is written.

4. The second area of ​​the OTP memory is a first portion having a capacity equal to that of the first area and capable of storing the first address value; a second portion having a capacity equal to that of the first area and capable of storing the first data; 3. The semiconductor integrated circuit according to claim 1, further comprising:

5. 3. The semiconductor integrated circuit according to claim 1, wherein the first volatile memory is a register.

6. Further comprising a second volatile memory separate from the first volatile memory; The OTP controller includes: A set of a second address value indicating a location in the second volatile memory and second data can be written to the second area of ​​the OTP memory; 3 . The semiconductor integrated circuit according to claim 1 , wherein the second data is writable to a location on the second volatile memory indicated by the second address value.

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