RAIL-TO-RAIL nMOS AMPLIFIER

Abstract

To provide a rail-to-rail amplifier assembly with high linearity within a complete / large rail-to-rail range.SOLUTION: An amplifier assembly 10 includes a first input circuit 20 connected to a first signal input node 12 for a first input level range, a second input circuit 30 connected to a second signal input node 14 for a second input level range, and a load circuit coupled to the first input circuit, the second input circuit, and an output node 16 of the amplifier assembly. The first input circuit includes a first auxiliary control transistor element 26 and a first control transistor element 24. The first signal input node is coupled to a control terminal of the first control transistor element and a control terminal of the first auxiliary control transistor element. A path connected in parallel to the first control transistor element includes the first auxiliary control transistor element.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a signal buffer. Signal buffers are widely adopted in analog front-ends, where an input signal is fed to the analog front-end through a signal buffer. To handle a wide range of input signal voltages, the signal buffer is usually required to operate rail-to-rail. [Background technology]

[0002] In "CMOS Analog Circuit Design" by Phillip E. Allen, Douglas R. Holberg et al. (Oxford University Press, 2011), examples of signal buffers with single pMOS, single nMOS, and combination of nMOS and pMOS transistors are used as input stages. However, pMOS or nMOS transistors as input stages do not always meet system requirements due to their limited voltage range. On the other hand, it is well known that combination of pMOS and nMOS is suitable for rail-to-rail input stage topology. However, this setup requires constant transconductance gm circuit and folded cascade as load stage, so using both constant transconductance gm and folded cascade stage increases signal quiescent current Iq and mounting area. Also, the overall circuit structure becomes complicated. Summary of the Invention [Problem to be solved by the invention]

[0003] To address the above-mentioned issues, there is a need for an amplifier assembly that provides rail-to-rail operation, low power operation, and minimal die area. [Means for solving the problem]

[0004] To address the above-mentioned problems, the present disclosure provides an amplifier assembly suitable for use as a rail-to-rail amplifier.

[0005] The amplifier assembly includes a first input circuit connected to a first signal input node, a second input circuit connected to a second signal input node, and a load circuit coupled to the first input circuit, the second input circuit, and an output node of the amplifier assembly. The first input circuit includes a first auxiliary control transistor element and a first control transistor element, and the first signal input node is coupled to a control terminal of the first control transistor element and a control terminal of the first auxiliary control transistor element. A path connected in parallel to the first control transistor element includes the first auxiliary control transistor element. A first input signal may be provided to the amplifier assembly by the first signal input node. A second input signal may be provided by the second signal input node. A signal having a first input level range may be provided at the first signal input node. A signal having a second input level range may be provided at the second signal input node. In some embodiments, the first input level range and the second input level range may be the same, overlapping, partially different, or completely different.

[0006] The phrase "connected in parallel" may specify a type of circuit connection. In some embodiments, the phrase "connected in parallel" may not specify an order of the layout.

[0007] This configuration of the amplifier assembly provides high linearity of the amplifier assembly due to the first auxiliary control transistor element, especially for low input voltages at the first input node. As a result, an amplifier assembly with low power operation having a small die area is provided. Furthermore, the input voltage offset may be reduced due to the linear compensation by the first auxiliary control transistor element. In this way, good accuracy can be achieved in a small mounting area even for small input voltages. The small input offset voltage in a small area also contributes to cost reduction for increasing the rail-to-rail input voltage range without the need for complex circuitry.

[0008] In some embodiments, the first input circuit may include a first clamp circuit. Here, the path connected in parallel to the first control transistor element may include a first clamp circuit connected in series. The first clamp circuit may define an operating point of the first auxiliary control transistor element. In this way, a negative effect of the first auxiliary control transistor element on the operation of the first control transistor at high input voltages at the first signal input node may be avoided. In summary, a rail-to-rail amplifier assembly having high linearity within the full / large rail-to-rail range may be provided.

[0009] In some embodiments, the first clamp circuit may include a first clamp transistor element, where a control terminal of the first clamp transistor element is controlled by an electrical quantity at a bias input node. In this way, the bias on the first auxiliary control transistor element may be adapted to be very flexible and precise, thus improving the accuracy of the transfer function. Furthermore, mismatches between the first auxiliary control transistor element and the first control transistor element, as well as other mismatches, may be efficiently accommodated with little effort.

[0010] In some embodiments, the second input circuit may include a second auxiliary control transistor element and a second control transistor element, where the second signal input node may be coupled to a control terminal of the second control transistor element and to a control terminal of the second auxiliary control transistor element, and a path connected in parallel to the second control transistor element may include the second auxiliary control transistor element.

[0011] In this way, the first and second auxiliary control transistor elements may provide a high linearity of the amplifier assembly for both the first and second signal input nodes, especially at low input voltages. As a result, an amplifier assembly with a small die area and low power operation is provided. Furthermore, the input voltage offset may be reduced due to the linear compensation by the second auxiliary control transistor element. In this way, good accuracy can be achieved in a small mounting area even for small input voltages. The small input offset voltage in a small area also contributes to cost reduction for increasing the rail-to-rail input voltage range without the need for complex circuitry.

[0012] In some embodiments, the second input circuit may include a second clamp circuit. Here, the path connected in parallel to the second control transistor element may include a second clamp circuit connected in series. In this way, adverse effects of the second auxiliary control transistor element on the operation of the first control transistor at high input voltages at the second signal input node may be avoided. In summary, a rail-to-rail amplifier assembly having high linearity within the full / large rail-to-rail range may be provided.

[0013] In some embodiments, the second clamp circuit may include a second clamp transistor element. Here, a control terminal of the second clamp transistor element may be controlled by an electrical quantity at a bias input node. In this manner, the bias of the second auxiliary control transistor element may be adapted to be highly flexible and accurate. Thus, the accuracy of the transfer function may be improved. Furthermore, mismatches of the second auxiliary control transistor element and the second control transistor element, as well as other mismatches, may be efficiently adjusted with little effort.

[0014] In some embodiments, a bias input node coupled to the first clamp transistor element may be coupled to a bias input node coupled to the second clamp transistor element, thus simplifying biasing and making it very fast.

[0015] In some embodiments, the bias input node coupled to the first clamp transistor element may be partially or completely decoupled from the bias input node coupled to the second clamp transistor element, thereby allowing for more accurate biasing and improving the overall linearity of the amplifier assembly, particularly when there is a mismatch between the first and second input circuits.

[0016] In some embodiments, the first clamp transistor element, the first auxiliary control transistor element, the first control transistor element, the second clamp transistor element, the second auxiliary control transistor element, and / or the second control transistor element may be nMOS transistor elements. In some embodiments, all transistor elements of the first input circuit and / or the second input circuit may be nMOS transistor elements. The use of nMOS transistor elements for the first and second input circuits may improve handling of high input voltages applied to the first and / or second signal input nodes.

[0017] In some embodiments, the first clamp transistor element, the first auxiliary control transistor element, the second clamp transistor element, and / or the second auxiliary control transistor element may be native MOS transistor elements. Reducing the threshold voltage of the first and / or second auxiliary control transistor element may improve the sensitivity for low voltages at the first and / or second signal input nodes. This may improve the offset voltage at the first and / or second control transistor element, and may increase the linearity of the amplifier assembly at low input voltages. Furthermore, a native input stage including one or more of the first auxiliary control transistor element, the second auxiliary control transistor element, the first clamp transistor element, and the second clamp transistor element may help to extend the input voltage range of the amplifier and reduce the input offset voltage at low input voltages. Also, using the native transistor element as the clamp transistor element may help to switch the native MOS first / second auxiliary control transistor element to the standard MOS first / second control transistor element as an analog operation. Thus, a smooth transition from native MOS to standard MOS may be achieved.

[0018] In some embodiments, the first control transistor element and / or the second control transistor element may be standard MOS transistor elements, which may result in a linear transfer function of the amplifier assembly for medium and high input voltages.

[0019] In some embodiments, the load circuit may include an output transistor element for controlling the output of the amplifier assembly based on the output electrical quantity of the first input circuit and the output electrical quantity of the second input circuit, which may have the advantage that a high output voltage close to the supply voltage of the amplifier assembly is possible (rail-to-rail output).

[0020] In some embodiments, the load circuit may include an output transistor element, where the first input circuit and the second input circuit may affect an electrical quantity at a control terminal of the output transistor element, which may have the advantage that a high output voltage close to the supply voltage of the amplifier assembly is possible (rail-to-rail output).

[0021] In some embodiments, the load circuit may include a current mirror circuit and an output transistor element, where the current mirror circuit may be coupled to the first input circuit, the second input circuit, and the output transistor element, and the output transistor element may control the output of the amplifier assembly, thereby allowing a simple and efficient coupling of the first input circuit and the second input circuit to control the output of the amplifier assembly.

[0022] In some embodiments, the load circuit may include an output transistor element, a first load transistor element, and a second load transistor element, where the first input circuit may be coupled to a control terminal of the first load transistor element, a control terminal of the second load transistor element, and a channel of the first load transistor element. The second input circuit may be coupled to the channel of the second load transistor element and to the control terminal of the output transistor element, and the channel of the output transistor element may be coupled to an output of the amplifier assembly. This allows for a simple and efficient coupling of the first input circuit and the second input circuit to control the output of the amplifier assembly.

[0023] In some embodiments, the output transistor element, the first load transistor element, and / or the second load transistor element may be pMOS transistor elements. In some embodiments, all transistor elements of the load circuit may be pMOS transistor elements. This may have the advantage of being able to output a high output voltage range, particularly close to the power supply voltage. Furthermore, the overall leakage current may be reduced.

[0024] In some embodiments, the output transistor element, the first load transistor element, and / or the second load transistor element may be standard MOS transistor elements. In some embodiments, all transistor elements of the load circuit may be standard MOS transistor elements. In this way, the overall size of the amplifier assembly may be reduced and the transconductance may be improved. Thus, the efficiency of the amplifier assembly may be increased.

[0025] In some embodiments, the output of the amplifier assembly may be coupled to the first signal input node or the second signal input node. In this manner, a simple and efficient voltage follower with a large voltage range and low losses can be provided.

[0026] In summary, an amplifier assembly with improved rail-to-rail range and simplified circuitry may be provided, in which an auxiliary control transistor element is connected in parallel to a control transistor element of an input circuit connected to an input node. The drain-source voltage of the auxiliary control transistor element may be dominant compared to the drain-source voltage of the control transistor element for the output of the respective input circuit at low input voltages. On the other hand, the auxiliary control transistor element may be decoupled by a clamp circuit, in particular a clamp transistor, at high input voltages. In this way, the drain-source voltage of the control transistor element may be dominant compared to the drain-source voltage of the auxiliary control transistor element for the output of the respective input circuit at high input voltages.

[0027] Thus, an amplifier assembly is provided that has a highly linear transfer function, a small input offset voltage, a small die area, and a large rail-to-rail range. More specifically, the small input offset voltage with a small area helps to achieve good precision. The small input offset voltage with a small area also helps to reduce trimming costs. Furthermore, the rail-to-rail input voltage range can be extended without complex circuitry, which saves energy and therefore reduces heat dissipation. Also, the large rail-to-rail amplifier assembly is simplified, so that only a small mounting area is required. The use of native nMOS as the clamp transistor element allows a smooth transition from the native nMOS input stage (native nMOS auxiliary control transistor element) to the standard nMOS input stage (standard nMOS control transistor element). Finally, the rail-to-rail operation without the constant transconductance gm circuit allows low signal quiescent current operation (Iq current operation). [Brief description of the drawings]

[0028] [Figure 1] FIG. 2 is a schematic diagram of an example amplifier assembly according to one embodiment. [Diagram 2] FIG. 2 is a schematic diagram of an example amplifier assembly according to another embodiment. [Diagram 3] FIG. 2 is a schematic diagram of an example amplifier assembly according to one embodiment. [Figure 4] FIG. 2 illustrates a schematic diagram of an example in which an amplifier assembly is used as a voltage follower, according to one embodiment. [Diagram 5] FIG. 5 is a schematic diagram illustrating an example of a transfer function of an amplifier assembly according to an embodiment connected as shown in FIG. 4. [Figure 6a]1 is a schematic diagram illustrating an example of a temperature dependence of a transfer function in an amplifier assembly, where the first auxiliary control transistor element, the second auxiliary control transistor element, the first clamp transistor element, and the second clamp transistor element are standard transistor elements, according to an embodiment. [Figure 6b] 1 is a schematic diagram illustrating an example of a temperature dependence of a transfer function in an amplifier assembly, where the first auxiliary control transistor element, the second auxiliary control transistor element, the first clamp transistor element, and the second clamp transistor element are native transistor elements, according to an embodiment. [Figure 7a] FIG. 6B is a schematic diagram showing an example of an error between the transfer function shown in FIG. 6a and an ideal linear rail-to-rail transfer function. [Figure 7b] FIG. 6B is a schematic diagram showing an example of an error between the transfer function shown in FIG. 6B and an ideal linear rail-to-rail transfer function. [Figure 8a] 1 illustrates an example of Monte Carlo simulation results over temperature of an amplifier assembly, where the auxiliary control transistor elements are standard MOS transistor elements, according to one embodiment. [Figure 8b] 1 illustrates an example of Monte Carlo simulation results over temperature of an amplifier assembly, where the auxiliary control transistor element is a native MOS transistor element, according to one embodiment. [Figure 9] FIG. 4 is a diagram showing an example of measurement results of a PWM converter versus supply voltage and temperature, in which an amplifier assembly as shown in any of the figures 1 to 3 is used; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] FIG. 1 is a schematic diagram of an example of an amplifier assembly 10 according to an embodiment of the present disclosure. The amplifier assembly 10 is suitable for use as a rail-to-rail amplifier and includes a first input circuit 20 connected to a first signal input node 12 for a first input level range, a second input circuit 30 connected to a second signal input node 14 for a second input level range, and a load circuit 40 coupled to the first input circuit 20, the second input circuit 30, and an output node 16 of the amplifier assembly 10. The first input circuit 20 includes a first auxiliary control transistor element 26 and a first control transistor element 24, where the first signal input node 12 is coupled to a control terminal of the first control transistor element 24 and a control terminal of the first auxiliary control transistor element 26. A path connected in parallel to the first control transistor element 24 includes the first auxiliary control transistor element 26.

[0030] The expression "a path connected in parallel to the first control transistor element" does not impose any geometric layout restrictions and determines whether or not amplifier assembly elements / units are connected.

[0031] 1, the first input circuit 20 may include a first clamp circuit 28. Here, a path connected in parallel to the first control transistor element 26 may include a first clamp circuit 28 connected in series.

[0032] 1, the second input circuit 30 may include a second auxiliary control transistor element 36 and a second control transistor element 34, where the second signal input node 14 may be coupled to a control terminal of the second control transistor element 34 and a control terminal of the second auxiliary control transistor element 36. A path connected in parallel to the second control transistor element 34 may include the second auxiliary control transistor element 36.

[0033] 1, the second input circuit 30 may include a second clamp circuit 38. Here, the path connected in parallel to the second control transistor element 34 may include a second clamp circuit 38 connected in series.

[0034] When the input voltage at the first signal input node 12 increases, the first clamp circuit 28 may clamp the path connected in parallel to the first control transistor element 24. In particular, the first auxiliary control transistor element may be clamped from control of the output of the first input circuit 20. As a result, the first auxiliary control transistor element 26 may be disconnected and the first control transistor element 24 may take over.

[0035] When the input voltage at the second signal input node 14 increases, the second clamp circuit 38 may clamp the path connected in parallel to the second control transistor element 34. In particular, the second auxiliary control transistor element 36 may be clamped from control of the output of the second input circuit 30. As a result, the second auxiliary control transistor element 36 may be disconnected and the first control transistor element 34 may take over.

[0036] On the other hand, when the first auxiliary control transistor element 26 and / or the second auxiliary control transistor element 36 are in the linear region, the output voltage of the first input circuit 20 and / or the second input circuit 30 may reach the source node of the first and / or the second auxiliary control transistor element, respectively, so that when the first and / or the second input signal, respectively, is about the power supply voltage Vdd, the first control transistor element 24 and / or the second control transistor element 34, respectively, may not operate.

[0037] In some embodiments, the amplifier assembly may comprise a bias current source 18 for biasing the first control transistor element 24 and / or the second control transistor element 34. Thus, the bias current source 18 may be connected in series with the first control transistor element 24 and / or the second control transistor element 34.

[0038] FIG. 2 is a schematic diagram of an example of an amplifier assembly 10 according to another embodiment. FIG. 2 is based on FIG. 1. FIG. 1 shows a load circuit 40 connected to a power supply voltage V DD , and the first input circuit 20 and the second input circuit 30 are coupled to a second potential V, which may be ground from the load circuit 40. SS 2 shows a configuration of the amplifier assembly 10 in which a first input circuit 20 and a second input circuit 30 form a path from a power supply voltage V DD , and the load circuit 40 is connected to a second potential V, which may be ground, from the first input circuit 20 and the second input circuit 30. SS In this regard, the circuit configurations of the first input circuit 20, the second input circuit 40, and the load circuit 40 may be adapted in response to such a reconfiguration.

[0039] Fig. 3 is a schematic diagram of an example of an amplifier assembly 10 according to another embodiment. Fig. 3 is based on the embodiment shown in Fig. 1. Moreover, the amplifier assembly shown in Fig. 3 may be adapted to match the embodiment shown in Fig. 2, similar to the embodiment shown in Fig. 1. Therefore, a description of the same or similar circuit elements will be omitted.

[0040] 3, the first clamp circuit 28 may include a first clamp transistor element 25, where a control terminal of the first clamp transistor element 25 may be controlled by an electrical quantity at a bias input node 29.

[0041] When the input voltage at the first signal input node 12 increases to reach the input voltage at the bias input node 29, the first clamp transistor element 25 may clamp or start to clamp the first auxiliary control transistor element 26. As a result, the first auxiliary control transistor element 26 is disconnected and therefore turned off, and the first control transistor element 24 takes over. This means that the output vd1 of the first input circuit 20 supplied to the load circuit 40 is essentially controlled by the first auxiliary control transistor element 26 at low input voltages at the first input node 12, and essentially controlled by the first control transistor element 24 at high input voltages at the first input node 12.

[0042] 3, the second clamp circuit 38 may include a second clamp transistor element 35, where a control terminal of the second clamp transistor element 35 may be controlled by an electrical quantity at a bias input node 39.

[0043] When the input voltage at the second signal input node 14 increases to reach the input voltage at the bias input node 39, the second clamp transistor element 35 may clamp or start to clamp the second auxiliary control transistor element 36. As a result, the second auxiliary control transistor element 36 is disconnected and therefore turned off, and the second control transistor element 34 takes over. This means that the output vd2 of the second input circuit 30, which is supplied to the load circuit 40, is essentially controlled by the second auxiliary control transistor element 36 at low input voltages at the second input node 14, and is essentially controlled by the second control transistor element 34 at high input voltages at the second input node 14.

[0044] In some embodiments, bias input node 29 may be coupled to bias input node 39. In some embodiments, bias input node 29 may be decoupled from bias input node 39.

[0045] The first clamp circuit may include a bias resistor 27 connected in series with the first clamp transistor element 25, and / or the second clamp circuit may include a bias resistor 37 connected in series with the second clamp transistor element 35. As shown in FIG. 3, the first bias resistor 27 and the second bias resistor 37 may be shared with each other by the first clamp circuit 28 and the second clamp circuit 38.

[0046] In some embodiments, the first clamp transistor element 25, the first auxiliary control transistor element 26, the first control transistor element 24, the second clamp transistor element 35, the second auxiliary control transistor element 36, and / or the second control transistor element 34 may be nMOS transistor elements. In some configurations, all transistor elements of the first input circuit 20 and / or the second input circuit 30 may be nMOS transistor elements.

[0047] In some embodiments, the first clamp transistor element 25, the first auxiliary control transistor element 26, the second clamp transistor element 35, and / or the second auxiliary control transistor element 36 may be native MOS transistor elements. In some configurations, the first control transistor element 24 and / or the second control transistor element 34 may be standard MOS transistor elements.

[0048] 3, the load circuit 40 may include an output transistor element 46 for controlling the output 16 of the amplifier assembly 10 based on an output electrical quantity vd1 of the first input circuit 20 and an output electrical quantity vd2 of the second input circuit 30. In some configurations, the first input circuit 20 and the second input circuit 30 affect an electrical quantity at a control terminal of the output transistor element 46.

[0049] In some alternative embodiments, the load circuit may control the output 16 of the amplifier assembly 10 based on the output electrical quantity vd1 of the first input circuit 20 and the output electrical quantity vd2 of the second input circuit 30, without going through the output transistor element 46, by directly outputting a control signal that is supplied to the output transistor element 46.

[0050] 3, the load circuit may include current mirror circuits 42, 44 and an output transistor element 46, where the current mirror circuits 42, 44 may be coupled to the first input circuit 20 and the second input circuit 30. In some embodiments, the output of the current mirror circuit may be output directly at the output node 16. In some alternative configurations, the current mirror circuit may be coupled to the first input circuit 20, the second input circuit 30, and the output transistor element 46, which controls the output 16 of the amplifier assembly 10.

[0051] 3, the load circuit may include an output transistor element 46, a first load transistor element 42, and a second load transistor element 44, where the first input circuit 20 may be coupled to the control terminal 42 of the first load transistor element, the control terminal 44 of the second load transistor element, and the channel of the first load transistor element 42, and the second input circuit 30 may be coupled to the channel of the second load transistor element 44 and the control terminal of the output transistor element 46, the channel of the output transistor element 46 being coupled to the output 16 of the amplifier assembly 10. In some embodiments, the output transistor element 46 may be omitted and the signal provided to the control terminal of the output transistor element 46 may be provided directly to the output 16 of the amplifier assembly.

[0052] In some configurations, the output transistor element 46, the first load transistor element 42, and / or the second load transistor element 44 may be pMOS transistor elements. In some embodiments, all transistor elements in the load circuit 40 may be pMOS transistor elements.

[0053] In some configurations, the output transistor element 46, the first load transistor element 42, and / or the second load transistor element 44 may be standard MOS transistor elements. In some embodiments, all of the transistor elements in the load circuit 40 may be standard MOS transistor elements.

[0054] In some configurations, the output 16 of the amplifier assembly 10 may be coupled to the first signal input node 12 or the second signal input node 14. Such a configuration may be used to obtain a voltage follower, particularly a wide range voltage follower.

[0055] In some embodiments, the amplifier assembly includes a load resistor R coupled to the output node 16. L 48 may be provided.

[0056] In addition to rail-to-rail operation, the disclosed amplifier assembly may optimize input offset voltage. At low voltage input ranges, the native nMOS transistor elements 25, 26, 35, 36 operate with a smaller threshold voltage because the native nMOS does not have a threshold voltage adjustment process. Thus, the native nMOS transistor elements 25, 26, 35, 36 provide improved voltage precision.

[0057] 4 is a schematic diagram of an example where the amplifier assembly is used as a voltage follower, according to one embodiment. As shown in FIG. 4, bias input node 29 and bias input node 39 are summed into a single bias input node. Additionally, the output of the amplifier assembly is coupled to a first signal input node 12, which forms the negative input of the amplifier assembly.

[0058] Figure 5 is a schematic diagram of an example transfer function of an amplifier assembly according to an embodiment connected as shown in Figure 4. On the x-axis, the input signal is shown in volts, and on the y-axis, the output signal is shown in volts.

[0059] Graph 51 in Figure 5 shows the transfer function of the amplifier assembly shown in Figure 3, excluding the paths connected in parallel to the first control transistor element 24 and the second control transistor element 34. Graph 52 in Figure 5 shows the transfer function of the amplifier assembly shown in Figure 3, but without the clamp transistor elements 25, 35 (clamp transistor elements 25 and 35 have been replaced by respective transmission lines). Graph 53 in Figure 5 shows the transfer function of the amplifier assembly described above with reference to Figure 3.

[0060] From the graphs 51 and 52, it can be seen that the first auxiliary control transistor element 26 and the second auxiliary control transistor element 36 improve the accuracy of the amplifier assembly for low input voltages. However, such adaptation causes an overshoot of the transfer function for high input voltages. By implementing the first clamp transistor element 25 and the second clamp transistor element 35, such overshoot for high input voltages can be avoided with little effort, since the first clamp transistor element 25 and the second clamp transistor element 35 isolate the first auxiliary control transistor element 26 and the second auxiliary control transistor element 36 by clamping the paths connected in parallel to the first control transistor element 24 and the second control transistor element 34, respectively. In this way, the first auxiliary control transistor element 26 and / or the second auxiliary control transistor element 36 can be turned off, respectively.

[0061] The transfer function shown in FIG. 5 is based on simulations for the following amplifier assembly configuration:

[0062] [Table 1]

[0063] FIG. 6a is a schematic diagram of an example of the temperature dependence of the transfer function in an amplifier assembly without an auxiliary control transistor element and a clamp transistor element.

[0064] 6b is a schematic diagram illustrating an example of the temperature dependence of the transfer function in an amplifier assembly, according to one embodiment, where the first auxiliary control transistor element 26, the second auxiliary control transistor element 36, the first clamp transistor element 25, and the second clamp transistor element 35 are native transistor elements.

[0065] In Figures 6a and 6b the amplifier assembly is connected as shown in Figure 4. On the x-axis the input voltage provided at the signal input node 14 is shown and on the y-axis the output voltage provided at the output node 16 is shown.

[0066] In the figure, graphs of several processes and temperatures (-40°C, 25°C, and 150°C) are shown. As shown in Figures 6a and 6b, when the first auxiliary control transistor element 26, the second auxiliary control transistor element 36, the first clamp transistor element 25, and the second clamp transistor element 35 are provided, the accuracy at low input voltages is high. Based on these results, when the first auxiliary control transistor element 26, the second auxiliary control transistor element 36, the first clamp transistor element 25, and the second clamp transistor element 35 are provided, the input voltage range can be increased, and therefore the overall rail-to-rail range can be improved.

[0067] Figures 7a and 7b are schematic diagrams showing an example of the error between the transfer function shown in Figures 6a and 6b and an ideal linear rail-to-rail transfer function, respectively. The x-axis shows the voltage supplied to the second signal input node 14. The y-axis shows the error between the output voltage shown in Figures 6a and 6b and an ideal linear rail-to-rail transfer function. The error is in mV.

[0068] FIG. 8a illustrates an example of a result of a Monte Carlo simulation over temperature of an amplifier assembly according to the embodiment shown in FIG. 3, where the auxiliary control transistor element is a standard MOS transistor element. FIG. 8b illustrates an example of a result of a Monte Carlo simulation over temperature of an amplifier assembly according to the embodiment shown in FIG. 3, where the auxiliary control transistor element is a native MOS transistor element. FIGs. 8a and 8b illustrate the results of a Monte Carlo simulation performed 300 times, respectively, over temperature values ​​of 40° C., 25° C., and 150° C., with a predetermined voltage of 1 V applied to the second signal input node 14.

[0069] A performance summary based on Monte Carlo simulations is shown below.

[0070] [Table 2]

[0071] A simulation point 81a indicates a simulation temperature of −40° C. A simulation point 81b indicates a simulation temperature of +25° C., and a simulation point 81c indicates a simulation temperature of +150° C.

[0072] Thus, even though the transistor elements 25, 26, 35, 36, which are native transistor elements, employ different aspect ratios compared to the transistor elements 25, 26, 35, 36, which are standard transistor elements, the amplifier assembly with the native configuration has a variation that is 0.5 mV (at 1 sigma) less than the amplifier assembly with the standard configuration. Thus, the output voltage variation at 1 sigma is reduced by 0.5 mV, improving overall accuracy. Thus, the use of native transistor elements for the transistor elements 25, 26, 35, 36 can improve input offset voltage and rail-to-rail operation. These considerations may be particularly relevant for automotive products.

[0073] FIG. 9 is a diagram showing an example of measurement results of a PWM (Pulse Width Modulation) converter versus supply voltage and temperature. Here, an amplifier assembly as shown in any of FIGS. 1 to 3 is used. On the x-axis the input voltage is shown and on the y-axis the generated duty ratio. The dotted line shows the ±3% error from the ideal result. The measurement points of the supply voltages are Vdd=4.5V, Vdd=5V and Vdd=5.5V. For each of these supply voltages, measurements were made at temperatures of -40°C, -20°C, 0°C, 25°C, 50°C, 75°C, 100°C, 125°C and 150°C.

[0074] As shown in Figure 9, the measurement graphs are very close to the ideal curves, all within the error range of ±3%. Therefore, the disclosed amplifier assembly improves the PWM input range and accuracy, and simplifies the circuit configuration. Thus, the disclosed amplifier assembly contributes not only to the circuit performance, but also to cost reduction.

[0075] Throughout this disclosure, references to voltages of transistor elements may refer to commonly known voltages that characterize transistor elements, such as gate-to-source voltage and drain-to-source voltage.

[0076] Voltages of nodes shown without a reference potential in this disclosure may refer to a common reference potential, such as ground.

[0077] It should also be noted that the embodiments illustrated in the accompanying drawings and the above description may be combined with each other.

[0078] In some embodiments, circuit elements can be added, divided, combined, and omitted without affecting the teachings of the present disclosure.

Claims

1. 1. An amplifier assembly suitable for use as a rail-to-rail amplifier, comprising: a first input circuit connected to a first signal input node for a first input level range; a second input circuit connected to a second signal input node for a second input level range; a load circuit coupled to the first input circuit, the second input circuit, and an output node of the amplifier assembly; Including, the first input circuit includes a first auxiliary control transistor element and a first control transistor element; the first signal input node is coupled to a control terminal of the first control transistor element and to a control terminal of the first auxiliary control transistor element; a path connected in parallel to the first control transistor element includes the first auxiliary control transistor element; Amplifier Assembly.

2. the first input circuit includes a first clamp circuit; the path connected in parallel with the first control transistor element includes the first clamp circuit connected in series; 2. The amplifier assembly of claim 1.

3. 3. The amplifier assembly of claim 2, wherein the first clamp circuit includes a first clamp transistor element, a control terminal of the first clamp transistor element being controlled by an electrical quantity at a bias input node.

4. the second input circuit includes a second auxiliary control transistor element and a second control transistor element; the second signal input node is coupled to a control terminal of the second control transistor element and to a control terminal of the second auxiliary control transistor element; a path connected in parallel to the second control transistor element includes the second auxiliary control transistor element; 2. The amplifier assembly of claim 1.

5. the second input circuit includes a second clamp circuit; the path connected in parallel to the second control transistor element includes the second clamp circuit connected in series; 5. An amplifier assembly as claimed in claim 4.

6. 6. The amplifier assembly of claim 5, wherein the second clamp circuit includes a second clamp transistor element, a control terminal of the second clamp transistor element being controlled by an electrical quantity at a bias input node.

7. the first clamp transistor element, the first auxiliary control transistor element, the first control transistor element, the second clamp transistor element, the second auxiliary control transistor element, and / or the second control transistor element are nMOS transistor elements; and / or all transistor elements of the first input circuit and / or the second input circuit are nMOS transistor elements; 2. The amplifier assembly of claim 1.

8. the first clamp transistor element, the first auxiliary control transistor element, the second clamp transistor element, and / or the second auxiliary control transistor element are native MOS transistor elements; and / or the first control transistor element and / or the second control transistor element are standard MOS transistor elements; 2. The amplifier assembly of claim 1.

9. 2. The amplifier assembly of claim 1, wherein the load circuit includes an output transistor element for controlling an output of the amplifier assembly based on an output electrical quantity of the first input circuit and an output electrical quantity of the second input circuit.

10. 2. The amplifier assembly of claim 1, wherein the load circuit includes an output transistor element, and the first input circuit and the second input circuit affect an electrical quantity at a control terminal of the output transistor element.

11. the load circuit includes a current mirror circuit and an output transistor element; the current mirror circuit is coupled to the first input circuit, the second input circuit, and the output transistor element; the output transistor element controls the output of the amplifier assembly; 2. The amplifier assembly of claim 1.

12. the load circuit includes an output transistor element, a first load transistor element, and a second load transistor element; the first input circuit is coupled to a control terminal of the first load transistor element, a control terminal of the second load transistor element, and a channel of the first load transistor element; the second input circuit is coupled to a channel of the second load transistor element and to a control terminal of the output transistor element; a channel of the output transistor element coupled to an output of the amplifier assembly; 2. The amplifier assembly of claim 1.

13. the output transistor element, the first load transistor element, and / or the second load transistor element are pMOS transistor elements; and / or all transistor elements of the load circuit are pMOS transistor elements; 13. An amplifier assembly as claimed in claim 12.

14. the output transistor element, the first load transistor element, and / or the second load transistor element are standard MOS transistor elements; and / or all transistor elements of said load circuit are standard MOS transistor elements; 13. An amplifier assembly as claimed in claim 12.

15. The amplifier assembly of claim 1 , wherein an output of the amplifier assembly is coupled to the first signal input node or the second signal input node.

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