Ldo type voltage regulator circuit and semiconductor device

Abstract

To prevent an inappropriate output voltage from being supplied to a voltage control target circuit.SOLUTION: A comparison circuit 11a outputs the result of comparing a target voltage with an output voltage. A variable resistance circuit 11b has switching elements 11b1 to 11bn connected in parallel to one another and respectively having a first terminal to which an input voltage is applied and a second terminal to which an output voltage is applied. A control circuit 11c controls the number of switching elements 11b1 to 11bn that are turned on or off based on the result of the comparison. When priority is given to avoiding errors during low voltage of a voltage control target circuit 12, a timing change circuit 11d delays the timing of turning off a first switching element among the switching elements 11b1 to 11bn. When priority is given to avoiding exceeding the withstand voltage of the voltage control target circuit 12, the timing change circuit 11d delays the timing at which the first switching element is turned on.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an LDO (Low Drop-Out) voltage regulator circuit and a semiconductor device. [Background technology]

[0002] An LDO voltage regulator is sometimes used to regulate the power supply voltage applied to logic circuits in LSIs (Large Scale Integrated circuits). In order to maintain the power supply voltage (the output voltage of the LDO voltage regulator circuit) at a target voltage even if the operating current of the voltage-controlled circuit fluctuates, the LDO voltage regulator circuit adjusts the resistance value of the variable resistance circuit according to the difference between the output voltage and the target voltage. The resistance value of the variable resistance circuit can be adjusted by controlling the number of on and off switching elements.

[0003] In addition, in the past, in order to shorten the time during which voltage control is not possible due to the periodic reset operation of the AD (Analog to Digital) converter, an LDO type voltage adjustment circuit has been proposed that provides two AD converters and switches between them to operate alternately (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2021 / 256352 Summary of the Invention [Problem to be solved by the invention]

[0005] In an LDO voltage regulator circuit that includes multiple switching elements, delay differences may occur between multiple control signals input to each switching element. For example, even if a control circuit transitions the logic levels of multiple control signals at the same timing, the transition timing may differ due to delay differences when the transitions of the logic levels of each control signal reach each switching element. When delay differences occur between multiple control signals in this way, the number of switching elements that are turned on or off may become unintended, causing the output voltage to temporarily deviate excessively from the target voltage, and there is a possibility that an inappropriate output voltage may be supplied to the voltage-controlled circuit.

[0006] According to one aspect, the present invention has an object to provide an LDO type voltage regulator circuit and a semiconductor device capable of preventing an inappropriate output voltage from being supplied to a voltage controlled circuit. [Means for solving the problem]

[0007] In one embodiment, there is provided an LDO type voltage regulator circuit having: a comparison circuit that outputs a comparison result between a target voltage and an output voltage; a variable resistance circuit having a plurality of switching elements connected in parallel, each of which has a first terminal to which an input voltage is applied and a second terminal to which the output voltage is applied; a control circuit that controls the number of the plurality of switching elements that are turned on or off based on the comparison result; and a timing change circuit that delays the timing of turning off a first switching element of the plurality of switching elements when priority is given to avoiding errors during low voltage in a voltage-controlled circuit, and delays the timing of turning on the first switching element when priority is given to avoiding the voltage-controlled circuit from exceeding its withstand voltage.

[0008] Also, in one embodiment, a semiconductor device is provided. Effect of the Invention

[0009] According to one aspect, it is possible to prevent an inappropriate output voltage from being supplied to a voltage controlled circuit. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 illustrates an example of a semiconductor device according to a first embodiment. [Diagram 2] 11A and 11B are diagrams illustrating an example of a shift in transition timing caused by a delay difference between control signals. [Diagram 3] 11A and 11B are diagrams illustrating an example of changes over time in a load current, an output voltage, and a control signal when two control signals with no delay difference transition to the same logic level. [Figure 4] 1A and 1B are diagrams illustrating an example of changes over time in a load current, an output voltage, and a control signal when two control signals with a delay difference transition to the same logic level. [Diagram 5] 11A and 11B are diagrams illustrating an example of changes over time in a load current, an output voltage, and a control signal when two control signals with no delay difference transition to different logic levels. [Figure 6] 11A and 11B are diagrams illustrating an example of changes over time in a load current, an output voltage, and a control signal when two control signals with a delay difference transition to different logic levels. [Figure 7] FIG. 13 is a diagram showing an example of the time change in the number of pMOS turned on and the output voltage. [Figure 8] 11 is a diagram showing an example in which a timing change circuit delays the on / off timing of a switching element; [Figure 9] FIG. 2 is a diagram illustrating a first example of a timing change circuit. [Figure 10] FIG. 13 is a diagram illustrating a second example of a timing change circuit. [Figure 11] FIG. 13 is a diagram illustrating a third example of a timing change circuit. [Figure 12] 11A and 11B are diagrams illustrating an example of adjustment of an output voltage according to a comparison result between a target voltage and an output voltage. [Figure 13] FIG. 11 illustrates an example of an LDO voltage regulator circuit according to a second embodiment. [Figure 14] FIG. 1 illustrates an example of a TDC. [Figure 15] FIG. 2 is a diagram illustrating a first example of a timing change circuit having an adjustment unit. [Figure 16]FIG. 13 is a diagram illustrating a second example of a timing change circuit having an adjustment unit. [Figure 17] FIG. 13 is a diagram illustrating a third example of a timing change circuit having an adjustment section. [Figure 18] FIG. 1 is a diagram illustrating an LDO type voltage regulator circuit of a comparative example. [Figure 19] FIG. 1 illustrates an example of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the invention will be described with reference to the drawings. (First embodiment) FIG. 1 is a diagram illustrating an example of a semiconductor device according to a first embodiment.

[0012] A semiconductor device 10 according to the first embodiment includes an LDO voltage regulator circuit 11 and a voltage controlled circuit 12. The semiconductor device 10 is, for example, an LSI chip. The LDO voltage regulator circuit 11 regulates the output voltage so as to approach the target voltage based on a digital signal corresponding to the difference between the output voltage (VDD) and the target voltage.

[0013] The LDO voltage regulator circuit 11 of the first embodiment includes a comparator circuit 11a, a variable resistor circuit 11b, a control circuit 11c, and a timing change circuit 11d. The comparator circuit 11a outputs a comparison result between the target voltage and the output voltage of the LDO voltage regulator circuit 11. The output voltage is supplied to the voltage-controlled circuit 12 as a power supply voltage for the voltage-controlled circuit 12.

[0014] The variable resistance circuit 11b has switching elements 11b1, 11b2, 11b3, ..., 11bn connected in parallel to one another. An input voltage (Vin) is applied to first terminals of the switching elements 11b1 to 11bn, and an output voltage is applied to second terminals. A control signal is supplied to third terminals of the switching elements 11b1 to 11bn.

[0015] In the following description, p-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), which are relatively easy to control on and off, are used as the switching elements 11b1 to 11bn. In this case, the first terminal is a source terminal, the second terminal is a drain terminal, and the third terminal is a gate terminal.

[0016] It is desirable that the voltage adjustment can be performed appropriately even when the operating current of the voltage-controlled circuit 12 fluctuates greatly or when the difference between Vin and VDD is large. For this reason, it is desirable that the difference between the maximum and minimum resistance values ​​of the variable resistance circuit 11b is large. Also, it is desirable that the minimum adjustment unit of the resistance value is small so that VDD can be adjusted with high precision. In order to meet these requirements, it is desirable to use a large number of p-channel MOSFETs (hereinafter abbreviated as pMOS) with small size (gate width).

[0017] However, the method of controlling many small pMOS with different control signals (also called the thermometer code method) requires a large number of control lines, so it is preferable to use a method that uses the smallest unit pMOS and pMOSs whose size is a power of 2 of that unit (also called the binary code method) in order to perform adjustments with high precision and a wide adjustment range.

[0018] For example, if the size is 2 0 , 2 1 , 2 2 , 2 3 In the case of the variable resistor circuit 11b using four pMOS transistors, only four control lines are required. n The pMOS is the smallest unit of pMOS, n However, two parallel connected n A common control signal is supplied to the pMOSs.

[0019] The switching elements 11b1 to 11bn are not limited to pMOSs, and may be PNP bipolar transistors, n-channel MOSFETs, NPN bipolar transistors, or the like.

[0020] The control circuit 11c controls the number of ON or OFF switching elements 11b1-11bn based on the comparison result of the comparator circuit 11a. The control circuit 11c changes the number of ON or ON switching elements by transitioning the logical level of the control signal supplied to the switching elements 11b1-11bn from H (High) level to L (Low) level or from L level to H level.

[0021] The timing change circuit 11d delays the timing of turning off any of the switching elements 11b1-11bn when priority is given to avoiding errors during low voltage in the voltage-controlled circuit 12. In addition, the timing change circuit 11d delays the timing of turning on any of the switching elements 11b1-11bn when priority is given to avoiding the voltage-controlled circuit 12 from exceeding its withstand voltage.

[0022] An example of the operation of the semiconductor device 10 according to the first embodiment will now be described. When the operating current of the voltage-controlled circuit 12 increases, VDD decreases. When VDD becomes lower than the target voltage, the control circuit 11c increases the number of ON (or decreases the number of OFF) switching elements 11b1 to 11bn. This decreases the resistance value of the variable resistance circuit 11b, and increases the output voltage.

[0023] On the other hand, when the operating current of the voltage-controlled circuit 12 decreases, VDD increases. When VDD becomes higher than the target voltage, the control circuit 11c reduces the number of ON (or increases the number of OFF) switching elements 11b1 to 11bn. This increases the resistance value of the variable resistance circuit 11b, and decreases the output voltage.

[0024] However, delay differences may occur among a plurality of control signals input to the switching elements 11b1-11bn. For example, even if the control circuit 11c transitions the logic levels of a plurality of control signals at the same timing, when the transitions reach the switching elements 11b1-11bn, the transition timings may differ due to delay differences.

[0025] FIG. 2 is a diagram showing an example of a shift in transition timing caused by a delay difference between control signals. In the variable resistance circuit 11b shown in FIG. 2, switching element groups 15a1, 15a2, . . . , 15am, each of which is made up of four switching elements, are provided at a plurality (m) of locations in accordance with the locations of the voltage-controlled circuit 12 to which VDD is applied.

[0026] In the example of Fig. 2, a switching element group 15am corresponds to the switching elements 11b1-11bn (where n=4) in Fig. 1. The switching elements 11b1-11b4 are controlled to be on and off by four control signals CTRL[0]-CTRL[3]. To prevent attenuation due to the propagation of the control signals CTRL[0]-CTRL[3], buffer groups 15b1, 15b2, ..., 15bm, each consisting of four buffers provided on four control signal lines, are provided at m locations in the propagation direction of the control signals.

[0027] 2 shows an example in which the control circuit 11c changes the logic levels of the control signals CTRL[2] and CTRL[3] at the same timing (at the same time). In the absence of the timing change circuit 11d, the transition timing of the control signals CTRL[2] and CTRL[3] is shifted by the delay difference td when they reach the switching element group 15am of the final stage.

[0028] Such delay differences occur due to manufacturing variations in buffers and control signal lines, parasitic capacitance between control signal lines, etc. Due to the occurrence of delay differences, the following problems may occur in an LDO voltage regulator circuit that does not have the timing change circuit 11d (hereinafter referred to as a comparative example LDO voltage regulator circuit).

[0029] Fig. 3 is a diagram showing an example of the load current, output voltage, and control signal changes over time when two control signals with no delay difference transition to the same logic level. Fig. 4 is a diagram showing an example of the load current, output voltage, and control signal changes over time when two control signals with a delay difference transition to the same logic level. Fig. 5 is a diagram showing an example of the load current, output voltage, and control signal changes over time when two control signals with no delay difference transition to different logic levels. Fig. 6 is a diagram showing an example of the load current, output voltage, and control signal changes over time when two control signals with a delay difference transition to different logic levels.

[0030] 3 to 6 show examples using the binary code method. A control signal CTRL[0] controls the on / off of one pMOS, a control signal CTRL[1] controls the on / off of two pMOSs connected in parallel, and a control signal CTRL[2] controls the on / off of four pMOSs connected in parallel.

[0031] In FIG. 3, until timing t1, the logical levels of the control signals CTRL[1] and CTRL[2] are H level, the logical level of the control signal CTRL[0] is L level, and the number of ON pMOS is 1. When the load current increases (timing t1), the output voltage of the LDO voltage regulator circuit of the comparative example starts to drop. At this time, control is performed to increase the number of ON pMOS. In the example of FIG. 3, the logical levels of the control signals CTRL[1] and CTRL[2] transition from H level to L level (timing t2). As a result, the number of ON pMOS connected in parallel increases from 1 to 7, the resistance decreases, and the output voltage increases.

[0032] 4, the timing t2b when the logic level of the control signal CTRL[1] transitions from H level to L level is later than the timing t2a when the logic level of the control signal CTRL[2] transitions from H level to L level. In other words, a delay difference tda occurs between the transition timings of the control signals CTRL[1] and CTRL[2].

[0033] During the period from timing t2a to t2b, the logic level of the control signal CTRL[2] drops to the L level, but the logic level of the control signal CTRL[1] remains at the H level, so the number of pMOSs turned on is 5. The effect of increasing the output voltage is weaker than in the case shown in Figure 3, and the output voltage continues to fall until timing t2b.

[0034] In FIG. 5, until timing t10, the logic level of the control signal CTRL[2] is H level, the logic levels of the control signals CTRL[0] and CTRL[1] are L level, and the number of ON pMOS is 3. When the load current increases (timing t10), the output voltage of the LDO type voltage regulator circuit of the comparative example starts to drop. At this time, control is performed to increase the number of ON pMOS. In the example of FIG. 5, the logic level of the control signal CTRL[1] transitions from L level to H level, and the logic level of the control signal CTRL[2] transitions from H level to L level (timing t11). As a result, the number of ON pMOS connected in parallel increases from 3 to 5, the resistance decreases, and the output voltage increases.

[0035] 6, the timing t11b when the logic level of the control signal CTRL[2] transitions from H level to L level is later than the timing t11a when the logic level of the control signal CTRL[1] transitions from L level to H level. In other words, a delay difference tdb occurs in the transition timings of the control signals CTRL[1] and CTRL[2].

[0036] During the period from timing t11a to t11b, the logic level of the control signal CTRL[1] rises to H level, but the logic level of the control signal CTRL[2] remains at H level, so the number of pMOS turned on is 1. At this time, the output voltage is adjusted to further decrease, and the output voltage deviates excessively from the target voltage.

[0037] This problem becomes more pronounced as the number of bits (the number of control signals) increases in the binary code system. 7 is a diagram showing an example of the time change in the number of pMOS turned on and the output voltage. In FIG. 7, the horizontal axis represents time, and the vertical axis represents the output voltage. The number of pMOS turned on is represented by multiple bits (binary representation).

[0038] An example is shown in which, when the number of pMOSs on is 7 (0111 in binary representation) and the output voltage is lower than the target voltage, the number of pMOSs on is changed to 8 (1000 in binary representation) in order to increase the output voltage.

[0039] If the control signal corresponding to the lower three bits is delayed compared to the control signal corresponding to the most significant bit, the number of pMOSs turned on may temporarily become 15 (1111 in binary representation). In this case, the output voltage exceeds the target voltage, as shown in Figure 7.

[0040] If the control signal corresponding to the most significant bit is delayed more than the control signal corresponding to the three lowest bits, the number of pMOSs that are on may temporarily become 0 (0000 in binary representation). In this case, the output voltage drops further, as shown in Figure 7.

[0041] In this way, especially when the most significant bit is inverted, the output voltage may deviate excessively from the target voltage due to the delay difference between the control signals. The change in the number of pMOSs turned on due to the inversion of the Nth bit is twice the change in the number of pMOSs turned on due to the inversion of the least significant bit. N Because it is twice as much.

[0042] 7, if the output voltage is lower than the target voltage and drops further, an error (such as a setup error) may occur at low voltage in the voltage-controlled circuit 12. If the output voltage is higher than the target voltage and rises further, the voltage-controlled circuit 12 may exceed its withstand voltage.

[0043] The LDO voltage regulator circuit 11 of the first embodiment has a timing change circuit 11d in order to prevent an inappropriate output voltage from being supplied to the voltage-controlled circuit 12.

[0044] When priority is given to avoiding errors when the voltage control target circuit 12 is at a low voltage, the timing change circuit 11d delays the timing of turning off any of the switching elements 11b1 to 11bn.

[0045] Fig. 8 is a diagram showing an example in which the timing change circuit delays the on / off timing of the switching element. For comparison, the left side of Fig. 8 shows an example of the load current, output voltage, and control signal changes over time shown in Fig. 6.

[0046] As in Figure 6, the two control signals in Figure 8 transition to opposite logic levels: the logic level of the control signal CTRL[1] transitions from an L level to an H level, and the logic level of the control signal CTRL[2] transitions from an H level to an L level.

[0047] The control circuit 11c transitions the logic levels of the control signals CTRL[1] and CTRL[2] at the same timing (at the same time) as described above. However, a delay difference tdb may occur between the control signals CTRL[1] and CTRL[2] while the control signals CTRL[1] and CTRL[2] are propagating through the control signal line.

[0048] The timing change circuit 11d delays the timing of turning off the switching element controlled by the control signal CTRL[1] from timing t11a to timing t11c. That is, the timing change circuit 11d delays the timing at which the logic level of the control signal CTRL[1] rises from L level to H level. As a result, the delay difference tdc between the control signal CTRL[1] and the control signal CTRL[2] becomes smaller than the delay difference tdb that occurs when the timing change circuit 11d is not used. That is, the period during which the number of pMOS (switching element) turned on is 1 is shortened. As a result, as shown in FIG. 8, the output voltage drops less compared to the case without the timing change circuit 11d, and the output voltage is prevented from deviating excessively from the target voltage.

[0049] Depending on the delay amount caused by the timing change circuit 11d, the transition of the logic level of the control signal CTRL[1] may be slower than the transition of the logic level of the control signal CTRL[2]. In that case, the number of pMOS turned on will change from 3 to 7 to 5, so the output voltage will not drop excessively from the target voltage.

[0050] When priority is given to avoiding the voltage control target circuit 12 from exceeding its withstand voltage, the timing change circuit 11d delays the timing of turning on any of the switching elements 11b1-11bn. This prevents the number of switching elements 11b1-11bn turned on from increasing to an unintended number, or shortens the period during which the number increases to an unintended number. This prevents the output voltage from rising excessively with respect to the target voltage.

[0051] It is preferable to set the delay difference between the control signals to 0, but the above-mentioned effects can be obtained even if the delay difference is not set to 0. For this reason, in the LDO type voltage regulator circuit 11 of the first embodiment, it is not necessary to measure the delay difference (for example, the delay difference tda in FIG. 4, and the delay difference tdb in FIG. 6 and FIG. 8).

[0052] Next, an example of the timing change circuit 11d will be described. (Example of the timing change circuit according to the first embodiment) FIG. 9 is a diagram illustrating a first example of a timing change circuit.

[0053] 9 is implemented when priority is given to avoiding errors at low voltages in the voltage-controlled circuit 12 over avoiding voltage overload. For example, such a timing change circuit 11d1 is used for the voltage-controlled circuit 12 that has a margin of tolerance in terms of voltage.

[0054] The timing change circuit 11d1 includes flip-flops (hereinafter abbreviated as FF) 21 and 22, and an AND (logical product) circuit . FFs 21 and 22 have a data input terminal D, a clock input terminal CK, and an output terminal Q. One control signal ctrl among the multiple control signals output by the control circuit 11c is received through the data input terminal D of FF21 in synchronization with the clock signal CLK and held. The received control signal ctrl is output as an output signal from the output terminal Q of FF21. The output signal of FF21 is received through the data input terminal D of FF22 in synchronization with the clock signal CLK whose logical level is inverted and held. The received control signal ctrl is output as an output signal from the output terminal Q of FF22.

[0055] The AND circuit 23 outputs the logical product of the output signals of the FFs 21 and 22 as the control signal CTRL. When the control circuit 11c changes a pMOS (switching element) from on to off by the control signal ctrl, the logic level of the control signal ctrl transitions from L level to H level. When the logic level of the control signal ctrl is L level, the logic levels of the output signals of FF21 and FF22 are L level. Therefore, the logic level of the control signal CTRL output by the AND circuit 23 is also L level.

[0056] When the logic level of the control signal ctrl transitions to H level, the logic level of the output signal of FF21 also transitions to H level in synchronization with the clock signal CLK, but the logic level of the output signal of FF22 remains at L level. Therefore, the logic level of the control signal CTRL, which is the output of the AND circuit 23, does not change, and the pMOS to whose gate the control signal CTRL is input also remains on.

[0057] When a half-cycle period of the clock signal CLK elapses after the logical level of the output signal of FF21 transitions to the H level, the logical level of the output signal of FF22 transitions from the L level to the H level. As a result, the logical level of the control signal CTRL, which is the output signal of the AND circuit 23, also transitions from the L level to the H level, and the pMOS, the gate of which receives the control signal CTRL, is turned off.

[0058] When the control circuit 11c changes a pMOS from OFF to ON by the control signal ctrl, the logic level of the control signal ctrl transitions from H level to L level. When the logic level of the control signal ctrl is H level, the logic levels of the output signals of FF21 and FF22 are H level. Therefore, the logic level of the control signal CTRL output by the AND circuit 23 is also H level.

[0059] When the logic level of the control signal ctrl transitions to the L level, the logic level of the output signal of FF21 also transitions to the L level in synchronization with the clock signal CLK, and the logic level of the control signal CTRL, which is the output of the AND circuit 23, also transitions to the L level. As a result, the pMOS, the gate of which receives the control signal CTRL, is turned on.

[0060] According to the above-described timing change circuit 11d1, the timing at which the control signal CTRL turns off the pMOS input to its gate is delayed by a time equivalent to a half cycle of the clock signal CLK, but the timing at which the pMOS is turned on is not delayed.

[0061] Fig. 10 is a diagram showing a second example of a timing change circuit, in which the same elements as those shown in Fig. 9 are denoted by the same reference numerals. 10 is implemented when priority is given to avoiding an error at a low voltage in the voltage-controlled circuit 12. For example, such a timing change circuit 11d2 is used for the voltage-controlled circuit 12 in which no error occurs even at a relatively low voltage.

[0062] The timing change circuit 11d2 uses an OR (logical sum) circuit 24 instead of the AND circuit 23 of the timing change circuit 11d1 shown in Fig. 9. The OR circuit 24 outputs the logical sum of the output signals of FFs 21 and 22 as a control signal CTRL.

[0063] When the control circuit 11c changes a pMOS from OFF to ON by the control signal ctrl, the logic level of the control signal ctrl transitions from H level to L level. When the logic level of the control signal ctrl is H level, the logic levels of the output signals of FF21 and FF22 are H level. Therefore, the logic level of the control signal CTRL output by the OR circuit 24 is also H level.

[0064] When the logic level of the control signal ctrl transitions to the L level, the logic level of the output signal of FF21 also transitions to the L level in synchronization with the clock signal CLK, but the logic level of the output signal of FF22 remains at the H level. Therefore, the logic level of the control signal CTRL, which is the output of the OR circuit 24, does not change, and the pMOS to whose gate the control signal CTRL is input also remains off.

[0065] When a half-cycle period of the clock signal CLK elapses after the logical level of the output signal of FF21 transitions to the L level, the logical level of the output signal of FF22 transitions from the H level to the L level. As a result, the logical level of the control signal CTRL, which is the output signal of the OR circuit 24, also transitions from the H level to the L level, and the pMOS, to whose gate the control signal CTRL is input, turns on.

[0066] When the control circuit 11c changes a pMOS from on to off by the control signal ctrl, the logic level of the control signal ctrl transitions from L level to H level. When the logic level of the control signal ctrl is L level, the logic levels of the output signals of FF21 and FF22 are L level. Therefore, the logic level of the control signal CTRL output by the OR circuit 24 is also L level.

[0067] When the logic level of the control signal ctrl transitions to the H level, the logic level of the output signal of FF21 also transitions to the H level in synchronization with the clock signal CLK, and the logic level of the control signal CTRL, which is the output of the OR circuit 24, also transitions to the H level. As a result, the pMOS, the gate of which receives the control signal CTRL, is turned off.

[0068] In the timing change circuit 11d2 as described above, the timing at which the control signal CTRL turns on the pMOS input to its gate is delayed by a time equivalent to a half cycle of the clock signal CLK, but the timing at which the pMOS is turned off is not delayed.

[0069] Fig. 11 is a diagram showing a third example of a timing change circuit, in which the same elements as those shown in Figs. 9 and 10 are denoted by the same reference numerals. The timing change circuit 11d3 in Fig. 11 includes both the AND circuit 23 shown in Fig. 9 and the OR circuit 24 shown in Fig. 10. The timing change circuit 11d3 further includes a selection circuit 25.

[0070] The selection circuit 25 selects one of the output signal of the AND circuit 23 and the output signal of the OR circuit 24 according to the selection signal SEL, and outputs it as the control signal CTRL. The output signal of the comparison circuit 11a that compares the target voltage with VDD can be used as the selection signal SEL. When VDD is lower than the target voltage, the selection circuit 25 selects and outputs the output signal of the AND circuit 23. In this way, the timing change circuit 11d3 functions as the timing change circuit 11d1 for prioritizing error avoidance at low voltage shown in FIG. 9. In the case where VDD is higher than the target voltage, the selection circuit 25 selects and outputs the output signal of the OR circuit 24. In this way, the timing change circuit 11d3 functions as the timing change circuit 11d2 for prioritizing avoidance of exceeding the withstand voltage shown in FIG. 10.

[0071] Fig. 12 is a diagram showing an example of adjustment of the output voltage according to the result of comparison between the target voltage and the output voltage, in which the horizontal axis represents time and the vertical axis represents the output voltage. FIG. 12 shows an example of VDD adjustment by the LDO type voltage adjustment circuit 11 when the timing change circuit 11d3 shown in FIG. 11 is used.

[0072] When VDD is lower than the target voltage, avoiding errors at low voltage takes priority, and the timing to turn off the pMOS is delayed. This prevents the number of pMOS turned on from decreasing to an unintended number, or shortens the period during which the number decreases to an unintended number. This prevents the output voltage from dropping too far below the target voltage.

[0073] When VDD is higher than the target voltage, avoiding exceeding the breakdown voltage takes priority, and the timing to turn on the pMOS is delayed. This prevents the number of pMOS turned on from increasing to an unintended number, or shortens the period during which the number increases to an unintended number. This prevents the output voltage from rising excessively above the target voltage.

[0074] By using such a timing change circuit 11d3, it is possible to avoid both errors occurring during low voltage operation and exceeding the withstand voltage. As described above, the LDO voltage regulator circuit 11 of the first embodiment includes the comparator circuit 11a, the variable resistor circuit 11b, the control circuit 11c, and the timing change circuit 11d. The comparator circuit 11a outputs a comparison result between the target voltage and VDD. The variable resistor circuit 11b includes switching elements 11b1-11bn, each of which has a first terminal to which Vin is applied and a second terminal to which VDD is applied, and which are connected in parallel to each other. The control circuit 11c controls the number of switching elements 11b1-11bn that are turned on or off based on the comparison result of the comparator circuit 11a. The timing change circuit 11d delays the timing of turning off any of the switching elements 11b1-11bn when priority is given to avoiding errors during low voltage in the voltage-controlled circuit 12. The timing change circuit 11d delays the timing of turning on any of the switching elements 11b1-11bn when priority is given to avoiding the voltage-controlled circuit 12 from exceeding its withstand voltage.

[0075] As a result, when priority is given to avoiding errors at low voltages, the number of ON switching elements 11b1-11bn is prevented from decreasing to an unintended number, or the period during which the number decreases to an unintended number is shortened. Therefore, the output voltage is prevented from dropping excessively relative to the target voltage. Also, when priority is given to avoiding exceeding the withstand voltage, the number of ON switching elements 11b1-11bn is prevented from increasing to an unintended number, or the period during which the number increases to an unintended number is shortened. Therefore, the output voltage is prevented from rising excessively relative to the target voltage.

[0076] As described above, the LDO voltage regulator circuit 11 of the first embodiment can prevent an inappropriate output voltage from being supplied to the voltage-controlled circuit 12. (Second embodiment) Fig. 13 is a diagram illustrating an example of an LDO type voltage regulator circuit according to the second embodiment. In Fig. 13, the same elements as those illustrated in Fig. 1 or 2 are denoted by the same reference numerals.

[0077] In the LDO voltage regulator circuit 30 of the second embodiment, two control signal lines of a variable resistor circuit 30a are provided with timing change circuits 31 and 32. In the example of Fig. 13, the timing change circuit 31 is provided on the control signal line through which the control signal CTRL[3] propagates, and the timing change circuit 32 is provided on the control signal line through which the control signal CTRL[2] propagates.

[0078] The control circuit 11c is connected to one end of the control signal line on which the timing change circuits 31 and 32 are provided, and the switching element 11b3 or the switching element 11b4 is connected to the other end. The timing change circuit 31 is provided in the middle between one end and the other end of the control signal line that propagates the control signal CTRL[3]. The timing change circuit 32 is provided in the middle between one end and the other end of the control signal line that propagates the control signal CTRL[2].

[0079] The timing change circuits 31 and 32 delay the timing of turning on or off a switching element (for example, switching elements 11b3 and 11b4) connected downstream of the timing change circuits 31 and 32 on the control signal line.

[0080] For example, when priority is given to avoiding errors during low voltage in the voltage-controlled circuit 12, the timing change circuit 31 delays the timing of turning off the switching element 11b4. When priority is given to avoiding the voltage-controlled circuit 12 from exceeding its withstand voltage, the timing change circuit 31 delays the timing of turning on any of the switching elements 11b4.

[0081] In the binary code method, the control signals CTRL[3] and CTRL[2] are used to invert the upper two bits of the on-number of pMOSs. As described above, when the upper bits are inverted in particular, the output voltage and the target voltage may deviate excessively due to the delay difference between the control signals, so providing the timing change circuits 31 and 32 is highly effective. However, a timing change circuit may be provided in the control signal line that propagates the control signals CTRL[1] and CTRL[0] used to invert the lower two bits.

[0082] In the LDO voltage regulator circuit 30 of the second embodiment, the timing change circuits 31 and 32 have an adjustment unit that adjusts the amount of delay. The amount of delay is adjusted based on the measurement result of the delay difference between the control signals CTRL[3] and CTRL[2]. The delay difference can be measured, for example, by connecting a measurement circuit such as a TDC (Time to Digital Converter) to the LDO voltage regulator circuit 30. In the example of FIG. 13, a TDC 40 is connected to an end of the control signal line through which the control signals CTRL[3] and CTRL[2] propagate (the end opposite to the end to which the control circuit 11c is connected).

[0083] FIG. 14 is a diagram illustrating an example of a TDC. The TDC 40 has buffers 41a, 41b, 41c, 41d, 41e, 41f, and 41g, buffers 42a, 42b, 42c, and 42d, and FFs 43a, 43b, 43c, 43d, 43e, 43f, and 43g.

[0084] The buffers 41a to 41g delay the control signal CTRL[3]. The buffers 42a to 42d delay the control signal CTRL[2]. The output signal of the last buffer 42d among the buffers 42a to 42d is input to the clock input terminals CK of the FFs 43a to 43g.

[0085] FF43a captures the value of the control signal CTRL[3] delayed by the buffer 41a in synchronization with the rising timing of the output signal of the buffer 42d. FF43b captures the value of the control signal CTRL[3] delayed by the buffers 41a and 41b in synchronization with the rising timing of the output signal of the buffer 42d. FF43c captures the value of the control signal CTRL[3] delayed by the buffers 41a to 41c in synchronization with the rising timing of the output signal of the buffer 42d. FF43d captures the value of the control signal CTRL[3] delayed by the buffers 41a to 41d in synchronization with the rising timing of the output signal of the buffer 42d. FF43e captures the value of the control signal CTRL[3] delayed by the buffers 41a to 41e in synchronization with the rising timing of the output signal of the buffer 42d. FF43f captures the value of the control signal CTRL[3] delayed by the buffers 41a to 41f in synchronization with the rising timing of the output signal of the buffer 42d. The FF 43g captures the value of the control signal CTRL[3] delayed by the buffers 41a to 41g in synchronization with the rising edge of the output signal from the buffer 42d.

[0086] In the following, the value of the control signal CTRL[3] loaded into FF43a to 43g is 0 when the logical level of the control signal CTRL[3] is L level, and 1 when the logical level of the control signal CTRL[3] is H level. Therefore, the values ​​loaded into FF43a to 43g are represented by a 7-bit value [6:0]. In the following, the value of the control signal CTRL[3] loaded into FF43a is the most significant bit, and the value of the control signal CTRL[3] loaded into FF43g is the least significant bit.

[0087] 14 measures the delay difference between the control signals CTRL[3] and CTRL[2] from the difference in the rising timing of both control signals. When measuring the delay difference from the difference in the falling timing of both control signals, an inverter may be inserted before the buffer 41a and before the buffer 42a.

[0088] 14, the delay difference between the control signals CTRL[3] and CTRL[2] corresponds to how many buffer stages of delay. The values ​​stored in the FFs 43a to 43g are read out by a delay difference measurement control circuit (not shown) that is connected to the semiconductor device or in the semiconductor device.

[0089] When [6:0]=1111000 or 1110000, it can be considered that there is no delay difference between the control signals CTRL[3] and CTRL[2]. When [6:0]=1100000, it can be considered that the control signal CTRL[3] is delayed by one buffer stage compared to the control signal CTRL[2]. In other words, the delay difference in this case is the delay amount of one buffer stage. When [6:0]=1000000, it can be considered that the control signal CTRL[3] is delayed by two buffer stages compared to the control signal CTRL[2]. In other words, the delay difference in this case is the delay amount of two buffer stages. When [6:0]=1111100, it can be considered that the control signal CTRL[3] is earlier than the control signal CTRL[2] by one buffer stage. In other words, the delay difference in this case is the delay amount of one buffer stage. When [6:0]=1111110, the control signal CTRL[3] can be considered to be two buffer stages earlier than the control signal CTRL[2]. In other words, the delay difference in this case is the delay amount of two buffer stages.

[0090] (Example of Timing Change Circuit of Second Embodiment) An example of the timing change circuit 31 shown in FIG. 13 will be described below. FIG. 15 is a diagram showing a first example of a timing change circuit having an adjustment unit.

[0091] The timing change circuit 31a is implemented when avoiding errors at low voltages in the voltage-controlled circuit 12 is given priority over avoiding exceeding the withstand voltage. For example, such a timing change circuit 31a is used for the voltage-controlled circuit 12 that has a margin of withstand voltage.

[0092] The timing change circuit 31 a includes an adjustment section 50 and an AND circuit 51 . The adjustment unit 50 includes buffers 50a1, 50a2, 50a3, 50a4, 50a5, and 50a6, and a selection circuit 50b.

[0093] The buffer 50a1 delays the control signal CTRL[3] by one buffer stage before outputting it. The serially connected buffers 50a2 and 50a3 delay the control signal CTRL[3] by two buffer stages before outputting it. The serially connected buffers 50a4 to 50a6 delay the control signal CTRL[3] by three buffer stages before outputting it.

[0094] The selection circuit 50b inputs the control signal CTRL[3], the control signal CTRL[3] delayed by one buffer stage, the control signal CTRL[3] delayed by two buffer stages, and the control signal CTRL[3] delayed by three buffer stages. The selection circuit 50b selects and outputs one of the four input signals based on the selection signal TAP[1:0]. The selection signal TAP[1:0] is input by, for example, a delay difference measurement control circuit (not shown). The delay difference measurement control circuit determines the value of the selection signal TAP[1:0] based on the measurement result of the delay difference between the control signals CTRL[3] and CTRL[2].

[0095] For example, if it is measured that there is no delay difference, TAP[1:0]=00, and if it is measured that there is a delay difference of one buffer stage, TAP[1:0]=01. If it is measured that there is a delay difference of two buffer stages, TAP[1:0]=10, and if it is measured that there is a delay difference of three buffer stages, TAP[1:0]=11. If TAP[1:0]=00, the selection circuit 50b selects and outputs the control signal CTRL[3], and if TAP[1:0]=01, the selection circuit 50b selects and outputs the control signal CTRL[3] delayed by one buffer stage. If TAP[1:0]=10, the selection circuit 50b selects and outputs the control signal CTRL[3] delayed by two buffer stages, and if TAP[1:0]=11, the selection circuit 50b selects and outputs the control signal CTRL[3] delayed by three buffer stages.

[0096] Note that a delay difference measurement control circuit (not shown) may determine the value of TAP[1:0] so that no delay difference is measured while measuring the delay difference. The AND circuit 51 outputs the logical product of the control signal CTRL[3] and the output signal of the selection circuit 50b.

[0097] When a pMOS (switching element) connected to a control signal line that propagates the control signal CTRL[3] is changed from on to off, the logic level of the control signal CTRL[3] transitions from L level to H level. When the logic level of the control signal CTRL[3] is L level, the logic level of the output signal of the AND circuit 51 is also L level.

[0098] When the logic level of the control signal CTRL[3] transitions to the H level, the following operation is performed according to the output signal of the selection circuit 50b. When the selection circuit 50b outputs the control signal CTRL[3], the logic level of the output signal of the AND circuit 51 also transitions to the H level. When the selection circuit 50b outputs the control signal CTRL[3] delayed by one buffer stage, the logic level of the output signal of the AND circuit 51 transitions to the H level after one buffer stage delay from when the control signal CTRL[3] transitions to the H level. When the selection circuit 50b outputs the control signal CTRL[3] delayed by two buffer stages, the logic level of the output signal of the AND circuit 51 transitions to the H level after two buffer stages delay from when the control signal CTRL[3] transitions to the H level. When the selection circuit 50b outputs the control signal CTRL[3] delayed by three buffer stages, the logic level of the output signal of the AND circuit 51 transitions to the H level after three buffer stages delay from when the control signal CTRL[3] transitions to the H level.

[0099] When the pMOS connected to the control signal line that propagates the control signal CTRL[3] is changed from OFF to ON, the logic level of the control signal CTRL[3] transitions from H level to L level. When the logic level of the control signal CTRL[3] is H level, the logic level of the output signal of the selection circuit 50b is H level. Therefore, the logic level of the output signal of the AND circuit 51 is also H level.

[0100] When the logic level of the control signal CTRL[3] transitions to the L level, the logic level of the output signal of the AND circuit 51 also transitions to the L level, regardless of the logic level of the output signal of the selection circuit 50b.

[0101] In the timing change circuit 31a as described above, the delay amount of the timing to turn off the pMOS can be selected from among 0 and 1 to 3 stages of buffers. The timing to turn on the pMOS is not delayed.

[0102] Fig. 16 is a diagram showing a second example of a timing change circuit having an adjustment unit, in which the same elements as those shown in Fig. 15 are denoted by the same reference numerals. 16 is implemented when priority is given to avoiding an error at a low voltage in the voltage-controlled circuit 12. For example, such a timing change circuit 31b is used for the voltage-controlled circuit 12 in which no error occurs even at a relatively low voltage.

[0103] The timing change circuit 31b uses an OR circuit 52 instead of the AND circuit 51 of the timing change circuit 31a shown in Fig. 15. The OR circuit 52 outputs the logical sum of the control signal CTRL[3] and the output signal of the selection circuit 50b.

[0104] When a pMOS (switching element) connected to a control signal line that propagates the control signal CTRL[3] is changed from OFF to ON, the logic level of the control signal CTRL[3] transitions from H level to L level. When the logic level of the control signal CTRL[3] is H level, the logic level of the output signal of the OR circuit 52 is also H level.

[0105] When the logic level of the control signal CTRL[3] transitions to the L level, the following operation is performed according to the output signal of the selection circuit 50b. When the selection circuit 50b outputs the control signal CTRL[3], the logic level of the output signal of the OR circuit 52 also transitions to the L level. When the selection circuit 50b outputs the control signal CTRL[3] delayed by one buffer stage, the logic level of the output signal of the OR circuit 52 transitions to the L level after one buffer stage delay from when the control signal CTRL[3] transitions to the L level. When the selection circuit 50b outputs the control signal CTRL[3] delayed by two buffer stages, the logic level of the output signal of the OR circuit 52 transitions to the L level after two buffer stages delay from when the control signal CTRL[3] transitions to the L level. When the selection circuit 50b outputs the control signal CTRL[3] delayed by three buffer stages, the logic level of the output signal of the OR circuit 52 transitions to the L level after three buffer stages delay from when the control signal CTRL[3] transitions to the L level.

[0106] When the pMOS connected to the control signal line that propagates the control signal CTRL[3] is changed from on to off, the logic level of the control signal CTRL[3] transitions from L level to H level. When the logic level of the control signal CTRL[3] is L level, the logic level of the output signal of the selection circuit 50b is L level. Therefore, the logic level of the output signal of the OR circuit 52 is also L level.

[0107] When the logic level of the control signal CTRL[3] transitions to the H level, the logic level of the output signal of the OR circuit 52 also transitions to the H level, regardless of the logic level of the output signal of the selection circuit 50b.

[0108] In the timing change circuit 31b as described above, the delay amount of the timing to turn on the pMOS can be selected from among 0 and 1 to 3 stages of buffers. The timing to turn off the pMOS is not delayed.

[0109] Fig. 17 is a diagram showing a third example of a timing change circuit having an adjustment unit, in which the same elements as those shown in Figs. 15 and 16 are denoted by the same reference numerals. The timing change circuit 31c in Fig. 17 includes both the AND circuit 51 shown in Fig. 15 and the OR circuit 52 shown in Fig. 16. The timing change circuit 31c further includes a selection circuit 53.

[0110] The selection circuit 53 selects and outputs one of the output signal of the AND circuit 51 and the output signal of the OR circuit 52 according to the selection signal SEL. The output signal of the comparison circuit 11a that compares the target voltage with VDD can be used as the selection signal SEL. When VDD is lower than the target voltage, the selection circuit 53 selects and outputs the output signal of the AND circuit 51. In this way, the timing change circuit 31c functions as the timing change circuit 31a for prioritizing error avoidance at low voltage shown in FIG. 15. In the case where VDD is higher than the target voltage, the selection circuit 53 selects and outputs the output signal of the OR circuit 52. In this way, the timing change circuit 31c functions as the timing change circuit 31b for prioritizing avoidance of exceeding the withstand voltage shown in FIG. 16.

[0111] 15 to 17, the delay amount can be selected from four types, i.e., 0 and 1 to 3 stages of buffers, but is not limited to this. For example, the delay amount may be selected from 0 and 1+K types, i.e., 1 to K stages of buffers.

[0112] Although three examples of the timing change circuit 31 shown in FIG. 13 have been shown above, the timing change circuit 32 shown in FIG. 13 can also be realized by a circuit configuration similar to that of the timing change circuits 31a to 31c in FIGS. 15 to 17.

[0113] In the LDO voltage regulator circuit 30 of the second embodiment as described above, the timing change circuits 31 and 32 can adjust the delay amount, so that the delay difference between the control signals CTRL[3] and CTRL[2] can be made smaller. As a result, when priority is given to avoiding errors at low voltages, the number of switching elements turned on is prevented from decreasing to an unintended number, or the period during which the number of switching elements turned on is reduced to an unintended number is made shorter. Also, when priority is given to avoiding exceeding the withstand voltage, the number of switching elements turned on is prevented from increasing to an unintended number, or the period during which the number of switching elements turned on is reduced to an unintended number is made shorter.

[0114] In addition, the timing change circuits 31 and 32 are provided in the middle between one end and the other end of the control signal line, so that in a location close to the control circuit 11c where the delay difference between the control signals is small, the timing change circuits 31 and 32 do not add delay, and it is possible to prevent the delay difference from widening.

[0115] (Comparative Example) Fig. 18 is a diagram showing an LDO voltage regulator circuit of a comparative example, in which the same elements as those shown in Fig. 2 are denoted by the same reference numerals.

[0116] In the variable resistance circuit 30b of the LDO type voltage regulator circuit 60, FF groups 61a1, 61a2, ..., 61am are provided at m locations in the propagation direction of the control signal of the control signal line. Each of the FF groups 61a1 to 61am has four FFs provided on four control signal lines.

[0117] By providing such FF groups 61a1-61am, the delay difference between the control signals CTRL[0]-CTRL[3] due to their propagation can be eliminated. However, the distribution of the clock signal and the arrangement of the FFs may lead to an increase in power consumption, an increase in area, and an increase in delay time.

[0118] In contrast, according to the LDO voltage regulator circuits 11 and 30 of the first and second embodiments, the timing change circuits 11d, 31, and 32 only need to be provided at one location in the propagation direction of the control signal, thereby suppressing increases in power consumption, area, and delay time.

[0119] (Example of semiconductor device) FIG. 19 is a diagram illustrating an example of a semiconductor device. A semiconductor device 70 in FIG. 19 includes LDO type voltage adjustment circuits (simply referred to as "LDO" in FIG. 19) 71a1, 71a2, and 71a3, and voltage controlled circuits 71b1, 71b2, and 71b3.

[0120] The LDO voltage adjustment circuits 71a1 to 71a3 output output voltages (VDD1, VDD2, VDD3) adjusted to approach different target voltages. VDD1 is supplied as a power supply voltage to the voltage-controlled circuit 71b1, VDD2 to the voltage-controlled circuit 71b2, and VDD3 to the voltage-controlled circuit 71b3.

[0121] The LDO voltage regulator circuits 11 and 30 according to the first and second embodiments can be applied to each of the LDO voltage regulator circuits 71a1 to 71a3. According to such a semiconductor device 70, it is possible to adjust the power supply voltage appropriately for each of the voltage control target circuits 71b1 to 71b3.

[0122] The number of LDO voltage regulator circuits is not limited to three. While one aspect of the LDO type voltage regulator circuit and semiconductor device of the present invention has been described above based on the embodiment, this is merely an example and the present invention is not limited to the above description. [Explanation of symbols]

[0123] 10 Semiconductor device 11 LDO voltage regulator 11a Comparison circuit 11b Variable resistor circuit 11b1~11bn Switching elements 11c Control circuit 11d Timing change circuit 12 Voltage controlled circuits

Claims

1. a comparison circuit that outputs a comparison result between the target voltage and the output voltage; a variable resistance circuit including a first terminal to which an input voltage is applied and a second terminal to which the output voltage is applied, the variable resistance circuit having a plurality of switching elements connected in parallel with each other; a control circuit for controlling the number of the switching elements to be turned on or off based on the comparison result; a timing change circuit that delays a timing for turning off a first switching element among the plurality of switching elements when priority is given to avoiding an error when the voltage control target circuit is at a low voltage, and that delays a timing for turning on the first switching element when priority is given to avoiding an overvoltage of the voltage control target circuit; An LDO type voltage regulator circuit having

2. The timing change circuit includes: When the output voltage is higher than the target voltage, giving priority to avoiding an excess of a withstand voltage; When the output voltage is lower than the target voltage, priority is given to avoiding errors during low voltage.

2. The LDO voltage regulator circuit of claim 1.

3. 2. The LDO type voltage regulator circuit according to claim 1, wherein the timing change circuit has an adjustment section that adjusts an amount of delay.

4. the adjustment unit adjusts the delay amount based on a measurement result of a delay difference between a first control signal supplied by the control circuit to the first switching element and a second control signal supplied by the control circuit to a second switching element of the plurality of switching elements; 4. The LDO voltage regulator circuit of claim 3.

5. the control circuit is connected to a first end of a control signal line that propagates a first control signal output from the control circuit to the first switching element; the first switching element is connected to a second end of the control signal line, 2. The LDO voltage regulator circuit according to claim 1, wherein the timing change circuit is provided in an intermediate portion between the first end and the second end of the control signal line.

6. 2. The LDO type voltage regulator circuit according to claim 1, wherein the timing change circuit delays a transition of a logic level of a control signal that inverts one of the upper bits among a plurality of bits representing the number of ON states of the plurality of switching elements, thereby delaying a timing of turning off or on the first switching element.

7. A voltage controlled circuit; an LDO type voltage regulator circuit that regulates a power supply voltage of the voltage control target circuit, The LDO type voltage regulator circuit includes: a comparison circuit that outputs a comparison result between a target voltage and an output voltage that is the power supply voltage; a variable resistance circuit including a first terminal to which an input voltage is applied and a second terminal to which the output voltage is applied, the variable resistance circuit having a plurality of switching elements connected in parallel with each other; a control circuit for controlling the number of the switching elements to be turned on or off based on the comparison result; a timing change circuit that delays a timing for turning off a first switching element among the plurality of switching elements when priority is given to avoiding an error during a low voltage of the voltage-controlled circuit, and that delays a timing for turning on the first switching element when priority is given to avoiding an overvoltage of the voltage-controlled circuit; A semiconductor device having the above structure.

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