An interface resistance calibration circuit

Abstract

The present invention provides an interface resistor calibration circuit, which includes a current mirror circuit. Two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage, and output to an interface resistor circuit to generate a calibration voltage. Multiple resistor branches are connected in parallel in the interface resistor circuit. The reference voltage and the calibration voltage are connected to a comparator for comparison, and the comparison result is output to control the interface resistor circuit to change the resistance value. The comparator sets a first switch between the connected reference voltage and the connected calibration voltage, and before the system starts resistance calibration, controls the first switch to be closed, and the comparator outputs an initial comparison result. Based on the initial comparison result, after the resistance calibration starts, when the comparison result output by the comparator jumps, the resistance value of the interface resistor circuit is selected. The present invention can effectively improve the accuracy of resistance calibration.

Description

Technical Field

[0001] The invention belongs to the technical field of resistance calibration, and in particular relates to an interface resistance calibration circuit. Background Art

[0002] An interface resistor calibration circuit is an electronic system used to dynamically adjust or compensate for resistance values ​​in interface circuits. This system aims to address resistance mismatch problems caused by environmental changes, aging, or process deviations, thereby ensuring signal integrity, improving measurement accuracy, or optimizing system performance.

[0003] The interface resistance calibration circuit in the prior art generally includes a comparator, a reference voltage, and a calibration voltage for the resistance circuit. The comparator compares the reference voltage with the calibration voltage. When the reference voltage and the calibration voltage meet the set ratio, the comparator jumps, indicating that the comparison process is completed. At this time, the resistance value in the resistance circuit is the required calibrated resistance value.

[0004] Comparators are commonly used components in electronic circuits, primarily for comparing two voltages or currents. In practical applications, comparator noise is unavoidable and can affect system performance. A comparator's offset voltage refers to a fixed voltage deviation at the comparator's input when the input is zero. This deviation affects the comparator's output. Specifically, comparator offset voltage can be divided into input offset voltage and output offset voltage. A comparator's offset voltage can be greater than or less than zero. A comparator offset voltage greater than zero indicates a high output when the inputs are connected to the same common-mode voltage. Alternatively, a voltage V0 with a greater negative voltage than the positive voltage (theoretically, the output should be low) is input, but the output remains high when V0 is less than the comparator offset voltage. This means that a comparator offset voltage greater than zero contributes a positive equivalent resistance to the resistor being calibrated.

[0005] The equivalent resistance contributed by the comparator offset voltage can be positive or negative. If added to the inherent error, this can result in either error superposition or error cancellation. Error superposition reduces the accuracy of the calibration resistor, so it's necessary to improve the interface resistor calibration circuit to enhance resistance calibration accuracy. Summary of the Invention

[0006] The present invention provides an interface resistance calibration circuit, which reduces the extra error caused by the offset voltage of the comparator and improves the resistance calibration accuracy.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] In order to achieve one or part or all of the above-mentioned purposes or other purposes, a technical solution of the present invention provides 1. an interface resistance calibration circuit, wherein the interface resistance calibration circuit includes a current mirror circuit, wherein the two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage, and output to an interface resistance circuit to generate a calibration voltage, wherein multiple resistance branches are connected in parallel in the interface resistance circuit, the reference voltage and the calibration voltage are connected to a comparator for comparison, and the comparison result is output to control the interface resistance circuit to change the resistance value; the comparator sets a first switch between the connected reference voltage and the connected calibration voltage, and before the system starts resistance calibration, controls the first switch to be closed, and the comparator outputs an initial comparison result; based on the initial comparison result, after the resistance calibration starts, when the comparison result output by the comparator jumps, the resistance value of the connected interface resistance circuit is selected.

[0009] The interface resistor circuit includes multiple parallel resistor branches, each of which is provided with a second switch and a MOSFET; the second switch is closed before the resistance calibration starts; after the resistance calibration starts, the comparator outputs a comparison result, and the gate of the MOSFET on the parallel resistor branch is connected to the resistance selection signal, and the resistance selection signal is changed according to the comparison result of the comparator to perform the resistance value traversal operation of the interface resistor circuit.

[0010] The resistance selection signal is a multi-bit binary selection signal, and each bit of the binary selection signal controls the conduction and opening of the corresponding resistance branch; the resistance selection signal is based on the comparison result of the comparator, and assigns a value to each bit of the signal in sequence according to the resistance traversal order, thereby controlling the increase or decrease in the number of branch resistors incorporated in the interface resistance circuit; when the comparison result of the comparator jumps, the comparison process ends.

[0011] The calibration voltage is connected to the negative electrode of the comparator. When the resistance value of the interface resistance circuit starts to traverse from high to low; if the initial comparison result output by the comparator is high, the resistance value of the interface resistance circuit corresponding to the current resistance selection signal is the calibration resistance result; if the initial comparison result output by the comparator is low, the resistance value of the interface resistance circuit corresponding to the previous resistance selection signal is the calibration resistance result.

[0012] When the resistance value of the interface resistance circuit starts to traverse from low to high; if the initial comparison result output by the comparator is low, the resistance value of the interface resistance circuit corresponding to the current resistance selection signal is the calibration resistance result; if the initial comparison result output by the comparator is high, the resistance value of the interface resistance circuit corresponding to the previous resistance selection signal is the calibration resistance result.

[0013] The first switch connects both input terminals of the comparator to the reference voltage before the interface resistance circuit starts to be calibrated. The initial comparison result output by the comparator is used to characterize the equivalent internal resistance of the comparator.

[0014] A third switch is provided between the current mirror circuit and the interface resistance calibration circuit; the first switch is controlled by a comparator initialization control signal, and the second switch and the third switch are controlled by a switch control signal; the control signals of the first switch, the second switch and the third switch are generated by a signal control circuit; the signal control circuit includes a plurality of delay circuits and an inverting circuit, and after an external enable signal is input into the signal control circuit, a switch control signal is obtained after delay processing, and the switch control signal is processed by delay processing and inverting processing to obtain a comparator initialization control signal, and the comparator initialization control signal is processed by delay processing and inverting processing to obtain a system working signal; when the system working signal is pulled high, the system starts to work normally.

[0015] After the comparator outputs the initial comparison result, the initial comparison result is saved. After the interface resistance circuit is calibrated, the resistance selection signal is selected based on the initial comparison result, thereby selecting the resistance value of the interface resistance circuit.

[0016] The initial comparison result is stored in the D input terminal of the D flip-flop.

[0017] A switch control signal is input to a clock signal input terminal of the D flip-flop, and the initial comparison result is input to a D input terminal of the D flip-flop.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. Before calibrating the resistance circuit, the present invention connects both ends of the comparator to the reference voltage, and outputs an initial comparison result through the comparator to characterize the offset voltage equivalent internal resistance when the calibration voltage is compared with the reference voltage, and selects the number of resistors connected to the final resistance circuit based on the output initial comparison result to improve the comparison accuracy and reduce errors.

[0019] 2. The present invention generates multiple switch control signals through a signal control circuit to realize the offset voltage equivalent internal resistance test and comparison result output of the resistance calibration circuit before calibration, and saves and outputs the initial comparison result through a D trigger. The circuit has a simple structure and will not excessively increase the area overhead of the interface resistance calibration circuit, while being able to efficiently output the comparison result.

[0020] In order to make the above and other objects, features and advantages of the present invention more clearly understood, preferred embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is a schematic diagram of the interface resistance calibration circuit of the present invention.

[0023] Figure 2 It is a schematic diagram of the signal control circuit and the timing control circuit of the present invention. DETAILED DESCRIPTION

[0024] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0025] Example 1

[0026] Embodiment 1 provides an interface resistor calibration circuit, which includes a current mirror circuit, wherein two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage, and output to an interface resistor circuit to generate a calibration voltage. Multiple resistor branches are connected in parallel in the interface resistor circuit, and the reference voltage and the calibration voltage are connected to a comparator for comparison, and the comparison result is output to control the interface resistor circuit to change the resistance value; the comparator sets a first switch between the connected reference voltage and the connected calibration voltage, and before the system starts resistance calibration, controls the first switch to be closed, and the comparator outputs an initial comparison result; based on the initial comparison result, after the resistance calibration starts, when the comparison result output by the comparator jumps, the resistance value of the connected interface resistor circuit is selected.

[0027] In the first embodiment, the same voltage is simultaneously input to the input terminals of the comparator before resistance calibration, and an initial comparison result is output. The initial comparison result can be used to characterize the equivalent internal resistance of the comparator offset voltage. Based on the characterized equivalent internal resistance of the comparator offset voltage, the resistance value of the access interface resistance circuit is selected.

[0028] The following is combined with Figure 1 The interface resistance calibration circuit of the present invention is explained in detail.

[0029] like Figure 1As shown, the interface resistance calibration circuit of the first embodiment includes a current mirror circuit and an interface resistance circuit, wherein the current mirror circuit includes two output branches, one of which is connected to an external standard resistor rext to generate a reference voltage compA, and the other output branch is connected to an external interface resistance circuit to generate a calibration voltage compB. The generated reference voltage compA is input into a differential amplifier together with the standard voltage cb_vref for operation, and the operation result is input into the gates of the two transistor circuits P5 and P6 in the current mirror circuit. The differential amplifier adjusts the gate outputs of the transistor circuits P5 and P6 until the reference voltage compA and the standard voltage cb_vref are the same. At the same time, the mirror ratio of the current mirror circuit can be set as needed. Different setting ratios can be used to adjust the resistance values ​​of the standard resistor rext and the interface resistance circuit to be calibrated, so that the reference voltage compA is consistent with the calibration voltage compB. The current ratio generated by the current mirror circuit is a conventional technology in the field, and this application will not be described in detail here.

[0030] See also Figure 1 The interface resistance circuit includes multiple parallel resistance branches, each resistance branch includes a MOSFET circuit (P0, P1, P2, P3, P4), a resistor (S3, S6, S12, S24, S48) and a second switch k2. The second switch k2 can be a transmission tube, and the second switch k2 is controlled to open and close by the switch control signal en1. Each resistance branch connected to the interface resistance circuit in turn will change the total resistance value of the interface resistance circuit.

[0031] When the switch control signal en1 is pulled high, the second switch k2 is closed, and the resistance branch of the interface resistance circuit is connected. At this time, the connected resistance branch is controlled by the MOSFET circuit (P0, P1, P2, P3, P4).

[0032] When performing resistance calibration, it is necessary to control the number of resistor branches in the interface resistor circuit based on the resistance selection signal. The resistance selection signal is a binary signal that is connected to the gate of the MOSFET circuit to perform the resistance traversal operation. Specifically, when the resistance selection signal is set to "1", the MOSFET circuit is turned on, and the resistance branch where the MOSFET is located is connected to the interface resistor circuit. Figure 1 For example, Figure 1The interface resistor circuit in the example has five resistor branches. When traversing the resistance from high to low, the first resistor is initially connected, and the interface resistor circuit has the highest resistance value. The resistance selection signal is then "00001." Starting from the lowest bit, signals "0" are then set to "1." For example, when the first and second resistor branches are connected, the resistance selection signal is "00011." When traversing the resistance from low to high, all resistor branches are initially connected to the interface resistor circuit, and the circuit selection signal is "11111." During traversal, the resistance selection signals are gradually set to "0," starting from the highest bit, causing the resistance value of the interface resistor circuit to gradually increase.

[0033] Reference voltage compA and calibration voltage compB are input to a comparator for comparison. Calibration voltage compB is input to the negative terminal of the comparator. By comparing the ratio of reference voltage compA to calibration voltage compB, the comparator outputs a transition when the ratio matches a preset ratio. (For example, with a current mirror current ratio of 1:1 and resistance values ​​traversing from high to low, the initial calibration voltage compB is higher than the reference voltage compA. When the calibration voltage compB falls below the reference voltage compA, the comparator outputs a transition.) This indicates that the comparison result meets expectations, and the comparison process ends. If the comparator outputs a transition, the number of resistor branches connected to the interface resistor circuit is adjusted using the D resistor selection signal (SW<0,4>) input to the gate of the MOSFET circuit until the comparator trips. Since the total resistance of the parallel resistance circuit does not change regularly after each resistor is connected, the resistance value in each resistance branch can be designed so that when the interface resistance circuit traverses the resistance value, the total resistance value of the interface resistance circuit changes regularly after each resistance branch is connected or a connected resistance branch is cancelled, and each equally changed resistance value is called a single resistance calibration step value.

[0034] Ideally, the resistance value of the interface resistor circuit when a comparator signal jumps is the calibrated resistance value. Because the comparator has an offset voltage (the offset voltage contributes an equivalent resistance, which can be positive or negative. When the comparison result is incorrectly superimposed, it can affect the resistance comparison), to mitigate the impact of the comparator's offset voltage on the comparison result, the solution in Embodiment 1 provides a first switch k1 at both input terminals of the comparator, controlled by a comparator initialization control signal enn. Before calibrating the interface resistor circuit, the comparator is initialized by connecting both input terminals to the reference voltage compA (because the reference voltage compA must ultimately equal the standard voltage cb_vref for the current mirror circuit to output a stable value, this is equivalent to connecting both terminals of the comparator to the standard voltage cb_vref). The initial comparison result comp_out_vdd is used to represent the comparator's offset voltage (i.e., the equivalent resistance contributed by the comparator's offset voltage). Here, both input terminals are connected to the reference voltage compA to characterize the offset voltage of the comparator. This is also because the calibration voltage compB needs to be compared with the reference voltage compA in the end. At this time, the comparator is initialized, and the comparator input is all the reference voltage compA. The comparison result of its output is used for calibration by comparing the voltage with the reference voltage compA.

[0035] In order to facilitate characterization of the offset voltage of the comparator, a third switch is further provided between the current mirror circuit and the interface resistor circuit. The third switch is controlled to be opened and closed by a switch control signal en1.

[0036] Embodiment 1 selects the resistance value of the interface resistance circuit based on the initial comparison result, and the specific selection method is as follows: the calibration voltage is connected to the negative pole of the comparator, when the resistance value of the interface resistance circuit starts to traverse from high to low; if the initial comparison result output by the comparator is high, then the resistance value of the interface resistance circuit corresponding to the current resistance selection signal is the calibration resistance result; if the initial comparison result output by the comparator is low, then the resistance value of the interface resistance circuit corresponding to the previous resistance selection signal is the calibration resistance result.

[0037] The reasons are as follows: A high initial comparator output result indicates that the offset voltage is greater than zero (equivalent to the offset voltage contributing an equivalent resistance greater than zero). When the comparator output jumps, if the resistor connected to compB uses the previous resistance value (the resistance value corresponding to the previous resistor selection signal), the actual resistance of compB will be greater (the offset voltage's equivalent resistance value is added). Therefore, the current resistance value should be used to avoid further error. A low initial comparator output result indicates that the offset voltage is less than zero (equivalent to the offset voltage contributing an equivalent resistance less than zero). When the comparator output jumps, the resistor connected to compB is not only smaller than the resistor connected to compA, but also smaller by the offset voltage's equivalent resistance (the equivalent resistance is negative; adding the offset voltage is equivalent to subtracting the equivalent resistance). Therefore, the resistor corresponding to the previous resistance value (the previous resistor selection signal) should be used to offset the offset voltage error.

[0038] When the resistance values ​​of the interface resistor circuit begin to traverse from low to high, if the initial comparison result output by the comparator is low, the resistance value of the interface resistor circuit corresponding to the current resistance selection signal is the calibration resistance result. If the initial comparison result output by the comparator is high, the resistance value of the interface resistor circuit corresponding to the previous resistance selection signal is the calibration resistance result. When the resistance values ​​begin to traverse from low to high, the selection of the resistance selection signal is exactly the opposite of the above resistance value traversal from high to low. The specific reasons are similar to those above and will not be explained in detail here.

[0039] To facilitate storage of the initial comparison result comp_out_vdd, Example 1 further provides a D flip-flop. The output initial comparison result comp_out_vdd is input to the D input terminal of the D flip-flop, and a switch control signal en1 is input to the clock interface of the D flip-flop. The D flip-flop collects the input initial comparison result comp_out_vdd on the rising edge of the input clock signal and outputs a sel signal. The output sel signal can be used to represent the selection of the resistor selection signal, thereby selecting the resistance value of the interface resistor circuit. For example, the example of resistors being connected to the interface resistor circuit step by step (the total resistance of the interface resistor circuit is traversed from high to low) indicates that the current total resistance of the interface resistor circuit is used. If sel is high, it indicates that the total resistance of the interface resistor circuit in the previous level is used. If sel is low, the total resistance of the interface resistor circuit in the previous level (the resistance value corresponding to the previous resistor selection signal) is used.

[0040] In order to facilitate the generation of switch control signal en1, comparator initialization control signal enn and system operation signal enok, a signal control circuit is set. The signal control circuit and control timing change are as follows: Figure 2As shown, the signal control circuit includes multiple delay circuits and an inversion circuit. The switch control signal en1 is a delayed signal of the external enable signal en, and the comparator initialization control signal enn is the delayed inverse of the switch control signal en1. The system operation signal enok is the delayed inverse of the comparator initialization control signal enn. The system operation signal enok indicates that the comparator offset voltage characterization has completed, system initialization has ended, and the system has begun resistance calibration. For the comparator initialization control signal en and the switch control signal en1, if both signals are low, the corresponding controlled switch is open, and if both signals are high, the corresponding controlled switch is closed.

[0041] Combine Figure 2 The present invention is further explained by referring to the timing changes in the circuit. The external enable signal en is input to the signal control circuit. At time to, the external enable signal en is pulled high. At this time, the switch control signal en1 is low, and all switches controlled by the switch control signal en1 are disconnected. The comparator initialization control signal enn is high, and the first switch is opened. At this time, the voltage of compA is equal to the voltage of compB and equal to cb_vref. At this time, the comparator initialization begins, and the comparator outputs the initial comparison result of the comparator, which is high or low. High represents a positive offset voltage of the comparator, and low represents a negative offset voltage of the comparator. At time t1, the switch control signal en1 jumps, and the switch control signal en1 is input to the clock signal port of the D flip-flop. At time t1, the D flip-flop reads the input initial comparison result of the comparator, latches the comparison output result to the sel signal, and the switch controlled by en1 is closed and turned on. At t2, the comparator initialization control signal enn is pulled low, and the first controlled switch is disconnected. At this time, the initialization of the comparator is completed, and the entire circuit can work normally. At t3, the system working signal enok is pulled high, indicating that the system starts to work normally. Later, by reading the sel signal, it can be known whether the gear selection is the current gear or the previous gear to reduce the error.

[0042] The comparator error control method of the present invention can greatly reduce the difficulty of design and comparison, and the comparison operation efficiency is extremely high with very low error.

[0043] The above describes in detail the interface resistance calibration circuit provided by the present invention. Specific examples are used herein to illustrate the structure and operating principles of the present invention. The description of the above embodiments is intended only to facilitate understanding of the method and core concept of the present invention. It should be noted that those skilled in the art will appreciate that various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications fall within the scope of protection of the claims.

Claims

1. An interface resistor calibration circuit, comprising a current mirror circuit, wherein two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage and to an interface resistor circuit to generate a calibration voltage, characterized in that ； Multiple resistance branches are connected in parallel in the interface resistance circuit, the reference voltage and the calibration voltage are connected to a comparator for comparison, and the comparison result is output to control the interface resistance circuit to change the resistance value; The comparator is provided with a first switch between the reference voltage and the calibration voltage, and before the system starts resistance calibration, the first switch is controlled to be closed, and both input terminals of the comparator are connected to the reference voltage. The comparator outputs an initial comparison result, and the initial comparison result output by the comparator is used to characterize the offset voltage existing in the comparator; Based on the initial comparison result, after the resistance calibration is started, when the comparison result output by the comparator jumps, the resistance value of the access interface resistance circuit is selected.

2. An interface resistance calibration circuit according to claim 1, characterized in that: The interface resistance circuit includes a plurality of parallel resistance branches, each of which is provided with a second switch and a MOS tube; The second switch is closed before starting resistance calibration; After the resistance calibration starts, the comparator outputs a comparison result, and the gate of the MOS tube on the parallel resistance branch is connected to the resistance selection signal. The resistance selection signal is changed according to the comparison result of the comparator to perform the resistance value traversal operation of the interface resistance circuit.

3. An interface resistance calibration circuit according to claim 2, characterized in that: The resistance selection signal is a multi-bit binary selection signal, and each bit of the binary selection signal controls the conduction and opening of the corresponding resistance branch; The resistor selection signal is based on the comparison result of the comparator, and assigns a value to each bit signal in sequence according to the resistance traversal order, thereby controlling the number of branch resistors incorporated into the interface resistor circuit to be increased or decreased in sequence; When the comparison result of the comparator jumps, the comparison process ends.

4. An interface resistance calibration circuit according to claim 3, characterized in that: The calibration voltage is connected to the negative electrode of the comparator, and when the resistance value of the interface resistance circuit starts to traverse from high to low; If the initial comparison result output by the comparator is high, the resistance value of the interface resistance circuit corresponding to the current resistance selection signal is the calibration resistance result; If the initial comparison result output by the comparator is low, the resistance value of the interface resistance circuit corresponding to the previous resistance selection signal is the calibration resistance result.

5. The interface resistance calibration circuit according to claim 3, characterized in that: When the resistance value of the interface resistance circuit starts to traverse from low to high; If the initial comparison result output by the comparator is low, the resistance value of the interface resistance circuit corresponding to the current resistance selection signal is the calibration resistance result; If the initial comparison result output by the comparator is high, the resistance value of the interface resistance circuit corresponding to the previous resistance selection signal is the calibration resistance result.

6. The interface resistance calibration circuit according to claim 1, characterized in that: The first switch connects both input terminals of the comparator to the reference voltage before the interface resistance circuit starts to be calibrated. The initial comparison result output by the comparator is used to characterize the equivalent internal resistance of the comparator.

7. The interface resistance calibration circuit according to claim 2, characterized in that: A third switch is provided between the current mirror circuit and the interface resistance calibration circuit; The first switch is controlled by a comparator initialization control signal, and the second switch and the third switch are controlled by a switch control signal; The control signals of the first switch, the second switch and the third switch are generated by a signal control circuit; The signal control circuit includes a plurality of delay circuits and an inversion circuit. After an external enable signal is input to the signal control circuit, a switch control signal is obtained after delay processing. The switch control signal is processed by delay processing and inversion processing to obtain a comparator initialization control signal. The comparator initialization control signal is processed by delay processing and inversion processing to obtain a system working signal. When the system working signal is pulled high, the system starts to work normally.

8. The interface resistance calibration circuit according to claim 7, characterized in that: After the comparator outputs the initial comparison result, the initial comparison result is saved. After the interface resistance circuit is calibrated, the resistance selection signal is selected based on the initial comparison result, thereby selecting the resistance value of the interface resistance circuit.

9. The interface resistance calibration circuit according to claim 8, characterized in that: The initial comparison result is stored in the D input terminal of the D flip-flop.

10. The interface resistance calibration circuit according to claim 9, characterized in that: The clock signal input terminal of the D flip-flop inputs a switch control signal, The initial comparison result is input to the D input terminal of the D flip-flop.

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