Novel analog switch for high-precision switched capacitor application
By designing a main path parallel to an auxiliary path and a T-type pseudo-resistor circuit, the problems of unstable error compensation and large leakage current in high-precision applications of analog switches are solved, achieving high stability and low power consumption performance of analog switches.
Patent Information
- Application Number
- CN202511270460.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-08
- Publication Date
- 2025-12-23
AI Technical Summary
Existing analog switches suffer from problems such as unstable error compensation, nonlinear distortion, large leakage current, and insufficient turn-off resistance in high-precision applications, which limit their applicability in high-resolution, low-power, or high-speed applications.
The design employs a main path parallel to an auxiliary path, combined with a T-type pseudo-resistor circuit. The charge injection error is eliminated through symmetrical design, and the pseudo-resistor device is used as an impedance barrier to increase the turn-off resistance and reduce leakage current.
Significantly reduces channel charge injection and clock feedthrough errors, improves the stability and turn-off resistance of analog switches, reduces leakage current, and achieves high linearity and low power consumption analog switch performance.
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Figure CN121193244A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of analog switches, and particularly relates to a novel analog switch for high-precision switched-capacitor applications. BACKGROUND
[0002] In modern high-precision analog and mixed-signal processing systems, switched-capacitor circuits are widely used in analog-to-digital converters (ADCs), analog filters, and signal sampling circuits due to their good linearity, controllable time constant, and compatibility with standard CMOS processes. Analog switches are the core devices for signal sampling and holding, and their on-off performance directly affects key indicators such as sampling accuracy, non-linear distortion, and dynamic range. Commonly used structures of analog switches include dummy transistor compensation, complementary transmission gate structure (NMOS and PMOS in parallel), bootstrapped drive, bottom plate sampling, and differential structure.
[0003] Problems existing in the prior art include: in the dummy transistor compensation structure, the error compensation mechanism relies on the assumption of average distribution of channel charges at the source and drain, which is subject to various process and operating parameters such as load impedance and clock edge rate, and is difficult to accurately control, resulting in unstable compensation effect; the complementary transmission gate often introduces asymmetric errors and non-linear distortions due to differences in threshold voltage, size matching, and body effect between PMOS and NMOS; the bootstrapped structure is complex to implement, has reliability risks in low-voltage or high-frequency scenarios, and is difficult to avoid dynamic performance degradation caused by switch tube body effect. In addition, the leakage current of most current analog switches in the off state is large, and the off resistance is insufficient, which can easily cause problems such as sampling charge leakage and output drift in the hold phase, thereby limiting its applicability in high-resolution, low-power, or high-speed applications.
[0004] Therefore, there is an urgent need for a high-linearity and stability analog switch with simple structure, small error, and high off resistance. SUMMARY
[0005] Therefore, the present application discloses a novel analog switch for high-precision switched-capacitor applications to solve the above problems; comprising:
[0006] A novel analog switch for high-precision switched-capacitor applications, comprising: a main path circuit, an auxiliary path circuit, and a holding capacitor; the auxiliary path is connected in parallel with the main path, the input end of the parallel connection serves as the input end of the novel analog switch for high-precision switched-capacitor applications, and the output end of the parallel connection is grounded through the holding capacitor and serves as the output end of the novel analog switch for high-precision switched-capacitor applications;
[0007] The main path comprises NMOS transistors M1 and M1S, the source of M1 is connected to the drain of M1S, and the gate of M1 is connected to the gate of M1S; the drain of M1 serves as the input end of the main path, and the source of M1S serves as the output end of the main path;
[0008] The auxiliary path comprises NMOS transistors M2 and M2S and a pseudo resistor; wherein the gate of M2 is connected to the gate of M2S, the source of M2 is connected to the input end of the pseudo resistor, and the drain of M2S is connected to the output end of the pseudo resistor; the drain of M2 serves as the input end of the auxiliary path, and the source of M2S serves as the output end of the auxiliary path;
[0009] The pseudo resistor adopts a T-shaped pseudo resistor circuit, comprising MR1, MR2 and MR3; the source of MR1 is connected to the drain of MR2 and the drain of MR3 respectively, and the gate of MR1 is connected to the gate of MR2 and the gate of MR3 respectively; the drain of MR1 serves as the input end of the T-shaped pseudo resistor circuit, and the source of MR1 serves as the output end of the T-shaped pseudo resistor circuit;
[0010] Further, the aspect ratios of M1 and M2 are the same, and the aspect ratios of M1S and M2S are the same.
[0011] The beneficial effects of the present application include:
[0012] A main path parallel auxiliary path analog switch structure is designed, the symmetrical design adopted can completely eliminate charge injection error in theory, the charge value of the output holding capacitor is always constant, channel charge injection and clock feedthrough error can be significantly reduced, and the stability of the analog switch is improved;
[0013] A T-shaped pseudo resistor circuit is provided, the nonlinear problem caused by ultra-high resistance is avoided, the resistance value of the MOS device adopted can be designed to be smaller than that of the traditional scheme, the high-off resistance of the analog switch is more easily realized, and the leakage current of the analog switch is reduced;
[0014] A simple structure, easy to implement, and excellent performance analog switch structure is provided, and a new design idea is provided for those skilled in the art. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 It is a circuit schematic diagram of a new analog switch for high-precision switched capacitor application in the embodiments of the present application;
[0016] Figure 2 It is a structure schematic diagram of a pseudo resistor structure and an equivalent circuit commonly used in the prior art;
[0017] Figure 3 It is a structure schematic diagram of a T-shaped pseudo resistor circuit and an equivalent circuit in the embodiments of the present application;
[0018] Figure 4 The above are simulation results of charge injection and clock feedthrough in the embodiments of this application;
[0019] Figure 5 The simulation results of the shutdown leakage current analysis in the embodiments of this application are as follows;
[0020] Figure 6 The simulation results show the shutdown isolation in the embodiments of this application. Detailed Implementation
[0021] To make the objectives, technical solutions, features, and advantages of this application clearer and to enable those skilled in the art to better understand the technical solutions of this application, the following detailed description of this application is provided in conjunction with the accompanying drawings and embodiments.
[0022] Example 1:
[0023] This embodiment includes a novel analog switch for high-precision switched capacitor applications, such as... Figure 1 As shown, it includes: main path circuit, auxiliary path circuit, and holding capacitor C. H The auxiliary path is connected in parallel with the main path. The parallel input terminal serves as the input terminal of a novel analog switch for high-precision switched capacitor applications, and the parallel output terminal is connected through a holding capacitor C. H It is grounded and serves as the output terminal of a novel analog switch for high-precision switched capacitor applications.
[0024] The main path includes NMOS transistors M1 and M1S, with the source of M1 connected to the drain of M1S and the gate of M1 connected to the gate of M1S. The drain of M1 serves as the input of the main path, and the source of M1S serves as the output of the main path. The auxiliary path includes NMOS transistors M2 and M2S, and a pseudo-resistor. The gate of M2 is connected to the gate of M2S, the source of M2 is connected to the input of the pseudo-resistor, and the drain of M2S is connected to the output of the pseudo-resistor. The drain of M2 serves as the input of the auxiliary path, and the source of M2S serves as the output of the auxiliary path.
[0025] like Figure 3 As shown, the pseudo resistor adopts a T-type pseudo resistor circuit, including: MR1, MR2, and MR3; the source of MR1 is connected to the drain of MR2 and the drain of MR3 respectively, and the gate of MR1 is connected to the gate of MR2 and the gate of MR3 respectively; the drain of MR1 serves as the input terminal of the T-type pseudo resistor circuit, and the source of MR1 serves as the output terminal of the T-type pseudo resistor circuit.
[0026] Furthermore, M1 and M2 have the same aspect ratio, and M1S and M2S have the same aspect ratio.
[0027] Furthermore, when the circuit is in operation:
[0028] When the main path is off, the auxiliary path is on, absorbing the channel charge released by the main path, realizing charge injection error cancellation; through the symmetric gate-drain covering capacitor, the clock feedthrough error is cancelled; in terms of off leakage control, the application designs a T-shaped pseudo resistor, taking three sub-threshold bias MOS tubes as impedance barriers to improve the off resistance.
[0029] As shown in Figure 1 , the gate of M1 and the gate of M2 are connected with clock signal and inverted clock signal , when the clock signal is in the sampling stage of high level, M1 and M1S are both in the on state, the circuit forms a low impedance path, the output signal keeps synchronization with the input voltage, at this time, the channel charge of M1 and M1S accumulates in the channel. The total charge of the transistor in the main path of the switch is:
[0030]
[0031] Among them, Qmain represents the total charge amount of the transistor in the main path, Q1 represents the channel charge of M1, Q1S represents the channel charge of M1S.
[0032] The application designs an auxiliary path to effectively eliminate the error caused by the switch. When the clock signal jumps from high level to low level, the transistor in the main path is closed and enters the holding stage, at this time, the clock signal of M2 and M2S transistors turns to high level and enters the on state, MR1, MR2 and MR3 are in the off state during this process, the total charge amount of all transistors in the auxiliary path can be calculated by the following formula:
[0033]
[0034] Among them, Qaux represents the total charge amount of the transistor in the auxiliary path, Q2 represents the channel charge of M2, Q2S represents the channel charge of M2S, Qres represents the charge accumulated by the T-shaped pseudo resistor circuit.
[0035] Since the transistors of the T-shaped pseudo resistor circuit are always in the off state during this process, the total charge accumulated in the channel of the transistors therein is zero, so can be rewritten as:
[0036]
[0037] Further, the aspect of the application designs the transistor M1 and M2 with the same aspect ratio, and the transistor M1S and M2S with the same aspect ratio. Therefore, the new analog switch for high-precision switched-capacitor applications of the aspect of the application has the following relationship in the working state:
[0038]
[0039] Therefore, the total charge injected by the transistor channel in the main path will be absorbed by the transistor in the auxiliary path, thereby forming its channel and starting to conduct.
[0040] Further, according to the above description, the new analog switch for high-precision switched-capacitor applications of the aspect of the application can theoretically completely eliminate the charge injection error. In practical applications, due to the existence of threshold voltage deviation of NMOS transistor, a small amount of charge injection error may be generated.
[0041] In addition to the charge injection error, the new analog switch for high-precision switched-capacitor applications of the aspect of the application can also effectively suppress the clock crosstalk error.
[0042] Specifically, since the unit width overlapping capacitance of the transistor M1S and the unit width overlapping capacitance of the transistor M2S are the same, when the M1S generates an error charge, the M2S eliminates the error through reverse coupling, so that the charge value of the output holding capacitor is always constant, which is expressed by the formula:
[0043]
[0044] wherein, represents the error voltage caused by clock feedthrough, represents the channel width of the MOS tube, represents the unit width overlapping capacitance of the M1S, represents the unit width overlapping capacitance of the M2S.
[0045] According to the above description, the switch designed by the aspect of the application can significantly reduce the channel charge injection and clock feedthrough error.
[0046] In addition to the charge injection and clock feedthrough error, the voltage drop caused by the leakage current in the off state of the switch will also reduce the performance of the analog switch in the device. The new analog switch for high-precision switched-capacitor applications of the aspect of the application also includes a T-shaped pseudo-resistor circuit as an impedance barrier to build a leakage current control mechanism.
[0047] Specifically, to minimize the leakage current of the switch, the design of the auxiliary path needs to ensure that the resistance value of its holding stage is at least 10 times that of the main path. For example, Figure 1As shown, a T-type pseudo-resistor circuit is placed between the stacked transistors in the auxiliary path as an impedance barrier. The T-type pseudo-resistor circuit provides the required turn-off resistance for the analog switch while maintaining the excellent charge injection and clock feedthrough compensation achieved by the proposed structure. Theoretically, realizing this impedance barrier requires a trillion-ohm resistor between M2 and M2S. In standard CMOS technology, such a high resistance is difficult to achieve, making pseudo-resistor devices an ideal choice. These MOS devices, by operating in the subthreshold region, can achieve ultra-high resistance values in the trillion-ohm range while significantly reducing silicon area.
[0048] The design of pseudo-resistors typically requires consideration of several electrical and physical issues, including simplicity of implementation, small chip area, low parasitic capacitance, and linearity. Existing technologies offer various implementation structures for pseudo-resistors. For example... Figure 2 The diagram shows a commonly used pseudo-resistor structure and its equivalent circuit in the prior art. This structure reduces distortion by connecting two MOS devices in series. The formula for calculating the equivalent resistance is:
[0049]
[0050] in, This represents the equivalent total resistance of a traditional pseudo-resistor. and These represent the equivalent resistance values of the two MOS devices MR1 and MR2 connected in series. The equivalent resistance of this structure is affected by the input voltage, and nonlinearity exists at high resistance values.
[0051] This application improves upon the structure of a traditional pseudo-resistor, and the designed T-type pseudo-resistor circuit (TPR) and its equivalent circuit are as follows: Figure 3 As shown, the formula for calculating the equivalent resistance of TPR is:
[0052]
[0053] in, This represents the equivalent resistance of the TPR. , , These represent the equivalent resistance values of MR1, MR2, and MR3, respectively. A comparison reveals that, under the same conditions, the equivalent resistance value of the TPR designed in this application is significantly higher than that of the traditional scheme. Based on this advantage, while avoiding nonlinearity problems caused by ultra-high resistance, the resistance values of each MOS device in the TPR can be designed to be smaller than those in the traditional scheme.
[0054] The formula for calculating the turn-off resistance value of the switch designed in this application during the holding time is as follows: ,in, represents the off resistance value of the new analog switch in the hold time, represents the main loop resistance, represents the auxiliary loop resistance, both in the hold state. Substituting the values of and into , we get:
[0055]
[0056] wherein, represents the equivalent resistance of M1 in the off state, represents the equivalent resistance of M1S in the off state, represents the equivalent resistance of M2 in the on state, represents the equivalent resistance of the T-type pseudo resistance circuit, represents the equivalent resistance of M2S in the on state.
[0057] It can be seen that TPR provides the switch with an ultra-high off resistance, which can significantly reduce the leakage current of the switch.
[0058] Embodiment 2:
[0059] This embodiment includes a new analog switch for high-precision switched capacitor applications, which is different from Embodiment 1 in that in this embodiment, the width-length ratio W / L of transistors M1, M1S, M2, M2S is 8 / 0.18, the width-length ratio W / L of MR1, MR2, MR3 is 0.22 / 0.22, and the hold capacitor C H The maximum resistance of the entire switch is 560 Ω.
[0060] The analog switch is simulated, and the simulation results are shown in Figure 4 It can be seen that in the case of a large change in the input signal, the output error charge caused by charge injection and clock feedthrough is at most 1.72 fC, which can be almost ignored. In addition, due to the adoption of the T-type pseudo resistance circuit with a unique leakage current control mechanism, the off resistance of the switch is increased, the leakage current is reduced, and the stability and reliability of the circuit are ensured.
[0061] As shown in Figure 5 , the off leakage current analysis is carried out, and the off leakage current of the switch in the working state of the entire input signal range is lower than 40 pA. Further, the off isolation is a measure of the impedance of the switch in the off state, which shows the degree of attenuation of the open circuit switch output when a voltage is applied to the input. To more accurately present the behavior evolution of the switch in the hold phase, the off isolation of the switch is further analyzed, and the simulation results are shown in Figure 6It can be seen that the off-isolation of the switch designed by the application is about 160 dB under a wide range of input signals, which provides excellent isolation between the input and output signals for wide range of applications.
[0062] The analog switch designed by the application has extremely low error in a wide input signal range and excellent dynamic performance, far exceeding traditional switches, and is suitable for high-precision and high-dynamic-range switched-capacitor circuits.
[0063] Finally, it should be noted that the above only describes some embodiments of the application, and those skilled in the art can make various changes, modifications, replacements and variations to these embodiments without departing from the principles and spirits of the application. The protection scope of the application is defined by the appended claims and their equivalents, and the above behaviors should be covered within the protection scope of the application.
Claims
1. A novel analog switch for high-precision switched capacitor applications, characterized in that, include: The circuit includes a main path circuit, an auxiliary path circuit, and a holding capacitor. The auxiliary path is connected in parallel with the main path. The parallel input terminal serves as the input terminal of a novel analog switch for high-precision switched capacitor applications. The parallel output terminal is grounded through the holding capacitor and serves as the output terminal of the novel analog switch for high-precision switched capacitor applications.
2. The novel analog switch for high-precision switched capacitor applications according to claim 1, characterized in that, The main path includes NMOS transistors M1 and M1S. The source of M1 is connected to the drain of M1S, and the gate of M1 is connected to the gate of M1S. The drain of M1 serves as the input terminal of the main path, and the source of M1S serves as the output terminal of the main path. The auxiliary path includes: NMOS transistors M2 and M2S, and a pseudo resistor; wherein, the gate of M2 is connected to the gate of M2S, the source of M2 is connected to the input terminal of the pseudo resistor, and the drain of M2S is connected to the output terminal of the pseudo resistor; the drain of M2 serves as the input terminal of the auxiliary path, and the source of M2S serves as the output terminal of the auxiliary path.
3. The novel analog switch for high-precision switched capacitor applications according to claim 2, characterized in that, The gates of M1 and M2 are connected to the clock signal and the inverted clock signal, respectively.
4. The novel analog switch for high-precision switched capacitor applications according to claim 2, characterized in that, The pseudo resistor adopts a T-type pseudo resistor circuit, including: MR1, MR2, and MR3; the source of MR1 is connected to the drain of MR2 and the drain of MR3 respectively, and the gate of MR1 is connected to the gate of MR2 and the gate of MR3 respectively; the drain of MR1 serves as the input terminal of the T-type pseudo resistor circuit, and the source of MR1 serves as the output terminal of the T-type pseudo resistor circuit.
5. The novel analog switch for high-precision switched capacitor applications according to claim 4, characterized in that, The formula for calculating the equivalent resistance of a T-type pseudo-resistor circuit is: ； in, This represents the equivalent resistance of a T-type pseudo-resistor circuit. , , These represent the equivalent resistances of MR1, MR2, and MR3, respectively.
6. The novel analog switch for high-precision switched capacitor applications according to claim 5, characterized in that, The formula for calculating the turn-off resistance value of the new analog switch during the holding time is as follows: ； in, This indicates the turn-off resistance value of the novel analog switch during the hold time. This represents the equivalent resistance of M1 in the off state. This represents the equivalent resistance of M1S in the off state. This represents the equivalent resistance of M2 when it is in the on state. This represents the equivalent resistance of M2S when it is in the on state.
7. The novel analog switch for high-precision switched capacitor applications according to claim 2, characterized in that, M1 and M2 have the same aspect ratio, and M1S and M2S have the same aspect ratio.
8. The novel analog switch for high-precision switched capacitor applications according to claim 7, characterized in that, The novel analog switch for high-precision switched capacitor applications exhibits the following relationship during operation: ； in, This represents the total charge of the transistors in the main path. This represents the total charge of the transistors in the auxiliary path.