Semiconductor device and method of manufacturing semiconductor device

Abstract

To provide a semiconductor device and a method of manufacturing a semiconductor device, capable of sufficiently ensuring adhesiveness between semiconductor chips and adhesiveness between a semiconductor chip and a support member.SOLUTION: A semiconductor device 1 includes: a substrate 2; a controller chip 3 bonded to a first side 2a of the substrate 2; a memory chip 4 laminated to the controller chip 3 and bonded to the controller chip 3; and a pair of support members 51, 52 disposed to sandwich the controller chip 3 therebetween on the first side 2a and bonded to the first side 2a and the memory chip 4. A heigh of the controller chip 3 from the first side 2a is higher than a height of the pair of support members 51, 52 from the first side 2a. Each of the pair of support members 51, 52 includes thermosetting resin layers A3, A4 and a high rigidity layer B1 with rigidity higher than the rigidity of the thermosetting resin layers A3, A4.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] One aspect of a semiconductor device is a structure in which a semiconductor chip is stacked on a controller chip arranged on a substrate. The semiconductor assembly described in Patent Document 1 has a structure called a dolmen structure (or tunnel structure). This conventional semiconductor assembly includes a substrate, a controller chip arranged on the substrate, and a memory chip arranged above the controller chip, and the memory chip is supported by a support member such as a pillar. The substrate and the controller chip, the substrate and the memory chip, and the memory chips themselves are bonded using an adhesive layer made of, for example, an adhesive film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2017-515306 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described above, in order to ensure reliability, the adhesion between the semiconductor chips and between the semiconductor chip and the support member after bonding is important. If gaps are generated between these members and the adhesion between the members is insufficient, it is considered that the gaps will become the starting point for peeling between the members.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can ensure sufficient adhesion between semiconductor chips and between a semiconductor chip and a support member. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present disclosure comprises a substrate, a first semiconductor chip bonded to one side of the substrate, a second semiconductor chip stacked on the first semiconductor chip and bonded to the first semiconductor chip, and a pair of support members arranged on one side of the substrate so as to sandwich the first semiconductor chip and bonded to the one side of the substrate and the second semiconductor chip, wherein the height of the first semiconductor chip from the one side of the substrate is greater than the height of the pair of support members from the one side of the substrate, and each of the pair of support members includes a thermosetting resin layer and a high-rigidity layer having higher rigidity than the thermosetting resin layer.

[0007] In this semiconductor device, the height of the first semiconductor chip is higher than the height of the pair of support members arranged to sandwich the first semiconductor chip when one surface of the substrate is used as a reference. Therefore, when the second semiconductor chip is pressed against the first semiconductor chip and the pair of support members through the adhesive layer, it is possible to increase the surface pressure between the first semiconductor chip and the second semiconductor chip, and the adhesion between the first semiconductor chip and the second semiconductor chip can be sufficiently ensured. Here, if the pair of support members are made of silicon or the like, it is considered that a gap will be generated between the pair of support members whose height from one surface of the substrate is lower than that of the first semiconductor chip and the second semiconductor chip. In contrast, in this semiconductor device, each of the pair of support members is configured to include a thermosetting resin layer and a high-rigidity layer, so that the high-rigidity layer ensures the rigidity required as a support member, while the thermosetting resin layer ensures the shape followability of the pair of support members. Therefore, even in a configuration in which the height of the first semiconductor chip from one surface of the substrate is higher than the height of the pair of support members, the adhesion between the pair of support members and the second semiconductor chip can be satisfactorily ensured. As a result, in this semiconductor device, sufficient adhesion can be ensured between the semiconductor chips and between the semiconductor chips and the pair of support members.

[0008] Each of the pair of support members may be configured in two layers, with a thermosetting resin layer on the substrate side and a high-rigidity layer on the second semiconductor chip side. In this case, the high-rigidity layer ensures the rigidity of the pair of support members, and the shape conformability of the pair of support members can be ensured with a simple configuration.

[0009] Each of the pair of support members may be configured as three layers, including a high-rigidity layer and a pair of thermosetting resin layers sandwiching the high-rigidity layer. In this case, the rigidity of the support member can be ensured by the high-rigidity layer, and the shape conformability of the pair of support members can be ensured by the thermosetting resin layers, with a simple configuration. One of the thermosetting resin layers can easily bond the support member to the substrate, and the other thermosetting resin layer is positioned on the second semiconductor chip side, so that the shape conformability of the pair of support members can be more reliably generated by the surface pressure when pressing the second semiconductor chip against the first semiconductor chip and the pair of support members via the adhesive layer.

[0010] The high-rigidity layer may be composed of a polyimide layer. By using a polyimide layer as the high-rigidity layer, it is possible to ensure sufficient rigidity of the pair of support members without impairing the shape conformability of the pair of support members.

[0011] The ratio of the height of the first semiconductor chip from one surface of the substrate to the height of the pair of support members from one surface of the substrate (height of the first semiconductor chip / height of the pair of support members) may be greater than 1 and not greater than 1.25. By making the height ratio greater than 1, it is possible to sufficiently increase the surface pressure between the first semiconductor chip and the second semiconductor chip, and to sufficiently ensure adhesion between the first semiconductor chip and the second semiconductor chip. Furthermore, by making the height ratio not greater than 1.25, it is possible to sufficiently ensure the shape conformability of the pair of support members by the thermosetting resin layer.

[0012] An adhesive layer may be provided on the surface of the second semiconductor chip facing the substrate, and the first semiconductor chip and the pair of support members may be bonded to the second semiconductor chip via the adhesive layer. In this case, the first semiconductor chip and the second semiconductor chip, and the pair of support members and the second semiconductor chip can be bonded simply and reliably using the common adhesive layer.

[0013] A manufacturing method for a semiconductor device according to one aspect of the present disclosure includes a first bonding step of bonding a first semiconductor chip to one surface of a substrate, a second bonding step of bonding a pair of support members arranged to sandwich the first semiconductor chip to one surface of the substrate, and a third bonding step of bonding a second semiconductor chip to the first semiconductor chip and the pair of support members, wherein the height of the first semiconductor chip from the one surface of the substrate is made higher than the height of the pair of support members from the one surface of the substrate, and the pair of support members include a thermosetting resin layer and a high-rigidity layer having higher rigidity than the thermosetting resin layer.

[0014] In this method of manufacturing a semiconductor device, the height of the first semiconductor chip may be higher than the height of a pair of support members arranged to sandwich the first semiconductor chip when one surface of the substrate is used as a reference. Therefore, when the second semiconductor chip is pressed against the first semiconductor chip and the pair of support members through the adhesive layer, it is possible to increase the surface pressure between the first semiconductor chip and the second semiconductor chip, and the adhesion between the first semiconductor chip and the second semiconductor chip can be sufficiently ensured. Here, if the pair of support members are made of silicon or the like, it is considered that a gap will be generated between the pair of support members whose height from one surface of the substrate is lower than that of the first semiconductor chip and the second semiconductor chip. In contrast, in this semiconductor device, since each of the pair of support members is configured to include a thermosetting resin layer and a high-rigidity layer, the high-rigidity layer ensures the rigidity required as a support member, while the thermosetting resin layer ensures the shape followability of the pair of support members. Therefore, even in a configuration in which the height of the first semiconductor chip from one surface of the substrate is higher than the height of the pair of support members, the adhesion between the pair of support members and the second semiconductor chip can be satisfactorily ensured. As a result, in this semiconductor device, sufficient adhesion can be ensured between the semiconductor chips and between the semiconductor chips and the pair of support members.

[0015] In the second bonding step, a pair of support members may be used that is configured in two layers by a thermosetting resin layer on the substrate side and a high-rigidity layer on the second semiconductor chip side. In this case, the high-rigidity layer ensures the rigidity of the pair of support members and the shape conformability of the pair of support members can be ensured with a simple configuration.

[0016] In the second bonding step, a pair of support members may be used that is configured as three layers by a high-rigidity layer and a pair of thermosetting resin layers sandwiching the high-rigidity layer. In this case, the rigidity of the support members can be ensured by the high-rigidity layer, and the shape conformability of the pair of support members can be ensured by the thermosetting resin layer with a simple configuration. One of the thermosetting resin layers can easily bond the pair of support members to the substrate, and the other thermosetting resin layer is positioned on the second semiconductor chip side, so that the shape conformability of the pair of support members can be more reliably generated by the surface pressure when pressing the second semiconductor chip against the first semiconductor chip and the pair of support members via the adhesive layer.

[0017] In the second bonding step, a pair of support members may be used in which the high-rigidity layer is made of a polyimide layer. By using a polyimide layer as the high-rigidity layer, the rigidity of the pair of support members can be sufficiently ensured without impairing the shape conformability of the pair of support members.

[0018] In the second bonding step, a pair of support members may be used such that the ratio of the height of the first semiconductor chip from one surface of the substrate to the height of the pair of support members from one surface of the substrate is greater than 1 and not greater than 1.25. By making the height ratio greater than 1, it is possible to sufficiently increase the surface pressure between the first semiconductor chip and the second semiconductor chip, and to sufficiently ensure the adhesion between the first semiconductor chip and the second semiconductor chip. In addition, by making the height ratio not greater than 1.25, it is possible to sufficiently cause the thermosetting resin layer to conform to the shape of the pair of support members.

[0019] In the third bonding step, a second semiconductor chip having an adhesive layer provided on a surface facing the substrate may be used to bond the first semiconductor chip and the pair of support members via the adhesive layer. In this case, the bonding between the first semiconductor chip and the second semiconductor chip, and the bonding between the pair of support members and the second semiconductor chip can be easily and reliably performed using a common adhesive layer.

[0020] In the third bonding step, the heating temperature used for bonding the second semiconductor chip to the first semiconductor chip and the pair of support members may be 90° C. to 120° C. Such temperature conditions can ensure good wettability in bonding, and can ensure good adhesion between the first semiconductor chip and the second semiconductor chip, and between the pair of support members and the second semiconductor chip.

[0021] In the third bonding step, a load used for bonding the second semiconductor chip to the first semiconductor chip and the pair of support members may be 15 N to 30 N. Such pressure conditions can ensure good wettability in bonding, and can ensure good adhesion between the first semiconductor chip and the second semiconductor chip, and between the pair of support members and the second semiconductor chip.

[0022] In the third bonding step, the heating and pressurizing time used for bonding the second semiconductor chip to the first semiconductor chip and the pair of support members may be 1 to 3 seconds. Such heating and pressurizing conditions can ensure good wettability in bonding, and can ensure good adhesion between the first semiconductor chip and the second semiconductor chip, and between the pair of support members and the second semiconductor chip. Effect of the Invention

[0023] According to the present disclosure, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device that can ensure sufficient adhesion between semiconductor chips and between a semiconductor chip and a support member. [Brief description of the drawings]

[0024] [Figure 1] FIG. 1 is a schematic plan view illustrating a configuration of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 3] 1 is a flowchart showing a process of a manufacturing method of a semiconductor device. [Figure 4]FIG. 1(a) is a diagram for explaining a first bonding step, and FIG. 1(b) is a diagram for explaining a second bonding step. [Diagram 5] 1A is a diagram for explaining the arrangement of memory chips in a third bonding step, and FIG. 1B is a diagram for explaining the application of heat and pressure to the memory chips in the third bonding step. [Figure 6] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a comparative example. [Figure 7] 13 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a modified example. [Figure 8] 13A and 13B are diagrams showing the results of an experiment comparing the state of adhesion between a pair of support members and a memory chip. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to one aspect of the present disclosure will be described in detail with reference to the drawings.

[0026] Fig. 1 is a schematic plan view showing the configuration of a semiconductor device 1 according to a first embodiment of the present disclosure, and Fig. 2 is a schematic cross-sectional view showing the configuration of the semiconductor device 1 according to the first embodiment of the present disclosure. The semiconductor device 1 is configured as a semiconductor package for a memory such as a NAND flash memory. The semiconductor device 1 includes a substrate 2, a controller chip 3 (first semiconductor chip), a memory chip 4 (second semiconductor chip), and a pair of support members 51 and 52.

[0027] 2, the controller chip 3 and the memory chip 4 are sealed by a sealant 6 provided on a first surface 2a, which is one surface of the substrate 2. The sealant 6 is made of, for example, an epoxy resin. The constituent materials of the sealant 6 may include a filler, a hardener, a hardening accelerator, etc. Furthermore, the sealant 6 may include a colorant, a release agent, a modifier, a flame retardant, etc., as necessary.

[0028] The substrate 2 is, for example, an organic substrate. The substrate 2 may be a metal substrate such as a lead frame. The substrate 2 has a first surface 2a and a second surface 2b opposite to the first surface 2a. The first surface 2a and the second surface 2b are surface-treated with a solder resist or the like. A plurality of connection terminals used for mounting the semiconductor device 1 are provided at predetermined positions on the second surface 2b. The substrate 2 is provided with a plurality of vias extending from the first surface 2a to the second surface 2b in correspondence with the positions of the plurality of connection terminals.

[0029] The controller chip 3 is bonded to the first surface 2a of the substrate 2 via a thermosetting resin layer A1. The controller chip 3 may be electrically connected to a predetermined connection terminal on the other surface 2b of the substrate 2 via a plurality of bonding wires and a conductive layer in a via of the substrate 2. The plurality of bonding wires may be sealed with a sealing material 6. For the electrical connection between the controller chip 3 and the electrodes of the substrate 2, bump connection (for example, connection using Cu bumps and solder) may be used instead of bonding wires.

[0030] 1, the shape of the controller chip 3 in a plan view is, for example, a rectangle (square or oblong). The length of one side of the controller chip 3 is, for example, 5 mm or less, and may be 2 to 5 mm or 1 to 5 mm. The thickness of the controller chip 3 is, for example, 10 to 150 μm, and may be 20 to 100 μm.

[0031] 2, the memory chip 4 is stacked on the controller chip 3 in the direction D1 which is the thickness direction of the substrate 2. A thermosetting resin layer A2 (adhesive layer) is provided on the surface of the memory chip 4 facing the substrate 2. The memory chip 4 is adhered to the controller chip 3 and the pair of support members 51, 52 on the side opposite the substrate 2 via the thermosetting resin layer A2. In other words, adhesion between the controller chip 3 and the memory chip 4, and adhesion between the pair of support members 51, 52 and the memory chip 4 are achieved by the thermosetting resin layer A2 which is a common adhesive layer.

[0032] The thermosetting resin layers A1 and A2 contain a thermosetting resin. The thermosetting resin layers A1 and A2 can be in a semi-cured (B stage) state, for example, and then in a completely cured (C stage) state by a subsequent curing process. The thermosetting resin composition contains an epoxy resin, a curing agent (e.g., phenolic resin), and an elastomer (e.g., acrylic resin, phenoxy resin, etc.). The elastomer may contain a crosslinkable functional group. The thermosetting resin composition may further contain a coupling agent, a curing accelerator, etc., as necessary.

[0033] 1, the shape of the memory chip 4 in a plan view is, for example, a rectangle (square or oblong), and the size of the memory chip 4 in a plan view is larger than the size of the controller chip 3. In the example of FIG. 1, the outer edge of the controller chip 3 is located inside the outer edge of the memory chip 4. The length of one side of the memory chip 4 is, for example, 20 mm or less, and may be 4 to 20 mm or 4 to 12 mm. The thickness of the memory chip 4 is, for example, 10 to 170 μm, and may be 20 to 120 μm.

[0034] The pair of support members 51, 52 are members for supporting the memory chip 4. The pair of support members 51, 52 also function as spacers that form a space around the controller chip 3.

[0035] 2, each of the pair of support members 51, 52 includes a thermosetting resin layer A3, a thermosetting resin layer A4, and a high-rigidity layer B1. In this embodiment, each of the pair of support members 51, 52 has a three-layer structure in which the high-rigidity layer B1 is sandwiched between the pair of thermosetting resin layers A3, A4 in the direction D1. The pair of support members 51, 52 are bonded to the first surface 2a of the substrate 2 via the thermosetting resin layer A4. The pair of support members 51, 52 are bonded to the memory chip 4 via the thermosetting resin layer A3.

[0036] The pair of support members 51, 52 are arranged at a predetermined interval on both sides of the controller chip 3 in a direction D2 that is one direction in the in-plane direction of the substrate 2 and perpendicular to the direction D1. The pair of support members 51, 52 are arranged to sandwich the controller chip 3 in the direction D2. As shown in FIG. 1, each of the pair of support members 51, 52 has a rectangular shape (a square or a rectangle) in a plan view, for example. In the example of FIG. 1, each of the pair of support members 51, 52 has a rectangular shape with the direction D2 side as the short side and the direction perpendicular to the direction D2 in the in-plane direction of the substrate 2 as the long side.

[0037] The thermosetting resin layers A3 and A4 are composed of a member equivalent to, for example, a die attach film (DAF). The thermosetting resin layers A3 and A4 can be in a semi-cured (B stage) state and then in a completely cured (C stage) state by a subsequent curing process. The thermosetting resin composition contains an epoxy resin, a curing agent (e.g., phenolic resin), and an elastomer (e.g., acrylic resin, phenoxy resin, etc.). The elastomer may contain a crosslinkable functional group. The thermosetting resin composition may further contain a coupling agent, a curing accelerator, etc., as necessary.

[0038] The high-rigidity layer B1 has higher rigidity than the thermosetting resin layers A3 and A4. The high-rigidity layer B1 is made of, for example, a polyimide layer or a metal layer. The high-rigidity layer B1 may be made of a dummy semiconductor chip (silicon chip) different from the controller chip 3 and the memory chip 4. The metal layer may be, for example, a copper layer or an aluminum layer.

[0039] 2, the height H1 of the controller chip 3 from the first surface 2a of the substrate 2 is greater than the height H2 of the pair of support members 51, 52 from the first surface 2a. The height H1 of the controller chip 3 here includes the thickness of the thermosetting resin layer A1.

[0040] The height H2 of the pair of support members 51, 52 is the maximum value of the height of the pair of support members 51, 52. Although details will be described later, in the semiconductor device 1, the thermosetting resin layer A3 is flexibly deformed so as to follow the curved shapes of the memory chip 4 and the thermosetting resin layer A2. As a result, the height of the pair of support members 51, 52 changes along the direction D2. In the example of FIG. 2, the thermosetting resin layer A3 is not deformed on the side surface of the pair of support members 51, 52 on the controller chip 3 side, so that the height of the pair of support members 51, 52 is maximum, and is the height H2. As it moves away from the controller chip 3, the deformation of the thermosetting resin layer A3 becomes larger, and the height of the pair of support members 51, 52 becomes smaller.

[0041] The ratio value (height H1 of the controller chip 3 / height H2 of the pair of support members 51, 52 from the first surface 2a) of the controller chip 3 from the first surface 2a of the pair of support members 51, 52 is, for example, greater than 1 and less than or equal to 1.25. As will be described in detail later, the memory chip 4 is bonded to the controller chip 3 and the pair of support members 51, 52 via the thermosetting resin layer A2 by applying pressure and heat toward the substrate 2. At this time, as described above, since the height H1 of the controller chip 3 from the first surface 2a of the substrate 2 is greater than the height H2 of the pair of support members 51, 52 from the first surface 2a, the memory chip 4 and the thermosetting resin layer A2 after bonding have a curved shape in the direction D2.

[0042] 2, the distance between the memory chip 4 and the thermosetting resin layer A2 and the substrate 2 gradually increases from the pair of support members 51, 52 side toward the controller chip 3 side. Even in such a case, the thermosetting resin layer A3 goes through, for example, a semi-cured (B stage) state, and therefore the thermosetting resin layer A3 flexibly deforms and bonds the memory chip 4 and the pair of support members 51, 52 without creating any gaps. In other words, the thermosetting resin layer A3 ensures the shape conformability of the pair of support members 51, 52.

[0043] Next, an embodiment of a method for manufacturing the semiconductor device 1 will be described. Fig. 3 is a flow chart showing one step of the method for manufacturing the semiconductor device 1. In this manufacturing method, first, the controller chip 3 is bonded to the first surface 2a of the substrate 2 (first bonding step ST1). Fig. 4(a) is a diagram for explaining the first bonding step ST1.

[0044] In the first bonding step ST1, first, the controller chip 3 is placed on the first surface 2a via the thermosetting resin layer A1. In the first bonding step ST1, for example, the substrate 2 is placed on a heating stage, and the heating stage applies heat to the thermosetting resin layer A1, thereby bonding the controller chip 3 to the first surface 2a. After bonding, the controller chip 3 is electrically connected to a predetermined connection terminal on the second surface 2b side of the substrate 2 via a plurality of bonding wires and a conductive layer in the via of the substrate 2.

[0045] Next, a pair of support members 51, 52 arranged to sandwich the controller chip 3 are bonded to the first surface 2a of the substrate 2 (second bonding step ST2). Fig. 4(b) is a diagram for explaining the second bonding step ST2. In the second bonding step ST2, first, the pair of support members 51, 52 are disposed on the first surface 2a so as to be spaced apart from the controller chip 3 in the direction D2 and to sandwich the controller chip 3 therebetween.

[0046] In the second bonding step ST2, the height H1 of the controller chip 3 from the first surface 2a of the substrate 2 is made higher than the height H2 of the pair of support members 51, 52 from the first surface 2a. Specifically, a pair of support members 51, 52 are used that are configured so that the ratio of the height H1 of the controller chip 3 from the first surface 2a to the height H2 of the pair of support members 51, 52 from the first surface 2a is greater than 1 and equal to or less than 1.25.

[0047] In the second bonding step ST2, the pair of support members 51, 52 are configured to include thermosetting resin layers A3, A4 and a high-rigidity layer B1 having higher rigidity than the thermosetting resin layers A3, A4. Specifically, in the second bonding step ST2, a pair of support members 51, 52 configured to have three layers including the high-rigidity layer B1 and a pair of thermosetting resin layers A3, A4 sandwiching the high-rigidity layer B1 is used. In the second bonding step ST2, a support member in which the high-rigidity layer B1 is configured of a polyimide layer is used.

[0048] After the pair of support members 51, 52 are arranged, in the second adhesion step ST2, the pair of support members 51, 52 are adhered to the first surface 2a by, for example, applying heat to the thermosetting resin layer A4 by a heating stage. In the example of Fig. 4(b), each of the pair of support members 51, 52 is arranged on the first surface 2a in a state in which the pair of thermosetting resin layers A3, A4 and the high-rigidity layer B1 are adhered in advance as a three-layer structure. Either the first adhesion step ST1 or the second adhesion step ST2 may be performed first, or they may be performed simultaneously.

[0049] Next, the memory chip 4 is bonded to the controller chip 3 and the pair of support members 51, 52 (third bonding step ST3). Figures 5(a) and 5(b) are diagrams for explaining the third bonding step ST3. In the third bonding step ST3, a memory chip 4 having a thermosetting resin layer A2 (adhesive layer) provided on the surface facing the substrate 2 is used.

[0050] 5(a), the memory chip 4 is placed on the controller chip 3 via the thermosetting resin layer A2. At this point, the height of the pair of support members 51, 52 from the first surface 2a is constant at height H2 in the direction D2. Since the height H3 of the controller chip 3 from the first surface 2a of the substrate 2 is higher than the height H2 of the pair of support members 51, 52 from the first surface 2a, a gap is generated between the pair of support members 51, 52 and the memory chip 4.

[0051] 5(b), the controller chip 3 and the pair of support members 51, 52 are bonded via the thermosetting resin layer A2. As a bonding method, the memory chip 4 is heated and pressurized from the side opposite the substrate 2. For example, a heating collet (not shown) is used to heat and pressurize the memory chip 4. The heating temperature is, for example, 90°C to 120°C. The pressure load is, for example, 15N to 30N. The heating and pressurizing time is, for example, 1 second to 3 seconds.

[0052] Since the height H3 of the controller chip 3 from the first surface 2a is higher than the height H2 of the pair of support members 51, 52 from the first surface 2a, the surface pressure between the controller chip 3 and the memory chip 4 is higher than the surface pressure between the pair of support members 51, 52 and the memory chip 4. As a result, a part of the controller chip 3 sinks into the thermosetting resin layer A2. In addition, the memory chip 4 and the thermosetting resin layer A2 are deformed so as to fill the gap between the pair of support members 51, 52 and the memory chip 4. As described above, the memory chip 4 and the thermosetting resin layer A2 can be curved in the direction D2. At that time, the thermosetting resin layer A3 is flexibly deformed, and the shape followability of the pair of support members 51, 52 is ensured.

[0053] As described above, in semiconductor device 1 according to one aspect of the present disclosure, when first surface 2a (one surface) of substrate 2 is used as a reference, the height of controller chip 3 (first semiconductor chip) is higher than the height of a pair of support members 51, 52 arranged to sandwich controller chip 3. Therefore, when memory chip 4 (second semiconductor chip) is pressed against controller chip 3 and the pair of support members 51, 52, it is possible to increase the surface pressure between controller chip 3 and memory chip 4, and sufficient adhesion between controller chip 3 and memory chip 4 can be ensured.

[0054] Here, if the pair of support members 51, 52 are made of silicon or the like, it is considered that a gap will be generated between the pair of support members 51, 52, whose height from the first surface 2a of the substrate 2 is lower than that of the controller chip 3, and the memory chip 4. In contrast, in the semiconductor device 1, each of the pair of support members 51, 52 is configured to include the thermosetting resin layers A3, A4 and the high rigidity layer B1, so that the high rigidity layer B1 ensures the rigidity required for the pair of support members 51, 52, while the thermosetting resin layer A3 ensures the shape conformability of the pair of support members 51, 52. Therefore, even in a configuration in which the height H1 of the controller chip 3 from the first surface 2a of the substrate 2 is higher than the height H2 of the pair of support members 51, 52, the adhesion between the pair of support members 51, 52 and the memory chip 4 can be satisfactorily ensured. As a result, in the semiconductor device 1, the adhesion between the semiconductor chips and between the semiconductor chips and the pair of support members 51, 52 can be sufficiently ensured.

[0055] Here, the effect of the semiconductor device 1 according to the embodiment will be further described using a semiconductor device 101A according to a comparative example. FIG. 6 is a schematic cross-sectional view showing the configuration of the semiconductor device 101A according to the comparative example. The semiconductor device 101A according to the comparative example is different from the semiconductor device 1 according to the embodiment in which the pair of support members 51, 52 do not include a silicon layer in that the pair of support members 151A, 152A includes a silicon layer S1. Specifically, the pair of support members 151A, 152A include a silicon layer S1 instead of the thermosetting resin layer A3 and the high-rigidity layer B1. In the semiconductor device 1A, the memory chip 4 and the silicon layer S1 are bonded via the thermosetting resin layer A2.

[0056] In the semiconductor device 101A, the memory chip 4 and the thermosetting resin layer A2 may also be curved in the direction D2. However, since the silicon layer S1 has higher rigidity and is less likely to deform than the thermosetting resin layer A3, a part R1 where the silicon layer S1 and the thermosetting resin layer A2 are in close contact and a part R2 where the silicon layer S1 and the thermosetting resin layer A2 are not in close contact (a part where a gap is generated) may occur between the silicon layer S1 and the thermosetting resin layer A2. In contrast, in the semiconductor device 1, the thermosetting resin layer A3 ensures the shape conformability of the pair of support members 51 and 52, so that even in a configuration in which the height of the controller chip 3 from the first surface 2a of the substrate 2 is higher than the height of the pair of support members 51 and 52 from the first surface 2a, the semiconductor device 1 can ensure good adhesion between the pair of support members 51 and 52 and the memory chip 4 compared to the semiconductor device 101A including the silicon layer S1 in the pair of support members 151A and 152A.

[0057] Each of the pair of support members 51, 52 is configured as three layers, including a high-rigidity layer B1 and a pair of thermosetting resin layers A3, A4 sandwiching the high-rigidity layer B1. In this case, the rigidity of the pair of support members 51, 52 can be ensured by the high-rigidity layer B1, and the shape conformability of the pair of support members 51, 52 can be ensured by the thermosetting resin layers A3, A4, with a simple configuration. The pair of support members 51, 52 can be easily bonded to the substrate 2 by one thermosetting resin layer A4, and the other thermosetting resin layer A3 is located on the memory chip 4 side, so that the shape conformability of the pair of support members 51, 52 can be more reliably generated by the surface pressure when pressing the memory chip 4 against the controller chip 3 and the pair of support members 51, 52.

[0058] The high-rigidity layer B1 is made of a polyimide layer. In this case, by using a polyimide layer as the high-rigidity layer B1, it is possible to ensure sufficient rigidity of the pair of support members 51, 52 without impairing the shape conformability of the pair of support members 51, 52.

[0059] The ratio of height H1 of controller chip 3 from first surface 2a of substrate 2 to height H2 of pair of support members 51, 52 from first surface 2a of substrate 2 is greater than 1 and not greater than 1.25. In this case, by making the height ratio greater than 1, it is possible to sufficiently increase the surface pressure between controller chip 3 and memory chip 4, and to sufficiently ensure adhesion between controller chip 3 and memory chip 4. Furthermore, by making the height ratio not greater than 1.25, it is possible to sufficiently ensure the shape conformability of the pair of support members 51, 52 by thermosetting resin layer A3.

[0060] A thermosetting resin layer A2 (adhesive layer) is provided on the surface of the memory chip 4 facing the substrate 2, and the controller chip 3 and the pair of support members 51, 52 are adhered to the memory chip 4 via the thermosetting resin layer A2. In this case, adhesion between the controller chip 3 and the memory chip 4, and adhesion between the pair of support members 51, 52 and the memory chip 4 can be easily and reliably performed by using the thermosetting resin layer A2, which is a common adhesive layer.

[0061] In the manufacturing method of a semiconductor device according to one aspect of the present disclosure, when the first surface 2a (one surface) of the substrate 2 is used as a reference, the height of the controller chip 3 (first semiconductor chip) is higher than the height of a pair of support members 51, 52 arranged to sandwich the controller chip 3. Therefore, when the memory chip 4 (second semiconductor chip) is pressed against the controller chip 3 and the pair of support members 51, 52, it is possible to increase the surface pressure between the controller chip 3 and the memory chip 4, and sufficient adhesion between the controller chip 3 and the memory chip 4 can be ensured.

[0062] Here, if the pair of support members 51, 52 are made of silicon or the like, it is considered that a gap will be generated between the pair of support members 51, 52, whose height from the first surface 2a of the substrate 2 is lower than that of the controller chip 3, and the memory chip 4. In contrast, in the semiconductor device 1, each of the pair of support members 51, 52 is configured to include the thermosetting resin layers A3, A4 and the high rigidity layer B1, so that the high rigidity layer B1 ensures the rigidity required for the pair of support members 51, 52, while the thermosetting resin layer A3 ensures the shape conformability of the pair of support members 51, 52. Therefore, even in a configuration in which the height H1 of the controller chip 3 from the first surface 2a of the substrate 2 is higher than the height H2 of the pair of support members 51, 52, the adhesion between the pair of support members 51, 52 and the memory chip 4 can be satisfactorily ensured. As a result, in the semiconductor device 1, the adhesion between the semiconductor chips and between the semiconductor chips and the pair of support members 51, 52 can be sufficiently ensured.

[0063] In the second bonding step ST2, a pair of support members 51, 52 is used, which is configured as three layers by a high-rigidity layer B1 and a pair of thermosetting resin layers A3, A4 sandwiching the high-rigidity layer B1. In this case, the rigidity of the pair of support members 51, 52 by the high-rigidity layer B1 and the shape conformability of the pair of support members 51, 52 by the thermosetting resin layers A3, A4 can be ensured with a simple configuration. The pair of support members 51, 52 and the substrate 2 can be easily bonded by one of the thermosetting resin layers A4, and the other thermosetting resin layer A3 is located on the memory chip 4 side, so that the shape conformability of the pair of support members 51, 52 can be more reliably generated by the surface pressure when pressing the memory chip 4 against the controller chip 3 and the pair of support members 51, 52.

[0064] In the second bonding step ST2, a pair of support members 51, 52 having a high rigidity layer B1 made of a polyimide layer are used. In this case, by using a polyimide layer as the high rigidity layer B1, it is possible to sufficiently ensure the rigidity of the pair of support members 51, 52 without impairing the shape conformability of the pair of support members 51, 52.

[0065] In the second bonding step ST2, a pair of support members 51, 52 are used that are configured so that the ratio value between the height H1 of the controller chip 3 from the first surface 2a of the substrate 2 and the height H2 of the pair of support members 51, 52 from the first surface 2a of the substrate 2 is greater than 1 and not greater than 1.25. In this case, by making the height ratio value greater than 1, it is possible to sufficiently increase the surface pressure between the controller chip 3 and the memory chip 4, and it is possible to sufficiently ensure adhesion between the controller chip 3 and the memory chip 4. In addition, by making the height ratio value 1.25 or less, it is possible to sufficiently cause the thermosetting resin layer A3 to conform to the shape of the pair of support members 51, 52.

[0066] In the third bonding step ST3, a memory chip 4 having a thermosetting resin layer A2 (adhesive layer) provided on the surface facing the substrate 2 is used, and the controller chip 3 and the pair of support members 51, 52 are bonded via the thermosetting resin layer A2. In this case, the bonding between the controller chip 3 and the memory chip 4, and the bonding between the pair of support members 51, 52 and the memory chip 4 can be easily and reliably performed by using the thermosetting resin layer A2, which is a common adhesive layer.

[0067] In the third bonding step ST3, the heating temperature used for bonding the memory chip 4 to the controller chip 3 and the pair of support members 51, 52 is 90°C to 120°C. The load used for bonding the memory chip 4 to the controller chip 3 and the pair of support members 51, 52 is 15N to 30N. The heating and pressurizing time used for bonding the memory chip 4 to the controller chip 3 and the pair of support members 51, 52 is 1 second to 3 seconds. Under these conditions, good wettability in bonding can be ensured, and good adhesion between the first semiconductor chip and the second semiconductor chip, and between the pair of support members and the second semiconductor chip can be ensured.

[0068] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. FIG. 7 is a schematic cross-sectional view showing the configuration of a semiconductor device 1A according to a modified example. The semiconductor device 1A according to the modified example differs from the semiconductor device 1 in which the pair of support members 51A, 52A are configured in two layers in that the pair of support members 51, 52A are configured in three layers. Specifically, the pair of support members 51A, 52A are configured in two layers by a thermosetting resin layer A4 on the substrate 2 side and a high-rigidity layer B1 on the memory chip 4 side. That is, the pair of support members 51A, 52A do not include a thermosetting resin layer A3. In the semiconductor device 1A, the memory chip 4 and the high-rigidity layer B1 are bonded via a thermosetting resin layer A2.

[0069] In such a semiconductor device 1A, the memory chip 4 and the thermosetting resin layer A2 may be curved in the direction D2. In this case, even in the pair of support members 51A, 52A having a two-layer structure, the high-rigidity layer B1 can ensure the necessary rigidity of the pair of support members 51, 52 while ensuring the shape conformability of the pair of support members 51A, 52A. This allows the memory chip 4 and the pair of support members 51A, 52A to be bonded together without any gaps. In the semiconductor device 1A, the high-rigidity layer B1 can ensure the rigidity of the support members and the shape conformability of the pair of support members 51A, 52A with a simple configuration. In addition, compared to the semiconductor device 1 according to the embodiment, the thickness ratio of the high-rigidity layer B1 in the pair of support members 51A, 52A is increased, and more rigidity can be ensured.

[0070] [Example] Hereinafter, examples of the present disclosure will be described. In this example, semiconductor devices of Example 1, Example 2, and Comparative Example 1 were prepared, and four device samples were manufactured for each of the eight experimental conditions No. 1 to No. 8 for each semiconductor device. For each device sample, the state of adhesion between the pair of support members and the memory chip was observed.

[0071] In Example 1, a semiconductor device was prepared in which each of a pair of support members had a three-layer structure, in accordance with the structure of semiconductor device 1 shown in Fig. 2. Specifically, in Example 1, the support member had a three-layer structure in which a high-rigidity layer was sandwiched between a pair of thermosetting resin layers. Then, the controller chip and the memory chip were bonded to the pair of support members while the height of the controller chip from the first surface of the substrate was made higher than the height of the pair of support members from the first surface.

[0072] In the second embodiment, each of the pair of support members was made to have a two-layer structure in accordance with the structure of the semiconductor device 1A shown in FIG.

[0073] In Comparative Example 1, a configuration was used in which each of a pair of support members included a silicon layer in accordance with the semiconductor device 101A shown in FIG.

[0074] The eight experimental conditions for No1 to No8 are as follows. The heating temperature condition is 120°C for No1 to No4, and 150°C for No5 to No8. The pressurized load condition is 15N for No1, 2, 5, 6, and 30N for No3, 4, 7, 8. The heating and pressurizing time condition is 1 second for No1, 3, 5, 7, and 2 seconds for No2, 4, 6, 8.

[0075] The observation method was appearance confirmation. For appearance confirmation, a microscope was used to confirm the state of adhesion between the pair of support members and the memory chip 4. The microscope used was an ultrasonic microscope (IS-350, manufactured by Insight Corporation). The measurement method was a transmission method, and the frequency of the ultrasonic waves was 75 MHz.

[0076] Fig. 8 shows the results of an experiment comparing the state of adhesion between a pair of support members and a memory chip in each of the semiconductor devices according to Example 1, Example 2, and Comparative Example 1. Fig. 8 shows the number of N samples in which sufficient adhesion was confirmed (e.g., no gap was confirmed between a pair of support members and a memory chip) out of the number of device samples N=4 under each of eight experimental conditions No1 to No8. For example, under measurement condition No1, the result of the semiconductor device according to the example is 2 / 4. This means that out of the number of samples N=4, the number of samples in which sufficient adhesion was confirmed was 2.

[0077] 8, the number of samples No. 1 to No. 8 in which sufficient adhesion was confirmed was 27 for the semiconductor device according to Example 1, 24 for the semiconductor device according to Example 2, and 7 for the semiconductor device according to Comparative Example 1. From this result, it can be said that in the semiconductor device according to Example 1, sufficient adhesion is most easily achieved between the pair of support members and the memory chip.

[0078] 8, the number of samples in which sufficient adhesion was confirmed in the semiconductor device according to Example 1 and the semiconductor device according to Example 2 was three times or more as large as that in the semiconductor device according to Comparative Example 1, and therefore it can be said that sufficient adhesion is remarkably easier to achieve than in the semiconductor device according to Comparative Example 1. It can be said that the semiconductor device according to Example 1 tends to achieve sufficient adhesion more easily when the temperature and load are high. It can be said that the semiconductor device according to Example 2 shows a low significant difference due to temperature, while it can be said that the semiconductor device according to Example 2 tends to achieve sufficient adhesion more easily when the load is high.

[0079] The gist of this disclosure is as follows: [1] to

[15] [1] A semiconductor device comprising: a substrate; a first semiconductor chip bonded to one side of the substrate; a second semiconductor chip stacked on the first semiconductor chip and bonded to the first semiconductor chip; and a pair of support members arranged on one side of the substrate so as to sandwich the first semiconductor chip and bonded to the one side of the substrate and the second semiconductor chip, wherein a height of the first semiconductor chip from the one side of the substrate is greater than a height of the pair of support members from the one side of the substrate, and each of the pair of support members includes a thermosetting resin layer and a high-rigidity layer having higher rigidity than the thermosetting resin layer. [2] The semiconductor device according to [1], wherein each of the pair of support members is configured as two layers, the thermosetting resin layer on the substrate side and the high rigidity layer on the second semiconductor chip side. [3] The semiconductor device according to [1], wherein each of the pair of support members is configured as three layers including the high-rigidity layer and a pair of the thermosetting resin layers sandwiching the high-rigidity layer. [4] The semiconductor device according to any one of [1] to [3], wherein the high-rigidity layer is composed of a polyimide layer. [5] The semiconductor device according to any one of [1] to [4], wherein the ratio of the height of the first semiconductor chip from one surface of the substrate to the height of the pair of support members from one surface of the substrate is greater than 1 and less than or equal to 1.25. [6] A semiconductor device according to any one of [1] to [5], wherein an adhesive layer is provided on a surface of the second semiconductor chip facing the substrate, and the first semiconductor chip and the pair of support members are adhered to the second semiconductor chip via the adhesive layer. [7] A method for manufacturing a semiconductor device, comprising: a first bonding step of bonding a first semiconductor chip to one surface of a substrate; a second bonding step of bonding a pair of support members arranged to sandwich the first semiconductor chip to one surface of the substrate; and a third bonding step of bonding a second semiconductor chip to the first semiconductor chip and the pair of support members, wherein a height of the first semiconductor chip from the one surface of the substrate is made higher than a height of the pair of support members from the one surface of the substrate, and the pair of support members include a thermosetting resin layer and a high-rigidity layer having higher rigidity than the thermosetting resin layer. [8] The method for manufacturing a semiconductor device described in [7], wherein in the second bonding step, a pair of support members configured as two layers by the thermosetting resin layer on the substrate side and the high rigidity layer on the second semiconductor chip side are used. [9] The method for manufacturing a semiconductor device described in [7], wherein in the second bonding step, a pair of support members each having a three-layer structure consisting of the high-rigidity layer and a pair of the thermosetting resin layers sandwiching the high-rigidity layer are used.

[10] The method for manufacturing a semiconductor device according to any one of [7] to [9], wherein in the second bonding step, the pair of support members, each of which is made of a polyimide layer, is used as the high-rigidity layer.

[11] The method for manufacturing a semiconductor device according to any one of [7] to

[10] , wherein in the second bonding step, a support member is used that is configured so that a ratio between a height of the first semiconductor chip from one side of the substrate and a height of the pair of support members from one side of the substrate is greater than 1 and not greater than 1.25.

[12] The method for manufacturing a semiconductor device according to any one of [7] to

[11] , wherein in the third bonding step, a second semiconductor chip having an adhesive layer provided on a surface facing the substrate is used, and the first semiconductor chip and the pair of support members are bonded via the adhesive layer.

[13] The method for manufacturing a semiconductor device according to any one of [7] to

[12] , wherein in the third bonding step, a heating temperature used for bonding the second semiconductor chip to the first semiconductor chip and the pair of support members is 90°C to 120°C.

[14] The method for manufacturing a semiconductor device according to any one of [7] to

[13] , wherein in the third bonding step, a load of 15N to 30N is used to bond the second semiconductor chip to the first semiconductor chip and the pair of support members.

[15] The method for manufacturing a semiconductor device described in any one of [7] to

[14] , wherein in the third bonding step, the heating and pressurizing time used to bond the second semiconductor chip to the first semiconductor chip and the pair of support members is 1 second to 3 seconds. [Explanation of symbols]

[0080] 1, 1A, 101A...semiconductor device, 2...substrate, 2a...first surface (one side), 51, 52...pair of support members, A3, A4...thermosetting resin layer, A2...thermosetting resin layer (adhesive layer), B1...high rigidity layer, ST1...first adhesive step, ST2...second adhesive step, ST3...third adhesive step.

Claims

1. A substrate; a first semiconductor chip bonded to one surface of the substrate; a second semiconductor chip that is stacked on the first semiconductor chip and bonded to the first semiconductor chip; a pair of support members disposed on one surface of the substrate so as to sandwich the first semiconductor chip therebetween and bonded to the one surface of the substrate and the second semiconductor chip; a height of the first semiconductor chip from the surface of the substrate is greater than a height of the pair of support members from the surface of the substrate; Each of the pair of support members includes a thermosetting resin layer and a high-rigidity layer having a higher rigidity than the thermosetting resin layer.

2. 2. The semiconductor device according to claim 1, wherein each of said pair of supporting members is configured as two layers, that is, a thermosetting resin layer on said substrate side and a high rigidity layer on said second semiconductor chip side.

3. 2. The semiconductor device according to claim 1, wherein each of said pair of support members is made up of three layers, including said high-rigidity layer and a pair of said thermosetting resin layers sandwiching said high-rigidity layer therebetween.

4. 4. The semiconductor device according to claim 1, wherein the high-rigidity layer is made of a polyimide layer.

5. The semiconductor device according to any one of claims 1 to 3, wherein a ratio of a height of the first semiconductor chip from one surface of the substrate to a height of the pair of support members from one surface of the substrate is greater than 1 and less than or equal to 1.

25.

6. an adhesive layer is provided on a surface of the second semiconductor chip facing the substrate; 4. The semiconductor device according to claim 1, wherein the first semiconductor chip and the pair of support members are bonded to the second semiconductor chip via the adhesive layer.

7. a first bonding step of bonding a first semiconductor chip to one surface of a substrate; a second bonding step of bonding a pair of support members arranged to sandwich the first semiconductor chip to one surface of the substrate; a third bonding step of bonding a second semiconductor chip to the first semiconductor chip and the pair of support members; a height of the first semiconductor chip from one surface of the substrate being greater than a height of the pair of support members from one surface of the substrate; The method for manufacturing a semiconductor device, wherein the pair of support members includes a thermosetting resin layer and a high-rigidity layer having a higher rigidity than the thermosetting resin layer.

8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the second bonding step, a pair of support members configured as two layers by the thermosetting resin layer on the substrate side and the high rigidity layer on the second semiconductor chip side are used.

9. 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the second bonding step, a pair of support members each having a three-layer structure including the high rigidity layer and a pair of the thermosetting resin layers sandwiching the high rigidity layer are used as the pair of support members.

10. 10. The method for manufacturing a semiconductor device according to claim 7, wherein in the second bonding step, the pair of support members are used, the high rigidity layer being constituted by a polyimide layer.

11. The method for manufacturing a semiconductor device according to any one of claims 7 to 9, wherein in the second bonding step, a pair of support members are used that are configured so that a ratio of a height of the first semiconductor chip from one surface of the substrate to a height of the pair of support members from one surface of the substrate is greater than 1 and is not greater than 1.

25.

12. In the third bonding step, a second semiconductor chip having an adhesive layer provided on a surface facing the substrate is used, 10. The method for manufacturing a semiconductor device according to claim 7, wherein the first semiconductor chip and the pair of support members are bonded via the adhesive layer.

13. The method for manufacturing a semiconductor device according to any one of claims 7 to 9, wherein in the third bonding step, a heating temperature used for bonding the second semiconductor chip to the first semiconductor chip and the pair of support members is 90°C to 120°C.

14. The method for manufacturing a semiconductor device according to any one of claims 7 to 9, wherein in the third bonding step, a load of 15N to 30N is used to bond the second semiconductor chip to the first semiconductor chip and the pair of support members.

15. The method for manufacturing a semiconductor device according to any one of claims 7 to 9, wherein in the third bonding step, the heating and pressurizing time used to bond the second semiconductor chip to the first semiconductor chip and the pair of support members is 1 to 3 seconds.

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