Semiconductor device, composite semiconductor device, and drive circuit

Abstract

To achieve a thin thickness of a gate insulating film of a semiconductor device to be driven and stable operation even if a high voltage power supply is used.SOLUTION: A p+ layer 17 is formed on a surface between a drain electrode 24 and an end of a gate electrode 22 or an end of an n layer 14 on a side of the gate electrode 22, and an auxiliary electrode 26 is connected to the p+ layer 17. If the voltage between the drain electrode 24 and a source electrode 23 is gradually increased when it is turned off, a depletion layer gradually expands from a p-n junction interface between an n layer 11 and a p layer 12. If the voltage between the drain electrode 24 and the source electrode 23 is further increased, the depletion layer reaches the p+ layer 17, and if the voltage is further increased, the depletion layer in the n layer 14 is expanded. However, since a potential in the p+ layer 17 does not reach complete depletion, the potential of the p+ layer 17 is saturated. If the auxiliary electrode 26 is connected to the gate of a switching device driven by an n-channel device 1, a gate oxide film of the switching device may be thinned.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor element used in a drive circuit that drives a switching element or the like, a composite semiconductor element in which this semiconductor element is combined, and a drive circuit in which this semiconductor element and the composite semiconductor element are used. [Background technology]

[0002] Power semiconductor elements (power control semiconductor elements) such as power MOSFETs and IGBTs are used to control the on / off of high-power loads such as motors, and the switching operation of the power semiconductor elements is controlled by the gate voltage applied to the gate. To optimally control this operation, this gate voltage is controlled by a drive circuit provided separately from the power semiconductor elements. The rated voltage of a power semiconductor element (e.g. IGBT) is, for example, about 600V.

[0003] On the other hand, the voltage used to control such power semiconductor elements (the gate voltage of the power semiconductor elements) is set to a relatively high voltage (for example, about 20 V) in order to prevent malfunctions caused by induced noise and floating components of the LCR components, and to allow a relatively large current to flow, and a drive circuit is provided to control the power semiconductor elements.

[0004] Therefore, as described in Patent Document 1, the gate oxide film of the semiconductor element used to control the power semiconductor element is generally made thicker to increase the gate breakdown voltage. However, such a thick gate oxide film has many disadvantages. For example, punch-through is more likely to occur when the gate oxide film is thick, so the gate length must be increased to deal with this. Alternatively, the current driving capability decreases when the gate oxide film is thick, so the gate width must be increased to compensate for this.

[0005] Also, a drive circuit that uses a CMOS level shift circuit to generate two types of voltages for driving a MOSFET is described in Patent Document 2. Also, Patent Document 3 describes a level shift circuit in which a p-type semiconductor region for an intermediate tap is provided in the p-type drain region of a semiconductor element (p-channel MOSFET P3) and the intermediate tap is connected to the gate of a power semiconductor element. The circuit in Patent Document 3 discloses that the gate oxide film of the switching element can be made thinner. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2004-96083 A [Patent Document 2] Japanese Patent Application Publication No. 5-308274 [Patent Document 3] Japanese Patent Application Publication No. 9-270699 Summary of the Invention [Problem to be solved by the invention]

[0007] In the technology described in Patent Document 3, the potential extracted from the intermediate tap electrode is lower than the potential extracted directly from the power supply voltage, but the potential extracted from the intermediate tap electrode increases in response to an increase in the drain-source voltage of the MOSFET in which the intermediate tap is provided.

[0008] For this reason, there has been a demand for a drive circuit, or a semiconductor element to be used therein, that allows the gate insulating film of the semiconductor element to be driven to be thin and that enables stable operation even when a relatively high-voltage power supply is used.

[0009] The present invention has been made in consideration of the above problems, and an object of the present invention is to provide an invention that solves the above problems. [Means for solving the problem]

[0010] In order to solve the above problems, the present invention has the following configuration. The semiconductor element (first) of the present invention comprises, on a surface of a semiconductor substrate, a first semiconductor region of p-type, a second semiconductor region of n-type formed on a surface within the first semiconductor region, a third semiconductor region of n-type formed away from the second semiconductor region, a fourth semiconductor region of n-type formed with a locally high impurity concentration on a side of the third semiconductor region away from the second semiconductor region, a gate electrode formed on the semiconductor substrate between the second semiconductor region and the third semiconductor region via an insulating film, a first main electrode connected to the second semiconductor region, and a second main electrode connected to the fourth semiconductor region, wherein a current flowing between the first main electrode and the second main electrode is controlled by the potential of the gate electrode, and further comprises a fifth semiconductor region of p-type formed locally between the fourth semiconductor region and the gate electrode on the surface of the third semiconductor region, and an auxiliary electrode connected to the fifth semiconductor region. A semiconductor element (second) of the present invention comprises, on a surface of a semiconductor substrate, a first semiconductor region of n type, a second semiconductor region of p type formed on a surface within the first semiconductor region, a third semiconductor region of p type formed away from the second semiconductor region, a fourth semiconductor region of p type formed with a locally high impurity concentration on a side of the third semiconductor region away from the second semiconductor region, a gate electrode formed on the semiconductor substrate between the second semiconductor region and the third semiconductor region via an insulating film, a first main electrode connected to the second semiconductor region, and a second main electrode connected to the fourth semiconductor region, wherein a current flowing between the first main electrode and the second main electrode is controlled by the potential of the gate electrode, and further comprises: a fifth semiconductor region of n type formed locally between the fourth semiconductor region and the gate electrode on the surface of the third semiconductor region, and an auxiliary electrode connected to the fifth semiconductor region. The composite semiconductor device of the present invention is characterized in that the second main electrode of the semiconductor device (first) and the second main electrode of the semiconductor device (second) are connected to each other. The drive circuit of the present invention is characterized in that the auxiliary electrode of the semiconductor element is electrically connected to a gate of another semiconductor element. The drive circuit of the present invention is a circuit for controlling the supply of power to a load connected to a point where the low-voltage side of a first power control element on the high-side side and the high-voltage side of a second power control element on the low-side side are connected, and is characterized in that the auxiliary electrode of the semiconductor element is connected to the gate of a switching element that outputs a signal to the gate of the first power control element. Effect of the Invention

[0011] Since the present invention is configured as described above, even if a relatively high-voltage power supply is used, it is possible to obtain a drive circuit that can thin the gate insulating film of the semiconductor element to be driven and that enables stable operation, or a semiconductor element and a composite semiconductor element used therein. [Brief description of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view showing a structure of a first example of a semiconductor element according to an embodiment of the present invention. [Diagram 2] 4 is a cross-sectional view showing a structure of a second example of a semiconductor element according to an embodiment of the present invention. [Diagram 3] 4 shows the results of calculating the relationship between the drain-source voltage and the auxiliary electrode-source voltage in the first example of the semiconductor element according to the embodiment of the present invention. [Figure 4] 1 shows the results of calculating a potential distribution during operation in a first example of a semiconductor element according to an embodiment of the present invention. [Diagram 5] 13 shows the results of calculating the relationship between the drain-source voltage and the auxiliary electrode-source voltage in a second example of a semiconductor element according to an embodiment of the present invention. [Figure 6] 13 is a result of calculating a potential distribution during operation in a second example of a semiconductor element according to an embodiment of the present invention. [Figure 7] 1 is a cross-sectional view showing a structure of a modified example of the first example of the semiconductor element according to the embodiment of the present invention. [Figure 8] FIG. 2 is a diagram showing a configuration of a first example of a drive circuit according to an embodiment of the present invention. [Figure 9] FIG. 1 is a diagram showing the symbolic correspondence between conventional normal MOSFETs (n-channel type, p-channel type) and semiconductor elements (n-channel type, p-channel type) according to an embodiment of the present invention. [Figure 10] FIG. 11 is a diagram showing the configuration of a second example of a conventional driving circuit. [Figure 11] FIG. 4 is a diagram showing a configuration of a second example of a drive circuit according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] First, a semiconductor device according to an embodiment of the present invention will be described below. This semiconductor device operates as a horizontal MOSFET, and can be realized as either an n-channel type or a p-channel type, similar to a normal MOSFET. These semiconductor devices can be used to configure a drive circuit (drive circuit) for a power semiconductor device, and in this power semiconductor device drive circuit, the gate insulating film of the next-stage semiconductor device driven by this semiconductor device can be made thin while still providing good operation.

[0014] 1 is a cross-sectional view showing a schematic structure of an n-channel element (semiconductor element) 1, which is an example of such a semiconductor element. Here, only the parts directly related to the present invention are shown in a simplified manner, and only the structure above the n-type layer (n layer 10), which is an epitaxial layer in a semiconductor substrate (silicon substrate), is shown.

[0015] A low-concentration n-type layer (n-layer 11) of an n-channel MOSFET is formed on the surface of n-layer 10. Note that n-layer 11 may be a low-concentration p-type layer instead of a low-concentration n-type layer. A low-concentration p-type layer (p-layer 12: first semiconductor region) that will become the body layer of the n-channel MOSFET is formed on the surface of n-layer 11. A high-concentration n-type layer (n +An n-type layer (n layer 14: third semiconductor region) which serves as a drain region and a drift region is formed on the surface of n layer 11. + It is formed apart from layer 13. + A gate electrode 22 is formed on the surface of the p-layer 12 between the layer 13 and the n-layer 14 via a thin gate insulating film (silicon oxide film: insulating film) 21. + A source electrode (first main electrode) 23 is connected to the layer 13, and the n-layer 14 is provided with a locally high-concentration n-type layer for contact at a location sufficiently separated from the gate electrode 22 in the horizontal direction. + A drain electrode (second main electrode) 24 is formed through a layer 15 (fourth semiconductor region). A p-type layer having a high concentration is formed locally on the surface of the p-layer 12 for contact. + A body electrode 25 is also formed through layer 16 .

[0016] In the above structure, when a voltage is applied between the drain electrode 24 and the source electrode 23, the current flowing between the drain electrode 24 and the source electrode 23 can be controlled on and off by controlling the voltage between the gate electrode 22 and the source electrode 23.

[0017] In this n-channel element 1, the drain electrode 24 (n + The surface of the n-layer 14 between the gate electrode 22 or the end of the n-layer 14 on the gate electrode 22 side is provided with p + A layer (fifth semiconductor region) 17 is formed, and this p + An auxiliary electrode 26 is connected to the layer 17. + Layer 15 and p + A buried oxide layer 27 made of a LOCOS oxide film or the like is formed on the surface of the n layer 14 between the layers 17 in order to provide electrical isolation therebetween. An insulating layer 28 is formed on the surface of the semiconductor substrate except where the electrodes are located.

[0018] 2 is a cross-sectional view showing a schematic structure of a p-channel type element 2, which is another example of this semiconductor element. In this structure, an n-layer 31 (first semiconductor region) is provided in an n-layer 10, which is a low-concentration n-type layer that is an epitaxial layer similar to that described above. + Layer (second semiconductor region) 33 and n + A layer 36 is provided, + A p-layer (third semiconductor region) 34 is provided as a drift region separated from the layer 33. + A layer (fourth semiconductor region) 35 is provided. + A gate electrode 42 is formed on the surface between the layer 33 and the p-layer 34 via a thin gate insulating film (silicon oxide film: insulating film) 41. + A source electrode (first main electrode) 43 is connected to the layer 33, and a p-type layer having a high concentration is formed locally in the p-layer 34 at a location sufficiently separated from the gate electrode 42 in the horizontal direction for contact. + A drain electrode (second main electrode) 44 is formed through a layer 35 (fourth semiconductor region). In addition, a drain electrode (second main electrode) 44 is formed through a layer 35 (fourth semiconductor region) ... + A body electrode 45 is also formed through the layer 36. + The layer (fifth semiconductor region) 37 is disposed in the p layer 34 so as to be closer to the p+ layer 33 than the p+ layer 35. + layer 35) and the gate electrode 42 or the end of the p-layer 34 on the gate electrode 42 side. + An auxiliary electrode 46 is connected to the layer 37. Note that the n-layer 10 may be a low-concentration p-type layer instead of a low-concentration n-type layer.

[0019] 1 and 2 show an n-channel element 1 and a p-channel element 2, respectively, but these can be formed on a common semiconductor substrate having an n-layer 10 to provide a composite semiconductor element. For example, by connecting the drain electrode 24 in Fig. 1 and the drain electrode 44 in Fig. 2, it can be used like a CMOS. Note that the gate insulating film 21 and the gate insulating film 41 are formed at the same time.

[0020] The details of the structure and operation of the n-channel element 1 in FIG. 1 will now be described.

[0021] The impurity concentration of the n-layer 14, which becomes the drift region, is set to 5×10 16 ~5×10 17 cm -3 On the other hand, when the n layer 14 is depleted, + Layer 17 is not depleted, so p + The impurity concentration of layer 17 is much higher, at 1×10 19 ~1×10 20 cm -3 When the voltage between the drain electrode 24 and the source electrode 23 is gradually increased during the off state, the depletion layer gradually expands from the pn junction interface between the n layer 11 and the p layer 12. When the voltage between the drain electrode 24 and the source electrode 23 is further increased, the depletion layer + When the voltage reaches layer 17 and is further increased, the depletion layer in n layer 14 expands further, but + Since the layer 17 is not completely depleted, + The potential of the layer 17 is saturated, and the increase in the potential of the auxiliary electrode 26 is suppressed compared to the increase in the potential of the drain electrode 24 .

[0022] The saturation potential of the auxiliary electrode 26 is the potential at the pn junction interface where the depletion layer in FIG. + The saturation potential depends on the lateral distance to layer 17, and the longer the distance, the higher the saturation potential becomes. If auxiliary electrode 26 is connected to the gate of a gate-driven switching element driven by n-channel element 1, the voltage applied to the gate of the switching element can be lowered even if the voltage applied to n-channel element 1 is relatively high. As a result, the gate insulating film of this switching element can be made thinner.

[0023] The details of the structure and operation of the p-channel element 2 in Fig. 2 will be described. The impurity concentration of the p-layer 34, which becomes the drift region, is set to 5 × 1016 ~5×10 17 cm -3 On the other hand, when the p-layer 34 is depleted, the n + Layer 37 is not depleted, so n + The impurity concentration of layer 37 is much higher, at 1×10 19 ~1×10 20 cm -3 When the voltage between the drain electrode 44 and the source electrode 43 is gradually increased during the off state, the depletion layer gradually expands from the pn junction interface between the n layer 10 and the p layer 34. When the voltage between the drain electrode 44 and the source electrode 43 is further increased, the depletion layer + When the voltage reaches layer 37 and is further increased, the depletion layer in p layer 34 expands further, but + The layer 37 is not completely depleted, and n + The potential of the layer 37 is saturated, and the increase in the potential of the auxiliary electrode 46 is suppressed compared to the increase in the potential of the drain electrode 44 .

[0024] The saturation potential of the auxiliary electrode 46 is the potential at the pn junction interface where the depletion layer in FIG. + The saturation potential depends on the lateral distance to layer 37, and the longer the distance, the higher the saturation potential becomes. That is, if auxiliary electrode 46 is connected to the gate of a gate-driven switching element driven by p-channel element 2, the voltage applied to the gate of the switching element can be lowered even if the voltage applied to p-channel element 2 is relatively high. As a result, the gate insulating film of this switching element can be made thinner.

[0025] FIG. 3 shows the n-channel element 1 of FIG. 1 with a gate oxide film thickness of 20 nm, an n-layer 11, a p-layer 12, an n-layer 14, and a p + The impurity concentration of layer 17 is (1×10 15 cm -3 , 1×10 17 cm -3 , 2×10 16 cm -3 , 1×10 19 cm -3 Let n layers be 14, p + The depth of layer 17 is 1.25 μm, 0.2 μm, and p+ When the width of the layer 17 is 1.1 μm and the distance between the p-layer 12 and the opposite end of the gate electrode 22 is 1.2 μm, + The figure shows the results of a simulation of the relationship between the drain-source voltage VDS and the auxiliary electrode-source voltage VxDS when the distance D between the layer 17 and the gate electrode 22 is set to 0.6 μm and 0.8 μm. As described above, even if VDS is increased, VxDS saturates at a certain voltage, and this saturation voltage is p + The location of layer 17 (gate electrode 22 and p + This can be adjusted by the distance D of the layer 17.

[0026] FIG. 4 shows equipotential lines (0.5 V apart) in the semiconductor substrate when the n-channel element 1 is off and VDS is set to 30 V, in the cases where the distance D between the gate electrode 22 and the p+ layer 17 is set to 0.6 μm (a) and where this distance D is set to 0.8 μm (b).

[0027] From this result, in the above setting, p + Layer 17 is not fully depleted, and p + It can be seen that the region near the surface between layer 17 and gate electrode 22 is fully depleted. + When the layer 17 is provided, p + Layer 17 and n + The surface side between the layers 15 (p + 1, a buried oxide layer 27 may be provided, as shown in Fig. 1. As described above, a LOCOS oxide film may be used as the buried oxide layer 27, but a trench oxide film, such as shallow trench isolation (STI), in which a CVD oxide film is buried in a groove (trench) formed by dry etching the substrate surface, may also be used.

[0028] FIG. 5 shows the relationship between the drain-source voltage VDS and the auxiliary electrode-source voltage VxDS in the p-channel element 2, as in FIG. 3, and FIG. 6(a) and (b) show equipotential lines (0.5 V intervals) in the semiconductor substrate when the p-channel element 2 is off and VDS is set to 20 V. Here, the n layer 10, the n layer 31, the p layer 34, the n + The impurity concentration of layer 37 is 1×10 15 cm -3 , 1×10 17 cm -3 , 2×10 16 cm -3 , 1×10 19 cm -3 ), the gate oxide film thickness is 20 nm, the depth of the p-layer 34 is 2.2 μm, and + The width of the layer 37 is 1.1 μm. + The distance D to the layer 37 is set to 0.6 μm and 0.8 μm as described above.

[0029] From Figure 5, even if VDS is increased, VxDS saturates at a certain voltage, and this saturation voltage is p + The location of layer 17 (gate electrode 22 and p + The distance between the layers 17 can be adjusted. + Layer 37 is not fully depleted, and n + It can be seen that the area between layer 37 and gate electrode 42 is fully depleted.

[0030] 7 is a cross-sectional view showing the structure of an n-channel element 3, which is a modification of the n-channel element 1. + The electric field strength at the surface of the n-layer 14 between the layer 17 and the area directly below the gate electrode 22 becomes locally high. + A buried oxide layer 29 is provided on the surface of the n-layer 14 between the layer 17 and immediately below the gate electrode 22. The buried oxide layer 29 can be a LOCOS oxide layer or a trench oxide layer. Similarly, in the p-channel element 2 of FIG. + A LOCOS oxide film or a trench oxide film may be provided on the surface of the p-layer 34 between the layer 37 and directly under the gate electrode 42 .

[0031] Fig. 8 is a diagram showing the configuration of a power semiconductor element drive circuit (drive circuit) 100 that uses the elements shown in Fig. 1 and Fig. 2. Here, power semiconductor elements S1 and S2 are provided as switching elements that turn on and off a coil CL. A point where the low voltage side of the high side power semiconductor element S1 and the high voltage side of the low side power semiconductor element S1 are connected is connected to one end of a coil CL as an example of a load.

[0032] Here, the symbolic correspondence between normal MOSFETs (n-channel, p-channel) and the n-channel element 1 and p-channel element 2 in Figures 1 and 2 is shown in Figure 9. In addition to the gate (G), source (S), and drain (D), the body electrode (B) is also shown, and the n-channel element 1 and p-channel element 2 are shown with the auxiliary electrode (PE) mentioned above added. The symbols shown here are used in Figure 8 and other figures.

[0033] In FIG. 8, the portion enclosed by the dashed line indicates the drive circuit, and a p-channel MOSFET P0 and an n-channel MOSFET N0 are connected to the gate of the high-side power semiconductor element S1. The gate of the p-channel MOSFET P0 is connected to the auxiliary electrode (PE) of the p-channel element P2. The gate of the p-channel element P2, which is the p-channel element 2, is connected to the auxiliary electrode (PE) of the p-channel element P1, which is the p-channel element 2. The gate of the n-channel element N2, which is the n-channel element 1, is connected to the auxiliary electrode (PE) of the n-channel element N1, which is the n-channel element 1, and the gate of the n-channel element N1 is connected to the auxiliary electrode (PE) of the n-channel element N2. As a result, the voltage of the gate connected to the auxiliary electrode (PE) is suppressed to the saturation voltage applied to the auxiliary electrode (PE), so that the potential of the gate connected to the auxiliary electrode (PE) can be made lower than the input voltage, and a thin gate insulating film can be used for this gate. That is, the gate insulating film of the p-channel MOSFET P0, the p-channel elements P1, P2, and the gate insulating film of the n-channel MOSFET N0, the n-channel elements N1, N2 can be uniformly thin and approximately the same thickness. Here, approximately the same thickness means that all of these gate insulating films are formed by a common oxidation process. In particular, the p-channel MOSFET P0 requires a relatively large current capacity to send a gate signal to the high-side power semiconductor element (IGBT) S1, and the effect of being able to use a thin gate insulating film is great. The same relationship is also established between the low-side n-channel MOSFET N0, the p-channel elements P4, P3 which are the p-channel element 2, and the n-channel elements N4, N3 which are the n-channel element 1.

[0034] A modification of the power semiconductor element drive circuit (drive circuit) 100 will be described. The effect of the present invention can be obtained even if one of the MOSFETs (p-channel MOSFET P0, p-channel elements P1, P2) constituting the CMOS is changed to a resistive load. In this case, although power consumption increases, since it is not necessary to form the p-channel MOSFET on the same chip, the manufacturing process can be simplified and the switching element drive circuit can be made inexpensive or compact.

[0035] First, the configuration of a conventional power semiconductor element drive circuit 910 using normal MOSFETs is shown in Fig. 10. Here, power semiconductor elements S11 and S12 are provided corresponding to the power semiconductor elements S1 and S2. Here, the configuration for controlling the gate voltage of power semiconductor element S11 is shown, and the configuration for controlling the gate voltage of power semiconductor element S12 is omitted.

[0036] The drain of an n-channel MOSFET (main switching element) N30 is connected to the gate of the power semiconductor element S11. The drain of an n-channel MOSFET N32 and the gate of an n-channel MOSFET N31 in the preceding stage are connected to the gate of the n-channel MOSFET N30. The gate of the n-channel MOSFET N32 is connected to the drain of the n-channel MOSFET N31. The operation of this power semiconductor element drive circuit (electrical circuit) 910 is also controlled by the input side switching element S01, and the power supply voltage used is also 25 V. A resistive load is provided between the power supply voltage and the n-channel MOSFETs N30, N31, and N32.

[0037] 11 shows a configuration in which a power semiconductor element drive circuit (drive circuit) 110 is used in which the n-channel MOSFETs N31, N32 are replaced with n-channel elements N21, N22, which are the above-mentioned n-channel element 1. Here, the n-channel MOSFET (main switching element) N20 in the final output stage is a normal MOSFET similar to the above-mentioned n-channel MOSFET N30.

[0038] Here, the gate of the n-channel MOSFET N20 is connected to an auxiliary electrode (PE) of an n-channel element N22 and the gate of an n-channel element N21. Also, the gate of the n-channel element N22 is connected to the auxiliary electrode (PE) of the n-channel element N21.

[0039] Even in this configuration, the gate voltage of the element (MOSFET) to which the auxiliary electrode (PE) is connected is kept low, so that the gate insulating film of the element to which the auxiliary electrode (PE) is connected can be made thin.

[0040] In the above example, a silicon substrate is used as the semiconductor substrate, and a MOS gate structure is used in which a silicon oxide film is used as the gate insulating film. However, the above configuration is also effective for switching elements using other semiconductor substrates and switching elements of MIS gate structure using other insulating films, since the thickness of the insulating film can be made thin and the chip can be made inexpensive. In addition, the power semiconductor elements S1, S2, S11, and S12 are not limited to IGBTs, and may be well-known power semiconductor elements such as MOSFETs and SJ-MOSFETs.

[0041] In addition, in electrical circuits other than the power semiconductor element drive circuit that drives the power semiconductor as described above, in which multiple types of MOSFETs with different operating voltages are used, the above n-channel element and p-channel element can be used in the same way, and by appropriately combining these, the MOSFET operating at a high voltage can be made to support a low voltage. This makes it possible to reduce the cost of the chip on which this electrical circuit is configured. [Explanation of symbols]

[0042] 1, 3, N1 to N4, N21, N22 n-channel element (semiconductor element) 2. P1 to P4 p-channel elements (semiconductor elements) 10, 11 n-layer 12 p layer (first semiconductor region) 13 n + layer (second semiconductor region) 14 n layer (third semiconductor region) 15 n + layer (fourth semiconductor region) 16 pages + layer 17 p + Layer (fifth semiconductor region) 21, 41 Gate oxide film (gate insulating film) 22, 42, G gate electrode 23, 43, S Source electrode (first main electrode) 24, 44, D Drain electrode (second main electrode) 25, 45, B Body Electrode 26, 46, PE auxiliary electrode 27, 29, 47 Buried oxide layer 28, 48 Insulation layer 31 n layer (first semiconductor region) 33 p + layer (second semiconductor region) 34 p layer (third semiconductor region) 35 p + layer (fourth semiconductor region) 36n + layer 37 n + Layer (fifth semiconductor region) 100, 110, 910 Power semiconductor element drive circuit (drive circuit) CL coil N0 n-channel MOSFET (second main switching element) N31, N32 n-channel MOSFETs N20, N30 n-channel MOSFET (main switching element) P0 p-channel MOSFET (first main switching element) S1, S2, S11, S12 Power semiconductor elements (power control elements) S01, S02 Input side switching element

Claims

1. On a surface of a semiconductor substrate, A first semiconductor region of p-type; A second semiconductor region which is n-type and is formed on a surface of the first semiconductor region; a third semiconductor region of n-type formed apart from the second semiconductor region; an n-type fourth semiconductor region having a locally high impurity concentration formed on a side of the third semiconductor region away from the second semiconductor region; a gate electrode formed on the semiconductor substrate between the second semiconductor region and the third semiconductor region via an insulating film; A first main electrode connected to the second semiconductor region; A second main electrode connected to the fourth semiconductor region; Equipped with a current flowing between the first main electrode and the second main electrode is controlled by a potential of the gate electrode; a p-type fifth semiconductor region locally formed on a surface of the third semiconductor region between the fourth semiconductor region and the gate electrode; an auxiliary electrode connected to the fifth semiconductor region; A semiconductor device comprising:

2. On a surface of a semiconductor substrate, a first semiconductor region of n-type; A second semiconductor region which is p-type and is formed on a surface of the first semiconductor region; a p-type third semiconductor region formed apart from the second semiconductor region; a fourth semiconductor region of p-type having a locally high impurity concentration formed on a side of the third semiconductor region away from the second semiconductor region; a gate electrode formed on the semiconductor substrate between the second semiconductor region and the third semiconductor region via an insulating film; A first main electrode connected to the second semiconductor region; A second main electrode connected to the fourth semiconductor region; Equipped with a current flowing between the first main electrode and the second main electrode is controlled by a potential of the gate electrode; a fifth semiconductor region of n-type locally formed on a surface of the third semiconductor region between the fourth semiconductor region and the gate electrode; an auxiliary electrode connected to the fifth semiconductor region; A semiconductor device comprising:

3. 3. The semiconductor device according to claim 1, wherein the fifth semiconductor region has an impurity concentration higher than an impurity concentration of the third semiconductor region.

4. 4. The semiconductor element according to claim 3, wherein a LOCOS oxide film or a trench oxide film is formed on the surface of the third semiconductor region between a portion to which the second main electrode is connected and the fifth semiconductor region.

5. 3. A composite semiconductor device, comprising: the second main electrode of the semiconductor device according to claim 1 and the second main electrode of the semiconductor device according to claim 2, connected to each other.

6. 3. A drive circuit comprising: a semiconductor element according to claim 1, wherein the auxiliary electrode of the semiconductor element is electrically connected to a gate of another semiconductor element.

7. a switching element for applying a signal to a gate of a power control element for controlling the supply of power to a load; 7. The drive circuit according to claim 6, wherein the auxiliary electrode of the semiconductor element according to claim 1 or 2 is electrically connected to a gate electrode of the switching element.

8. A semiconductor device comprising: a first semiconductor element which is the semiconductor element according to claim 1 or 2; and a second semiconductor element having a MOS structure and gate-driven at a lower voltage than the first semiconductor element, the second semiconductor element being disposed on the semiconductor substrate; 7. The drive circuit according to claim 6, wherein the thickness of the insulating film of the first semiconductor element and the thickness of the insulating film of the MOS structure of the second semiconductor element are substantially the same.

9. A circuit for controlling power supply to a load connected to a point where a low voltage side of a first power control element on a high side and a high voltage side of a second power control element on a low side are connected, 3. A drive circuit, comprising: a gate of a switching element which outputs a signal to a gate of the first power control element; and a gate of the semiconductor element according to claim 1, the auxiliary electrode of the semiconductor element being connected to the gate of the switching element.

Images