Display panel, manufacturing method thereof, and head-mounted display device

Abstract

To provide a display panel, a manufacturing method thereof, and a head-mounted display device that can control the angle of emitted light.SOLUTION: A display panel DP comprises: a substrate; a pixel circuit layer disposed on the substrate and including at least one switching element and at least one storage element; a light-emitting element layer including light-emitting elements electrically connected to the pixel circuit layer and disposed on the pixel circuit layer; an overcoat layer disposed on the light-emitting element layer and having a first refractive index; and a cover window disposed on the overcoat layer and having a second refractive index greater than the first refractive index. At least one of the overcoat layer and the cover window includes a plurality of inclined surfaces, and inclination angles of the plurality of inclined surfaces in a central area of the substrate are different from those in an edge area of the substrate. The display panel, a manufacturing method thereof, and a head-mounted display device can control the angle of emitted light.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] An embodiment of the present disclosure relates to a display panel, a manufacturing method thereof, and a head-mounted display device. [Background technology]

[0002] As information technology develops, the importance of display devices, which are a connection medium between users and information, is increasing. Accordingly, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0003] 2. Description of the Related Art Since a display device displays an image in an area close to the user's eyes, various researches are being conducted on techniques for controlling the angle at which light is emitted from a display device (or a display panel of a display device). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2020 / 111101 Summary of the Invention [Problem to be solved by the invention]

[0005] The technical problem to be solved by the present invention is to provide a display panel in which the angle of emitted light is controlled, a manufacturing method thereof, and a head-mounted display device. [Means for solving the problem]

[0006] An embodiment of the present disclosure can provide a display panel including a substrate, a pixel circuit layer disposed on the substrate and including one or more switching elements and one or more storage elements, a light emitting element layer including a light emitting element electrically coupled to the pixel circuit layer and disposed on the pixel circuit layer, an overcoat layer disposed on the light emitting element layer and having a first refractive index, and a cover window disposed on the overcoat layer and having a second refractive index greater than the first refractive index, at least one of the overcoat layer and the cover window including a plurality of inclined surfaces, and inclination angles of the plurality of inclined surfaces are different in a central region of the substrate and an edge region of the substrate.

[0007] The inclination angle of the plurality of inclined surfaces may be smallest in a central region of the display panel and largest in an edge region of the display panel.

[0008] In the central region of the display panel, light emitted from the light-emitting element may be emitted in a normal direction to the substrate, and in the edge region of the display panel, light emitted from the light-emitting element may be emitted in a direction toward the outer periphery of the substrate, which is different from the normal direction to the substrate.

[0009] The overcoat layer may include a plurality of inclined surfaces, the height of which may increase from the outer side to the inner side of the substrate.

[0010] The cover window may include a plurality of inclined surfaces, the height of which may increase from the inner side to the outer side of the substrate.

[0011] Each of the plurality of inclined surfaces can be arranged in units of light emitting elements.

[0012] Two or more light emitting elements may be arranged in the light emitting element layer, and each of the plurality of inclined surfaces may be arranged in units of two or more light emitting elements.

[0013] At least a portion of the plurality of inclined surfaces may be positioned on a vertical line of the light emitting element, shifted toward an outer side of the substrate.

[0014] The light emitting device may further include an optical function layer located between the light emitting element layer and the overcoat layer. The optical function layer may include a color filter layer including a color filter configured to convert a wavelength band of light emitted from the light emitting element, and a lens array including lenses. The optical function layer may be positioned by moving in the same direction as at least a part of the plurality of inclined surfaces.

[0015] The overcoat layer may include an epoxy resin having a first refractive index and the cover window may include a glass having a second refractive index. The first refractive index may be between 1.2 and 1.4 and the second refractive index may be between 1.5 and 1.9.

[0016] An embodiment of the present disclosure may provide a method for manufacturing a display panel, including the steps of preparing a lower substrate, forming an overcoat layer on the lower substrate, pressing the lower substrate on which the overcoat layer is formed with a stamp including an inclined surface mold, forming an inclined surface corresponding to the inclined surface mold, and forming a cover window on the overcoat layer.

[0017] In the step of pressing with a stamp, the stamp may press the upper surface of the overcoat layer, and in the step of forming the inclined surface, an inclined surface may be formed on the overcoat layer.

[0018] In the step of forming a cover window, a glass having a sloped surface on its underside corresponding to the sloped surface of the overcoat layer can be placed on the overcoat layer.

[0019] The method for manufacturing a display panel according to an embodiment of the present disclosure may further include applying a photoresist onto the overcoat layer. In the step of pressing with a stamp, the stamp presses the photoresist, and an inclined surface corresponding to the inclined surface mold may be formed on the photoresist.

[0020] The method for manufacturing a display panel according to an embodiment of the present disclosure may further include an etching step, in which an etcher etches the photoresist and the overcoat layer on which the inclined surface is formed, and in the inclined surface forming step, an inclined surface corresponding to the inclined surface mold may be formed on the overcoat layer.

[0021] In the step of preparing the lower substrate, a pixel circuit layer, a light emitting element layer, a thin film encapsulation layer, an adhesive layer, a color filter layer, and a lens array can be sequentially formed on the substrate.

[0022] An embodiment of the present disclosure can provide a head-mounted display device including: a first display panel disposed within a display storage case and having a protective layer arranged on the top layer which includes a plurality of inclined surfaces; a right-eye lens disposed within the display storage case and configured to refract light refracted by the plurality of inclined surfaces of the first display panel again toward the user's right eye; a second display panel positioned apart from the first display panel within the display storage case and having a protective layer arranged on the top layer which includes a plurality of inclined surfaces; and a left-eye lens disposed within the display storage case and configured to refract light refracted by the plurality of inclined surfaces of the second display panel again toward the user's left eye.

[0023] Light emitted from the central region of the first display panel is incident on the central region of the right eye lens, light emitted from the edge region of the first display panel is incident on the edge region of the right eye lens, light emitted from the central region of the second display panel is incident on the central region of the left eye lens, and light emitted from the edge region of the second display panel is incident on the edge region of the left eye lens.

[0024] Each of the first display panel and the second display panel includes a substrate, a pixel circuit layer disposed on the substrate and including one or more switching elements and one or more storage elements, a light emitting element layer including a light emitting element electrically connected to the pixel circuit layer and disposed on the pixel circuit layer, an overcoat layer disposed on the light emitting element layer and having a first refractive index, and a cover window disposed on the overcoat layer and having a second refractive index greater than the first refractive index, at least one of the overcoat layer and the cover window includes a plurality of inclined surfaces, and the inclination angles of the plurality of inclined surfaces can be different in a central region of the substrate and an edge region of the substrate.

[0025] The inclination angles of the plurality of inclined surfaces may increase as they move away from the central region of the substrate. Effect of the Invention

[0026] According to the display panel, the manufacturing method thereof, and the head mounted display device according to the embodiments of the present disclosure, the angle of emitted light can be controlled. [Brief description of the drawings]

[0027] [Figure 1] FIG. 1 is a system block diagram of a display device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a block diagram showing an embodiment of one of the sub-pixels of FIG. 1. [Diagram 3] 3 is an equivalent circuit diagram according to one embodiment of the sub-pixel of FIG. 2. [Figure 4] FIG. 2 is a plan view of an embodiment of the display panel of FIG. [Diagram 5] 5 is an exploded perspective view showing a part of the display panel of FIG. 4. [Figure 6] FIG. 6 is a plan view showing one of the pixels of FIG. 5 according to an embodiment; [Figure 7] 7 is an example of a cross-sectional view of the pixel of FIG. 6 taken along line II'. [Figure 8] 10A and 10B are diagrams illustrating exemplary angles at which light is emitted from a display panel according to an embodiment of the present disclosure. [Figure 9] 9 is a cross-sectional view illustrating an angle at which light is emitted from a first pixel according to the embodiment of FIG. 8. [Figure 10a] 9 is an example of a cross-sectional view for explaining an angle at which light is emitted from a second pixel according to the embodiment of FIG. 8; [Figure 10b] 9 is another example of a cross-sectional view illustrating an angle at which light is emitted from a second pixel according to the embodiment of FIG. 8; [Figure 10c] 9 is yet another example of a cross-sectional view illustrating an angle at which light is emitted from a second pixel according to the embodiment of FIG. 8; [Figure 11] 9 is a cross-sectional view illustrating an angle at which light is emitted from a third pixel according to the embodiment of FIG. 8. [Figure 12] 9 is a cross-sectional view illustrating an angle at which light is emitted from a fourth pixel according to the embodiment of FIG. 8. [Figure 13] 9 is a cross-sectional view illustrating an angle at which light is emitted from a fifth pixel according to the embodiment of FIG. 8. [Figure 14a] FIG. 2 is an example of a top view of a display panel according to an embodiment of the present disclosure. [Figure 14b] 1 is an example of a side view of a display panel according to an embodiment of the present disclosure. [Figure 14c] 1 is an example of a side view of a display panel according to an embodiment of the present disclosure. [Figure 14d] 1 is an example of a side view of a display panel according to an embodiment of the present disclosure. [Figure 14e] 1 is an example of a side view of a display panel according to an embodiment of the present disclosure. [Figure 15] 9 is a cross-sectional view illustrating an angle at which light is emitted from a first pixel according to another embodiment of FIG. 8. [Figure 16a] 9 is an example of a cross-sectional view illustrating an angle at which light is emitted from a second pixel according to another embodiment of FIG. 8; [Figure 16b] 9 is another example of a cross-sectional view illustrating an angle at which light is emitted from a second pixel according to another embodiment of FIG. 8; [Figure 17] 9 is another example of a cross-sectional view illustrating an angle at which light is emitted from a third pixel according to another embodiment of FIG. 8; [Figure 18] 9 is another example of a cross-sectional view for explaining the angle at which light is emitted from the fourth pixel in FIG. 8. [Figure 19] 9 is another example of a cross-sectional view for explaining the angle at which light is emitted from the fifth pixel in FIG. 8. [Figure 20a] FIG. 2 is an example of a top view of a display panel according to an embodiment of the present disclosure. [Figure 20b] 1 is an example of a side view of a display panel according to an embodiment of the present disclosure. [Figure 20c] 1 is an example of a side view of a display panel according to an embodiment of the present disclosure. [Figure 21] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 22] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 23] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 24] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure. [Diagram 25] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 26] 11A to 11D are diagrams illustrating a method for manufacturing a display panel according to another embodiment of the present disclosure. [Figure 27] 11A to 11D are diagrams illustrating a method for manufacturing a display panel according to another embodiment of the present disclosure. [Figure 28] 11A to 11D are diagrams illustrating a method for manufacturing a display panel according to another embodiment of the present disclosure. [Figure 29] 11A to 11D are diagrams illustrating a method for manufacturing a display panel according to another embodiment of the present disclosure. [Diagram 30] 11A to 11D are diagrams illustrating a method for manufacturing a display panel according to another embodiment of the present disclosure. [Diagram 31] 11A to 11C are other diagrams illustrating the manufacturing method of the display panel according to the embodiment of the present disclosure. [Diagram 32] 11A to 11C are other diagrams illustrating the manufacturing method of the display panel according to the embodiment of the present disclosure. [Diagram 33]11A to 11C are other diagrams illustrating the manufacturing method of the display panel according to the embodiment of the present disclosure. [Diagram 34] 11A to 11C are other diagrams illustrating the manufacturing method of the display panel according to the embodiment of the present disclosure. [Diagram 35] 11A to 11C are other diagrams illustrating the manufacturing method of the display panel according to the embodiment of the present disclosure. [Diagram 36] 11A to 11C are other diagrams illustrating the manufacturing method of the display panel according to the embodiment of the present disclosure. [Figure 37] 11A to 11C are other diagrams illustrating the manufacturing method of the display panel according to the embodiment of the present disclosure. [Figure 38] FIG. 2 illustrates a lens array according to an embodiment of the present disclosure. [Figure 39] FIG. 2 illustrates a lens array according to an embodiment of the present disclosure. [Diagram 40] FIG. 2 illustrates a lens array according to an embodiment of the present disclosure. [Diagram 41] FIG. 1 illustrates an embodiment of a display system according to an embodiment of the present disclosure. [Diagram 42] FIG. 42 is a perspective view showing an application example of the display system of FIG. [Diagram 43] FIG. 1 is a diagram showing a head-mounted display device worn by a user. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings, in which: FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present invention;

[0029] In order to clearly explain the present invention, parts that are not relevant to the description will be omitted, and the same reference numerals will be used throughout the specification to refer to the same or similar components. Therefore, the same reference numerals can be used in other drawings.

[0030] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, thicknesses may be exaggerated to clearly show multiple layers and regions.

[0031] In addition, "the same" in the description includes cases where it means "substantially the same." In other words, it includes cases where it is the same to the extent that a person with ordinary skill in the art would be convinced that it is the same. Other expressions may also omit "substantially."

[0032] Terms such as first and second are used to describe various components, but the components should not be limited by said terms. The terms are used only for the purpose of distinguishing one component from another component. For example, a first component can be called a second component, and similarly, a second component can be called a first component, without departing from the scope of the present invention. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0033] Terms such as "under", "below", "up" and "above" are used to describe the relative relationships of features shown in the drawings. The terms are relative concepts and will be described with reference to the directions shown in the drawings.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and are expressly defined herein, unless interpreted in an idealized or overly formal sense.

[0035] It should be understood that terms such as "comprise" or "have" are intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof that are stated in the specification, but do not preclude the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0036] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] FIG. 1 is a system block diagram of a display device 100 according to an embodiment of the present disclosure.

[0038] Referring to FIG. 1, a display device 100 according to an embodiment of the present disclosure may include a display panel 110, a gate driving circuit 120, a data driver 130, a voltage generator 140, a controller 150, a temperature sensor 160, and the like.

[0039] The display panel 110 may include a plurality of sub-pixels SP. The display panel 110 may be arranged with first to m-th gate lines GL1 to GLm (m is an integer of 2 or more) connected to the plurality of sub-pixels SP. The display panel 110 may be arranged with first to n-th data lines DL1 to DLn (n is an integer of 2 or more) connected to the plurality of sub-pixels SP.

[0040] The sub-pixels SP may be connected (e.g., electrically connected) to the gate driving circuit 120 via the first to m-th gate lines GL1 to GLm. The sub-pixels SP may be connected (e.g., electrically connected) to the data driver 130 via the first to n-th data lines DL1 to DLn.

[0041] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. Each of the sub-pixels SP may generate light of a color (e.g., a specific color or a specific wavelength band), such as red, green, blue, cyan, magenta, yellow, etc. Two or more sub-pixels of the sub-pixels SP may constitute one pixel PXL. For example, as shown in FIG. 1, three sub-pixels may constitute one pixel PXL.

[0042] The gate driving circuit 120 may be connected (e.g., electrically connected) to a plurality of sub-pixels SP (e.g., a plurality of sub-pixels SP generally arranged in a first direction DR1) via first to m-th gate lines GL1 to GLm. The first direction DR1 may be, for example, a direction crossing the display panel 110 from one side (e.g., the left side) to the other side (e.g., the right side). The first direction DR1 may be, for example, a row direction.

[0043] The gate driving circuit 120 may output gate signals (e.g., gate signals of turn-on or turn-off levels) to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with the timing at which a data signal is applied, and the like.

[0044] In the embodiment, the display panel 110 may further include first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP. The first to m-th emission control lines EL1 to ELm may be arranged extending in the row direction from the display panel 110. The sub-pixels SP may be connected (e.g., electrically connected) to the first to m-th emission control lines EL1 to ELm. In the above embodiment, the gate driving circuit 120 may include a emission control driver configured to control the first to m-th emission control lines EL1 to ELm. The emission control driver may operate according to the control of the controller 150.

[0045] The gate drive circuit 120 may be disposed on one side of the display panel 110. However, embodiments are not limited thereto. For example, the gate drive circuit 120 may be divided into two or more physically and / or logically divided drive circuits, and such drive circuits may be disposed on one side and the other side of the display panel 110 (e.g., the other side of the display panel 110 opposite the one side). In this manner, the gate drive circuit 120 may be disposed within or around the display panel 110 in various forms depending on the embodiment.

[0046] The data driver 130 may be connected (e.g., electrically connected) to a plurality of sub-pixels SP (e.g., a plurality of sub-pixels SP generally arranged in a second direction DR2) via first to n-th data lines DL1 to DLn. The second direction DR2 may be, for example, a direction crossing the display panel 110 from one side (e.g., a lower side) to the other side (e.g., an upper side). The second direction DR2 may be, for example, a column direction.

[0047] The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0048] The data driver 130 may apply a data signal having a gray scale voltage corresponding to the image data DATA to the first to n-th data lines DL1 to DLn using a voltage (e.g., a gamma voltage Vgamma) from the voltage generator 140. When a gate signal (e.g., a gate signal of a turn-on level) is applied to each of the first to m-th gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the data lines DL1 to DLm. Each of the plurality of sub-pixels SP may receive an input of a data signal applied at a corresponding timing in response to the gate signal (e.g., a gate signal of a turn-on level). The plurality of sub-pixels SP may generate light corresponding to the input data signal. As a result, an image may be displayed on the display panel 110.

[0049] In an embodiment, the gate drive circuit 120 and the data driver 130 may each include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0050] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 can be configured to generate a plurality of voltages and provide the generated voltages to the components of the display device 100. For example, the voltage generator 140 can receive an input voltage from outside the display device 100. The voltage generator 140 can adjust (e.g., lower) a level of the received voltage and regulate the voltage whose level is adjusted. The voltage generator 140 can be configured to generate a plurality of voltages.

[0051] The voltage generator 140 may generate, for example, a first power supply voltage VDD, a second power supply voltage VSS, a gamma voltage Vgamma, etc. The generated first and second power supply voltages VDD and VSS may be applied (e.g., commonly applied) to a plurality of sub-pixels SP. The first power supply voltage VDD may have a relatively high voltage level. The second power supply voltage VSS may have a voltage level lower than the first power supply voltage VDD. The generated gamma voltage Vgamma may be provided to the data driver 130. In another embodiment, the first power supply voltage VDD and / or the second power supply voltage VSS may be provided by an external device (e.g., a power management integrated circuit (PMIC)) of the display device 100.

[0052] According to the embodiment, the voltage generator 140 may generate other voltages. For example, the voltage generator 140 may generate an initialization voltage to be applied (for example, commonly applied) to the plurality of sub-pixels SP. For example, during a sensing operation for sensing electrical characteristics of the transistors and / or light emitting elements of the plurality of sub-pixels SP, a predetermined reference voltage may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate such reference voltage.

[0053] The controller 150 may be configured to control the overall operation of the display device 100. The controller 150 may receive input image data IMG from the outside and a control signal CTRL for controlling the display thereof. The controller 150 may provide a gate control signal GCS, a data control signal DCS, a voltage control signal VCS, etc. in response to the received control signal CTRL.

[0054] The controller 150 may convert the input image data IMG to be compatible with the display device 100 or the display panel 110, and output the image data DATA. In an embodiment, the controller 150 may align the input image data IMG to be compatible with the sub-pixels SP arranged in rows, and output the image data DATA.

[0055] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 can be implemented in one integrated circuit. As shown in FIG. 1, the data driver 130, the voltage generator 140, and the controller 150 can be included in a driver integrated circuit DIC. In such a case, the data driver 130, the voltage generator 140, and the controller 150 can be functionally separate components in one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 can be implemented in the driver integrated circuit DIC, and the other can be provided implemented in an integrated circuit separate from the driver integrated circuit DIC.

[0056] The temperature sensor 160 is configured to sense a temperature (e.g., a temperature of its surroundings) and generate temperature data TEP representing the sensed temperature. According to an embodiment, the temperature sensor 160 may be disposed in the display panel 110. According to an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC. According to an embodiment, the display device 100 may include two or more temperature sensors 160.

[0057] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may adjust at least one of a data signal, a first power supply voltage VDD, and a second power supply voltage VSS input to the display panel 110 by controlling components such as the data driver 130 and / or the voltage generator 140.

[0058] FIG. 2 is a block diagram showing an embodiment of any one of the sub-pixels SPij of FIG.

[0059] FIG. 2 exemplarily shows the subpixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and j-th column (j is an integer greater than or equal to 1 and less than or equal to n) of the multiple subpixels SP shown in FIG.

[0060] Referring to FIG. 2, the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0061] The light emitting element LD may be connected (e.g., electrically connected) between a first power supply voltage node VDDN and a second power supply voltage node VSSN. The first power supply voltage node VDDN may be a node to which the first power supply voltage VDD in FIG 1 is applied. The second power supply voltage node VSSN may be a node to which the second power supply voltage VSS in FIG 1 is applied.

[0062] The light emitting element LD may include a first electrode, a light emitting structure EMS, and a second electrode. The first electrode may be any one of the anode electrode AE ​​and the cathode electrode CE of the light emitting element LD. The second electrode may be the other one of the anode electrode AE ​​and the cathode electrode CE of the light emitting element LD. Hereinafter, for convenience of explanation, an example will be given in which the first electrode of the light emitting element LD is the anode electrode AE ​​and the second electrode of the light emitting element LD is the cathode electrode CE.

[0063] An anode electrode AE ​​of the light emitting element LD may be connected (e.g., electrically connected) to a first power supply voltage node VDDN via a sub-pixel circuit SPC. A cathode electrode CE of the light emitting element LD may be connected (e.g., electrically connected) to a second power supply voltage node VSSN. For example, an anode electrode AE ​​of the light emitting element LD may be connected (e.g., electrically connected) to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0064] The sub-pixel circuit SPC of the sub-pixel SPij may be connected (e.g., electrically connected) to the ith gate line GLi of the first to mth gate lines GL1 to GLm of FIG. 1. The sub-pixel circuit SPC of the sub-pixel SPij may be connected (e.g., electrically connected) to the ith emission control line ELi of the first to mth emission control lines EL1 to ELm of FIG. 1. The sub-pixel circuit SPC of the sub-pixel SPij may be connected (e.g., electrically connected) to the jth data line DLj of the first to nth data lines DL1 to DLn of FIG. 1. The sub-pixel circuit SPC is configured to control the emission timing and / or emission brightness of the light emitting element LD according to (or in response to) signals received via such signal lines.

[0065] The sub-pixel circuit SPC may operate in response to a gate signal received via an i-th gate line GLi. The sub-pixel circuit SPC may operate in response to a light emission control signal received via an i-th light emission control line ELi.

[0066] The sub-pixel circuit SPC may receive a data signal via a j-th data line DLj. The sub-pixel circuit SPC may store a voltage of the data signal (or a voltage corresponding to the data signal) in response to a gate signal (e.g., a gate signal of a turn-on level) received via the ith gate line GLi. The sub-pixel circuit SPC may adjust a timing at which a current flows to the light emitting element LD in response to a light emitting control signal (e.g., a light emitting control signal of a turn-on level) applied via the ith light emitting control line ELi. The magnitude of the current flowing to the light emitting element LD may vary depending on the voltage stored in the sub-pixel circuit SPC. The light emitting element LD may generate light of a brightness corresponding to the data signal.

[0067] FIG. 3 is an equivalent circuit diagram according to an embodiment of the sub-pixel SPij of FIG.

[0068] 3, the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD. The sub-pixel circuit SPC may be connected (e.g., electrically connected) to the i-th gate line GLi, the i-th light-emitting control line ELi, and the j-th data line DLj.

[0069] The i-th gate line GLi may include two or more sub-gate lines. Referring to FIG 3, the i-th gate line GLi may include a first sub-gate line SGL1, a second sub-gate line SGL2, and a third sub-gate line SGL3.

[0070] The i-th light-emitting control line ELi may include two or more sub-light-emitting control lines. Referring to FIG 3, the i-th light-emitting control line ELi may include a first sub-light-emitting control line SEL1 and a second sub-light-emitting control line SEL2.

[0071] The sub-pixel circuit SPC may include two or more switching elements (e.g., transistors) and one or more storage elements (e.g., capacitors). Referring to Fig. 3, the sub-pixel circuit SPC according to the embodiment of the present disclosure may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2.

[0072] The first transistor T1 may be connected between a first power supply voltage node VDDN and a first node N1. Referring to FIG. 3, the first transistor T1 may be connected between a sixth transistor T6 and the first node N1. A gate of the first transistor T1 may be connected (e.g., electrically connected) to a second node N2. The first transistor T1 may be turned on according to a voltage level of the second node N2. The magnitude of a current (e.g., a driving current) flowing through the first transistor T1 may be controlled to be different according to the voltage level of the second node N2. The first transistor T1 may be referred to as a driving transistor.

[0073] The second transistor T2 may be coupled between the j-th data line DLj and a second node N2. Referring to FIG. 3, the second transistor T2 may be configured to switch an electrical connection between the j-th data line DLj and the first capacitor C1. A gate of the second transistor T2 may be coupled to a first sub-gate line SGL1. The second transistor T2 may be controlled in response to a first gate signal SCAN1 applied to the first sub-gate line SGL1. The second transistor T2 may be turned on in response to the first gate signal SCAN1 at a turn-on level. The second transistor T2 may be referred to as a switching transistor.

[0074] The third transistor T3 may be configured to switch an electrical connection between the first node N1 and the second node N2. A gate of the third transistor T3 may be coupled (e.g., electrically coupled) to a second sub-gate line SGL2. The third transistor T3 may be controlled in response to a second gate signal SCAN2 applied to the second sub-gate line SGL2. The third transistor T3 may be turned on in response to the second gate signal SCAN2 having a turn-on level.

[0075] The fourth transistor T4 may be connected between the first node N1 and the anode electrode AE ​​of the light emitting element LD. Referring to FIG. 3, the fourth transistor T4 may be configured to switch an electrical connection between the first node N1 and the fourth node N4. A gate of the fourth transistor T4 may be connected to a second sub-emission control line SEL2. The fourth transistor T4 may be controlled in response to a second emission control signal EM2 applied to the second sub-emission control line SEL2. The fourth transistor T4 may be turned on in response to the second emission control signal EM2 having a turn-on level.

[0076] The fifth transistor T5 may be connected between the anode electrode AE ​​of the light emitting element LD and an initialization voltage node VINTN. Referring to FIG. 3, the fifth transistor T5 may be configured to switch an electrical connection between the fourth node N4 and the initialization voltage node VINTN. The initialization voltage node VINTN is configured to transmit an initialization voltage VINT. In an embodiment, the initialization voltage VINT may be provided by the voltage generator 140 of FIG. 1. In another embodiment, the initialization voltage VINT may be provided by an external device (e.g., a power management circuit (PMIC)) separate from the display device 100. A gate of the fifth transistor T5 may be connected (e.g., electrically connected) to a third sub-gate line SGL3. The fifth transistor T5 may be controlled in response to a third gate signal SCAN3 applied to the third sub-gate line SGL3. The fifth transistor T5 may be turned on in response to the third gate signal SCAN3 of a turn-on level.

[0077] The sixth transistor T6 may be connected between a first power supply voltage node VDDN and the first transistor T1. Referring to FIG. 3, the sixth transistor T6 may be configured to switch an electrical connection between the third node N3 and the first transistor T1. A gate of the sixth transistor T6 may be connected to a first sub-emission control line SEL1. The sixth transistor T6 may be controlled in response to a first light-emitting control signal EM1 applied to the first sub-emission control line SEL1. The sixth transistor T6 may be turned on in response to the first light-emitting control signal EM1 having a turn-on level.

[0078] The first capacitor C1 may be coupled between the second transistor T2 and the second node N2. The first capacitor C1 may include an electrode on one side coupled (e.g., electrically coupled) to the second transistor T2 and an electrode on the other side coupled (e.g., electrically coupled) to the second node N2. Due to a coupling phenomenon of the first capacitor C1, a data voltage Vdata (or a voltage corresponding to the data voltage Vdata) may be applied to the second node N2.

[0079] The second capacitor C2 may be coupled between the third node N3 and the second node N2. The second capacitor C2 may include an electrode on one side coupled (e.g., electrically coupled) to the second node N2 and an electrode on the other side coupled (e.g., electrically coupled) to the third node N3. The second capacitor C2 may be configured to maintain a voltage difference between the second node N2 and the third node N3.

[0080] The first capacitor C1 and the second capacitor C2 may not be parasitic capacitors, for example, the first capacitor C1 and the second capacitor C2 may be intentionally formed capacitors.

[0081] As described above, the sub-pixel circuit SPC may include the first to sixth transistors T1 to T6 and the first and second capacitors C1, C2. However, the embodiments of the present disclosure are not limited to those described above. The sub-pixel circuit SPC may be realized by any one of various types of circuits including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. According to the embodiments of the sub-pixel circuit SPC, the number of sub-gate lines SGL included in the i-th gate line GLi may be different. According to the embodiments, the number of sub-emission control lines SEL included in the i-th emission control line ELi may be different.

[0082] Referring to FIG. 3, each of the first to sixth transistors T1 to T6 may be a P-type transistor (e.g., a transistor including a P-type semiconductor). At least one of the first to sixth transistors T1 to T6 may be a Metal Oxide Silicon Field Effect Transistor (MOSFET). However, the embodiments of the present disclosure are not limited thereto. For example, at least one of the first to sixth transistors T1 to T6 may be replaced with an N-type transistor (e.g., a transistor including an N-type semiconductor).

[0083] In the embodiment, the first to sixth transistors T1 to T6 may include an amorphous silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0084] The light emitting element LD may include an anode electrode AE, a cathode electrode CE, and a light emitting structure EMS. The light emitting structure EMS may be disposed between the anode electrode AE ​​and the cathode electrode CE. A data signal Vdata written to the sub-pixel SPij via a data line DL (e.g., the j-th data line DLj) may be reflected as a voltage of the second node N2 due to a coupling phenomenon of the first capacitor C1. When the first and second light emitting control signals EM1 and EM2 are enabled to a turn-on level (e.g., a low level), the fourth and sixth transistors T4 and T6 may be turned on. The first transistor T1 may be turned on according to the voltage of the second node N2, and a current (e.g., a driving current) having a magnitude corresponding to the voltage of the second node N2 may flow through the first transistor T1. Thus, a current may flow from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light emitting element LD may emit light with a luminance corresponding to the magnitude of the flowing current (e.g., a driving current).

[0085] FIG. 4 is a plan view of an embodiment of the display panel DP of FIG.

[0086] The display panel DP of FIG. 4 can be applied to the display panel 110 of FIG.

[0087] 4, the display panel DP may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be disposed around the display area DA (e.g., in an edge area).

[0088] The display panel DP may include a substrate SUB, a plurality of sub-pixels SP arranged (or formed) on the substrate SUB, and a plurality of pads PD arranged (or formed) on the substrate SUB.

[0089] When the display panel DP according to the embodiment of the present disclosure is used as a display screen of a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, or the like, the display panel DP may be located very close to the user's eyes. In the above-mentioned embodiment, the sub-pixels SP may need to be integrated relatively densely. In order to increase the integration density of the sub-pixels SP, the substrate SUB according to the embodiment of the present disclosure may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on the substrate SUB of the silicon substrate. A display device 100 (see FIG. 1) including the display panel DP formed on the substrate SUB of the silicon substrate may be called an OLEDoS (OLED on Silicon) display device.

[0090] A plurality of sub-pixels SP may be arranged in a display area DA on a substrate SUB. Referring to FIG. 4, the sub-pixels SP may be arranged in a matrix shape along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment of the present disclosure is not limited thereto. For example, the plurality of sub-pixels SP according to the embodiment of the present disclosure may be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. For example, the plurality of sub-pixels SP may be arranged in a pentile shape. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction. Two or more sub-pixels SP among the plurality of sub-pixels SP may constitute one pixel PXL.

[0091] Components for controlling the sub-pixels SP may be arranged in the non-display area NDA on the substrate SUB. For example, wiring such as the first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn in FIG. 1 may be arranged to extend to at least a portion of the non-display area NDA.

[0092] At least one of the gate drive circuit 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 in FIG. 1 may be disposed (eg, integrally disposed) in the non-display area NDA of the display panel DP.

[0093] 1 may be formed and disposed in the non-display area NDA of the display panel DP, or may be realized as a separate integrated circuit separate from the display panel DP and mounted in the non-display area NDA.

[0094] 1 is disposed in the non-display area NDA to sense the temperature of the display panel DP. As an example, the temperature sensor 160 may be disposed at an apex of the display panel DP or an area corresponding thereto. Two or more temperature sensors 160 may be disposed on the display panel DP.

[0095] The pads PD may be disposed in a non-display area NDA on the substrate SUB. The pads PD may be electrically connected to the sub-pixels SP via wiring. For example, the pads PD may be connected to the sub-pixels SP via first to n-th data lines DL1 to DLn.

[0096] The pad PD can interface the display panel DP with other components of the display device 100 (see FIG. 1). In an embodiment, voltages and signals required for operation of components included in the display panel DP can be provided from the driver integrated circuit DIC of FIG. 1 via the pad PD. For example, the first to n-th data lines DL1 to DLn (see FIG. 1) can be connected to the driver integrated circuit DIC via the pad PD. For example, the first and second power supply voltages VDD and VSS (see FIG. 1) can be received from the driver integrated circuit DIC via the pad PD. In an embodiment in which the gate driving circuit 120 (see FIG. 1) is implemented in the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate driving circuit 120 via the pad PD.

[0097] In an embodiment, the circuit board may be electrically connected to the pads PD using a conductive adhesive member such as an anisotropic conductive film. In this case, the circuit board may be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. A driver integrated circuit DIC (see FIG. 1) may be mounted on the circuit board and electrically connected to the pads PD.

[0098] In an embodiment, the display area DA can have various shapes. For example, the display area DA can have a closed loop shape including straight and / or curved sides. For example, the display area DA can have a polygonal, circular, semicircular, elliptical, etc.

[0099] In an embodiment, the display panel DP may have a flat display surface. In another embodiment, the display panel DP may have an at least partially round display surface. In an embodiment, the display panel DP may be bendable, foldable or rollable. The display panel DP and / or the substrate SUB may comprise a rigid or flexible material.

[0100] FIG. 5 is an exploded perspective view showing a part of the display panel DP of FIG.

[0101] For clarity and conciseness of explanation, Figure 5 shows only a schematic representation of the portions of the display panel DP corresponding to the first and second pixels PXL1, PXL2 of the pixels PXL of Figure 4. The portions of the display panel DP corresponding to the remaining pixels may be similarly configured.

[0102] 4 and 5, the first and second pixels PXL1 and PXL2 may be adjacent to each other in the second direction DR2. Each of the first and second pixels PXL1 and PXL2 may include a plurality of sub-pixels. Referring to FIG. 5, each of the first and second pixels PXL1 and PXL2 may include first, second and third sub-pixels SP1, SP2 and SP3. However, the embodiments of the present disclosure are not limited thereto. For example, each of the first and second pixels PXL1 and PXL2 may include four sub-pixels or two sub-pixels.

[0103] 5, the first to third sub-pixels SP1 to SP3 are shown as having a rectangular shape and the same size when viewed from a third direction DR3 that intersects with the first and second directions DR1 and DR2 (for example, perpendicular to the first and second directions DR1 and DR2). However, the embodiment is not limited thereto. The first to third sub-pixels SP1 to SP3 may be modified to have various shapes.

[0104] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, a thin film encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0105] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like. In another embodiment, the substrate SUB may include a glass substrate. In yet another embodiment, the substrate SUB may include a polyimide (PI) substrate.

[0106] A pixel circuit layer PCL is disposed on a substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may function as at least a part of a circuit element, a wiring, etc. The conductive pattern may include copper, but examples are not limited thereto.

[0107] The circuit elements may include subpixel circuits SPC (see FIG. 2) for each of the first to third subpixels SP1 to SP3. The subpixel circuits SPC may include two or more transistors and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode superimposed on the semiconductor portion (e.g., the channel region of the semiconductor portion). In an embodiment in which the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment in which the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. The capacitor may include electrodes spaced apart from each other (e.g., facing each other). For example, each capacitor may include electrodes spaced apart from each other on a plane defined by the first and second directions DR1, DR2. For example, the capacitor may include electrodes spaced apart from each other in a third direction DR3 with an insulating layer sandwiched therebetween.

[0108] The wirings of the pixel circuit layer PCL may include signal lines, such as gate lines, emission control lines, and data lines, connected to the first to third sub-pixels SP1 to SP3, respectively. The wirings may further include a wiring connected to the first power supply voltage node VDDN of FIG. 2. The wirings may further include a wiring connected to the second power supply voltage node VSSN of FIG. 2.

[0109] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0110] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may be coupled (e.g., contacted) to a circuit element of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material that may reflect light. However, the embodiments of the present disclosure are not limited thereto.

[0111] A pixel defining layer PDL may be disposed on the anode electrodes AE. The pixel defining layer PDL may include an opening OP exposing at least a portion of each of the anode electrodes AE. The opening OP of the pixel defining layer PDL may correspond to the light emitting regions of each of the first to third sub-pixels SP1 to SP3.

[0112] In an embodiment, the pixel defined membrane PDL may include an inorganic material. In the above embodiment, the pixel defined membrane PDL may include an inorganic layer (e.g., multiple stacked inorganic layers). For example, the pixel defined membrane PDL may include silicon oxide (SiOx) and / or silicon nitride (SiNx). In another embodiment, the pixel defined membrane PDL may include an organic layer including an organic material. However, the materials constituting the pixel defined membrane PDL according to the embodiments of the present disclosure are not limited to those described above.

[0113] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel definition film PDL. The light emitting structure EMS may include one or more functional layers. For example, the light emitting structure EMS may include functional layers such as a light generating layer (or light emitting layer) (not shown) configured to generate light, an electron transport layer (not shown) configured to transport electrons, and a hole transport layer (not shown) configured to transport holes.

[0114] In the embodiment, the light emitting structure EMS may fill the opening OP of the pixel defining film PDL. In the embodiment, the light emitting structure EMS may be entirely disposed on the upper part of the pixel defining film PDL. For example, the light emitting structure EMS may extend over the first to third sub-pixels SP1 to SP3. In the above embodiment, at least a part of the functional layer in the light emitting structure EMS may be cut or bent at the boundary between the first to third sub-pixels SP1 to SP3. However, the embodiment of the present disclosure is not limited thereto. For example, the parts of the light emitting structure EMS corresponding to the first to third sub-pixels SP1 to SP3 may be separated from each other, and each of them may be disposed in the opening OP of the pixel defining film PDL.

[0115] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend across the first to third sub-pixels SP1 to SP3. The cathode electrode CE may be provided as a common electrode commonly connected to the first to third sub-pixels SP1 to SP3.

[0116] The cathode electrode CE may have optical transparency. For example, the cathode electrode CE may be a thin metal layer having a thickness that allows the light emitted from the light emitting structure EMS to pass through. The cathode electrode CE may be formed of a metal material to have a relatively thin thickness, or may be formed of an optically transparent (e.g., transparent) conductive material. In an embodiment, the cathode electrode CE may include at least one of various transparent conductive materials, including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. However, the materials constituting the cathode electrode CE according to the embodiment of the present disclosure are not limited to those described above. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects the light emitted from the light emitting structure EMS.

[0117] Any one of the anode electrodes AE, a portion of the light emitting structure EMS overlapping therewith, and a portion of the cathode electrode CE overlapping therewith may be understood to constitute one light emitting element LD (see FIG. 2). Each of the light emitting elements LD of the first to third sub-pixels SP1 to SP3 may include one anode electrode AE, a portion of the light emitting structure EMS overlapping therewith, and a portion of the cathode electrode CE overlapping therewith. In each of the first to third sub-pixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transported into the light emitting structure EMS to form excitons, and when the excitons transition from an excited state to a ground state, light may be generated. The luminance of the light may be determined according to the amount of current flowing through the light emitting structure EMS. The wavelength band of the light generated by the light emitting structure EMS may be determined according to the configuration of the light emitting structure EMS.

[0118] A thin-film encapsulation layer TFE is disposed on the cathode electrode CE. The thin-film encapsulation layer TFE may cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The thin-film encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. In an embodiment, the thin-film encapsulation layer TFE may include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic film may include silicon nitride, silicon oxide, silicon oxynitride (SiOxNy), or the like. For example, the organic film may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenyleneether resin, a polyphenylenesulfide resin, or benzocyclobutene (BCB). However, the materials of the organic and inorganic films of the thin film encapsulation layer TFE are not limited to those mentioned above.

[0119] In order to improve the encapsulation efficiency of the thin film encapsulation layer TFE, the thin film encapsulation layer TFE may further include a thin film containing aluminum oxide (AlOx). The thin film containing aluminum oxide may be located on an upper surface of the thin film encapsulation layer TFE facing the optical function layer OFL and / or on a lower surface of the thin film encapsulation layer TFE facing the light emitting element layer LDL. The thin film containing aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the embodiments of the present disclosure are not limited thereto. The thin film encapsulation layer TFE may further include a thin film formed of at least one of various materials suitable for improving the encapsulation efficiency.

[0120] The optical functional layer OFL may be disposed on the thin film encapsulation layer TFE. The optical functional layer OFL may include a color filter layer CFL and a lens array LA. In an embodiment, the optical functional layer OFL may be attached to the thin film encapsulation layer TFE via an adhesive layer (not shown). For example, the optical functional layer OFL may be manufactured separately and attached to the thin film encapsulation layer TFE via an adhesive layer. The adhesive layer may further perform the function of protecting the lower layer including the thin film encapsulation layer TFE.

[0121] The color filter layer CFL may be disposed between the thin film encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the light emitting structure EMS to selectively output light of a wavelength band corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the color filters CF may pass light of a wavelength band corresponding to the corresponding sub-pixel. For example, the color filter corresponding to the first sub-pixel SP1 may pass red light, the color filter corresponding to the second sub-pixel SP2 may pass green light, and the color filter corresponding to the third sub-pixel SP3 may pass blue light. At least a part of the color filter CF may be omitted according to the light emitted from the light emitting structure EMS in each sub-pixel. According to an embodiment, the color filter layer CFL may be omitted. In an embodiment, the color filter CF may overlap (for example, partially overlap) in a boundary region between the first to third sub-pixels SP1 to SP3. In another embodiment, the color filters CF may be spaced apart from each other in boundary regions between the first to third sub-pixels SP1 to SP3, and a black matrix may be provided between the color filters CF.

[0122] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS may improve light output efficiency by outputting light emitted from the light emitting structure EMS to an intended path. The lens array LA may have a relatively high refractive index. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylate material. However, the material constituting the lens LS is not limited thereto.

[0123] In an embodiment, at least a part of the color filters CF and / or at least a part of the lenses LS may be shifted compared to the position of the aperture OP of the pixel definition film PDL. For example, at least a part of the color filters CF of the color filter layer CFL and at least a part of the lenses LS of the lens array LA may be shifted in any one direction parallel to the plane defined by the first and second directions DR1, DR2 from a line perpendicular to the aperture OP (or the center of the aperture OP).

[0124] Specifically, in the central region of the display area DA, the center of the color filter CF and the center of the lens LS can be aligned or overlapped with the center of the opening OP of the corresponding pixel definition film PDL when viewed from the third direction DR3. For example, in the central region of the display area DA, the opening OP of the pixel definition film PDL can be completely overlapped with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the region adjacent to the non-display area NDA of the display area DA, the center of the color filter CF and the center of the lens LS can be shifted in the planar direction from the center of the opening OP of the corresponding pixel definition film PDL when viewed from the third direction DR3. For example, in the region adjacent to the non-display area NDA of the display area DA, the opening OP of the pixel definition film PDL can be partially overlapped with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. As a result, in the center of the display area DA, the light emitted from the light emitting structure EMS can be efficiently output in the normal direction of the display surface. At the outer periphery of the display area DA, the light emitted from the light emitting structure EMS can be efficiently output in a direction inclined at a predetermined angle with respect to the normal direction of the display surface.

[0125] The overcoat layer OC may be disposed on the lens array LA. The overcoat layer OC may cover the optical function layer OFL, the thin film encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting its underlying layers from foreign substances such as dust, moisture, and the like.

[0126] A cover window CW may be disposed on the overcoat layer OC. The cover window CW may be configured to protect the underlying layer. According to an embodiment, the cover window CW may include optically transparent (e.g., transparent) glass, metal, etc. However, the embodiment of the present disclosure is not limited thereto.

[0127] FIG. 6 is a plan view of one embodiment of the pixels of FIG.

[0128] For clarity and conciseness, Fig. 6 simply illustrates a first pixel PXL1 of the first and second pixels PXL1 and PXL2 in Fig. 5. The remaining pixels may be configured similarly to the first pixel PXL1. The first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in a first direction DR1.

[0129] The first subpixel SP1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA around the first light-emitting region EMA1. The second subpixel SP2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA around the second light-emitting region EMA2. The third subpixel SP3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA around the third light-emitting region EMA3.

[0130] The first light-emitting region EMA1 may be a region where light is emitted from a portion of the light-emitting structure EMS (see FIG. 5) corresponding to the first sub-pixel SP1. The second light-emitting region EMA2 may be a region where light is emitted from a portion of the light-emitting structure EMS corresponding to the second sub-pixel SP2. The third light-emitting region EMA3 may be a region where light is emitted from a portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3. As described with reference to FIG. 5, each light-emitting region can be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3.

[0131] FIG. 7 is an example of a cross-sectional view of the pixel PXL1 in FIG. 6 taken along line II'.

[0132] Referring to FIG. 7, the pixel PXL1 may include a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB.

[0133] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0134] A pixel circuit layer PCL may be disposed on a substrate SUB. The substrate SUB and the pixel circuit layer PCL may include at least a part of the circuit elements of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be any one of the transistors included in the sub-pixel circuit SPC of the first sub-pixel SP1 (see FIG. 2). The transistor T_SP2 of the second sub-pixel SP2 may be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2. The transistor T_SP3 of the third sub-pixel SP3 may be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. In FIG. 7, for clarity and conciseness, one of the transistors of each of the first to third sub-pixels SP1 to SP3 is shown, and the remaining circuit elements of the sub-pixel circuit SPC are not shown.

[0135] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0136] The source region SRA and the drain region DRA may be disposed in a substrate SUB. The source region SRA and the drain region DRA may be disposed spaced apart from each other in a well WL of the substrate SUB. The well WL may be formed via an ion implantation process. In the well WL, a region between the source region SRA and the drain region DRA may be defined as a channel region.

[0137] The gate electrode GE may be located overlapping (e.g., overlapping in a third direction DR3) a channel region between the source region SRA and the drain region DRA. The gate electrode GE may be included in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL (or the channel region) by an insulating material (e.g., an insulating material such as a gate insulating layer GI). The gate electrode GE may include a conductive material.

[0138] The layers included in the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may include first and second conductive patterns CP1 and CP2. The first conductive pattern CP1 may be connected (e.g., electrically connected) to the drain region DRA via a drain connector DRC that penetrates one or more insulating layers. The second conductive pattern CP2 may be connected (e.g., electrically connected) to the source region SRA via a source connector SRC that penetrates one or more insulating layers.

[0139] By connecting the gate electrode GE, the first conductive pattern CP1, and the second conductive pattern CP2 to other circuit elements and / or wiring, the transistor T_SP1 of the first sub-pixel SP1 can be provided as any one of the transistors of the pixel circuit SPC (see FIG. 2).

[0140] The transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 may each be configured the same (or similarly) as the transistor T_SP1 of the first sub-pixel SP1.

[0141] As described above, the substrate SUB and / or the pixel circuit layer PCL may include circuit elements for each of the first to third sub-pixels SP1 to SP3.

[0142] A via layer VIAL may be disposed on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL. The via layer VIAL may have a generally flat surface (e.g., a flat upper surface). The via layer VIAL may be configured to planarize steps on the pixel circuit layer PCL. The via layer VIAL may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon carbon nitride (SiCN), although embodiments of the present disclosure are not limited thereto.

[0143] The light emitting element layer LDL may be disposed on the via layer VIAL. The light emitting element layer LDL may include first to third reflective electrodes RE1 to RE3, a planarization layer PLNL, first to third anode electrodes AE1 to AE3, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0144] The first to third reflective electrodes RE1 to RE3 can be disposed on the via layer VIAL for the first to third sub-pixels SP1 to SP3, respectively. Each of the first to third reflective electrodes RE1 to RE3 can be in contact with a circuit element disposed in the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0145] The first to third reflective electrodes RE1 to RE3 may function as mirrors (for example, full mirrors) that reflect light emitted from the light emitting structure EMS toward the display surface (or the cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments of the present disclosure are not limited thereto.

[0146] In an embodiment, a buffer electrode (not shown) may be disposed under each of the first to third reflective electrodes RE1 to RE3. The buffer electrode may improve electrical connection characteristics between the corresponding reflective electrode and a circuit element of the pixel circuit layer PCL. The buffer electrode may have a multi-layer structure. The buffer electrode may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment of the present disclosure is not limited thereto. In an embodiment, the corresponding reflective electrode may be located between the buffer electrodes (e.g., between the multiple layers constituting the buffer electrodes).

[0147] At least one of the first to third reflective electrodes RE1 to RE3 may be disposed on a buffer pattern BFP. The buffer pattern BFP may be configured to control the position of the reflective electrode (e.g., the position of the reflective electrode in the third direction DR3). The buffer pattern BFP may include an inorganic material such as silicon carbon nitride, but the embodiment of the present disclosure is not limited thereto. Referring to FIG. 7, by disposing the buffer pattern BFP, the position of the corresponding reflective electrode (e.g., the height in the third direction DR3) may be adjusted. Referring to FIG. 7, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0148] The first to third reflective electrodes RE1 to RE3 may function as full mirrors, and the cathode electrode CE may function as a half mirror. At least a part of the light emitted from the light emitting structure EMS may be amplified by traveling back and forth between the corresponding reflective electrodes and the cathode electrode CE. The above phenomenon may be understood as a resonance phenomenon. The amplified light may be output through the cathode electrode CE. The distance between each reflective electrode and the cathode electrode CE may be understood as a resonance distance for the light emitted from the light emitting structure EMS. The resonance distance may be adjusted by the buffer pattern BFP.

[0149] 7, the first sub-pixel SP1 may have a shorter resonance distance than the other sub-pixels due to the buffer pattern BFP. The adjusted resonance distance may effectively and efficiently amplify light of a specific wavelength band (e.g., red color). Thus, the first sub-pixel SP1 may effectively and efficiently output light of the corresponding wavelength band.

[0150] Referring to FIG. 7, the buffer pattern BFP is shown to be provided in the first sub-pixel SP1, but not in the second and third sub-pixels SP2 and SP3. However, the embodiments of the present disclosure are not limited thereto. At least one of the second and third sub-pixels SP2 and SP3 may also be provided with a buffer pattern to adjust the resonance distance of at least one of the second and third sub-pixels SP2 and SP3. For example, the first to third sub-pixels SP1 to SP3 may correspond to sub-pixels configured to emit red, green, and blue light, respectively. The distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE. The distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0151] The planarization layer PLNL may be configured to planarize steps between the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may entirely cover the first to third reflective electrodes RE1 to RE3 and the via layer VIAL. The planarization layer PLNL may have a flat surface (e.g., an upper surface in the third direction DR3). In an embodiment, the planarization layer PLNL may be omitted.

[0152] The first to third anode electrodes AE1 to AE3 may be disposed on the planarization layer PLNL. The first to third anode electrodes AE1 to AE3 may overlap (for example, overlap in the third direction DR3) with the first to third reflective electrodes RE1 to RE3, respectively. The first to third anode electrodes AE1 to AE3 may have shapes similar to the first to third light emitting regions EMA1 to EMA3 of FIG. 6 when viewed from the third direction DR3. The first to third anode electrodes AE1 to AE3 are connected to the first to third reflective electrodes RE1 to RE3, respectively. The first anode electrode AE1 may be connected (for example, electrically connected) to the first reflective electrode RE1 through a first via VIA1 penetrating the planarization layer PLNL. The second anode electrode AE2 may be connected (for example, electrically connected) to the second reflective electrode RE2 through a second via VIA2 penetrating the planarization layer PLNL. The third anode electrode AE3 may be connected (eg, electrically connected) to the third reflective electrode RE3 through a third via VIA3 penetrating the planarization layer PLNL.

[0153] In the embodiment, the first to third anode electrodes AE1 to AE3 may include at least one of light-transmitting (e.g., transparent) conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the materials of the first to third anode electrodes AE1 to AE3 are not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0154] The pixel defining film PDL may be disposed on a portion of the first to third anode electrodes AE1 to AE3 and the planarizing layer PLNL. The pixel defining film PDL may include an opening OP exposing at least a portion of each of the first to third anode electrodes AE1 to AE3. The opening OP of the pixel defining film PDL may define a light emitting region from which light is emitted from each of the first to third sub-pixels SP1 to SP3. The pixel defining film PDL may be disposed in the non-light emitting region NEA of FIG. 6. The pixel defining film PDL may define the first to third light emitting regions EMA1 to EMA3 of FIG. 6.

[0155] In an embodiment, the pixel defining film PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers constituting the pixel defining film PDL may include at least one of silicon oxide (SiOx) and silicon nitride (SiNx). For example, the pixel defining film PDL may include first to third inorganic insulating layers sequentially stacked, and the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon oxynitride, respectively. However, the embodiment of the present disclosure is not limited thereto. The first to third inorganic insulating layers may have a stepped cross section in a region adjacent to the opening OP.

[0156] The pixel PXL1 may include a separator SPR provided (or disposed) in a boundary region BDA between adjacent sub-pixels, i.e., a separator SPR may be provided in each of the boundary regions BDA between the sub-pixels SP of FIG.

[0157] The separator SPR can form a discontinuity in the light emitting structure EMS at the boundary region BDA, for example, the separator SPR can cause the light emitting structure EMS to be cut or bent at the boundary region BDA.

[0158] The separator SPR can be provided in or on the pixel definition film PDL. The pixel definition film PDL can include one or more trenches TRCH1, TRCH2 as separators SPR in the boundary region BDA. In an embodiment, as shown in FIG. 7, the one or more trenches TRCH1, TRCH2 can penetrate the pixel definition film PDL and partially penetrate at least a part of the planarization layer PLNL. In another embodiment, the one or more trenches TRCH1, TRCH2 can penetrate the pixel definition film PDL and the planarization layer PLNL and partially penetrate at least a part of the via layer VIAL. In yet another embodiment, the one or more trenches TRCH1, TRCH2 can at least partially penetrate at least a part of the planarization layer PLNL and / or at least a part of the via layer VIAL, and at least a part of the pixel definition film PDL can be disposed in the one or more trenches TRCH1, TRCH2.

[0159] Referring to FIG. 7, a plurality of trenches (e.g., a first trench TRCH1 and a second trench TRCH2) are shown to be provided (or disposed) in the boundary region BDA. For convenience of explanation, an embodiment in which two trenches TRCH1, TRCH2 are provided in the boundary region BDA will be described below. However, the embodiments of the present disclosure are not limited thereto. For example, the pixel definition film PDL may include a single trench in the boundary region BDA. For example, the pixel definition film PDL may include three or more trenches in the boundary region BDA.

[0160] The first and second trenches TRCH1 and TRCH2 may form a void as a discontinuous portion in the boundary region BDA. Referring to FIG. 7, discontinuous portions such as the first void VD1 and the second void VD2 may be formed (or disposed) in the light emitting structure EMS. Some of the layers stacked in the light emitting structure EMS may be cut or bent by the first and second voids VD1 and VD2. For example, at least one charge generation layer (CGL) included in the light emitting structure EMS may be cut by the first and second voids VD1 and VD2. At least some of the light emitting structures EMS included in the first to third sub-pixels SP1 to SP3 may be partially separated by the first and second trenches TRCH1 and TRCH2.

[0161] 7, first and second voids VD1 and VD2 are shown to be formed in the light emitting structure EMS in the boundary region BDA. However, this is merely an example, and the embodiments of the present disclosure are not limited thereto. For example, a valley having a concave shape may be formed in the light emitting structure EMS in the boundary region BDA. Depending on the shapes of the first and second trenches TRCH1 and TRCH2, the discontinuous portions formed in the light emitting structure EMS may be variously changed.

[0162] In the embodiment, the light emitting structure EMS may be formed through a process such as vacuum deposition, inkjet printing, etc. In the above embodiment, the light emitting structure EMS (or the same material as the light emitting structure EMS) may be located on a bottom surface of the first and second trenches TRCH1 and TRCH2 adjacent to the via layer VIAL.

[0163] The separator SPR may be provided in various modifications so that the light emitting structure EMS may have a discontinuous portion in the boundary region BDA. In an embodiment, an inorganic insulating pattern may be provided that is further stacked on the pixel defining layer PDL in the boundary region BDA without the first and second trenches TRCH1 and TRCH2. The width of the uppermost inorganic insulating pattern among the further stacked inorganic insulating patterns may be larger than the width of the inorganic insulating pattern disposed immediately below it. For example, in an embodiment in which the first to third inorganic insulating patterns are sequentially stacked from the pixel defining layer PDL in the boundary region BDA, the width of the third inorganic insulating pattern disposed at the uppermost position may be larger than the width of the second inorganic insulating pattern disposed immediately below it. For example, the pixel defining layer PDL may have a "T"-shaped or "I"-shaped cross section in the boundary region BDA. Depending on the pixel defining layer PDL having a "T"-shaped or "I"-shaped cross section, at least a portion of the layers included in the light emitting structure EMS may be partially cut or bent in the boundary region BDA.

[0164] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and be disposed over the first to third sub-pixels SP1 to SP3. As described above, at least a part of the light emitting structure EMS may be partially cut or bent in the boundary area BDA by the separator SPR. Thus, during operation of the display panel DP (see FIG. 1), the magnitude of a current (e.g., leakage current) flowing from each of the first to third sub-pixels SP1 to SP3 to the adjacent sub-pixels through a layer included in the light emitting structure EMS may be reduced (or eliminated). Therefore, the first to third light emitting elements LD1 to LD3 may operate with relatively high reliability.

[0165] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may be provided (or disposed) in common to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0166] The first anode electrode AE1, a portion of the light emitting structure EMS overlapping the first anode electrode AE1, and a portion of the cathode electrode CE overlapping the first anode electrode AE1 may form a first light emitting element LD1. The second anode electrode AE2, a portion of the light emitting structure EMS overlapping the second anode electrode AE2, and a portion of the cathode electrode CE overlapping the second anode electrode AE2 may form a second light emitting element LD2. The third anode electrode AE3, a portion of the light emitting structure EMS overlapping the third anode electrode AE3, and a portion of the cathode electrode CE overlapping the third anode electrode AE3 may form a third light emitting element LD3.

[0167] The thin-film encapsulation layer TFE may be disposed on the cathode electrode CE. The thin-film encapsulation layer TFE may prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL.

[0168] The optical functional layer OFL can be disposed on the thin film encapsulation layer TFE. The optical functional layer OFL can include a color filter layer CFL and a lens array LA. In an embodiment, the optical functional layer OFL can be attached to the thin film encapsulation layer TFE via an adhesive layer APL. For example, the optical functional layer OFL can be manufactured separately and attached to the thin film encapsulation layer TFE via an adhesive layer APL. The adhesive layer APL can further perform the function of protecting the lower layer including the thin film encapsulation layer TFE.

[0169] The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 are capable of transmitting light of different wavelength bands. For example, the first to third color filters CF1 to CF3 are capable of transmitting red, green, and blue color light, respectively.

[0170] In an embodiment, the first to third color filters CF1 to CF3 may partially overlap each other at the boundary area BDA. In another embodiment, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix (not shown) may be provided (or disposed) between each of the first to third color filters CF1 to CF3.

[0171] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third lenses LS1 to LS3 may improve light output efficiency by outputting the light emitted from the first to third light emitting elements LD1 to LD3 to intended paths.

[0172] The overcoat layer OC may be disposed on the lens array LA. The overcoat layer OC may include various substances suitable for protecting the lower layer from foreign matter such as dust, moisture, and the like. For example, the overcoat layer OC may include an inorganic insulating film. For example, the overcoat layer OC may include an epoxy resin, but the embodiment is not limited thereto. The overcoat layer OC may have a refractive index lower than that of the lens array LA. The refractive index (for example, absolute refractive index) of the overcoat layer OC may be a first refractive index. The range of the first refractive index may be, for example, about 1.2 to 1.4, but the embodiment of the present disclosure is not limited thereto.

[0173] The cover window CW may be disposed on the overcoat layer OC. The cover window CW may have a refractive index greater than that of the overcoat layer OC. According to an embodiment, the cover window CW may include glass, metal, etc. However, the embodiment of the present disclosure is not limited thereto. The cover window CW may be configured to protect components disposed thereunder. The refractive index (e.g., absolute refractive index) of the cover window CW may be a second refractive index. The range of the second refractive index may be, for example, about 1.5 to 1.9, but the embodiment of the present disclosure is not limited thereto. The cover window CW may be referred to as a sealing glass.

[0174] The cover window CW may be in contact with the outside (eg, air). For example, in an embodiment in which the cover window CW is in contact with air, the refractive index (eg, absolute refractive index) of air may be about 1.0.

[0175] The overcoat layer OC and the cover window CW may constitute a protective layer PTL. In the embodiment of the present disclosure, the protective layer PTL may function to guide the direction in which light (e.g., light emitted from the light-emitting element layer LDL) is emitted to the outside of the protective layer PTL.

[0176] FIG. 8 is a diagram showing an example of the angle at which light is emitted from a display panel DP according to an embodiment of the present disclosure.

[0177] Referring to FIG. 8, first to fifth pixels PXLa to PXLe in a display panel DP according to an embodiment of the present disclosure are shown.

[0178] The first pixel PXLa may represent a pixel located in a central region of the display panel DP, the second pixel PXLb and the third pixel PXLc may represent a pixel located in an edge region of the display panel DP, and the fourth pixel PXLd and the fifth pixel PXLe may represent a pixel located between the central region and the edge region of the display panel DP.

[0179] Referring to FIG. 8, the first pixel PXLa is shown as being located in the first direction DR1 from the second pixel PXLb. However, the embodiment of the present disclosure is not limited thereto. For example, the position of the second pixel PXLb may be located in the second direction DR2 from the first pixel PXLa. For example, the second pixel PXLb may be located in an area indicated by a vector obtained by combining a vector in the first direction DR1 and a vector in the second direction DR2 from the first pixel PXLa. In the following, for convenience of explanation, an embodiment in which the first pixel PXLa is located in the first direction DR1 from the second pixel PXLb will be described as an example, but the embodiment of the present disclosure is not limited thereto.

[0180] Referring to FIG. 8, the third pixel PXLc is shown as being located in the first direction DR1 from the first pixel PXLa. However, the embodiment of the present disclosure is not limited thereto. For example, the position of the third pixel PXLc can be located in the second direction DR2 from the first pixel PXLa. For example, the third pixel PXLc may be located in an area indicated by a vector obtained by combining a vector in the first direction DR1 and a vector in the second direction DR2 from the first pixel PXLa. In the following, for convenience of explanation, an embodiment in which the third pixel PXLc is located in the first direction DR1 from the first pixel PXLa will be described as an example, but the embodiment of the present disclosure is not limited thereto.

[0181] 8, the fourth pixel PXLd is shown as being located between the first pixel PXLa and the second pixel PXLb. However, the embodiment of the present disclosure is not limited thereto. For example, the fourth pixel PXLd may be located in an area off the line connecting the first pixel PXLa and the second pixel PXLb. In the following, for convenience of explanation, an embodiment in which the fourth pixel PXLd is located between the first pixel PXLa and the second pixel PXLb is described as an example, but the embodiment of the present disclosure is not limited thereto.

[0182] Referring to FIG. 8, the fifth pixel PXLe is shown as being located between the first pixel PXLa and the third pixel PXLc. However, the embodiment of the present disclosure is not limited thereto. For example, the fifth pixel PXLe may be located in an area off the line connecting the first pixel PXLa and the third pixel PXLc. In the following, for convenience of explanation, an embodiment in which the fifth pixel PXLe is located between the first pixel PXLa and the third pixel PXLc will be described as an example, but the embodiment of the present disclosure is not limited thereto.

[0183] The light LT1 emitted from the first pixel PXLa may be emitted from the display panel DP at an angle (e.g., a predetermined angle) with the display panel DP. Referring to Fig. 8, the angle between the light LT1 emitted from the first pixel PXLa and the normal NM of the display panel DP may be a first angle θ1. The first angle θ1 may be 0°.

[0184] The light LT2 emitted from the second pixel PXLb may be emitted from the display panel DP at an angle (e.g., a predetermined angle) with the display panel DP. Referring to FIG. 8, the angle that the light LT2 emitted from the second pixel PXLb makes with the normal NM of the display panel DP may be a second angle θ2. The second angle θ2 may be an acute angle in a range greater than 0 and less than 90°. As an example, the second angle θ2 may be about 40°, but the embodiment of the present disclosure is not limited thereto. For example, the second angle θ2 may be about 30°. The light LT2 emitted from the second pixel PXLb may be emitted mainly in the outer direction of the display panel DP (or the substrate SUB (see FIG. 5)).

[0185] The light LT3 emitted from the third pixel PXLc may be emitted from the display panel DP at an angle (e.g., a predetermined angle) with the display panel DP. Referring to FIG. 8, the angle that the light LT3 emitted from the third pixel PXLc makes with the normal NM of the display panel DP may be a third angle θ3. The third angle θ3 may be an acute angle in a range greater than 0 and less than 90°. As an example, the third angle θ3 may be about 40°, but the embodiment of the present disclosure is not limited thereto. For example, the third angle θ3 may be about 30°. The light LT3 emitted from the third pixel PXLc may be emitted mainly in the outer direction of the display panel DP (or the substrate SUB (see FIG. 5)).

[0186] The angle that the light emitted from the fourth pixel PXLd makes with the normal NM of the display panel DP may be between the first angle θ1 and the second angle θ2. As an example, the angle that the light emitted from the fourth pixel PXLd makes with the normal NM of the display panel DP may be about 15°. The angle that the light emitted from the fifth pixel PXLe makes with the normal NM of the display panel DP may be between the first angle θ1 and the third angle θ3. As an example, the angle that the light emitted from the fifth pixel PXLe makes with the normal NM of the display panel DP may be about 15°.

[0187] The light LT1, LT2, and LT3 emitted from the display panel DP may be incident on the external lens 810. The external lens 810 may refract the incident light LT1, LT2, and LT3. The light LT refracted by the external lens 810 may be emitted toward the user USR. The external lens 810 may be configured to adjust a focal length. The external lens 810 allows the user USR to more clearly see the display panel DP located close to the user USR. The external lens 810 may be realized by a pancake lens as an example, but the embodiment of the present disclosure is not limited thereto.

[0188] The magnitude of the angle that the light emitted from the certain pixel makes with the normal NM of the display panel DP may vary depending on the distance between a first pixel PXLa located at the center of the display panel DP and a certain pixel located in an arbitrary region of the display panel DP. For example, the angle that the light emitted from the display panel DP makes with the normal NM of the display panel DP may become larger from the central region to the peripheral region (e.g., edge region) of the display panel DP.

[0189] 8, a first angle θ1 between the light LT1 emitted from the first pixel PXLa located in the central region of the display panel DP and the normal NM of the display panel DP may be 0°, which may be the smallest angle compared to the angles at which light is emitted from other pixels in the display panel DP. The angles (second angle θ2, third angle θ3) between the light LT2, LT3 emitted from the second pixel PXLb or the third pixel PXLc located in the edge region of the display panel DP and the normal NM of the display panel DP may be the largest angle compared to the angles at which light is emitted from other pixels in the display panel.

[0190] FIG. 9 is a cross-sectional view for explaining the angle at which the light LT1 is emitted from the first pixel PXLa according to the embodiment of FIG.

[0191] 9, light LT1 is shown being emitted from the first pixel PXLa onto the cover window CW (for example, in the third direction DR3). The light LT1 may be emitted in a vertical direction, and the first angle θ1 may be 0°.

[0192] The inclination angle of the upper surface of the overcoat layer OC with respect to the plane defined by the first direction DR1 and the second direction DR2 may be related to the angle of the light emitted from the pixel with the normal to the display panel. For example, when the inclination angle of the upper surface of the overcoat layer OC with respect to the plane defined by the first direction DR1 and the second direction DR2 increases, the angle of the light emitted from the pixel with the normal to the display panel may increase. For example, when the inclination angle of the upper surface of the overcoat layer OC with respect to the plane defined by the first direction DR1 and the second direction DR2 decreases, the angle of the light emitted from the pixel with the normal to the display panel may decrease.

[0193] 9, the inclination angle that the upper surface of the overcoat layer OC makes with the plane defined by the first direction DR1 and the second direction DR2 is shown as a first inclination angle r1. The first inclination angle r1 may be 0°. The first angle θ1 that the light LT1 emitted from the first pixel PXLa makes with the normal to the display panel may be 0°. The upper surface of the overcoat layer OC may include a flat surface PLN.

[0194] FIG. 10a is an example of a cross-sectional view illustrating an angle at which light is emitted from the second pixel PXLb according to the embodiment of FIG.

[0195] 10a, light LT2 is shown being emitted from the second pixel PXLb onto the cover window CW (eg, in the third direction DR3). The light LT2 may be emitted at a second angle θ2 with the normal NM.

[0196] The inclination angle that the top surface of the overcoat layer OC makes with the plane defined by the first direction DR1 and the second direction DR2 is indicated as the second inclination angle r2. The overcoat layer OC may include an inclined surface ICN. The inclination angle of the inclined surface ICN may be the second inclination angle r2. The overcoat layer OC may include a step STP following the inclined surface ICN.

[0197] The second tilt angle r2 may be an acute angle greater than 0. The second angle θ2 that the light LT2 emitted from the second pixel PXLb makes with the normal NM to the display panel may be an acute angle greater than 0.

[0198] The refractive index of the overcoat layer OC may be smaller than the refractive index of the cover window CW.

[0199] According to an embodiment, the inclined surface ICN may be arranged in units of sub-pixels SP (e.g., units of light-emitting elements LD). According to an embodiment, the inclined surface ICN may be arranged so as to cover two or more sub-pixels SP (e.g., two or more light-emitting elements LD). According to an embodiment, the inclined surface ICN may be arranged in units of pixels PXL. According to an embodiment, the inclined surface ICN may be arranged so as to cover two or more pixels PXL.

[0200] 10a, an embodiment in which an inclined surface ICN is disposed in each unit of the first to third sub-pixels SP1 to SP3 is shown. In the above embodiment, the inclined surface ICN may be disposed in correspondence with the lens array LA and the color filter layer CFL. However, the embodiment of the present disclosure is not limited thereto.

[0201] According to an embodiment, the step STP may be disposed between adjacent sub-pixels SP. In one embodiment, the step STP may be at the same (or substantially the same) distance to the light-emitting element LD of each of the adjacent sub-pixels SP. In another embodiment, the step STP may be at different distances to the light-emitting element LD of each of the adjacent sub-pixels SP.

[0202] Referring further to FIG. 8, the inclined surface ICN of the overcoat layer OC may be formed with an inclination such that the height increases as it moves from the outside (corresponding to the left side in FIG. 10a) of the display panel DP toward the inside (corresponding to the right side in FIG. 10a).

[0203] Referring to Fig. 10a, the refractive index of the overcoat layer OC may be smaller than the refractive index of the cover window CW. As a result, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted by the inclined surface ICN in the direction in which the inclined surface is inclined (primary refraction) and refracted by the upper surface of the cover window CW (secondary refraction). As a result, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted in a direction (corresponding to the left side in Fig. 10a) outside the display panel DP (see Fig. 8) at an angle (e.g., a predetermined angle) larger than 0 with respect to the normal line NM, and may be emitted.

[0204] FIG. 10b is another example of a cross-sectional view illustrating the angle at which the light LT2 is emitted from the second pixel PXLb according to the embodiment of FIG.

[0205] 10b, light LT2 is shown being emitted from the second pixel PXLb onto the cover window CW (eg, in the third direction DR3). The light LT2 may be emitted at a second angle θ2 with the normal NM.

[0206] The inclined surface ICN may be disposed so as to cover two or more sub-pixels SP. Referring to FIG. 10b, an embodiment in which the inclined surface ICN is disposed so as to cover two or more of the first to third sub-pixels SP1 to SP3 (for example, the first sub-pixel SP1 and the second sub-pixel SP2) is shown. In the above embodiment, the inclined surface ICN may be disposed in a unit different from that of the lens array LA and the color filter layer CFL. This may make it easier to align the overcoat layer OC and the light-emitting elements LD1, LD2, LD3 compared to the embodiment shown in FIG. 10a.

[0207] FIG. 10c is yet another example of a cross-sectional view illustrating the angle at which the light LT2 is emitted from the second pixel PXLb according to the embodiment of FIG.

[0208] 10c, light LT2 is shown being emitted from the second pixel PXLb onto the cover window CW (eg, in the third direction DR3). The light LT2 may be emitted at a second angle θ2 with the normal NM.

[0209] The inclination angle that the top surface of the overcoat layer OC makes with the plane defined by the first direction DR1 and the second direction DR2 is indicated as the second inclination angle r2'. The overcoat layer OC may include an inclined surface ICN. The inclination angle of the inclined surface ICN may be the second inclination angle r2'. The overcoat layer OC may include a step STP continuing from the inclined surface ICN.

[0210] The second tilt angle r2' may be an acute angle greater than 0. The second angle θ2 that the light LT2 emitted from the second pixel PXLb makes with the normal NM to the display panel may be an acute angle greater than 0.

[0211] The refractive index of the overcoat layer OC may be smaller than the tilt angle of the cover window CW.

[0212] The optical function layer OFL may be shifted. For example, at least one of the color filter layer CFL and the lens array LA may be shifted in one direction from the light emitting element LD. Referring to FIG. 10c, the color filter CFL and the lens array LA of the second pixel PXLb may be shifted in one direction (for example, the opposite direction of the first direction DR1). The direction in which the optical function layer OFL is shifted may correspond to the horizontal component (for example, the opposite direction of the first direction DR1) of the light LT2 emitted from the corresponding pixel (for example, the second pixel PXLb).

[0213] In the embodiment in which the optical function layer OFL is shifted, the size of the step STP' (or the height of the step STP') can be relatively small compared to the size of the step STP (or the height of the step STP) in the embodiment of FIG. 10a. This allows the thickness of the overcoat layer OC to be relatively small. This allows a thin display panel DP (see FIG. 1) to be provided.

[0214] The step STP' may have a different distance to the light-emitting element LD of each of the adjacent sub-pixels SP. Referring to Fig. 10c, for the step STP' located in the boundary region between the first sub-pixel SP1 and the second sub-pixel SP2, the distance between the step STP' and the first light-emitting element LD1 may be relatively closer than the distance between the step STP' and the second light-emitting element LD2.

[0215] Referring to Fig. 10c, the inclined surface ICN' may be moved in one direction (e.g., moved by a predetermined distance) on a line perpendicular to the light-emitting element LD. Referring further to Fig. 8, the direction in which the inclined surface ICN' moves on a line perpendicular to the light-emitting element LD may be toward the outside of the display panel DP (corresponding to the left side in Fig. 10c). In the above embodiment, the optical function layer OFL may be moved toward the outside of the inclined surface ICN' and the display panel DP.

[0216] FIG. 11 is a cross-sectional view for explaining the angle at which the light LT3 is emitted from the third pixel PXLc according to the embodiment of FIG.

[0217] 11, light LT3 is shown being emitted from the third pixel PXLc onto the cover window CW (for example, in a third direction DR3). The light LT3 may be emitted at a third angle θ3 with the normal NM.

[0218] The inclination angle that the top surface of the overcoat layer OC makes with the plane defined by the first direction DR1 and the second direction DR2 is indicated as the third inclination angle r3. The overcoat layer OC may include an inclined surface ICN. The inclination angle of the inclined surface ICN may be the third inclination angle r3. The overcoat layer OC may include a step STP continuing from the inclined surface ICN.

[0219] The inclined surface ICN of the third pixel PXLc may be inclined in a direction opposite to the inclined surface ICN of the second pixel PXLb (see FIGS. 10a to 10c).

[0220] The third tilt angle r3 may be an acute angle greater than 0. The third angle θ3 that the light LT3 emitted from the third pixel PXLc makes with the normal NM to the display panel may be an acute angle greater than 0. In an embodiment in which the third tilt angle r3 is the same as the second tilt angle r2 (see FIGS. 10a to 10c), the third angle θ3 may be the same (or substantially the same) as the second angle θ2 (see FIGS. 10a to 10c).

[0221] 11, the refractive index of the overcoat layer OC may be smaller than the refractive index of the cover window CW. As a result, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted by the inclined surface ICN in the direction in which the inclined surface is inclined (primary refraction) and refracted by the upper surface of the cover window CW (secondary refraction). As a result, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted in a direction (corresponding to the right side in FIG. 11) outside the display panel DP (see FIG. 8) at an angle (e.g., a predetermined angle) larger than 0 with respect to the normal line NM, and may be emitted.

[0222] FIG. 12 is a cross-sectional view for explaining the angle at which the light LT4 is emitted from the fourth pixel PXLd according to the embodiment of FIG.

[0223] 12, light LT4 is shown being emitted from the fourth pixel PXLd onto the cover window CW (for example, in the third direction DR3). The light LT4 may be emitted at a fourth angle θ4 with the normal NM.

[0224] The inclination angle that the top surface of the overcoat layer OC makes with the plane defined by the first direction DR1 and the second direction DR2 is shown as a fourth inclination angle r4. The overcoat layer OC may include an inclined surface ICN. The inclination angle of the inclined surface ICN may be the fourth inclination angle r4. The overcoat layer OC may include a step STP continuing from the inclined surface ICN.

[0225] The inclined direction of the inclined surface ICN of the fourth pixel PXLd may be the same (or substantially the same) as the inclined direction of the inclined surface ICN of the second pixel PXLb (see FIGS. 10a to 10c).

[0226] The fourth tilt angle r4 may be an acute angle greater than 0 and smaller than the second tilt angles r2, r2' (see FIGS. 10a to 10c). The fourth angle θ4 that the light LT4 emitted from the fourth pixel PXLd makes with the normal NM to the display panel may be an acute angle greater than 0 and smaller than the second angle θ2 (see FIGS. 10a to 10c).

[0227] 12, the refractive index of the overcoat layer OC may be smaller than the refractive index of the cover window CW. As a result, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted by the inclined surface ICN in the inclined direction of the inclined surface ICN (primary refraction) and refracted by the upper surface of the cover window CW (secondary refraction). As a result, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted in a direction (corresponding to the left side in FIG. 12) outside the display panel DP (see FIG. 8) at an angle (e.g., a predetermined angle) larger than 0 with respect to the normal line NM, and may be emitted.

[0228] 10a, the fourth tilt angle r4 of the fourth pixel PXLd may be smaller than the second tilt angle r2 of the second pixel PXLb, so that the fourth angle θ4 between the light LT4 emitted from the fourth pixel PXLd and the normal line NM may be smaller than the second angle θ2 between the light LT2 emitted from the second pixel PXLb and the normal line NM.

[0229] FIG. 13 is a cross-sectional view for explaining the angle at which the light LT5 is emitted from the fifth pixel PXLe according to the embodiment of FIG.

[0230] 13, light LT5 is shown being emitted from the fifth pixel PXLe onto the cover window CW (for example, in the third direction DR3). The light LT5 may be emitted at a fifth angle θ5 with the normal NM.

[0231] The inclination angle that the top surface of the overcoat layer OC makes with the plane defined by the first direction DR1 and the second direction DR2 is indicated as a fifth inclination angle r5. The overcoat layer OC may include an inclined surface ICN. The inclination angle of the inclined surface ICN may be the fifth inclination angle r5. The overcoat layer OC may include a step STP continuing from the inclined surface ICN.

[0232] The tilt direction of the inclined surface ICN of the fifth pixel PXLe may be opposite to the tilt direction of the inclined surface ICN of the fourth pixel PXLd (see FIG. 12) described above.

[0233] The fifth tilt angle r5 may be an acute angle greater than 0 and smaller than the third tilt angle r3 (see FIG. 11). The fifth angle θ5 between the light LT5 emitted from the fifth pixel PXLe and the normal NM to the display panel may be an acute angle greater than 0 and smaller than the third angle θ3 (see FIG. 11). In an embodiment in which the fifth tilt angle r5 is the same as the fourth tilt angle r4 (see FIG. 12), the fifth angle θ5 may be the same as (or substantially the same as) the fourth angle θ4 (see FIG. 12).

[0234] 13, the refractive index of the overcoat layer OC may be smaller than the refractive index of the cover window CW. As a result, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted by the inclined surface ICN in the inclined direction of the inclined surface ICN (primary refraction) and refracted by the upper surface of the cover window CW (secondary refraction). As a result, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted in a direction (corresponding to the right side in FIG. 13) outside the display panel DP (see FIG. 8) at an angle (e.g., a predetermined angle) larger than 0 with respect to the normal line NM, and may be emitted.

[0235] 11, the fifth tilt angle r5 of the fifth pixel PXLe may be smaller than the third tilt angle r3 of the third pixel PXLc, so that the fifth angle θ5 between the light LT5 emitted from the fifth pixel PXLe and the normal line NM may be smaller than the third angle θ3 between the light LT3 emitted from the third pixel PXLc and the normal line NM.

[0236] Referring to Figures 8 to 13 as a whole, from the pixel PXL located in the central region of the display panel DP to the pixel PXL located in the edge region of the display panel DP, the relationship between the inclination angle r of the inclined surface ICN and the angle θ at which light is emitted with respect to the refractive index (or the first refractive index) of the overcoat layer OC and the refractive index (or the second refractive index) of the cover window CW can be illustratively explained through the following Tables 1 and 2.

[0237] [Table 1]

[0238] [Table 2]

[0239] In Tables 1 and 2, the first refractive index may correspond to the refractive index of the overcoat layer OC. The second refractive index may correspond to the refractive index of the cover window CW. r may correspond to the inclination angle of the inclined surface ICN. θ may correspond to the angle at which light (for example, light of a predetermined wavelength band) emitted from the pixel PXL having the inclined surface ICN with the corresponding inclination angle r is emitted to the upper surface of the cover window CW. In Tables 1 and 2, the pixel with the inclination angle r of 0° may correspond to the first pixel PXLa in FIG. 8. In Tables 1 and 2, the pixel with the inclination angle r of 40° may correspond to the second pixel PXLb or the third pixel PXLc in FIG. 8. In Tables 1 and 2, the pixel with the inclination angle r of 10° to 30° may correspond to the fourth pixel PXLd or the fifth pixel PXLe. The values ​​presented in Tables 1 and 2 are merely examples for explaining the present invention, and the present invention should not be interpreted as being limited to the examples described through Tables 1 and 2.

[0240] As a result, the embodiment of the present disclosure can refract light (e.g., refract it in a predetermined direction) in the display panel DP and emit it. As a result, light emitted from the central region and the edge region of the display panel DP can be uniformly incident on the user. As a result, color deviation and brightness deviation in each region of the display panel DP can be improved.

[0241] The height of the steps STP, STP' may be determined depending on the distance between the sub-pixels SP and the tilt angle r. For example, the size of the steps STP, STP' in the embodiments where the distance between the sub-pixels SP is 1 μm (micrometer), 3 μm, and 5 μm for the embodiments where the tilt angles r are 10°, 20°, 30°, 40°, and 45° can be illustrated in Table 3 below.

[0242] [Table 3]

[0243] In Table 3, r corresponds to the inclination angle of the inclined surface ICN formed on the overcoat layer OC. PP corresponds to the distance between the sub-pixels. STP corresponds to the size of the step (or the height of the step). Referring to Table 3, the step STP formed on the overcoat layer OC in the display panel DP may be between 0 and 5 μm.

[0244] FIG. 14a is an example of a top view of a display panel DP according to an embodiment of the present disclosure.

[0245] Referring to FIG. 14a, a display panel DP according to an embodiment of the present disclosure may have a flat surface PLN located in a central region of the display panel DP and an inclined surface ICN surrounding the flat surface PLN.

[0246] The inclined surface ICN may be a region between the steps STP. The steps STP may be arranged in the form of concentric circles surrounding the flat surface PLN. The steps STP may be formed in the overcoat layer OC.

[0247] The inclination angle of the inclined surface ICN may become gradually larger as it moves away from the flat surface PLN located at the center of the display panel DP.

[0248] 14b to 14e are example side views of a display panel DP according to an embodiment of the present disclosure.

[0249] 14b, a display panel DP according to an embodiment of the present disclosure may include a lower substrate 1410, an overcoat layer OC on the lower substrate 1410, and a cover window CW on the overcoat layer OC. The lower substrate 1410 may include the substrate SUB to the optical function layer OFL described above in FIG.

[0250] As shown in FIG. 14b, in the overcoat layer OC according to the embodiment of the present disclosure, the uppermost ends of the multiple inclined surfaces ICN and the flat surface PLN can be located on the same plane.

[0251] As shown in FIG. 14c, in the overcoat layer OC according to the embodiment of the present disclosure, the lowest ends of the multiple inclined surfaces ICN and the flat surface PLN can be located on the same plane.

[0252] As shown in FIG. 14d, the overcoat layer OC according to the embodiment of the present disclosure may not include a step and may be composed of only an inclined surface ICN and a flat surface PLN.

[0253] In the embodiment of Figure 14d, the distance from the pixels located in the central region of the lower substrate 1410 to the upper surface of the overcoat layer OC may be relatively far, and the distance from the pixels located in the edge region of the lower substrate 1410 to the upper surface of the overcoat layer OC may be relatively close.

[0254] According to the embodiment of FIG. 14d, alignment between the overcoat layer OC and the light emitting elements LD1, LD2, and LD3 can be made easier than in the embodiment shown in FIGS. 10a to 10c.

[0255] Referring to FIG. 14 e , the display panel DP according to an embodiment of the present disclosure may further include a lower substrate 1410 , an overcoat layer OC, a cover window CW, and a light refracting layer 1420 .

[0256] Referring to Fig. 14e, the light refraction layer 1420 may include an inclined surface ICN and a flat surface PLN. According to an embodiment, the light refraction layer 1420 may further include the above-mentioned steps STP, STP' (see Figs. 9 to 13). In the above embodiment, the overcoat layer OC, the cover window CW, and the light refraction layer 1420 may constitute a protective layer PTL. The light refraction layer 1420 may function to guide a path along which light is emitted from the display panel DP.

[0257] FIG. 15 is a cross-sectional view for explaining the angle at which light LT1 is emitted from the first pixel PXLa according to another embodiment of FIG.

[0258] 15, light LT1 is shown being emitted from the first pixel PXLa onto the cover window CW (for example, in the third direction DR3). The light LT1 may be emitted in a vertical direction, and the first angle θ1 may be 0°.

[0259] The inclination angle of the top surface of the cover window CW with respect to the plane defined by the first direction DR1 and the second direction DR2 may be related to the angle of the light emitted from the pixel with the normal to the display panel. For example, when the inclination angle of the top surface of the cover window CW with respect to the plane defined by the first direction DR1 and the second direction DR2 increases, the angle of the light emitted from the pixel with the normal to the display panel may increase. For example, when the inclination angle of the top surface of the cover window CW with respect to the plane defined by the first direction DR1 and the second direction DR2 decreases, the angle of the light emitted from the pixel with respect to the normal to the display panel may decrease.

[0260] 15, the inclination angle that the top surface of the cover window CW makes with the plane defined by the first direction DR1 and the second direction DR2 is indicated as a first inclination angle r1. The first inclination angle r1 may be 0°. The first angle θ1 that the light LT1 emitted from the first pixel PXLa makes with the normal to the display panel may be 0°. The top surface of the cover window CW may include a flat surface PLN.

[0261] FIG. 16a is an example of a cross-sectional view illustrating an angle at which light is emitted from the second pixel PXLb according to another embodiment of FIG.

[0262] 16a, light LT2 is shown being emitted from the second pixel PXLb onto the cover window CW (e.g., in the third direction DR3). The light LT2 may be emitted at a second angle θ2 with the normal NM.

[0263] The inclination angle that the top surface of the cover window CW makes with the plane defined by the first direction DR1 and the second direction DR2 is denoted as the second inclination angle r2. The cover window CW may include an inclined surface ICN. The inclination angle of the inclined surface ICN may be the second inclination angle r2. The cover window CW may include a step STP continuing from the inclined surface ICN.

[0264] The second tilt angle r2 may be an acute angle greater than 0. The second angle θ2 that the light LT2 emitted from the second pixel PXLb makes with the normal NM to the display panel may be an acute angle greater than 0.

[0265] The refractive index of the cover window CW may be greater than the refractive index of the overcoat layer OC. Compared with Fig. 10a, the inclined surface ICN formed on the cover window CW may be formed in the opposite direction compared to the inclined surface ICN formed on the overcoat layer OC (see Fig. 10a).

[0266] According to an embodiment, the inclined surface ICN may be arranged in units of sub-pixels SP (or units of light-emitting elements LD). According to an embodiment, the inclined surface ICN may be arranged so as to cover two or more sub-pixels SP (or two or more light-emitting elements LD). According to an embodiment, the inclined surface ICN may be arranged in units of pixels PXL. According to an embodiment, the inclined surface ICN may be arranged so as to cover two or more pixels PXL.

[0267] 16a shows an embodiment in which an inclined surface ICN is disposed in units of the first to third sub-pixels SP1 to SP3. In the above embodiment, the inclined surface ICN may be disposed in correspondence with the lens array LA and the color filter layer CFL. However, the embodiment of the present disclosure is not limited thereto.

[0268] According to an embodiment, the step STP may be disposed between adjacent sub-pixels SP. In one embodiment, the step STP may be at the same (or substantially the same) distance to the light-emitting element LD of each of the adjacent sub-pixels SP. In another embodiment, the step STP may be at different distances to the light-emitting element LD of each of the adjacent sub-pixels SP.

[0269] Referring further to FIG. 8, the inclined surface ICN of the cover window CW may be inclined so that its height increases from the inside (corresponding to the right side in FIG. 16a) of the display panel DP toward the outside (corresponding to the left side in FIG. 16a).

[0270] Referring to Fig. 16a, the refractive index of the cover window CW may be greater than the refractive index of the external air. Thus, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted (primary refraction) at the inclined surface ICN in a direction opposite to the inclined direction of the inclined surface. Thus, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted and emitted in a direction (corresponding to the left side in Fig. 16a) outside the display panel DP (see Fig. 8) at an angle (e.g., a predetermined angle) greater than 0 with respect to the normal line NM.

[0271] FIG. 16b is another example of a cross-sectional view illustrating the angle at which the light LT2 is emitted from the second pixel PXLb according to the other embodiment of FIG.

[0272] 16b, light LT2 is shown being emitted from the second pixel PXLb onto the cover window CW (e.g., in the third direction DR3). The light LT2 may be emitted at a second angle θ2 with the normal NM.

[0273] The inclined surface ICN may be disposed so as to cover two or more sub-pixels SP. Referring to FIG. 10b, an embodiment in which the inclined surface ICN is disposed so as to cover two or more of the first to third sub-pixels SP1 to SP3 (for example, the first sub-pixel SP1 and the second sub-pixel SP2) is shown. In the above embodiment, the inclined surface ICN may be disposed in a unit different from that of the lens array LA and the color filter layer CFL. This may make it easier to align the overcoat layer OC and the light-emitting elements LD1, LD2, LD3 compared to the embodiment shown in FIG. 16a.

[0274] FIG. 17 is another example of a cross-sectional view for explaining the angle at which the light LT3 is emitted from the third pixel PXLc according to the other embodiment of FIG.

[0275] 17, light LT3 is shown being emitted from the third pixel PXLc onto the cover window CW (for example, in a third direction DR3). The light LT3 may be emitted at a third angle θ3 with the normal NM.

[0276] The inclination angle that the top surface of the cover window CW makes with the plane defined by the first direction DR1 and the second direction DR2 is denoted as the third inclination angle r3. The cover window CW may include an inclined surface ICN. The inclination angle of the inclined surface ICN may be the third inclination angle r3. The cover window CW may include a step STP continuing from the inclined surface ICN.

[0277] The inclined direction of the inclined surface ICN of the third pixel PXLc may be opposite to the inclined direction of the inclined surface ICN of the second pixel PXLb (see FIGS. 16a and 16b).

[0278] The third tilt angle r3 may be an acute angle greater than 0. The third angle θ3 that the light LT3 emitted from the third pixel PXLc makes with the normal NM to the display panel may be an acute angle greater than 0. In an embodiment in which the third tilt angle r3 is the same as the second tilt angle r2 (see FIGS. 10a to 10c), the third angle θ3 may be the same (or substantially the same) as the second angle θ2 (see FIGS. 10a to 10c).

[0279] 17, the refractive index of the cover window CW may be greater than the refractive index of the external air. Thus, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted (primary refraction) by the inclined surface ICN in a direction opposite to the inclined direction of the inclined surface. Thus, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted and emitted in a direction (corresponding to the right side in FIG. 17) outside the display panel DP (see FIG. 8) at an angle (e.g., a predetermined angle) greater than 0 with respect to the normal line NM.

[0280] FIG. 18 is another example of a cross-sectional view for explaining the angle at which the light LT4 is emitted from the fourth pixel PXLd in FIG.

[0281] 18, light LT4 is shown being emitted from the fourth pixel PXLd onto the cover window CW (for example, in the third direction DR3). The light LT4 may be emitted at a fourth angle θ4 with the normal NM.

[0282] The inclination angle that the top surface of the cover window CW makes with the plane defined by the first direction DR1 and the second direction DR2 is denoted as a fourth inclination angle r4. The cover window CW may include an inclined surface ICN. The inclination angle of the inclined surface ICN may be a fourth inclination angle r4. The cover window CW may include a step STP continuing from the inclined surface ICN.

[0283] The direction in which the inclined surface ICN of the fourth pixel PXLd is inclined may be the same (or substantially the same) as the direction in which the inclined surface ICN of the second pixel PXLb (see FIGS. 16a and 16b) is inclined.

[0284] The fourth tilt angle r4 may be an acute angle greater than 0 and smaller than the second tilt angle r2 (see FIGS. 16a and 16b). The fourth angle θ4 that the light LT4 emitted from the fourth pixel PXLd makes with the normal NM to the display panel may be an acute angle greater than 0 and smaller than the second angle θ2 (see FIGS. 16a and 16b).

[0285] 18, the refractive index of the cover window CW may be greater than the refractive index of the external air. Thus, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted (primary refraction) by the inclined surface ICN in a direction opposite to the inclined direction of the inclined surface. Thus, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted and emitted in a direction (corresponding to the left side in FIG. 18) outside the display panel DP (see FIG. 8) at an angle (e.g., a predetermined angle) greater than 0 with respect to the normal line NM.

[0286] 16a, the fourth tilt angle r4 of the fourth pixel PXLd may be smaller than the second tilt angle r2 of the second pixel PXLb, so that the fourth angle θ4 between the light LT4 emitted from the fourth pixel PXLd and the normal line NM may be smaller than the second angle θ2 between the light LT2 emitted from the second pixel PXLb and the normal line NM.

[0287] FIG. 19 is another example of a cross-sectional view for explaining the angle at which the light LT5 is emitted from the fifth pixel PXLe in FIG.

[0288] 19, light LT5 is shown being emitted from the fifth pixel PXLe onto the cover window CW (for example, in the third direction DR3). The light LT5 can be emitted at a fifth angle θ5 with the normal NM.

[0289] The inclination angle that the top surface of the cover window CW makes with the plane defined by the first direction DR1 and the second direction DR2 is denoted as a fifth inclination angle r5. The cover window CW may include an inclined surface ICN. The inclination angle of the inclined surface ICN may be a fifth inclination angle r5. The cover window CW may include a step STP following the inclined surface ICN.

[0290] The tilt direction of the inclined surface ICN of the fifth pixel PXLe may be opposite to the tilt direction of the inclined surface ICN of the fourth pixel PXLd (see FIG. 18) described above.

[0291] The fifth tilt angle r5 may be an acute angle greater than 0 and less than the third tilt angle r3 (see FIG. 17). The fifth angle θ5 between the light LT5 emitted from the fifth pixel PXLe and the normal NM to the display panel may be an acute angle greater than 0 and less than the third angle θ3 (see FIG. 17). In an embodiment in which the fifth tilt angle r5 is the same as the fourth tilt angle r4 (see FIG. 18), the fifth angle θ5 may be the same (or substantially the same) as the fourth angle θ4 (see FIG. 18).

[0292] 19, the refractive index of the cover window CW may be greater than the refractive index of the external air. Thus, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted (primary refraction) by the inclined surface ICN in a direction opposite to the inclined direction of the inclined surface. Thus, the light emitted from the light emitting elements LD1, LD2, and LD3 may be refracted and emitted in a direction (corresponding to the right side in FIG. 19) outside the display panel DP (see FIG. 8) at an angle (e.g., a predetermined angle) greater than 0 with respect to the normal line NM.

[0293] 17, the fifth tilt angle r5 of the fifth pixel PXLe may be smaller than the third tilt angle r3 of the third pixel PXLc, so that the fifth angle θ5 between the light LT5 emitted from the fifth pixel PXLe and the normal line NM may be smaller than the third angle θ3 between the light LT3 emitted from the third pixel PXLc and the normal line NM.

[0294] Referring to Figures 8 and 15 to 19 as a whole, the relationship between the inclination angle r of the inclined surface ICN with respect to the refractive index (or the second refractive index) of the cover window CW and the angle θ at which light is emitted, from the pixel PXL located in the central region of the display panel DP to the pixel PXL located in the edge region of the display panel DP, can be illustratively explained through the following Tables 4 to 6.

[0295] [Table 4]

[0296] [Table 5]

[0297] [Table 6]

[0298] In Tables 4 to 6, the second refractive index may correspond to the refractive index of the cover window CW. r may correspond to the inclination angle of the inclined surface ICN. θ may correspond to the angle at which light (e.g., light of a predetermined wavelength band) emitted from a pixel PXL having an inclined surface ICN with a corresponding inclination angle r is emitted to the upper surface of the cover window CW. Referring to Table 6, since light emitted from a light emitting element of a pixel with an inclination angle r of 40° is totally reflected by the inclined surface ICN, the second refractive index may have a value smaller than 1.6 in the embodiments of FIGS. 15 to 19. Alternatively, in the embodiments in which the second refractive index is 1.6 or more, the inclination angle r of a pixel located in an edge region of the display panel DP may have a value smaller than 40°.

[0299] In Tables 4 to 6, a pixel with a tilt angle r of 0° may correspond to the first pixel PXLa in FIG. 8. In Tables 3 to 5, a pixel with a tilt angle r of 40° may correspond to the second pixel PXLb or the third pixel PXLc in FIG. 8. In Tables 1 and 2, a pixel with a tilt angle r of 10° to 30° may correspond to the fourth pixel PXLd or the fifth pixel PXLe. The values ​​presented in Tables 4 to 6 are merely examples for explaining the present invention, and the present invention should not be construed as being limited to the examples described through Tables 4 to 6.

[0300] As a result, the embodiment of the present disclosure can refract light from the display panel DP (for example, refract it in a predetermined direction) and emit it. As a result, light emitted from the central region and the edge region of the display panel DP can be uniformly incident on the user. As a result, color deviation and brightness deviation in each region of the display panel DP can be improved.

[0301] The size of the step STP (or the height of the step STP) may be determined by the distance between the sub-pixels SP and the tilt angle r. For example, the size of the step STP in the embodiments in which the distance between the sub-pixels SP is 1 μm (micrometer), 3 μm, and 5 μm for the embodiments in which the tilt angles r are 10°, 20°, 30°, 40°, and 45°, respectively, may be exemplarily described through the following Table 7.

[0302] [Table 7]

[0303] In Table 7, r corresponds to the inclination angle of the inclined surface ICN formed on the cover window CW. PP corresponds to the distance between the sub-pixels. STP corresponds to the size of the step (or the height of the step). Referring to Table 7, the step STP formed on the cover window CW in the display panel DP may be between 0 and 5 μm.

[0304] FIG. 20a is an example of a top view of a display panel DP according to an embodiment of the present disclosure.

[0305] Referring to FIG. 20a, a display panel DP according to an embodiment of the present disclosure may have a flat surface PLN located in a central region of the display panel DP and an inclined surface ICN surrounding the flat surface PLN.

[0306] The inclined surface ICN may be a region between the steps STP. The steps STP may be arranged in the form of concentric circles surrounding the flat surface PLN. The steps STP may be formed in the cover window CW.

[0307] The inclination angle of the inclined surface ICN may become gradually larger as it moves away from the flat surface PLN located at the center of the display panel DP.

[0308] 20b and 20c are examples of side views of a display panel DP according to an embodiment of the present disclosure.

[0309] 20b, a display panel DP according to an embodiment of the present disclosure may include a lower substrate 1410, an overcoat layer OC on the lower substrate 1410, and a cover window CW on the overcoat layer OC. The lower substrate 1410 may include the substrate SUB to the optical function layer OFL described above in FIG.

[0310] As shown in FIG. 20b, in the cover window CW according to the embodiment of the present disclosure, the uppermost ends of the multiple inclined surfaces ICN and the flat surface PLN can be located on the same plane.

[0311] As shown in FIG. 20c, in the cover window CW according to the embodiment of the present disclosure, the lowest ends of the multiple inclined surfaces ICN and the flat surface PLN can be located on the same plane.

[0312] 21 to 25 are diagrams illustrating a manufacturing method of a display panel according to an embodiment of the present disclosure.

[0313] Referring to Figures 21 to 25, a manufacturing method for a display panel according to an embodiment of the present disclosure may include step S2000 of preparing a lower substrate, step S2100 of forming an overcoat layer OC, step S2200 of pressing with a stamp, step S2300 of forming an inclined surface, and step S2400 of forming a cover window, etc.

[0314] In step S2000 of preparing a lower substrate, a pixel circuit layer PCL (see FIG. 5), a light emitting element layer LDL, a thin film encapsulation layer TFE, an adhesive layer APL, a color filter layer CFL, and a lens array LA may be sequentially formed on a substrate SUB (see FIG. 5). The lower substrate may be configured the same as or similar to the lower substrate 1410 described in FIGS. 14b to 14e, 20b, and 20c.

[0315] In the step S2100 of forming the overcoat layer OC, the overcoat layer OC may be disposed on the lower substrate. For example, in an embodiment in which the overcoat layer OC includes an epoxy resin, in the step S2100 of forming the overcoat layer OC, the epoxy resin may be applied onto the lens array LA.

[0316] In the stamp pressing step S2200, a stamp SMP may be prepared. The stamp SMP may include an inclined surface mold ICN_m. In the stamp pressing step S2200, the stamp SMP may press a protective layer (e.g., an overcoat layer OC) in one direction (e.g., the opposite direction of the third direction DR3). In the stamp pressing step S2200, the protective layer (e.g., the overcoat layer OC) may be hardened.

[0317] According to an embodiment, the inclined surface mold ICN_m may be arranged in units of sub-pixels SP. According to an embodiment, the inclined surface mold ICN_m may be arranged to cover two or more sub-pixels SP. According to an embodiment, the inclined surface mold ICN_m may be arranged in units of pixels PXL. According to an embodiment, the inclined surface mold ICN_m may be arranged to cover two or more pixels PXL.

[0318] In the step S2300 of forming the inclined surface, the stamp SMP may be detached from the protective layer (e.g., the overcoat layer OC). The protective layer (e.g., the overcoat layer OC) may be formed with an inclined surface ICN corresponding to the inclined surface mold ICN_m.

[0319] In the step S2400 of forming a cover window, the cover window CW may be formed on the overcoat layer OC. Referring to Fig. 25, in the step S2400 of forming a cover window, the cover window CW may be formed on the overcoat layer OC having an inclined surface ICN formed thereon. For example, in an embodiment in which the cover window CW includes glass, the cover window CW may be formed on the overcoat layer OC in such a manner that the glass having an inclined surface ICN on its lower surface is disposed.

[0320] 26 to 30 are diagrams illustrating a manufacturing method of a display panel according to another embodiment of the present disclosure.

[0321] Referring to Figures 26 to 30, a manufacturing method for a display panel according to an embodiment of the present disclosure may include step S2500 of preparing a lower substrate, step S2600 of forming an overcoat layer OC, step S2700 of forming a cover window, step S2800 of pressing with a stamp, and step S2900 of forming an inclined surface.

[0322] In step S2500 of preparing a lower substrate, a light emitting element layer LDL, a thin film encapsulation layer TFE, an adhesive layer APL, a color filter layer CFL, and a lens array LA may be sequentially formed on the substrate. The lower substrate may be configured the same as or similar to the lower substrate 1410 described in Figures 14b to 14e, 20b, and 20c.

[0323] In the step S2600 of forming the overcoat layer OC, the overcoat layer OC may be disposed on the lower substrate. For example, in an embodiment in which the overcoat layer OC includes an epoxy resin, in the step S2600 of forming the overcoat layer OC, the epoxy resin may be applied onto the lens array LA.

[0324] In step S2700 of forming a cover window, the cover window CW may be formed on the overcoat layer OC. Referring to Fig. 28, in step S2700 of forming a cover window, the cover window CW may be formed on the overcoat layer OC having a flat upper surface (e.g., a surface in the third direction DR3).

[0325] In the stamp pressing step S2800, a stamp SMP can be prepared. The stamp SMP can include an inclined surface mold ICN_m. In the stamp pressing step S2200, the stamp SMP can press a protective layer (e.g., a cover window CW) in one direction (e.g., the opposite direction of the third direction DR3). In the stamp pressing step S2800, the protective layer (e.g., the cover window CW) can be hardened.

[0326] According to an embodiment, the inclined surface mold ICN_m may be arranged in units of sub-pixels SP. According to an embodiment, the inclined surface mold ICN_m may be arranged to cover two or more sub-pixels SP. According to an embodiment, the inclined surface mold ICN_m may be arranged in units of pixels PXL. According to an embodiment, the inclined surface mold ICN_m may be arranged to cover two or more pixels PXL.

[0327] In the step S2900 of forming an inclined surface, the stamp SMP may be detached from a protective layer (e.g., a cover window CW). An inclined surface ICN corresponding to the inclined surface mold ICN_m may be formed in the protective layer (e.g., a cover window CW).

[0328] 31 to 37 are other views illustrating the method for manufacturing a display panel according to an embodiment of the present disclosure.

[0329] 31 to 37, a manufacturing method for a display panel according to an embodiment of the present disclosure may include step S3000 of preparing a lower substrate, step S3100 of forming an overcoat layer OC, step S3200 of forming a photoresist PR, step S3300 of pressing with a stamp, step S3400 of etching the photoresist PR and the protective layer, step S3500 of forming an inclined surface, and step S3600 of forming a cover window.

[0330] In step S3000 of preparing a lower substrate, a light emitting element layer LDL, a thin film encapsulation layer TFE, an adhesive layer APL, a color filter layer CFL, and a lens array LA may be sequentially formed on the substrate. The lower substrate may be configured the same as or similar to the lower substrate 1410 described in Figures 14b to 14e, 20b, and 20c.

[0331] In the step S3100 of forming the overcoat layer OC, the overcoat layer OC may be disposed on the lower substrate. For example, in an embodiment in which the overcoat layer OC includes an epoxy resin, in the step S3100 of forming the overcoat layer OC, the epoxy resin may be applied onto the lens array LA.

[0332] In step S3200 of forming a photoresist PR, a photoresist PR may be applied on the overcoat layer OC. The photoresist PR may include a chemical substance whose properties change in response to light.

[0333] In the stamp pressing step S3300, a stamp SMP may be prepared. The stamp SMP may include an inclined surface mold ICN_m. In the stamp pressing step S2200, the stamp SMP may press the photoresist PR in one direction (e.g., the opposite direction to the third direction DR3).

[0334] According to an embodiment, the inclined surface mold ICN_m may be arranged in units of sub-pixels SP. According to an embodiment, the inclined surface mold ICN_m may be arranged to cover two or more sub-pixels SP. According to an embodiment, the inclined surface mold ICN_m may be arranged in units of pixels PXL. According to an embodiment, the inclined surface mold ICN_m may be arranged to cover two or more pixels PXL.

[0335] In step S3400 of etching the photoresist PR and the protective layer, at least a portion of the photoresist PR and the protective layer (e.g., the overcoat layer OC) may be etched by the etcher ETC. The photoresist PR removed by the etcher ETC may have an inclined surface ICN corresponding to the inclined surface mold ICN_m. According to an embodiment, the photoresist PR may be entirely removed by the etcher ETC, but the embodiment of the present disclosure is not limited thereto.

[0336] In step S3500 of forming the inclined surface, the photoresist PR (see FIG. 35) may be removed from the overcoat layer OC. The overcoat layer OC may have an inclined surface ICN formed thereon, which corresponds to the inclined surface mold ICN_m (see FIG. 34). The inclined surface ICN may be formed by removing at least a portion of the overcoat layer OC by an etcher ETC (see FIG. 35).

[0337] In the step S3600 of forming a cover window, the cover window CW may be formed on the overcoat layer OC. Referring to Fig. 37, in the step S3600 of forming a cover window, the cover window CW may be formed on the overcoat layer OC having an inclined surface ICN formed thereon. For example, in an embodiment in which the cover window CW includes glass, the cover window CW may be formed on the overcoat layer OC in such a manner that the glass having an inclined surface ICN on its lower surface is disposed on the overcoat layer OC.

[0338] 38 to 40 are diagrams showing a lens array LA according to an embodiment of the present disclosure.

[0339] 38 to 40, various embodiments for the shape of the lens array LA according to the embodiments of the present disclosure are shown.

[0340] 38, the lens array LA according to the embodiment of the present disclosure may include a first lens LS1. The first lens LS1 may have a quadrilateral (e.g., trapezoidal) shape. The first lens LS1 may have a shape that narrows in width in the third direction DR3. The first lens LS1 may have a flat upper surface (e.g., a surface in the third direction DR3).

[0341] Referring to Fig. 39, the lens array LA according to the embodiment of the present disclosure may include a second lens LS2. The second lens LS2 may be configured as a polygon including two or more tapered inclined surfaces on the side. For example, the second lens LS2 may have a polygonal shape other than a square (e.g., a hexagon). The second lens LS2 may have a flat upper surface (e.g., a surface in the third direction DR3).

[0342] 40, the lens array LA according to the embodiment of the present disclosure may include a third lens LS3. The third lens LS3 may have a semicircular or water drop shape. The third lens LS3 may have a curved upper surface (e.g., a surface in the third direction DR3).

[0343] However, the shape of the lens array LA according to the embodiment of the present disclosure is not limited to the above, and the shape of the lens array LA presented in FIGS. 38 to 40 is merely one example.

[0344] FIG. 41 is a diagram illustrating an example of a display system 4000 according to an embodiment of the present disclosure.

[0345] Referring to FIG. 41, a display system 4000 may include a processor 4010 and one or more display devices 4020, 4030.

[0346] The processor 4010 can perform various tasks and calculations. In an embodiment, the processor 4010 can include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. The processor 4010 can be coupled to and control other components of the display system 4000 via a bus system.

[0347] 41, a display system 4000 is shown including first and second display devices 4020, 4030. A processor 4010 may be coupled to the first display device 4020 via a first channel CH1 and to the second display device 4030 via a second channel CH2.

[0348] Through the first channel CH1, the processor 4010 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 4020. The first display device 4020 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 4020 can be configured similarly to the display device 100 described with reference to FIG. 1. In this case, the first image data IMG1 and the first control signal CTRL1 can be provided as the input image data IMG and the control signal CTRL, respectively, of FIG. 1.

[0349] Through the second channel CH2, the processor 4010 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 4030. The second display device 4030 may display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 4030 may be configured similarly to the display device 100 described with reference to FIG. 1. In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as the input image data IMG and the control signal CTRL, respectively, of FIG. 1.

[0350] The display system 4000 may include a computing system providing a video display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. The display system 4000 may also include at least one of a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0351] FIG. 42 is a perspective view showing an application example of the display system 4000 of FIG.

[0352] 42, the display system 4000 of FIG. 41 can be applied to a head-mounted display device 4100. The head-mounted display device 4100 can be a wearable electronic device that can be worn on a user's head.

[0353] The head-mounted display device 4100 may include a head-mounted band 4110 and a display device housing case 4120. The head-mounted band 4110 may be coupled to the display device housing case 4120. The head-mounted band 4110 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 4100 to the user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the top of the user's head. However, the embodiment is not limited thereto. For example, the head-mounted band 4110 may be realized in the shape of a glasses frame, a helmet, or the like.

[0354] The display device housing case 4120 can house the first and second display devices 4020 and 4030 of Fig. 41. The display device housing case 4120 can further house the processor 4010 of Fig. 41.

[0355] FIG. 43 is a diagram showing a head-mounted display device 4100 worn by a user.

[0356] 43, a first display panel DP1 of a first display device 4020 (see FIG. 41) and a second display panel DP2 of a second display device 4030 (see FIG. 41) may be disposed in a head-mounted display device 4100. The head-mounted display device 4100 may further include one or more lenses. For example, the head-mounted display device 4100 may include a left-eye lens LLNS and a right-eye lens RLNS.

[0357] Within the display device housing case 4120, the right eye lens RLNS can be disposed between the first display panel DP1 and the right eye of the user USR. Within the display device housing case 4120, the left eye lens LLNS can be disposed between the second display panel DP2 and the left eye of the user USR.

[0358] An image output from the first display panel DP1 can be viewed by the right eye of the user USR through the right eye lens RLNS. The right eye lens RLNS can refract light emitted from the first display panel DP1 so that it is directed toward the right eye of the user USR. The right eye lens RLNS can perform an optical function for adjusting the viewing distance between the first display panel DP1 and the right eye of the user USR.

[0359] The image output from the second display panel DP2 can be viewed by the left eye of the user USR through the left eye lens LLNS. The left eye lens LLNS can refract light emitted from the second display panel DP2 so that it is directed toward the left eye of the user USR. The left eye lens LLNS can perform an optical function for adjusting the viewing distance between the second display panel DP2 and the left eye of the user USR.

[0360] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. In the above embodiment, each of the first and second display panels DP1 and DP2 may output images corresponding to the sub-regions of the multi-channel lens, and the output images may pass through the corresponding sub-regions and be viewed by the user USR.

[0361] The right-eye lens RLNS can be realized by applying the above-mentioned external lens 810 (see FIG. 8). The left-eye lens LLNS can be realized by applying the above-mentioned external lens 810 (see FIG. 8).

[0362] Referring further to FIG. 8 described above, light emitted from the central region of the first display panel DP1 may be incident on the central region of the right-eye lens RLNS. Light emitted from the peripheral region (e.g., edge region) of the first display panel DP1 may be incident on the peripheral region (e.g., edge region) of the right-eye lens RLNS. Light emitted from the central region of the second display panel DP2 may be incident on the central region of the left-eye lens LLNS. Light emitted from the peripheral region (e.g., edge region) of the second display panel DP2 may be incident on the peripheral region (e.g., edge region) of the left-eye lens LLNS.

[0363] The drawings and detailed description of the invention described above are merely illustrative of the present invention, and are used merely for the purpose of explaining the present invention, and are not used to limit the meaning or the scope of the present invention described in the claims. Therefore, a person having ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical ideas of the accompanying claims. [Explanation of symbols]

[0364] 100, 4020, 4030 display device 110, DP1, DP2 display panel 120 Gate drive circuit 130 Data Driver 140 Voltage Generator 150 Controller 160 Temperature Sensor 810 External Lens 1410 Lower Board 1420 Photorefractive layer 4000 Display System 4010 Processor 4100 Head-mounted display device 4110 Headband 4120 Display device storage case SUB board PCL Pixel circuit layer PXL Pixel LDL Light emitting device layer AE anode electrode PDL Pixel Defined Membrane EMS Light-emitting Structure CE cathode electrode TFE thin film encapsulation layer OFL optical functional layer CFL color filter layer CF Color Filter LA Lens Array LS, LS1, LS2, LS3 Lenses OC overcoat layer CW Cover Window PTL protection layer ICN, ICN' inclined plane STP, STP' step PLN flat surface SMP Stamp PR Photoresist ETC Etching Machine

Claims

1. A substrate; a pixel circuit layer disposed on the substrate, the pixel circuit layer including one or more switching elements and one or more storage elements; a light emitting device layer disposed on the pixel circuit layer, the light emitting device layer including a light emitting device electrically connected to the pixel circuit layer; an overcoat layer disposed on the light-emitting element layer and having a first refractive index; a cover window disposed on the overcoat layer and having a second refractive index greater than the first refractive index; A display panel, characterized in that at least one of the overcoat layer and the cover window includes a plurality of inclined surfaces, the inclination angles of the plurality of inclined surfaces being different in a central region of the substrate and an edge region of the substrate.

2. The display panel according to claim 1 , wherein the inclination angle of the plurality of inclined surfaces is smallest in the central region of the display panel and largest in the edge region of the display panel.

3. In the central region of the display panel, the light emitted from the light emitting element is emitted in a normal direction of the substrate, The display panel of claim 2 , wherein the light emitted from the light emitting element in the edge region of the display panel is emitted in a direction toward an outer edge of the substrate different from the normal direction of the substrate.

4. the overcoat layer includes the plurality of inclined surfaces, The display panel according to claim 1 , wherein the plurality of inclined surfaces increase in height from an outer side to an inner side of the substrate.

5. the cover window includes the plurality of inclined surfaces, The display panel according to claim 1 , wherein the plurality of inclined surfaces increase in height from the inside to the outside of the substrate.

6. The display panel according to claim 1 , wherein each of the plurality of inclined surfaces is disposed in units of the light-emitting elements.

7. Two or more light emitting elements are arranged in the light emitting element layer, The display panel according to claim 1 , wherein each of the plurality of inclined surfaces is arranged in units of two or more light emitting elements.

8. The display panel according to claim 1 , wherein at least some of the inclined surfaces are positioned on a line perpendicular to the light emitting element and shifted toward an outer side of the substrate.

9. The light-emitting element layer further includes an optical functional layer located between the light-emitting element layer and the overcoat layer, The optical functional layer is a color filter layer including a color filter configured to convert a wavelength band of light emitted from the light emitting element; a lens array including a lens; The display panel according to claim 8 , wherein the optical function layer is positioned so as to move in the same direction as the at least some of the plurality of inclined surfaces.

10. the overcoat layer includes an epoxy resin having a refractive index of the first refractive index, and the cover window includes a glass having a refractive index of the second refractive index; 2. The display panel according to claim 1, wherein the first refractive index is in the range of 1.2 to 1.4, and the second refractive index is in the range of 1.5 to 1.

9.

11. Providing a bottom substrate; forming an overcoat layer on the lower substrate; pressing the lower substrate on which the overcoat layer is formed with a stamp including an inclined surface mold; forming a corresponding inclined surface on the inclined surface mold; and forming a cover window on the overcoat layer.

12. In the step of pressing with the stamp, the stamp presses the upper surface of the overcoat layer; The method of claim 11 , wherein in the step of forming the inclined surface, the inclined surface is formed on the overcoat layer.

13. 13. The method of claim 12, wherein in the step of forming the cover window, a glass having an inclined surface on a lower surface thereof corresponding to the inclined surface of the overcoat layer is disposed on the overcoat layer.

14. further comprising applying a photoresist onto the overcoat layer; In the step of pressing with the stamp, the stamp presses the applied photoresist; The method of claim 11, wherein the photoresist has an inclined surface corresponding to the inclined surface mold.

15. further comprising the step of etching; In the etching step, an etching machine etches the photoresist and the overcoat layer on which the inclined surface is formed; The method of claim 14, wherein in the step of forming the inclined surface, the overcoat layer is provided with an inclined surface corresponding to the inclined surface mold.

16. 12. The method of claim 11, wherein in the step of preparing the lower substrate, a pixel circuit layer, a light emitting element layer, a thin film encapsulation layer, an adhesive layer, a color filter layer, and a lens array are sequentially formed on the substrate.

17. a first display panel that is disposed in the display device storage case and has a protective layer disposed on the top layer, the protective layer including a plurality of inclined surfaces; a right eye lens disposed in the display device storage case and configured to refract the light refracted by the plurality of inclined surfaces of the first display panel again toward the right eye of the user; a second display panel located in the display device storage case and spaced apart from the first display panel, the second display panel having a protective layer disposed on the topmost layer and including a plurality of inclined surfaces; a left eye lens disposed within the display device storage case and configured to refract light refracted by the multiple inclined surfaces of the second display panel again toward the user's left eye.

18. light emitted from a central region of the first display panel is incident on a central region of the right eye lens, and light emitted from an edge region of the first display panel is incident on an edge region of the right eye lens, The head-mounted display device of claim 17, wherein light emitted from a central region of the second display panel is incident on a central region of the left eye lens, and light emitted from an edge region of the second display panel is incident on an edge region of the left eye lens.

19. Each of the first display panel and the second display panel is A substrate; a pixel circuit layer disposed on the substrate, the pixel circuit layer including one or more switching elements and one or more storage elements; a light emitting device layer disposed on the pixel circuit layer, the light emitting device layer including a light emitting device electrically connected to the pixel circuit layer; an overcoat layer disposed on the light-emitting element layer and having a first refractive index; a cover window disposed on the overcoat layer and having a second refractive index greater than the first refractive index; 18. The head-mounted display device of claim 17, wherein at least one of the overcoat layer and the cover window includes a plurality of inclined surfaces, the inclination angles of the plurality of inclined surfaces being different in a central region of the substrate and an edge region of the substrate.

20. The head mounted display device according to claim 19 , wherein the inclination angles of the plurality of inclined surfaces increase with increasing distance from the central region of the substrate.

Images