Power stage controller

Abstract

To provide a controller for controlling a power stage having one or more phases.SOLUTION: A controller includes: a reference circuit that generates a reference signal; a ramp generator that generates a feedback ramp signal on the basis of a feedback signal from a power stage; and a modulator adapted to generate a control signal for controlling at least one phase of the power stage. The control signal may be formed of continuous pulses, and each pulse may be associated with the corresponding phase of the power stage.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to a controller for controlling a power stage, and more particularly, to a controller for controlling a constant on-time (COT) converter. [Background technology]

[0002] Constant on-time switching converters offer several advantages over other types of switching converters, including faster transient response, higher efficiency under light loads, and smoother transition from continuous conduction mode (CCM) to discontinuous conduction mode (DCM) operation.

[0003] Although COT converters can be implemented with multiple phases, traditional multi-phase COT requires complex wiring signals, which increases the power supply footprint and limits system integration. Summary of the Invention [Problem to be solved by the invention]

[0004] It is an objective of the present disclosure to address one or more of the limitations set forth above. [Means for solving the problem]

[0005] According to a first aspect of the present disclosure, there is provided a controller for controlling a power stage having one or more phases, the controller including a reference circuit adapted to generate a reference signal, a ramp generator adapted to generate a feedback ramp signal based on a feedback signal of the power stage, and a modulator adapted to generate a control signal for controlling at least one phase of the power stage.

[0006] Optionally, the feedback ramp signal has a frequency that is a function of the number of active phases of the power stage.

[0007] Optionally, the control signal consists of a series of pulses, each pulse associated with a corresponding phase of the power stage.

[0008] Optionally, each pulse is associated with an on-time of the corresponding phase.

[0009] Optionally, the modulator includes a comparator adapted to compare the feedback ramp signal and a reference signal to obtain a modulated signal, a sampling circuit configured to sample the modulated signal and generate a digital modulated signal, a logic circuit configured to generate a control signal based on the digital modulated signal, and an oscillator coupled to the sampling circuit and the logic circuit.

[0010] For example, the sampling circuit may include a first storage device serially coupled to a second storage device, which may be a D-type flip-flop.

[0011] Optionally, the logic circuitry includes a counter configured to calculate the duration between successive pulses of the control signal.

[0012] Optionally, the logic circuitry is configured to encode the digitally modulated signal for a particular protocol.

[0013] Optionally, the logic circuit is a state machine, for example the state machine may be a finite state machine (FSM).

[0014] Optionally, the ramp generator includes a capacitor, a first transconductance amplifier coupled to the capacitor via a first switch, a second transconductance amplifier coupled to the capacitor via a second switch, and a timer configured to control the first switch and the second switch.

[0015] Optionally, the controller includes a closed loop operational amplifier.

[0016] Optionally, the controller further includes a duty cycle estimator configured to estimate a duty cycle of the power stage, and a ramp amplitude adjuster configured to adjust an amplitude of the feedback ramp signal based on the estimate of the duty cycle.

[0017] According to a second aspect of the present disclosure, there is provided a power supply apparatus according to the first aspect coupled to a power stage having one or more phases.

[0018] Optionally, the controller is coupled to the power stage via a single wire interface, which may for example be a single wire modulated transport interface.

[0019] Optionally, the power stage includes a plurality of phases, each phase including a high-side power switch coupled to a low-side power switch at a switching node.

[0020] Optionally, for each phase, the power stage includes a driver. The driver includes a decoder for decoding the control signal.

[0021] Optionally, the decoder is configured to measure the pulse width of each pulse of the control signal and to compare the measured pulse width with a predefined predetermined pulse width value.

[0022] Optionally, the power supply is a constant on-time converter.

[0023] According to a third aspect of the present disclosure, there is provided a method of controlling a power stage having one or more phases, the method comprising: generating a reference signal; generating a feedback ramp signal based on a feedback signal of a power stage; generating a control signal for controlling at least one phase of a power stage; Includes.

[0024] Optionally, the control signal is a single control signal.

[0025] Optionally, the method includes calculating a duration between successive pulses of the control signal, activating one or more phases if the duration is less than a first threshold, and deactivating one or more phases if the duration is greater than a second threshold.

[0026] The first threshold may be a minimum duration and the second threshold may be a maximum duration. [Brief description of the drawings]

[0027] The present disclosure will now be described in further detail, by way of example only, with reference to the accompanying drawings, in which: [Figure 1] FIG. 1 illustrates a conventional constant on-time buck converter. [Diagram 2] 2 is a plot of lamp voltage as a function of time illustrating the operation of the converter of FIG. 1. [Diagram 3] FIG. 1 illustrates a conventional multi-phase converter. [Figure 4] 4 illustrates the feedback ramp voltage, the reference voltage, the control signal, and the state of the high-side power switch for each phase of the multi-phase converter of FIG. 3. [Diagram 5] 4 is a flowchart of a method for controlling a power stage according to the present disclosure. [Figure 6] FIG. 1 illustrates a power supply device according to the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating the operation of the power supply device of FIG. [Figure 8A] FIG. 7 is a diagram illustrating an example of implementation of the controller in FIG. 6. [Figure 8B] FIG. 8B illustrates an alternative implementation of a ramp generator used in the circuit of FIG. 8A. [Figure 8C] FIG. 8B illustrates a further alternative implementation of a ramp generator for use in the circuit of FIG. 8A. [Figure 8D] FIG. 4 is a functional diagram of a state machine for generating control signals. [Figure 8E] FIG. 8E is a plot diagram illustrating the operation of the state machine of FIG. 8D. [Figure 9] FIG. 8B illustrates an example implementation of a power stage having two phases for use with the controller of FIG. 8A. [Figure 10] FIG. 7 is a waveform diagram illustrating the operation of the system of FIG. [Figure 11] FIG. 4 is a waveform diagram showing a feedback ramp voltage having two different amplitudes. [Figure 12] FIG. 13 is a plot of normalized lamp amplitude as a function of duty cycle obtained with and without scaling. [Figure 13] FIG. 13 is a diagram illustrating an implementation example of a duty cycle estimator. [Figure 14] FIG. 7 illustrates the operation of the circuit of FIG. 6 under transient load conditions. [Figure 15] FIG. 7 is a plot showing the output voltage, inductor currents in each phase, and switching periods during a load transient for the circuit of FIG. 6. [Figure 16] 7 is a plot diagram illustrating the feedback ramp signal, the sampling clock signal, the modulation signal, and the control signal of the circuit of FIG. 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] 1 shows a conventional constant on-time (COT) buck converter. The converter 100 includes a high-side power switch S1, a low-side power switch S2, an inductor L, a driver 110, and an output regulation loop for regulating the output voltage of the converter. The output regulation loop is regulated by a feedback ramp signal V RAMP and a pulse width modulation (PWM) comparator 130. The PWM comparator 130 has a first input for receiving a reference signal Vref and a second input for receiving a feedback ramp voltage V RAMP and one output coupled to the driver 110.

[0029] FIG. 2 is a plot diagram illustrating the operation of the converter of FIG. 1. The upper waveform shows the feedback reference voltage, and the lower waveform shows the state (on or off) of switch S1. During operation, the feedback lamp voltage V RAMP When (=Vout+ramp) reaches Vref, comparator 130 sends a logic high to driver 110. Driver 110 then turns on high-side switch S1 for a fixed duration D*T, where D represents the duty cycle and T represents the switching period, hence the name "constant on-time switching converter." Once this fixed duration has elapsed, driver 110 turns off switch S1 and turns on switch S2. The output voltage is regulated to be D*Vin, where V in represents the supply voltage. The on-time of S1 is a predefined time, when which S1 is turned off. To accommodate larger output loads, it is common practice to have multiple power stages paralleled.

[0030] 3 shows a conventional multi-phase converter. Multi-phase converter 300 is a four-phase step-down converter with four phases coupled in parallel. For clarity of illustration, only two phases 310 and 340 are shown.

[0031] Each phase includes a high-side power switch coupled to a low-side power switch at a switching node, an inductor coupled to the switching node, and a driver U for driving the high-side power switch and the low-side power switch. Each phase includes separate control and feedback. A controller 305 is provided to generate four control signals CNTL1-CNTL4 for controlling the drivers U1-U4, respectively. Thus, each phase includes a separate ramp signal V RAMP1 ~V RAMP4 There is a separate control signal that comes from

[0032] To ensure proper operation, additional controllers (not shown) are required, e.g., for load sharing and phase control. Each converter in the multi-phase converter may be implemented as a COT buck converter.

[0033] FIG. 4 illustrates the feedback ramp voltage, the reference voltage, the control signal, and the state of the high-side power switch for each phase of the multi-phase converter of FIG.

[0034] The four phases operate in anti-phase with each other, but may operate in phase under dynamic load (transient) conditions. Each phase is controlled by a separate ramp signal, which determines the on and off states of the power switches. When the ramp voltage equals the reference voltage, a control signal is generated that turns on the power transistors. Once in the on state, the power transistors remain on for a predefined, predetermined fixed on-time (COT).

[0035] The converter in Figure 3 requires a separate control signal (to turn each phase on / off) and a separate feedback ramp signal for each phase, which not only increases the system footprint (e.g., routing of signal traces), but also makes the system more susceptible to noise and reduces the system integration.

[0036] The converter of Figure 3 can also be limited by thermal instability. The use of different control and feedback signals for each phase presents the challenge of balancing the on-time, and therefore the load, of each phase. Any imbalance in the output current of each phase can lead to thermal instability and reduced reliability.

[0037] 5 is a flow chart of a method for controlling a power stage according to the present disclosure. The method includes steps 510 to 530.

[0038] A reference signal is generated in step 510. The reference signal Vref may be selected to result in a desired output voltage, i.e., such that the converter operates with Vout=Vref.

[0039] A feedback ramp signal is generated based on the feedback signal of the power stage at step 520. At step 530, a control signal is generated for controlling at least one phase of the power stage.

[0040] For example, a power stage may include multiple phases, and the control signal is configured to control all phases of the power stage.

[0041] 6 is a diagram illustrating a power supply according to the present disclosure. The power supply or converter 600 includes a controller 605 coupled to a power stage that includes four phases coupled in parallel. For clarity of illustration, only two phases 610 and 640 are shown. Note that the number of phases can be more or less depending on the application. The controller 605 is coupled to each phase of the power stage via a single connection that splits into multiple branches, one for each phase of the power stage.

[0042] Each phase includes a high-side power switch coupled to a low-side power switch at a switching node, an inductor coupled to the switching node, and a driver U for driving the high-side power switch and the low-side power switch. Each driver also includes a decoder for decoding control signals. For example, driver U1 of phase 610 includes a decoder D1. Similarly, driver U4 of phase 640 includes a decoder D4.

[0043] The controller 605 generates a single feedback ramp signal V RAMP Therefore, there is no need to generate a separate feedback ramp signal for each phase.

[0044] The architecture of power supply 600 is scalable from single phase to multi-phase, which may be used to increase power density and simplify system integration.

[0045] Figure 7 illustrates the operation of the power supply of Figure 6. Shown in Figure 7 are a ramp voltage 710, a reference voltage 720, and a control signal 730. Also shown is the state of the high-side power switch of each phase (either on or off). Waveform 740 represents the state of high-side power switch S1 of the first phase, waveform 750 represents the state of high-side power switch S3 of the second phase, waveform 760 represents the state of high-side power switch S5 of the third phase, and waveform 770 represents the state of high-side power switch S7 of the fourth phase.

[0046] In operation, the controller 605 generates a single control signal 730 to initiate a turn-on state of all phases (1 to n, in this embodiment n=4). The control signal 730 is composed of multiple pulses. In this embodiment, pulses T1, T3, T5, and T7 are used to switch the high-side power switches S1, S3, S5, and S7, respectively. The pulses directed to a particular phase may have a particular pulse width. Thus, the pulses T1, T3, T5, and T7 may have different pulse widths.

[0047] Each driver receives the same control signal 730. A decoder within the driver then decodes the control signal to pass only the relevant pulse. For example, decoder D1 passes pulse T1, which is directed to power switch S1, and blocks the other pulses T3, T5, and T7. Similarly, decoder D4 passes pulse T7, which is directed to power switch S7, and blocks the other pulses T1, T3, and T5.

[0048] To identify the appropriate pulses, the decoder may measure the pulse width of each received pulse and compare the measured pulse width to a predetermined pulse width value. If the pulse width equals the predetermined value, the pulse is passed, otherwise the pulse is blocked. The decoder may be implemented in a variety of ways, using analog or digital circuitry.

[0049] The power converter 600 uses a single-wire modulation transport interface (SWMTI) to transmit control signals over a single wire to the n drivers for the n phases. This approach minimizes the need for other communications between the controller 605 and the drivers. The controller 605 only requires connections to the power input voltage and the converter output voltage, and does not require connections to switching nodes. The power converter 600 automatically optimizes its operation for every possible duty cycle operation. For example, the slope of the ramp may be adjusted to suit the operating conditions.

[0050] 8A is a diagram illustrating an example implementation of the controller of FIG. 6. The controller 800 has multiple input ports for receiving an input voltage VIN, a feedback signal FB from the power converter, and optionally a total average current from all phases. The controller 800 also includes an output port for communicating with a multi-phase power stage via a single-wire modulation transport interface (SWMTI). The signal FB may be equal to VOUT. Alternatively, the feedback signal may be a function of VOUT, for example, FB may be defined as FB=Vout-X or FB=Vout / X, where X represents a constant value.

[0051] The controller 800 includes a reference circuit 810 for generating a reference signal, a ramp generator 820 for generating a feedback ramp signal, and a modulator 830 adapted to generate a control signal for controlling a plurality of drivers of the multi-phase power stage.

[0052] The reference circuit 810 includes a feedback circuit 812 coupled to a compensation circuit 814. The feedback circuit 812 has a DAC for generating a compensated reference signal Vref_comp. The compensation circuit 814 includes a transconductance amplifier having a first input for receiving the signal Vref_comp and a second input for receiving the feedback signal FB. The output of the reference circuit 810 is a reference voltage Vref.

[0053] The modulator 830 includes a comparator 832, two D-type flip-flops 833a and 833b coupled in series, an oscillator 834, and a logic circuit 835 for generating a control signal. The comparator 832 has a first input for receiving a reference signal Vref and a second input for receiving a feedback ramp signal V RAMP a second input for receiving a modulating signal V MOD to the input of a first D-type flip-flop 833a. RAMP In the case of V MOD is high (logic 1), otherwise V MOD is low (logic 0).

[0054] Comparing the ramp signal Vramp directly to Vref can introduce errors in the DC output voltage, so a small correction is added using a transconductance amplifier and the RcCc network in circuit 814 to correct for the small error, however this is not necessary and Vref can be fed directly to the Vcomp node.

[0055] D-type flip-flops 833a and 833b constitute a sampling circuit. MOD and is used to provide a digital modulated signal at an input of logic circuit 835. Logic circuit 835 may be a state machine configured to encode a digital version of the modulated signal for a particular protocol. Different protocols may be associated with different algorithms implemented by the state machine. Logic circuit 835 may also include a period counter (not shown) for calculating the duration or period between successive pulses of a control signal (see control signal 730 of FIG. 7).

[0056] The counter measures the time between two toggles of the comparator output signal Vmod. The output of the logic circuit 835 is the control signal S_cont.

[0057] The ramp generator 820 includes two transconductance amplifiers gm1 and gm2. Each transconductance amplifier is coupled to a common node A via a corresponding switch M1 and M2, respectively. The first transconductance amplifier gm1 receives an input voltage VIN and a feedback voltage FB. The second transconductance amplifier gm2 receives the feedback voltage FB and ground. A capacitor Cf is provided having a first terminal coupled to the feedback voltage FB and a second terminal coupled to the node A.

[0058] A closed loop operational amplifier 822 is provided having a non-inverting input coupled to the feedback shifter of circuit 810 and an inverting input coupled to the output of the amplifier in the closed loop. The output of amplifier 822 is coupled to node A via resistor Rf.

[0059] The output impedance of the closed loop amplifier 822 is less than Rf but can be high. A fast feedback path is provided via Cf. The closed loop amplifier 822 is used to bring the average voltage of the feedback ramp to a desired level. The closed loop amplifier 822 is used to set the average voltage of the ramp. If the ramp is in the range between Va (valley) and Vb (peak), then peak to peak is Vb-Va. The amplitude can be peak to peak and the average amplitude can be (Vb-Va) / 2. Therefore, the desired level of the average voltage of the feedback ramp is referred to here as the average value (Va+Vb) / 2.

[0060] The ramp generator 820 also includes a timer 824 for controlling the switches M1 and M2.

[0061] FIG. 8B illustrates an alternative ramp generator for use in the circuit of FIG. 8A.

[0062] This is a simpler implementation that provides a fast feedback path, but in this case the average voltage of the lamp is close to the output voltage.

[0063] Figure 8C shows yet another ramp generator for use in the circuit of Figure 8A. The closed loop amplifier allows the average voltage of the ramp to be set at a desired position. However, the closed loop amplifier has a low output impedance.

[0064] In operation, the logic circuit 835 sends a signal to the timer 824, which controls the operation of the switches M1 and M2. When M1 is on and M2 is off, the first transconductance amplifier gm1 is activated and the capacitor Cf is charged. When M2 is on and M1 is off, the second transconductance amplifier gm2 is activated and the capacitor Cf is discharged. The charging and discharging of the capacitor Cf results in a feedback ramp voltage V RAMP This occurs.

[0065] The timer circuit 824 is configured to calculate the on-time TON_ideal of the power supply for all phases. For example, if the power supply has four phases, then TON_ideal=TON_phase1=TON_phase2=TON_phase3=TON_phase4. The TON of each phase may be different, but in most cases they are the same or similar. TON_ideal is based on the input voltage VIN and output voltage VOUT of the power supply as TON_ideal=TswVOUT / VIN, where Tsw represents the desired switching period of the power switch. The switching cycle of M1 and M2 is determined by TON_ideal divided by the number of active phases of the power supply. For example, if TON_ideal=100ns and the power supply has one phase, the switching cycle is 100ns. If the power supply has four phases all activated, the switching cycle is 25ns. If the power supply has four phases and only two phases are activated, the switching cycle is 50ns. The on-time of the lamp is TON_ideal / number of phases.

[0066] Compared to the prior art, the feedback ramp voltage is N times faster, where N represents the number of phases (4 times faster in this numerical example), which allows a single control signal to be used to control all phases.

[0067] Optionally, the logic circuit 835 may be connected to a current measurement circuit 860 having an input for receiving the total output average current of all phases I_avg_total. The configured current measurement circuit 860 may be implemented in different ways, for example as an analog-to-digital converter or as a set of comparators.

[0068] Optionally, controller 800 may also include a ramp amplitude adjuster 840 coupled to duty cycle estimator 850 to adaptively adjust the amplitude of the feedback ramp signal. In operation, ramp amplitude adjuster 840 receives the duty cycle from duty cycle estimator 850 and varies transconductances gm1 and gm2 to adjust the amplitude of the ramp signal.

[0069] 8D is a functional diagram of a state machine for generating the control signal. As mentioned above, the logic circuit 835 may be implemented as a state machine, such as a finite state machine FSM. Reference is provided using Verilog as the hardware description language. For example, 3'b010 means binary 010 (using 3 bits).

[0070] Figure 8E is a plot diagram illustrating the operation of the state machine of Figure 8D, showing waveforms of the clock signal from clock 834, the modulation signal VMOD provided by comparator 832, the outputs of D-type flip-flops 833a and 833b, the state of the FSM, the control signal S_cont, and the phase (0, 1, 2, or 3).

[0071] Figure 9 is a diagram illustrating an example implementation of a power stage having two phases for use with the controller of Figure 8 A. Power stage 900 is also referred to as a dual power stage DPU.

[0072] A driver 910 is provided for the first phase and a driver 920 is provided for the second phase. Each driver is implemented in a similar manner. The driver 910 includes a logic circuit 912 coupled to an oscillator OSC, a zero current detector ZCD, a low side sensor LS:Isns, an on-time calculator Ton, and optionally an average current sensor Iavg. The on-time calculator may be configured to generate a ramp that charges a capacitor C with a current (Vin-Vout) / R. The ramp starts from 0 at the beginning of the on-time and the ramp reaches Vout at the ideal Ton. A voltage comparator may compare the ramp against Vout and toggles at the end of the on-time.

[0073] The low-side sensor LS:Isns is configured to measure the current through the low-side switch. The logic circuit 910 includes a decoder (not shown) for decoding the control signal received via a single-wire modulation transport interface (SWMTI). The output of each average current sensor is combined to generate a total average current I_avg_total. It should be noted that the topology of the circuit 900 may be extended to any number N of phases.

[0074] Figure 10 is a waveform diagram illustrating the operation of the power supply of Figure 6. Shown in Figure 10 are inductor currents 1011, 1012, 1013 and 1014 for the first, second, third and fourth phases, respectively, a pulsed first phase control signal 1021, a second phase control signal 1022, a third phase control signal 1023 and a fourth phase control signal 1024, a feedback ramp signal 1030, a reference signal 1040 (the positive input received by the comparator 832), and a modulation signal VMOD 1050.

[0075] The control signal 1020 indicates that the on-time of each phase can be divided evenly based on the number of phases. This improves the stability and reliability of the power converter. The use of a single control signal for all phases makes it easier to balance the phases.

[0076] Figure 11 shows the feedback lamp voltage V before and after amplitude adjustment. RAMP 1 is a plot showing the duty cycle having a large effect on the lamp voltage. Different applications have different duty cycle ranges. A small lamp amplitude voltage provides better transient performance but is more susceptible to noise. Too small a lamp amplitude voltage can also make the converter unstable. A large lamp amplitude voltage provides a stable converter but can be noisy. By adaptively adjusting the lamp amplitude signal as a function of duty cycle, the converter performance can be improved.

[0077] FIG. 12 is a plot of normalized ramp amplitude as a function of duty cycle obtained without scaling (waveform 1210) and with scaling (waveform 1220). At a duty cycle of 0.5 the normalized ramp peak-to-peak value is 1. By varying gm1 and gm2 as a function of the ideal duty cycle of the converter, the ramp amplitude is maintained within a relatively small range around the desired amplitude level. Different duty cycle threshold levels are used in points 1-8 to adjust gm1 and gm2. The amplitude adjuster may be a state machine configured to adjust gm1 and gm2 at different duty cycle threshold levels. The transconductances gm1 and gm2 are changed in the same ratio; i.e. a change of 0.5 means that gm1 is divided by 2 and gm2 is divided by 2.

[0078] FIG. 13 illustrates an exemplary embodiment of a duty cycle estimator for estimating the ideal duty cycle of a converter.

[0079] Circuit 1300 is a sigma-delta ADC that includes an integrator 1310 coupled to a comparator 1320, a sample circuit 1330, and a DAC 1340. In operation, the integrator 1310 integrates the error between the output voltage Vout and the modulation average value. The comparator 1320 compares the variation, and the output of 1320 is sampled via 1330 and fed back to the DAC 1340. The sampled 1-bit wide comparator output is also fed to a digital low pass filter 1350 that accumulates the 1-bit modulation to give an 8-bit value.

[0080] FIG. 14 illustrates the operation of the circuit of FIG. 6 under transient load conditions. In steady state, one phase operates in anti-phase with the other phases. When a transient load occurs, for example when the load goes from minimum to maximum, it is possible for multiple phases to be turned on simultaneously for a short period of time to accommodate the increased load. However, the circuit of FIG. 6 uses a single control signal that turns on the phases in series as shown in FIG. 7.

[0081] FIG. 14 is a flow chart of a method for improving transient response using a single control signal. A period counter in logic circuit 835 calculates the duration (or period) between successive pulses of the control signal. If the period / duration is too short (e.g., below a first threshold), all phases are activated. If the period / duration is too long (e.g., above a second threshold), only one phase is maintained and the other phases are deactivated. If the period / duration is within a desired range (e.g., between a first threshold and a second threshold), no rapid reaction is required. Information for activating or deactivating one or more phases may be encoded into the control signal 730 by logic circuit 835.

[0082] Figure 15 is a plot illustrating the operation of the circuit of Figure 6 during a load transient, showing the converter output voltage Vout 1510, the inductor currents 1521, 1522, 1523 and 1524 for the first, second, third and fourth phases respectively, and the switching period Tsw 1530 in counts.

[0083] Before time t1, the converter operates in steady state using a single phase (the third phase) and associated steady-state switching period. After time t1, the converter enters a transient load state. The switching period decreases and becomes shorter than the steady-state switching period. The other phases are activated sequentially (the fourth phase followed by the first phase, then the second phase), until all phases are activated.

[0084] Figure 16 is another waveform diagram illustrating the operation of the system of Figure 6. In Figure 16, a feedback ramp signal 1610, a reference signal 1620, a sampling clock signal 1630, a modulation signal VMOD 1640, and a control signal 1650 are shown.

[0085] The modulation signal VMOD is sampled by D-type flip-flops 833a and 833b. This allows the switching frequency to be known with a precision defined by the sampling period, i.e. the duration of pulses T1, T3, T5, T7 of 730. High frequency sampling (oversampling) of the voltage difference between the compensation signal Vcomp=Vref and the ramp signal Vramp prevents bus congestion and allows proper bus arbitration.

[0086] It should be noted that although the controller described herein is described as being used with a step-down COT converter, the controller may also be used with a step-up COT converter.

[0087] Those skilled in the art will appreciate that variations of the disclosed arrangements are possible without departing from the present disclosure. Thus, the above description of specific embodiments is for purposes of illustration and not limitation. It will be apparent to those skilled in the art that minor modifications can be made without significantly altering the operation described above.

Claims

1. 1. A controller for controlling a power stage having one or more phases, comprising: a reference circuit adapted to generate a reference signal; a ramp generator adapted to generate a feedback ramp signal based on a feedback signal of the power stage; a modulator adapted to generate a control signal for controlling at least one of the phases of the power stage; Including, the controller.

2. The controller of claim 1 , wherein the feedback ramp signal has a frequency that is a function of a number of the phases that are active in the power stage.

3. The controller of claim 1 , wherein the control signal comprises a series of pulses, each of the pulses being associated with a corresponding one of the phases of the power stage.

4. The controller of claim 3 , wherein each of the pulses is associated with an on-time of a corresponding one of the phases.

5. The modulator comprises: a comparator adapted to compare the feedback ramp signal with the reference signal to obtain a modulation signal; a sampling circuit configured to sample the modulated signal to generate a digital modulated signal; a logic circuit configured to generate the control signal based on the digitally modulated signal; an oscillator coupled to the sampling circuit and the logic circuit; The controller of claim 1 , comprising:

6. The controller of claim 5 , wherein the logic circuit includes a counter configured to calculate a duration between successive pulses of the control signal.

7. The controller of claim 5 , wherein the logic circuitry is configured to encode the digitally modulated signal for a particular protocol.

8. The controller of claim 1 , wherein the logic circuit is a state machine.

9. The ramp generator comprises: A capacitor; a first transconductance amplifier coupled to the capacitor through a first switch; a second transconductance amplifier coupled to the capacitor through a second switch; a timer configured to control the first switch and the second switch; The controller of claim 1 , comprising:

10. The controller of claim 9 including a closed loop operational amplifier.

11. 2. The controller of claim 1, further comprising: a duty cycle estimator configured to estimate a duty cycle of the power stage; and a ramp amplitude adjuster configured to adjust an amplitude of the feedback ramp signal based on an estimate of a duty cycle.

12. 10. A power supply comprising the controller of claim 1 coupled to a power stage having one or more phases.

13. The power supply of claim 12 , wherein the controller is coupled to the power stage via a single wire interface.

14. 13. The power supply of claim 12, wherein the power stage includes a plurality of phases, each of the phases including a high side power switch coupled to a low side power switch at a switching node.

15. 15. The power supply of claim 14, wherein for each of the phases, the power stage includes a driver, the driver including a decoder for decoding control signals.

16. 16. The power supply of claim 15, wherein the decoder is configured to measure a pulse width of each of the pulses of the control signal and to compare the measured pulse width with a predefined predetermined pulse width value.

17. 13. The power supply of claim 12 which is a constant on-time converter.

18. 1. A method for controlling a power stage having one or more phases, comprising the steps of: generating a reference signal; generating a feedback ramp signal based on a feedback signal of the power stage; generating a control signal for controlling at least one phase of the power stage; A method comprising:

19. The method of claim 18 , wherein the control signal is a single control signal.

20. calculating the duration between successive pulses of said control signal; activating one or more of the phases if the duration is less than a first threshold; deactivating one or more of the phases if the duration exceeds a second threshold; 20. The method of claim 18, comprising:

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